K6E0808C1E-C/E-L, K6E0808C1E-I/E-P For Cisco CMOS SRAM Document Title 32Kx8 Bit High-Speed CMOS Static RAM(5V Operating). Operated at Commercial and Industrial Temperature Ranges. Revision History Rev .No. History Rev. 0.0 Initial release with Preliminary. Aug. 1. 1998 Preliminary Rev. 1.0 Release to Final Data Sheet. Nov. 2. 1998 Final Rev. 2.0 2.1. Add Low Power Version. Feb. 25. 1999 Final Draft Data Remark 2.2. Add data retention charactoristic. The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Revision 2.0 Feburary 1999 For Cisco CMOS SRAM K6E0808C1E-C/E-L, K6E0808C1E-I/E-P 32K x 8 Bit High-Speed CMOS Static RAM FEATURES GENERAL DESCRIPTION • Fast Access Time 10, 12, 15ns(Max.) • Low Power Dissipation Standby (TTL) : 20mA(Max.) (CMOS) : 2mA(Max.) 0.6mA(Max.) L-ver. Only Operating K6E0808C1E-10 : 80mA(Max.) K6E0808C1E-12 : 80mA(Max.) K6E0808C1E-15 : 80mA(Max.) • Single 5.0V±10% Power Supply • TTL Compatible Inputs and Outputs • I/O Compatible with 3.3V Device • Fully Static Operation - No Clock or Refresh required • Three State Outputs • 2V Minimum Data Retention : L-Ver. only • Standard Pin Configuration K6E0808C1E-J : 28-SOJ-300 K6E0808C1E-T : 28-TSOP1-0813. 4F The K6E0808C1E is a 262,144-bit high-speed Static Random Access Memory organized as 32,768 words by 8 bits. The K6E0808C1E uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG′s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The K6E0808C1E is packaged in a 300mil 28-pin plastic SOJ or TSOP1 forward. PIN CONFIGURATION(Top View) OE A11 A9 A8 A13 WE Vcc A14 A12 A7 A6 A5 A4 A3 ORDERING INFORMATION K6E0808C1E-C10/C12/C15 Commercial Temp. K6E0808C1E-I10/I12/I15 Industrial Temp. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 TSOP1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 Vss I/O3 I/O2 I/O1 A0 A1 A2 FUNCTIONAL BLOCK DIAGRAM Row Select I/O1 ~I/O8 28 Vcc A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 Pre-Charge-Circuit Clk Gen. A0 A1 A2 A3 A4 A5 A6 A7 A8 A14 1 Memory Array 512 Rows 64x8 Columns Data Cont. A3 7 I/O Circuit Column Select SOJ 22 OE A2 8 21 A10 A1 9 20 CS A0 10 19 I/O8 I/O1 11 18 I/O7 I/O2 12 17 I/O6 I/O3 13 16 I/O5 Vss 14 15 I/O4 CLK Gen. PIN FUNCTION A9 A10 A11 A12 A13 A14 Pin Name A0 - A14 CS WE OE Address Inputs WE Write Enable CS Chip Select OE Output Enable I/O1 ~ I/O8 -2- Pin Function Data Inputs/Outputs VCC Power(+5.0V) VSS Ground Revision 2.0 Feburary 1999 For Cisco CMOS SRAM K6E0808C1E-C/E-L, K6E0808C1E-I/E-P ABSOLUTE MAXIMUM RATINGS* Parameter Symbol Rating Unit VIN, VOUT -0.5 to 7.0 V Voltage on VCC Supply Relative to VSS VCC -0.5 to 7.0 V Power Dissipation PD 1.0 W Voltage on Any Pin Relative to V SS TSTG -65 to 150 °C Commercial TA 0 to 70 °C Industrial TA -40 to 85 °C Storage Temperature Operating Temperature * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C) Parameter Symbol Min Typ Max Unit Supply Voltage VCC 4.5 5.0 5.5 V Ground VSS 0 0 0 V Input High Voltage VIH 2.2 - VCC+0.5*** V Input Low Voltage VIL -0.5** - 0.8 V * The above parameters are also guaranteed at industrial temperature range. ** V IL(Min) = -2.0(Pulse Width≤7ns) for I≤20mA. *** VIH (Max) = VCC+2.0V(Pulse Width≤7ns) for I≤20mA. DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C,VCC=5.0V±10% unless otherwise specified) Min Max Unit Input Leakage Current ILI VIN = VSS to VCC -2 2 µA Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL VOUT = VSS to VCC -2 2 µA Operating Current ICC Min. Cycle, 100% Duty CS=VIL, VIN = V IH or VIL, IOUT=0mA 10ns - 80 mA 12ns - 80 15ns - 80 - 20 mA mA Parameter Standby Current Symbol Test Conditions ISB Min. Cycle, CS=VIH ISB1 f=0MHz, CS≥VCC-0.2V, VIN≥VCC-0.2V or VIN≤0.2V Normal - 2 L-Ver - 0.6 Output Low Voltage Level VOL IOL=8mA - 0.4 V Output High Voltage Level VOH IOH=-4mA 2.4 - V - 3.95 V VOH1** IOH1=0.1mA * The above parameters are also guaranteed at industrial temperature range. ** VCC=5.0V±5%, Temp.=25°C. CAPACITANCE*(TA=25°C, f=1.0MHz) Item Symbol Test Conditions MIN Max Unit Input/Output Capacitance CI/O VI/O=0V - 8 pF Input Capacitance CIN VIN=0V - 7 pF * Capacitance is sampled and not 100% tested. -3- Revision 2.0 Feburary 1999 For Cisco CMOS SRAM K6E0808C1E-C/E-L, K6E0808C1E-I/E-P AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.) TEST CONDITIONS Parameter Value Input Pulse Levels 0V to 3V Input Rise and Fall Times 3ns Input and Output timing Reference Levels 1.5V Output Loads See below * The above test conditions are also applied at industrial temperature range. Output Loads(A) Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +5V +5.0V 480Ω 480Ω DOUT 255Ω DOUT 255Ω 30pF* 5pF* * Including Scope and Jig Capacitance READ CYCLE* Parameter Symbol K6E0808C1E-10 K6E0808C1E-12 K6E0808C1E-15 Unit Min Max Min Max Min Max tRC 10 - 12 - 15 - ns Address Access Time tAA - 10 - 12 - 15 ns Chip Select to Output tCO - 10 - 12 - 15 ns Output Enable to Valid Output tOE - 5 - 6 - 7 ns Chip Enable to Low-Z Output tLZ 3 - 3 - 3 - ns Output Enable to Low-Z Output tOLZ 0 - 0 - 0 - ns Chip Disable to High-Z Output tHZ 0 5 0 6 0 7 ns Output Disable to High-Z Output tOHZ 0 5 0 6 0 7 ns Output Hold from Address Change tOH 3 - 3 - 3 - ns Chip Selection to Power Up Time tPU 0 - 0 - 0 - ns Chip Selection to Power DownTime tPD - 10 - 12 - 15 ns Read Cycle Time * The above parameters are also guaranteed at industrial temperature range. -4- Revision 2.0 Feburary 1999 For Cisco CMOS SRAM K6E0808C1E-C/E-L, K6E0808C1E-I/E-P WRITE CYCLE* Parameter Symbol K6E0808C1E-10 K6E0808C1E-12 K6E0808C1E-15 Min Max Min Max Min Max Unit Write Cycle Time tWC 10 - 12 - 15 - ns Chip Select to End of Write tCW 8 - 9 - 10 - ns Address Setup Time tAS 0 - 0 - 0 - ns Address Valid to End of Write tAW 8 - 9 - 10 - ns Write Pulse Width(OE High) tWP 8 - 9 - 10 - ns Write Pulse Width(OE Low) tWP1 10 - 12 - 15 - ns Write Recovery Time tWR 0 - 0 - 0 - ns Write to Output High-Z tWHZ 0 5 0 6 0 7 ns Data to Write Time Overlap tDW 5 - 6 - 7 - ns Data Hold from Write Time tDH 0 - 0 - 0 - ns End Write to Output Low-Z tOW 0 - 0 - 0 - ns * The above parameters are also guaranteed at industrial temperature range. TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL , WE=VIH) tRC Address tAA Data Out Valid Data Previous Valid Data -5- Revision 2.0 Feburary 1999 For Cisco CMOS SRAM K6E0808C1E-C/E-L, K6E0808C1E-I/E-P TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO CS tHZ(3,4,5) tOHZ tOE OE tOLZ tOH tLZ(4,5) Data out Valid Data VCC ICC Current ISB tPU tPD 50% 50% NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock) tWC Address tWR(5) tAW OE tCW(3) CS tWP(2) tAS(4) WE tDW Data in High-Z tDH Valid Data tOHZ(6) High-Z(8) Data out -6- Revision 2.0 Feburary 1999 For Cisco CMOS SRAM K6E0808C1E-C/E-L, K6E0808C1E-I/E-P TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed) tWC Address tWR(5) tAW tCW(3) CS tAS(4) tWP1(2) WE tDW Data in High-Z tDH Valid Data tWHZ(6) tOW (10) (9) High-Z(8) Data out TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled) tWC Address tAW tWR(5) tCW(3) CS tAS(4) tWP(2) WE tDW Data in High-Z Valid Data tLZ Data out tDH High-Z tWHZ(6) High-Z(8) High-Z NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. t CW is measured from the later of CS going low to end of write. 4. t AS is measured from the address valid to the beginning of write. 5. t WR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. -7- Revision 2.0 Feburary 1999 For Cisco CMOS SRAM K6E0808C1E-C/E-L, K6E0808C1E-I/E-P FUNCTIONAL DESCRIPTION CS WE OE Mode I/O Pin Supply Current H X X* Not Select High-Z ISB, ISB1 L H H Output Disable High-Z ICC L H L Read DOUT ICC L L X Write DIN ICC * X means Don ′t Care. DATA RETENTION CHARACTERISTICS*(TA=0 to 70°C) Parameter Symbol Test Condition Min. Typ. Max. Unit VCC for Data Retention VDR CS≥VCC-0.2V 2.0 - 5.5 V Data Retention Current IDR VCC=3.0V, CS≥VCC-0.2V VIN≥VCC-0.2V or VIN≤0.2V - - 0.5 mA Data Retention Set-Up Time tSDR 0 - - ns Recovery Time tRDR See Data Retention Wave form(below) 5 - - ms * The above parameters are also guaranteed at industrial temperature range. Data Retention Characteristic is for L-Ver only. DATA RETENTION WAVE FORM CS controlled VCC tSDR Data Retention Mode tRDR 4.5V VIH VDR CS≥VCC - 0.2V CS GND -8- Revision 2.0 Feburary 1999 For Cisco CMOS SRAM K6E0808C1E-C/E-L, K6E0808C1E-I/E-P Units:millimeters/Inches PACKAGE DIMENSIONS 28-SOJ-300 #15 7.62 0.300 #28 8.51 ±0.12 0.335 ±0.005 6.86 ±0.25 0.270 ±0.010 +0.10 -0.05 0.20 #1 0.008+0.004 -0.002 #14 0.69 MIN 0.027 18.82 MAX 0.741 18.41 ±0.12 0.725 ±0.005 ( ( ( 0.43 0.95 ) 0.0375 +0.10 -0.05 0.017 +0.004 -0.002 1.27 0.050 0.71 1.30 ) 0.051 0.051 ) 3.76 MAX 0.148 0.10 0.004 MAX +0.10 -0.05 0.028+0.004 -0.002 0.10 MAX 0.004 MAX 28-TSOP1-0813.4F 13.40 ±0.20 0.528 ±0.008 #28 #14 #15 ( 8.40 0.331 MAX #1 0.55 0.0217 0.25 0.010 TYP 0.425 ) 0.017 8.00 0.315 +0.10 -0.05 +0.004 0.008 -0.002 0.20 1.00 ±0.10 0.039 ±0.004 11.80 ±0.10 0.465 ±0.004 0.15 0.006 +0.10 -0.05 +0.004 -0.002 1.20 0.047 MAX 0.05 0.002 MIN 0~8 ° 0.45 ~0.75 0.018 ~0.030 ( -9- 0.50 ) 0.020 Revision 2.0 Feburary 1999