TI1 GD75323DW Multiple rs-232 drivers and receiver Datasheet

GD75323
MULTIPLE RS-232 DRIVERS AND RECEIVERS
SLLS213A – JANUARY 1996 – REVISED JUNE 1999
D
D
D
D
D
D
D
Single Chip With Easy Interface Between
UART and Serial-Port Connector of an
External Modem or Other Computer
Peripheral
Five Drivers and Three Receivers Meet or
Exceed the Requirements of ANSI Standard
TIA/EIA-232-F and ITU Recommendation
V.28 Standards
Supports Data Rates up to 120 kbit/s
Complement to the GD75232
Provides Pin-to-Pin Replacement for the
Goldstar GD75323
Pin-Out Compatible With SN75196
Functional Replacement for the MC145405
DW OR N PACKAGE
(TOP VIEW)
VCC
1DA
2DA
3DA
1RY
2RY
4DA
3RY
5DA
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VDD
1DY
2DY
3DY
1RA
2RA
4DY
3RA
5DY
VSS
description
The GD75323 combines five drivers and three receivers from the trade-standard SN75188 and SN75189
bipolar quadruple drivers and receivers, respectively. The flow-through design of the GD75323 decreases the
part count, reduces the board space required, and allows easy interconnection of the UART and serial-port
connector. The all-bipolar circuits and processing of the GD75323 provide a rugged, low-cost solution for this
function.
The GD75323 complies with the requirements of the ANSI TIA/EIA-232-F and ITU (formerly CCITT) V.28
standards. These standards are for data interchange between a host computer and a peripheral at signal rates
up to 20 kbit/s. The switching speeds of the GD75323 are fast enough to support rates up to 120 kbit/s with lower
capacitive loads (shorter cables). Interoperability at the higher signaling rates cannot be assured unless the
designer has design control of the cable and the interface circuits at both ends. For interoperability at signaling
rates up to 120 kbit/s, use of ANSI Standard TIA/EIA-423-B and TIA/EIA-422-B and ITU Recommendations V.10
and V.11 are recommended.
The GD75323 is characterized for operation over a temperature range of 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
GD75323
MULTIPLE RS-232 DRIVERS AND RECEIVERS
SLLS213A – JANUARY 1996 – REVISED JUNE 1999
logic symbol†
1DA
2DA
3DA
1RY
2RY
4DA
3RY
5DA
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
1DY
2DY
3DY
1RA
2RA
4DY
3RA
5DY
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1DA
2DA
3DA
1RY
2RY
4DA
3RY
5DA
2
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
POST OFFICE BOX 655303
1DY
2DY
3DY
1RA
2RA
4DY
3RA
5DY
• DALLAS, TEXAS 75265
GD75323
MULTIPLE RS-232 DRIVERS AND RECEIVERS
SLLS213A – JANUARY 1996 – REVISED JUNE 1999
schematic (each driver)
To Other Drivers
VDD
11.6 kΩ
9.4 kΩ
Input DAx
75.8 Ω
320 Ω
DYx Output
4.2 kΩ
GND
To Other
Drivers
10.4 kΩ
3.3 kΩ
68.5 Ω
VSS
To Other Drivers
Resistor values shown are nominal.
schematic (each receiver)
To Other Receivers
VCC
9 kΩ
5 kΩ
1.66 kΩ
RYx Output
2 kΩ
3.8 kΩ
Input RAx
10 kΩ
GND
To Other Receivers
Resistor values shown are nominal.
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3
GD75323
MULTIPLE RS-232 DRIVERS AND RECEIVERS
SLLS213A – JANUARY 1996 – REVISED JUNE 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 V
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Supply voltage, VSS (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 15 V
Input voltage range, VI: Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –15 V to 7 V
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 30 V to 30 V
Output voltage range, VO (Driver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 15 V to 15 V
Low-level output current, IOL (Receiver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to the network ground terminal.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
Supply voltage
VDD
VSS
High-level input voltage, VIH
VCC
Driver
Low-level input voltage, VIL
Driver
MIN
NOM
MAX
7.5
9
13.5
– 7.5
–9
– 13.5
4.5
5
5.5
1.9
–6
Receiver
– 0.5
Driver
High level output current,
High-level
current IOL
6
Receiver
Operating free-air temperature,TA
V
V
0.8
Driver
High level output current,
High-level
current IOH
UNIT
16
0
70
V
mA
mA
°C
supply currents over operating free-air temperature range
PARAMETER
IDD
ISS
ICC
4
TEST CONDITIONS
MAX
All inputs at 1.9
1 9 V,
V
No load
VDD = 9 V,
VDD = 12 V,
VSS = – 9 V
VSS = – 12 V
25
All inputs at 0.8
0 8 V,
V
No load
VDD = 9 V,
VDD = 12 V,
VSS = – 9 V
VSS = – 12 V
7.5
1 9 V,
V
All inputs at 1.9
No load
VDD = 9 V,
VDD = 12 V,
VSS = – 9 V
VSS = – 12 V
– 25
All inputs at 0.8
0 8 V,
V
No load
VDD = 9 V,
VDD = 12 V,
VSS = – 9 V
VSS = – 12 V
– 5.3
VCC= 5 V,
All inputs at 5 V,
No load
Supply current from VDD
Supply current from VSS
Supply current from VCC
MIN
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32
9.5
– 32
– 5.3
20
UNIT
mA
mA
mA
mA
mA
GD75323
MULTIPLE RS-232 DRIVERS AND RECEIVERS
SLLS213A – JANUARY 1996 – REVISED JUNE 1999
DRIVER SECTION
electrical characteristics over operating free-air temperature range, VDD = 9 V, VSS = –9 V,
VCC = 5 V (unless otherwise noted)
PARAMETER
VOH
VOL
High-level output voltage
IIH
IIL
High-level input current
IOS(H)
IOS(L)
ro
TEST CONDITIONS
MIN
TYP
6
7.5
MAX
UNIT
VIL = 0.8 V,
VIH = 1.9 V,
RL = 3 kΩ,
See Figure 1
RL = 3 kΩ,
See Figure 1
–6
V
See Figure 2
10
µA
Low-level input current
VI = 5 V,
VI = 0,
See Figure 2
– 1.6
mA
High-level short-circuit output current
(see Note 4)
VIL = 0.8 V,
VO = 0,
See Figure 1
– 4.5
–9
– 19.5
mA
VIH = 2 V,
VO = 0,
VCC = VDD = VSS = 0,
See Figure 1
4.5
9
19
mA
Low-level output voltage (see Note 3)
Low-level short-circuit output current
– 7.5
V
VO = – 2 V to 2 V
300
Ω
NOTES: 3. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic
levels only, e.g., if – 10 V is maximum, the typical value is a more negative voltage.
4. Output short-circuit conditions must maintain the total power dissipation below absolute maximum ratings.
5. Test conditions are those specified by TIA/EIA-232-F and as listed above.
Output resistance (see Note 5)
switching characteristics, VDD = 12 V, VSS = –12 V, VCC = 5 V ± 10%, TA = 25°C
PARAMETER
tPLH
tPHL
tTLH
tTHL
TEST CONDITIONS
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
time lowlow to high-level
high level output
Transition time,
Transition time, highg to low-level output (see
(
Note 5)
TYP
MAX
UNIT
315
500
ns
75
175
ns
CL = 15 pF,
60
100
ns
RL = 3 kΩ to 7 kΩ,
See Figure 3 and Note 6
CL = 2500 pF,
1.7
2.5
µs
RL = 3 kΩ to 7 kΩ,
See Figure 3
CL = 15 pF,
40
75
ns
RL = 3 kΩ to 7 kΩ,
See Figure 3 and Note 7
CL = 2500 pF,
1.5
2.5
µs
RL = 3 kΩ to 7 kΩ,,
See Figure 3
CL = 15 pF,,
RL = 3 kΩ to 7 kΩ,
See Figure 3
MIN
NOTES: 6. Measured between – 3-V and 3-V points of the output waveform (TIA/EIA-232-F conditions), all unused inputs are tied either high
or low.
7. Measured between 3-V and – 3-V points of the output waveform (TIA/EIA-232-F conditions), all unused inputs are tied either high
or low.
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GD75323
MULTIPLE RS-232 DRIVERS AND RECEIVERS
SLLS213A – JANUARY 1996 – REVISED JUNE 1999
RECEIVER SECTION
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
TA = 0°C to 70 °C
TYPĔ
MAX
1.75
1.9
2.3
VIT
IT+
Positive going input threshold voltage
Positive-going
VIT–
Vhys
Negative-going input threshold voltage
VOH
High level output voltage
High-level
IOH = – 0.5
0 5 mA
VIH = 0.75 V
Inputs open
VOL
Low-level output voltage
IIH
High level input current
High-level
IOL = 10 mA,
VI = 25 V,
VI = 3 V
See Figure 5
3.6
See Figure 5
0.43
IIL
Low level input current
Low-level
VI = 3 V,
VI = – 25 V,
See Figure 5
– 3.6
VI = – 3 V,
See Figure 5
– 0.43
Input hysteresis voltage (VIT+ – VIT–)
See Figure 5
MIN
1.55
0.75
See Figure 5
2.3
0.97
1.25
4
5
0.2
0.45
UNIT
V
0.5
2.6
2.6
IOS
Short-circuit output current
See Figure 4
† All typical values are at TA = 25°C, VCC = 5 V, VDD = 9 V, and VSS = – 9 V.
8.3
– 8.3
V
V
mA
mA
– 3.4
–12
mA
TYP
MAX
UNIT
107
500
ns
switching characteristics, VCC = 5 V, VDD = 12 V, VSS = –12 V, TA = 25°C
PARAMETER
TEST CONDITIONS
tPLH
tPHL
Propagation delay time, low- to high-level output
tTLH
tTHL
Transition time, low- to high-level output
Propagation delay time, high- to low-level output
CL = 50 pF,
See Figure 6
MIN
RL = 5 kΩ,
Transition time, high- to low-level output
42
150
ns
175
525
ns
16
60
ns
PARAMETER MEASUREMENT INFORMATION
IOS(L)
VDD
VCC
VDD
VDD or GND
– IOS(H)
IIH
VSS or GND
VI
VCC
VI
– IIL
VO
RL = 3 kΩ
VI
VSS
VSS
Figure 1. Driver Test Circuit
for VOH, VOL, IOS(H), and IOS(L
6
POST OFFICE BOX 655303
Figure 2. Driver Test Circuit for IIH and IIL
• DALLAS, TEXAS 75265
GD75323
MULTIPLE RS-232 DRIVERS AND RECEIVERS
SLLS213A – JANUARY 1996 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
3V
1.5 V
Input
VDD
Input V
CC
1.5 V
0V
t PHL
Pulse
Generator
VO
CL
(see Note A)
RL
See Note B
90%
Output
VSS
t PLH
50%
10%
50%
10%
90%
VOL
t THL
TEST CIRCUIT
VOH
t TLH
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns.
Figure 3. Driver Test Circuit and Voltage Waveforms
VDD
VCC
VDD
VCC
– IOS
– IOH
VIT, VI
VOH
VI
VOL
IOL
VSS
VSS
Figure 4. Receiver Test Circuit for IOS
Figure 5. Receiver Test Circuit
for VIT, VOH, and VOL
5V
VDD
Input
50%
Input
50%
–5 V
VCC
t PHL
Pulse
Generator
VO
CL
(see Note A)
RL
See Note B
90%
Output
50%
10%
t PLH
50%
10%
90%
VOL
VSS
t THL
TEST CIRCUIT
VOH
t TLH
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: tw = 25 µs, PRR = 20 kHz, ZO = 50 Ω, tr = tf < 50 ns.
Figure 6. Receiver Propagation and Transition Times
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GD75323
MULTIPLE RS-232 DRIVERS AND RECEIVERS
SLLS213A – JANUARY 1996 – REVISED JUNE 1999
TYPICAL CHARACTERISTICS
DRIVER SECTION
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
VOLTAGE-TRANSFER CHARACTERISTICS
VO
VO – Output Voltage – V
9
6
3
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
20
VDD = 12 V, VSS = – 12 V
16
VDD = 9 V, VSS = – 9 V
12
IO
I O – Output Current – mA
12
VDD = 6 V, VSS = – 6 V
0
–3
–6
–9
– 12
ÎÎÎÎ
ÎÎÎÎ
VDD = 9 V
VSS = – 9 V
TA = 25°C
4
0
–4
ÎÎÎ
3-kΩ
Load Line
–8
VOH(VI = 0.8 V)
– 16
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VI – Input Voltage – V
– 20
– 16
2
– 12
SHORT-CIRCUIT OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
VDD = 9 V
VSS = – 9 V
RL = 3 kΩ
TA = 25°C
IOS(L) (VI = 1.9 V)
SR – Slew Rate – V/ µs
6
3
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎ
ÁÁ
ÎÎÎÎÎÎ
ÁÁ
0
VDD = 9 V
VSS = – 9 V
VO = 0
–3
16
ÁÁÁÁÁ
ÁÁÁÁÁ
ÎÎÎÎÎ
ÁÁÁÁÁ
1000
9
12
SLEW RATE
vs
LOAD CAPACITANCE
12
IIOS
OS – Short-Circuit Output Current – mA
–8
–4
0
4
8
VO – Output Voltage – V
Figure 8
Figure 7
100
10
–6
IOS(H) (VI = 0.8 V)
–9
1
– 12
0
10
20
30
40
50
60
70
10
TA – Free-Air Temperature – °C
100
Figure 10
POST OFFICE BOX 655303
1000
CL – Load Capacitance – pF
Figure 9
8
VOL(VI = 1.9 V)
– 12
RL = 3 kΩ
TA = 25°C
0
8
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎ ÎÎÎÎÎ
• DALLAS, TEXAS 75265
10000
GD75323
MULTIPLE RS-232 DRIVERS AND RECEIVERS
SLLS213A – JANUARY 1996 – REVISED JUNE 1999
TYPICAL CHARACTERISTICS
RECEIVER SECTION
INPUT THRESHOLD VOLTAGE
vs
SUPPLY VOLTAGE
2.4
2
2.2
1.8
V – Input Threshold Voltage – V
IT
V – Input Threshold Voltage – V
IT
INPUT THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
VIT +
2
1.8
1.6
1.4
1.2
VIT–
0.8
0.6
0.4
VIT+
1.6
1.4
1.2
1
VIT–
0.8
0.6
0.4
0.2
0
10
20
30
40
50
60
0
2
70
TA – Free-Air Temperature – °C
3
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÁÁÁÁ
ÎÎÎÎÎ
ÁÁÁÁ
ÎÎÎÎÎ
NOISE REJECTION
ÁÁÁÁ
ÁÁÁÁ
ÎÎÎÎ
ÁÁÁ
ÎÎÎÎ
ÁÁÁ
CC = 500 pF
CC = 12 pF
2
CC = 100 pF
1
0
10
40
100
400 1000
4000
tw – Pulse Duration – ns
10000
NOTE A: This figure shows the maximum amplitude of a
positive-going pulse that, starting from 0 V, does not
cause a change of the output level.
20
30
40
50
60
TA – Free-Air Temperature – °C
70
14
VDD – Maximum Supply Voltage – V
Amplitude – V
3
10
16
CC = 300 pF
4
9
MAXIMUM SUPPLY VOLTAGE
vs
FREE-AIR TEMPERATURE
VCC = 5 V
TA = 25°C
See Note A
5
5
6
7
8
VCC – Supply Voltage – V
Figure 12
Figure 11
6
4
12
10
8
6
4
2
RL ≥ 3 kΩ (from each output to GND)
0
0
10
Figure 13
Figure 14
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GD75323
MULTIPLE RS-232 DRIVERS AND RECEIVERS
SLLS213A – JANUARY 1996 – REVISED JUNE 1999
APPLICATION INFORMATION
Diodes placed in series with the VDD and VSS leads protect the GD75323 in the fault condition in which the device
outputs are shorted to VDD or VSS, and the power supplies are at low and provide low-impedance paths to
ground (see Figure 15).
VDD
± 15 V
VDD
Output
GD75323
GD75323
VSS
VSS
Figure 15. Power-Supply Protection to Meet Power-Off Fault Conditions of TIA / EIA-232-F
TIA/EIA-232-F
DB9S
Connector
– 12 V
TL16C450
ACE
10
RI 43
9
DTR 37
8
CTS 40
7
SO 13
6
RTS 36
5
SI 11
4
DSR 41
3
DCD 42
2
1
GND
VSS
5DA
5DY
3RY
3RA
4DA
4DY
2RY
2RA
GD75323
1RY
1RA
3DA
3DY
2DA
2DY
1DA
1DY
VCC
VDD
11
12
5
9
RI
13
DTR
14
CTS
15
TX
16
RTS
17
RX
18
DSR
19
20
C5†
C4†
DCD
C3†
6
C2†
C1†
1
12 V
5V
† See Figure 10 to select the correct values for the loading capacitors (C1, C2, C3, C4, and C5), which may be required to meet the RS-232
maximum slew-rate requirement of 30 V/µs. The value of the loading capacitors required depends upon the line length and desired slew rate,
but is typically 330 pF.
NOTE C: To use the receivers only, VDD and VSS both must be powered or tied to ground.
Figure 16. Typical Connection
10
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
GD75323DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
GD75323
GD75323DWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
GD75323
GD75323DWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
GD75323
GD75323N
OBSOLETE
PDIP
N
20
TBD
Call TI
Call TI
0 to 70
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
GD75323DWR
Package Package Pins
Type Drawing
SOIC
DW
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
10.8
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.0
2.7
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
GD75323DWR
SOIC
DW
20
2000
367.0
367.0
45.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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