NSC LMX2531LQ1146E Evaluation board operating instruction Datasheet

LMX2531LQ1146E
Evaluation Board Operating Instructions
National Semiconductor Corporation
Timing Devices Business Group
10333 North Meridian
Suite 400
Indianapolis, IN 46290
LMX2531LQ1146EFPEB Rev 3.31.2008
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Table of Contents
TABLE OF CONTENTS ...................................................................................................................... 2
LOOP FILTER .................................................................................................................................. 3
QUICK SETUP ................................................................................................................................. 3
TROUBLESHOOTING ........................................................................................................................ 4
PHASE NOISE ................................................................................................................................. 5
FREE-RUNNING VCO PHASE NOISE (INTERNAL DIVIDE BY 2 DISABLED) ............................................ 6
FREE-RUNNING VCO PHASE NOISE (INTERNAL DIVIDE BY 2 ENABLED) ............................................. 7
FRACTIONAL SPURS (INTERNAL DIVIDE BY 2 DISABLED).................................................................... 8
FRACTIONAL SPURS (INTERNAL DIVIDE BY 2 ENABLED)..................................................................... 9
INTEGER SPURS (INTERNAL DIVIDE BY 2 DISABLED)........................................................................ 10
INTEGER SPURS (INTERNAL DIVIDE BY 2 ENABLED) ........................................................................ 11
CODELOADER SETTINGS ............................................................................................................... 12
SCHEMATIC .................................................................................................................................. 17
BILL OF MATERIALS ....................................................................................................................... 18
TOP LAYER ................................................................................................................................... 19
MID LAYER 1 "GROUND PLANE"..................................................................................................... 20
MID LAYER 2 "POWER".................................................................................................................. 21
BOTTOM LAYER "SIGNAL" .............................................................................................................. 22
TOP BUILD DIAGRAM ..................................................................................................................... 23
2
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Loop Filter
Loop Bandwidth
7.9
Kφ
1440 uA (16X)
Phase Margin
61.4
Fcomp
10 MHz
Crystal Frequency
10 MHz
Output Frequency
1106 - 1184 MHz (DIV2=0)
553 - 592 MHz (DIV2=1)
Supply Voltage
3.0 Volts
VCO Gain
2.5-5.5 MHz/Volt
CPout
20 KΩ
20 KΩ
VCO
100 nF
100 pF
100 pF
1 KΩ
open
Vtune
Quick Setup
•
•
•
•
•
•
•
•
Install the CodeLoader software which is available at www.national.com/timing.
Attach the parallel , or USB to parallel, port cable to the computer and the evaluation board.
Connect 3.0 volts to the Vcc connector
Connect the Fout connector to a spectrum analyzer or phase noise analyzer
Connect a clean 10 MHz source to the OSCin pin. Typically, the 10 MHz output from the back
of the RF test equipment is a good source. Signal generators tend to be very noisy and should
be used with caution. If a signal generator is used, the signal generator phase noise
contribution can be reduced by setting the signal to 80 MHz and dividing this down to a phase
detector frequency of 10 MHz.
Set up the CodeLoader software
o Select the proper part from the menu as Select Part->PLL+VCO->LMX2531LQ1146E
o Select the proper mode from the Mode menu
o Load the part by pressing Ctrl+L or selecting Keyboard Controls->Load Device from
the menu
It is recommended to ensure proper communication with the device
o Click the REG_RST bit on the bits/pins page and observe the current go to 0 mA
o Unclick the REG_RST bit AND press Ctrl+L. The current should be approximately
35 mA
o If device does not respond to this, consult the troubleshooting section
When using the lower frequency band with divide by 2 enabled (DIV2=1), be aware that the
frequency programmed to the VCO is actually twice the output frequency of the device
because the VCO frequency is being divided by 2.
3
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Troubleshooting
Far-out
Phase
noise is worse
than evaluation
board
instructions show
Close-in
phase
noise is worse
than
evaluation
board
instructions show
Part responds to
programming,
but
does not lock to the
correct frequency
Software does not communicate with the evaluation boards
Problem
Corrective Actions
All Modes
• Ensure a valid signal is presented to the OSCin connector. If a signal generator
is used, ensure the RF is ON.
• Consult the CodeLoader instructions for more detailed information on
communication issues
LPT Mode (Uses Parallel Port Cable)
• Ensure that CodeLoader is selected to LPT mode on the Port Setup tab
• Ensure the proper port number is selected (LPT1, LPT2, LPT3). CodeLoader
does NOT automatically detect this.
• Ensure the LPT cable is securely connected to the computer and board.
• Exit and Restart CodeLoader
• Ensure the parallel port is in the correct mode
o Windows often requires Administrative access to write to the parallel
port
o Ensure that the parallel port is set to “Enabled” in windows device
manager
o A reboot upon installation of CodeLoader is sometimes necessary to get
the parallel port to work.
o Standard mode is the most reliable. This can be set in the BIOS mode
of the computer as “Normal”, “Output Only”, or “AT”
USB Mode (Uses USB to Parallel Port Converter)
• On the menu, select USB->Version to verify communication with the board
• Ensure the Green LEDs are lit on the USB board
• Ensure there are no conflicts with other USB devices and reinstall the board
• Ensure that there is a valid signal presented to the OSCin connector. If a signal
generator is used, ensure that the RF is set to ON.
• If using the lower frequency band (DIV2=1), the VCO frequency in CodeLoader
should be twice the frequency at the Fout pin.
• Ensure that the VCO FREQUENCY CAL bits on the Bits/Pins tab are correct
• Ensure that the loop filter is optimized if the charge pump current, phase detector
frequency, or loop filter values have been changed from their original settings.
Ensure that the integrated loop filter components on CodeLoader are set to their
proper settings
• Ensure the signal presented to OSCin connector is clean. Try another source,
or if it is a signal generator, try using a higher frequency and dividing it down to
the phase detector frequency.
• Ensure the OSCin signal and cable provide sufficient power level.
• If the phase detector frequency or charge pump current are lowered from their
original settings, the in-band phase noise can be degraded, even if the loop filter
is re-designed for the same loop bandwidth. If the loop bandwidth is decreased,
in-band phase noise can be degraded
• Ensure the measurement equipment noise floor is not limiting the measurement.
For spectrum analyzers, the noise floor at a particular setting can be measured
by removing the RF input signal
• If the settings are changed from what the board was designed for, ensure the
delta-sigma modulator is not increasing the far-out noise. To know this, tune to
an integer channel and set the ORDER bit to “Reset Modulator”. The far out
phase noise should not decrease. If it does, try a loop filter with more
attenuation or select a lower order delta-sigma modulator.
4
Output Frequency = 1146 MHz
Internal Divide by 2 Disabled (DIV2=0)
Output Frequency = 573 MHz
Internal Divide by 2 Enabled (DIV2=1)
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Phase Noise
5
B O A R D
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Fout = 1106 MHz
Free-Running VCO Phase Noise (Internal Divide by 2 Disabled)
The plots to the left show the true phase noise capability of the
VCO.
In order to take these plots, the E5052 phase nose
Fout = 1146 MHz
analyzer was used.
The method was to lock the PLL to the
proper frequency, then disable the EN_PLL, EN_PLLLDO1, and
EN_PLLLDO2 bits. The equipment needs to be able to track
the VCO phase noise to measure in this way, and one can not
let the VCO drift too far off in frequency. If this kind of equipment
is not available, the VCO phase noise can also be measured by
Fout = 1184 MHz
making a very narrow loop bandwidth filter.
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Fout = 553 MHz (1106 MHz/2)
Free-Running VCO Phase Noise (Internal Divide by 2 Enabled)
The plots to the left show the true phase noise capability of the
VCO.
In order to take these plots, the E5052 phase nose
analyzer was used.
The method was to lock the PLL to the
Fout = 573 MHz (1146 MHz/2)
proper frequency, then disable the EN_PLL, EN_PLLLDO1, and
EN_PLLLDO2 bits. The equipment needs to be able to track
the VCO phase noise to measure in this way, and one can not
let the VCO drift too far off in frequency. If this kind of equipment
is not available, the VCO phase noise can also be measured by
making a very narrow loop bandwidth filter.
When divide by 2 is enabled, the phase noise at lower offsets is
about 6 dB better; but at high offsets, the phase noise
improvement may be less because the divider is noise floor is
Fout = 592 MHz (1184 Mhz/2)
adding to the phase noise.
7
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Fractional Spurs (Internal Divide by 2 Disabled)
Fractional Spur at 250 kHz offset at a
worst case frequency of 1110.25 MHz is
–78.6 dBc. Worst case channels occur
at exactly one channel spacing above or
below a multiple of the crystal frequency.
Fractional Spur at 250 kHz offset at a
worst case frequency of 1150.25 MHz is
–73.3 dBc.
The sub-fractional spur at
125 kHz offset of -81.3 dBc is also
visible
Fractional Spur at 250 kHz offset at a
worst case frequency of 1180.25 MHz is
– 76.4 dBc.
8
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Fractional Spurs (Internal Divide by 2 Enabled)
Spur at 250 kHz offset at a frequency of
555.125 MHz is –92.5 dBc. Since this
mode uses the divide by 2 mode, the
channel spacing here is actually 125
kHz.
The spur at 125 kHz could be
completely
eliminated
changing
the
fractional denominator.
Spur at 250 kHz offset for a frequency of
575.125 MHz is -83.4 dBc.
Spur at 250 kHz offset for a frequency of
590.125 MHz is –83.6 dBc.
9
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Integer Spurs (Internal Divide by 2 Disabled)
Spur at 10 MHz offset for a frequency of
1106 MHz is -94.7 dBc .
Spur at 10 MHz offset for a frequency of
1146 MHz is -93.2 dBc..
Spur at 10 MHz offset for a frequency of
1184 MHz
is below the spectrum
analyzer noise floor.
10
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Integer Spurs (Internal Divide by 2 Enabled)
Spur at 10 MHz offset for a frequency of
553 MHz
is below the spectrum
analyzer noise floor.
Spur at 10 MHz offset for a frequency of
573 MHz
is below the spectrum
analyzer noise floor.
Spur at 10 MHz offset for a frequency of
592 MHz is below the spectrum analyzer
noise floor.
11
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CodeLoader Settings
CodeLoader runs many devices. When CodeLoader is first started, it is
necessary to select the correct device.
12
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There can be different modes defined for a particular part. A mode can be
recalled easily from the menu. This restores bit settings and frequencies, but not
the Port Setup information. For the CodeLoader program, the default reference
oscillator used for these instructions was 10 MHz, but there is a mode for a 61.44
MHz oscillator as well. If the bits become scrambled, their original state may be
recalled by choosing the appropriate mode. If the internal divide by 2 (DIV2) is
enabled, the VCO frequency still reflects the VCO frequency before the divide by
2.
13
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The Bits/Pins tab displays many of the bits used to program the part. Right
mouse click any bit to view more information about what this does.
When the DIV2 bit is enabled, the frequency from the part will be half of that
shown on the PLL/VCO tab. The frequency on the PLL/VCO tab does not reflect
this because the divide by 2 is actually after the VCO. Also be sure to load the
device (Ctrl+L) after changing this bit to allow the VCO to calibrate for optimal
phase noise performance.
14
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The Registers tab shows the literal bits that are being sent to the part. These are
the registers every time the PLL is loaded by using the menu command or Ctrl+L.
R5 (INIT1) and R5 (INIT 2) are just the R5 register being used to properly
initialize the part. So a single CNT+L will load the part.
15
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The port setup tells CodeLoader what information goes where. If this is wrong,
the part will not program. Although LPT1 is usually correct, CodeLoader does
NOT automatically detect the correct port. On some laptops, it may be LPT3.
16
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Schematic
2
3
R2
2
4
6
8
R3
C1
R6
VccBUF
D
C3
VccPLL
C7
C4
VccDIG
R22
VccPLL
R2pLF
VregDI G
NC
GND
Test
OSCin*
OSCin
Ftest/LD
NC
Vr egPLL2
R24
C
C18
VccDIG
C10
C100
C11
R17
VccDIG
NC
GND
NC
NC
VregBUF
NC
DATA
CLK
VccPLL
VregPLL1
FLout
CPout
Vtune
VccBUF
Fout
GND
GND
27
26
25
24
23
22
21
20
19
LE
CE
NC
NC
NC
NC
VccVCO
Vr egVCO
Vr efVCO
SLG1
SLG2
SLG3
R19
R10
R9
C8
C102
C15
B
C101
C14
C13
R18
R11
Fout
R21
C12
R14
R12
C17
10
11
12
13
14
15
16
17
18
37
38
39
VccVCO
R13
VccBUF
R20
B
R15
C
C16
U1
R16
C2pLF
1
2
3
4
5
6
7
8
9
C9
C20
C19
36
35
34
33
32
31
30
29
28
C23
C24
C105
R23
C1_LF
C5
C103
C21
R5
R7
R2_LF
R4
Ftest/LD
C2_LF
D
OSCin
VccVCO
C2
6
C22
R1
Vcc
1
3
5
7
5
C6
POWER
Vcc
4
C104
1
R8
Vcc
2
4
6
8
10
TRIGGER
GND
A
FRAME
A
uWIRE
Title
LMX2531 Evaluation Board
1
3
5
7
9
Size
1
2
B
Note that Any Component with Designator 100 or Higher is on the BottomSide of the Board
3
4
17
Date:
File:
5
Number
Revision
LMX2531SLBCBPCB
01-06-2006
6-Jan-2006
Sheet of
C:\Documentum\Checkout\LMX2531LQEBPCB.ddb.ddb
Drawn By: Dan Chappel l
6
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Bill of Materials
Bill of Materials
Item
QTY
Manufacturer
LMX2531_LF
Part #
Size
Tol
Voltage
Material
20
Revision 3.28.2008
Value
Open Capacitors
0
n/a
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
7
1
1
2
1
6
1
1
1
1
2
2
4
1
1
4
4
16
1
17
18
1
3
19
1
20
1
21
22
Designators
C1_LF, C2pLF, C2, C3, C4, C5, C9,
C11, C14, C17, C18, C19, C21, C24,
C100, C101, C102, C103, C104, C105
R2pLF,R7, R8, R17, R19, R21, R24
Ftest/LD
C16
C10, C23
C2_LF
C6, C7, C12, C15, C22, C20
C8
C13
C1
R20
R22, R23
R1, R18
R2, R3, R4, R5
R6
R2_LF
R9, R11, R13, R15
R10, R12, R14, R16
Kemet
Kemet
Kemet
Kemet
Kemet
Kemet
Kemet
Vishay
Panasonic
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Comm Con
Connectors
FCI Electronics
Johnson Components
National
Semiconductor
National
Semiconductor
C0603C101J5GAC
C0603C103J5RAC
C0805C104K5RACTU
C0603C104J3RAC
C0603C105K4RAC
C0603C475K9PAC
C0805C106K8PAC
CRCW0603000ZRT1
P.22AHCT-ND
CRCW06033R3JRT1
CRCW0603100JRT1
CRCW0603510JRT1
CRCW0603102JRT1
CRCW0603103JRT1
CRCW0603123JRT1
603
603
805
603
603
603
805
603
603
603
603
603
603
603
603
5%
5%
5%
5%
10%
10%
10%
5%
10%
5%
5%
5%
5%
5%
5%
50V
50V
25V
25V
16V
6.3V
10V
0.1W
0.1W
0.1W
0.1W
0.1W
0.1W
0.1W
0.1W
C0G
X7R
C0G
X7R
X5R
X5R
X5R
Thick Film
Thick Film
Thick Film
Thick Film
Thick Film
Thick Film
Thick Film
Thick Film
Open Resistors
Open Miscellaneous
100pF
10nF
100nF
100nF
1uF
4.7uF
10uF
0Ω
0.22Ω
3.3Ω
10Ω
51Ω
1KΩ
10KΩ
12KΩ
HTSM3203-8G2
2X4
n/a
n/a
Metal/Plastic
Header
POWER
52601-S10-8
142-0701-851
2X5
SMA
n/a
n/a
n/a
n/a
n/a
n/a
n/a
Header
SMA
PCB Board
1st Layer 10 mils
uWire
Fout, OSCin, Vcc
LMX2531LQEBPCB
Metal/Plastic
Metal
FR4
62 mil Thick
LMX2531
LLP36
n/a
2.7
Silicon
LMX2531
U1
4
Com Con Connectors
CCIJ255G
2-Pin
n/a
n/a
Metal/Plastic
Shunt
4
SPC Technology
SPCS-8
0.156"
n/a
n/a
Nylon
Nylon Standoffs
18
n/a
Place Across:
POWER: 1-2, 3-4, 5-6, 7-8
Place in 4 Holes in Corners of Board
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Top Layer
19
I N S T R U C T I O N S
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B O A R D
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I N S T R U C T I O N S
Mid Layer 1 "Ground Plane" (15 Mils Down FR4)
20
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I N S T R U C T I O N S
Mid Layer 2 "Power"
21
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Bottom Layer "Signal"
Note:
Total Board Thickness = 61 mils
22
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Top Build Diagram
23
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