Cypress CY29940AXCT 2.5 v or 3.3 v, 200-mhz, 1:18 clock distribution buffer 200-mhz clock support Datasheet

CY29940
2.5 V or 3.3 V, 200-MHz,
1:18 Clock Distribution Buffer
2.5 V or 3.3 V, 200-MHz, 1:18 Clock Distribution Buffer
Features
Description
■
200-MHz clock support
The CY29940 is a low-voltage 200-MHz clock distribution buffer
with the capability to select either a differential LVPECL or a
LVCMOS/LVTTL compatible input clock. The two clock sources
can be used to provide for a test clock as well as the primary
system clock. All other control inputs are LVCMOS/LVTTL
compatible. The eighteen outputs are 2.5 V or 3.3 V
LVCMOS/LVTTL compatible and can drive 50  series or parallel
terminated transmission lines. For series terminated
transmission lines, each output can drive one or two traces giving
the device an effective fanout of 1:36. Low output-to-output
skews make the CY29940 an ideal clock distribution buffer for
nested clock trees in the most demanding of synchronous
systems.
■
LVPECL or LVCMOS/LVTTL clock input
■
LVCMOS/LVTTL compatible inputs
■
18 clock outputs: drive up to 36 clock lines
■
60 ps typical output-to-output skew
■
Dual or single supply operation:
❐ 3.3 V core and 3.3 V outputs
❐ 3.3 V core and 2.5 V outputs
❐ 2.5 V core and 2.5 V outputs
■
Pin compatible with MPC940L, MPC9109
■
Available in Commercial and Industrial temperature
■
32-pin LQFP package
Block Diagram
VDD
PECL_CLK
PECL_CLK#
0
TCLK
1
VDDC
18
Q0-Q17
TCLK_SEL
Cypress Semiconductor Corporation
Document #: 38-07283 Rev. *E
•
Q0
Q1
Q2
VDDC
Q3
Q4
Q5
VSS
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
Q15
VSS
Q14
Q13
Q12
VDDC
CY29940
Q16
1
2
3
4
5
6
7
8
Q17
VSS
VSS
TCLK
TCLK_SEL
PECL_CLK
PECL_CLK#
VDD
VDDC
32
Pin Configuration
198 Champion Court
24
23
22
21
20
19
18
17
•
Q6
Q7
Q8
VDD
Q9
Q10
Q11
VSS
San Jose, CA 95134-1709
•
408-943-2600
Revised May 11, 2011
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CY29940
Pin Description[1]
Pin
Name
PWR
I/O
Description
5
PECL_CLK
I, PU
PECL Input Clock
6
PECL_CLK#
I, PD
PECL Input Clock
3
TCLK
I, PD
External Reference/Test Clock Input
9, 10, 11, 13, 14,
15, 18, 19, 20, 22,
23, 24, 26, 27, 28,
30, 31, 32
Q(17:0)
4
TCLK_SEL
8, 16, 29
VDDC
3.3 V or 2.5 V Power Supply for Output Clock Buffers
7, 21
VDD
3.3 V or 2.5 V Power Supply
1, 2, 12, 17, 25
VSS
Common Ground
VDDC
O
I, PD
Clock Outputs
Clock Select Input. When LOW, PECL clock is selected and when HIGH
TCLK is selected.
Note
1. PD = Internal Pull-Down, PU = Internal Pull-up
Document #: 38-07283 Rev. *E
Page 2 of 10
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CY29940
Maximum Ratings[2]
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For proper
operation, Vin and Vout should be constrained to the range:
Maximum Input Voltage Relative to VSS ............. VSS – 0.3 V
Maximum Input Voltage Relative to VDD............. VDD + 0.3 V
Storage Temperature ................................ –65 C to +150 C
VSS < (Vin or Vout) < VDD
Operating Temperature............................... –40 C to +85 C
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
Maximum ESD Protection .............................................. 2 kV
Maximum Power Supply................................................ 5.5 V
Maximum Input Current ............................................. ±20 mA
DC Parameters[2]
VDD = 3.3 V ± 5% or 2.5 V ± 5%, VDDC = 3.3 V ± 5% or 2.5 V ± 5%, TA = –40 C to +85 C
Parameter
Description
Conditions
Min
Typ
Max
Unit
VIL
Input Low Voltage
VSS
–
0.8
V
VIH
Input High Voltage
2.0
–
VDD
V
IIL
Input Low
Current[3]
–
–
–200
µA
IIH
Input High Current[3]
–
–
200
µA
VPP
Peak-to-Peak Input Voltage
PECL_CLK
500
–
1000
mV
VCMR
Common Mode Range[4]
PECL_CLK
VDD = 3.3 V
VDD – 1.4
–
VDD – 0.6
V
VDD = 2.5 V
VDD – 1.0
–
VDD – 0.6
V
IOL = 20 mA
–
–
0.5
V
IOH = –20 mA, VDDC = 3.3 V
2.4
–
–
V
IOH = –20 mA, VDDC = 2.5 V
1.8
–
–
V
–
5
7
mA
VDD = 3.3 V, Outputs @ 150 MHz,
CL = 15 pF
–
285
–
mA
VDD = 3.3 V, Outputs @ 200 MHz,
CL = 15 pF
–
335
–
VDD = 2.5 V, Outputs @ 150 MHz,
CL = 15 pF
–
200
–
VDD = 2.5 V, Outputs @ 200 MHz,
CL = 15 pF
–
240
–
VDD = 3.3 V
8
12
16
VDD = 2.5 V
10
15
20
–
4
–
VOL
VOH
Output Low
Voltage[5, 6, 7]
Output High
Voltage[5, 6, 7]
IDDQ
Quiescent Supply Current
IDD
Dynamic Supply Current
Zout
Output Impedance
Cin
Input Capacitance

pF
Notes
2. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range
and the input lies within the VPP specification. Driving series or parallel terminated 50  (or 50  to VDD/2) transmission lines
5. Outputs driving 50 transmission lines.
6. See Figure 1 on page 5 and Figure 2 on page 5.
7. 50% input duty cycle.
Document #: 38-07283 Rev. *E
Page 3 of 10
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CY29940
AC Parameters[8]
VDD = 3.3 V ± 5% or 2.5 V ± 5%, VDDC = 3.3 V ± 5% or 2.5 V ± 5%, TA = –40 C to +85 C
Parameter
Description
Conditions
Min
Typ
Max
Unit
Fmax
Input Frequency
–
–
–
200
MHz
tPD
PECL_CLK to Q Delay[9, 10, 11]  150 MHz VDD = 3.3 V, 85 C
tPHL
2.0
–
3.2
ns
tPLH
2.1
–
3.4
VDD = 3.3 V, 70 C
tPHL
1.9
–
3.1
tPLH
2.0
–
3.2
VDD = 2.5 V, 85 C
tPHL
2.5
–
5.2
tPLH
2.6
–
5
VDD = 2.5 V, 70 C
tPHL
2.5
–
5
tPLH
2.6
–
5
VDD = 3.3 V, 85 C
tPHL
1.9
–
3
tPLH
2.0
–
3.2
VDD = 3.3 V, 70 C
tPHL
1.8
–
2.9
tPLH
1.8
–
3.1
VDD = 2.5 V, 85 C
tPHL
2.5
–
4
tPLH
2.5
–
4
VDD = 2.5 V, 70 C
tPHL
2.3
–
3.8
tPLH
tPD
tJ
FoutDC
Tskew
Tskew(pp)
Tskew(pp)
Tskew(pp)
tR/tF
LVCMOS to Q Delay[9, 10, 11]  150 MHz
Total Jitter
Output Duty
Cycle[9, 10, 12]
Output-to-Output Skew[9, 10]
Part-to-Part Skew[13]
Part-to-Part Skew[13]
Part to Part Skew[14]
Output Clocks Rise/Fall Time[9, 10]
ns
2.3
–
3.8
VDD = 3.3 V @ 150 MHz
–
–
10
ps
FCLK < 134 MHz
–
–
55
%
FCLK > 134 MHz
–
–
60
VDD = 3.3 V
–
60
150
VDD = 2.5 V
–
–
200
PECL, VDDC = 3.3 V
–
–
1.4
PECL, VDDC = 2.5 V
–
–
2.2
TCLK, VDDC = 3.3 V
–
–
1.2
TCLK, VDDC = 2.5 V
–
–
1.7
PECL_CLK
–
–
850
TCLK
–
–
750
0.7 V to 2.0 V, VDDC = 3.3 V
0.3
–
1.1
0.5 V to 1.8 V, VDDC = 2.5 V
0.3
–
1.2
ps
ns
ns
ps
ns
Notes
8. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
9. Outputs driving 50 transmission lines.
10. See Figure 1 on page 5 and Figure 2 on page 5.
11. Parameters tested @ 150 MHz.
12. 50% input duty cycle.
13. Across temperature and voltage ranges, includes output skew.
14. For a specific temperature and voltage, includes output skew.
Document #: 38-07283 Rev. *E
Page 4 of 10
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CY29940
Figure 1. LVCMOS_CLK CY29940 Test Reference for VCC = 3.3 V and VCC = 2.5 V
CY29940 DUT
Zo = 50 ohm
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
RT = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 2. PECL_CLK CY29940 Test Reference for VCC = 3.3 V and VCC = 2.5 V
CY29940 DUT
Zo = 50 ohm
Differential
Pulse
Generator
Z = 50 ohm
Zo = 50 ohm
Zo = 50 ohm
RT = 50 ohm
VTT
RT = 50 ohm
VTT
Figure 3. Propagation Delay (TPD) Test Reference
PECL_CLK
PECL_CLK
VPP
VCMR
VCC
Q
VCC /2
tPD
GND
Figure 4. LVCMOS Propagation Delay (TPD) Test Reference
VCC
LVCMOS_CLK
VCC /2
GND
VCC
Q
VCC /2
tPD
Document #: 38-07283 Rev. *E
GND
Page 5 of 10
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CY29940
Figure 5. Output Duty Cycle (FoutDC)
VCC
VCC /2
tP
GND
T0
DC = tP / T0 x 100%
Figure 6. Output-to-Output Skew tsk(0)
VCC
VCC /2
GND
VCC
VCC /2
tSK(0)
GND
Ordering Information
Part Number
Package Type
Production Flow
Pb-free
CY29940AXI
32-pin LQFP
Industrial, –40 C to +85 C
CY29940AXIT
32-pin LQFP – Tape and Reel
Industrial, –40 C to +85 C
CY29940AXC
32-pin LQFP
Commercial, 0 C to 70 C
CY29940AXCT
32-pin LQFP – Tape and Reel
Commercial, 0C to 70 C
Ordering Code Definitions
CY 29940 A
X
X
T
T = Tape and Reel; blank = Tube
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package: A = 32-pin LQFP
Base part number
Company ID: CY = Cypress
Document #: 38-07283 Rev. *E
Page 6 of 10
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CY29940
Package Drawing and Dimensions
Figure 7. 32-pin TQFP 7 × 7 × 1.4 mm A32.14
51-85088 *C
Document #: 38-07283 Rev. *E
Page 7 of 10
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CY29940
Acronyms
Acronym
Document Conventions
Description
ESD
electrostatic discharge
I/O
input/output
Units of Measure
Symbol
°C
Unit of Measure
degree Celsius
LQFP
low-profile quad flat package
LVCMOS
low voltage complementary metal oxide
semiconductor
LVPECL
low-voltage positive emitter-coupled logic
µA
micro Amperes
LVTTL
low-voltage transistor-transistor logic
mA
milli Amperes
TQFP
thin quad flat pack
mm
milli meter
mV
milli Volts
ns
nano seconds

ohms
Document #: 38-07283 Rev. *E
kV
kilo Volts
MHz
Mega Hertz
%
percent
pF
pico Farad
ps
pico seconds
V
Volts
W
Watts
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CY29940
Document History Page
Document Title: CY29940, 2.5 V or 3.3 V, 200-MHz, 1:18 Clock Distribution Buffer
Document Number: 38-07283
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
111094
02/01/02
BRK
New data sheet
*A
116776
08/15/02
HWT
Incorporate results of final characterization using corporate methods, added
output impedance on page 3 and added output duty cycle on page 4.
Add commercial temperature range in the ordering information on page 6.
*B
122875
12/21/02
RBI
Add power up requirements to maximum rating information
*C
448379
See ECN
RGL
Add typical value for output-to-output skew
Add Lead-free devices
*D
2899304
03/25/10
BASH/KVM
*E
3254185
05/11/2011
CXQ
Document #: 38-07283 Rev. *E
Removed inactive parts from Ordering Information.
Updated package diagram.
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Updated in new template.
Page 9 of 10
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CY29940
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2002-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07283 Rev. *E
Revised May 11, 2011
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