FAST CMOS BUFFER/CLOCK DRIVER IDT54/74FCT810BT/CT Integrated Device Technology, Inc. LCC packages • Military product compliant to MIL-STD-883, Class B FEATURES: • • • • • • • • 0.5 MICRON CMOS technology Guaranteed low skew < 600ps (max.) Very low duty cycle distortion < 700ps (max.) Low CMOS power levels TTL compatible inputs and outputs TTL level output voltage swings High drive: –32mA IOH, 48mA IOL Two independent output banks with 3-state control – One 1:5 Inverting bank – One 1:5 Non-Inverting bank • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • Available in DIP, SOIC, SSOP, QSOP, CERPACK and DESCRIPTION: The IDT54/74FCT810BT/CT is a dual bank inverting/ noninverting clock driver built using advanced dual metal CMOS technology. It consists of two banks of drivers, one inverting and one non-inverting. Each bank drives five output buffers from a standard TTL-compatible input. The IDT54/ 74FCT810BT/CT have low output skew, pulse skew and package skew. Inputs are designed with hysteresis circuitry for improved noise immunity. The outputs are designed with TTL output levels and controlled edge rates to reduce signal noise. The part has multiple grounds, minimizing the effects of ground inductance. FUNCTIONAL BLOCK DIAGRAMS PIN CONFIGURATIONS OEA 5 INA OA1-OA5 OEB 5 INB OB1-OB5 VCC 1 20 VCC OA1 2 19 OB1 OA2 3 18 OB2 OA3 4 17 OB3 GND 5 16 GND OA4 6 15 OB4 OA5 7 14 OB5 GND 8 13 GND OEA 9 12 OEB INA 10 11 INB P20-1 D20-1 SO20-2 SO20-7 SO20-8 & E20-1 3103 drw 01 3103 drw 02 OA3 4 GND 5 OA4 6 OA5 7 GND 8 1 OB1 2 VCC 3 VCC OA1 INDEX OA2 DIP/SOIC/SSOP/QSOP/CERPACK TOP VIEW 20 19 L20-2 18 OB2 17 OB3 16 GND 15 OB4 14 OB5 MILITARY AND COMMERCIAL TEMPERATURE RANGES 9.4 GND INB OEB LCC TOP VIEW The IDT logo is a registered trademark of Integrated Device Technology, Inc. 1995 Integrated Device Technology, Inc. INA OEA 9 10 11 12 13 3103 drw 03 OCTOBER 1995 DSC-4646/3 1 IDT54/74FCT810BT/CT FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) PIN DESCRIPTION Pin Names OEA, OEB Description 3-State Output Enable Inputs (Active LOW) INA, INB Clock Inputs OAn, OBn Clock Outputs Symbol Rating VTERM(2) Terminal Voltage with Respect to GND VTERM(3) Terminal Voltage with Respect to GND TA Operating Temperature TBIAS Temperature Under Bias TSTG Storage Temperature I OUT DC Output Current 3103 tbl 01 CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V Typ. 4.5 VOUT = 0V 5.5 Max. Unit 6.0 pF 8.0 NOTE: 1. This parameter is measured at characterization but not tested. pF 3103 lnk 02 Commercial –0.5 to +7.0 Military –0.5 to +7.0 Unit V –0.5 to VCC +0.5 –0.5 to VCC +0.5 V 0 to +70 –55 to +125 °C –55 to +125 –65 to +135 °C –55 to +125 –65 to +150 °C –60 to +120 –60 to +120 mA 3103 lnk 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals. 3. Output and I/O terminals. DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified Commercial: TA = 0°C to +70°C, V CC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10% Symbol VIH Parameter Input HIGH Level Test Conditions(1) Guaranteed Logic HIGH Level Min. 2.0 Typ.(2) — Max. — Unit V VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V II H Input HIGH Current (5) VCC = Max. VI = 2.7V — — ±1 µA II L Input LOW Current (5) VCC = Max. VI = 0.5V — — ±1 µA I OZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1 µA I OZL (3-State Output pins) (5) VO = 0.5V — — ±1 µA — — ±1 µA Current (5) II Input HIGH VIK Clamp Diode Voltage VCC = Min., IIN= –18mA — –0.7 –1.2 V I OS Short Circuit Current VCC = Max.(3) , VO = GND –60 –120 –225 mA VOH Output HIGH Voltage VCC = Min. VIN = VIH or VIL 2.4 3.3 — V 2.0 3.0 — — 0.3 0.55 V — — ±1 µA — 150 — mV — 5 500 µA VOL Output LOW Voltage IOFF Input/Output Power Off Leakage(5) VH Input Hysteresis for all inputs I CCL I CCH I CCZ Quiescent Power Supply Current VCC = Max., VI = VCC (Max.) I OH = –12mA MIL. I OH = –15mA COM'L. I OH = –24mA MIL. I OH = –32mA COM'L.(4) VCC = Min. I OL = 32mA MIL. VIN = VIH or VIL I OL = 48mA COM'L. VCC = 0V, VIN or VO ≤ 4.5V — VCC = Max., VIN = GND or V CC NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25°C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second. 5. The test limit for this parameter is ± 5µA at TA = –55°C. 9.4 3103 lnk 04 2 IDT54/74FCT810BT/CT FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS Test Conditions(1) Min. Typ.(2) Max. Unit — 0.5 2.0 mA VIN = VCC VIN = GND — 60 100 µA/ MHz/bit VCC = Max. Outputs Open fo= 25MHz 50% Duty Cycle OEA = GND, OEB =VCC VIN = VCC VIN = GND — 7.5 13 mA VIN = 3.4V VIN = GND — 7.8 14.0 VCC = Max. Outputs Open fo = 50MHz 50% Duty Cycle OEA = OEB = GND VIN = VCC VIN = GND — 30.0 50.5 (5) VIN = 3.4V VIN = GND — 30.5 52.5 (5) Symbol Parameter ∆ICC Quiescent Power Supply Current TTL Inputs HIGH VCC = Max. VIN = 3.4V(3) ICCD Dynamic Power Supply Current (4) VCC = Max. Outputs Open OEA = OEB = GND 50% Duty Cycle IC Total Power Supply Current (6) NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input; (VIN = 3.4V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fONO) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fO= Output Frequency NO= Number of Outputs at fO All currents are in milliamps and all frequencies are in megahertz. 9.4 3103 tbl 05 3 IDT54/74FCT810BT/CT FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE(3,4) Symbol Parameter tPLH Propagation Delay INA to OAn, INB to OBn tPHL tR Output Rise Time tF IDT54/74FCT810BT IDT54/74FCT810CT Com'l. Com'l. Condition(1) Min.(2) CL = 50pF RL = 500Ω Output Fall Time Mil. Mil. Max. Min.(2) Max. Min.(2) Max. 1.5 4.5 1.5 4.9 1.5 4.3 1.5 4.6 Unit ns — 1.5 — 2.0 — 1.5 — 2.0 ns Min. (2) Max. — 1.5 — 1.5 — 1.5 — 1.5 ns tSK1(o) Output skew (same bank): skew between outputs of same bank and same package (same transition) — 0.5 — 0.9 — 0.3 — 0.7 ns tSK2(o) Output skew (all banks): skew between outputs of all banks of same package (inputs tied together) — 0.7 — 1.1 — 0.6 — 1.0 ns tSK(p) Pulse skew: skew between opposite transitions of same output |(tPHL-tPLH)| — 0.7 — 1.2 — 0.7 — 1.1 ns tSK(t) Package skew: skew between outputs of different packages at same power supply voltage, temperature, package type and speed grade — 1.2 — 1.5 — 1.0 — 1.2 ns tPZL tPZH tPLZ tPHZ Output Enable Time OEA to OAn, OEB to OBn Output Disable Time OEA to OAn, OEB to OBn 1.5 6.0 1.5 6.5 1.5 5.0 1.5 6.0 ns 1.5 6.0 1.5 6.5 1.5 5.0 1.5 6.0 ns 3103 tbl 06 NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested. 4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew. 9.4 4 IDT54/74FCT810BT/CT FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS ENABLE AND DISABLE TIME SWITCH POSITION TEST CIRCUIT FOR ALL OUTPUTS VCC 7.0V Test Disable LOW Enable LOW Disable HIGH Enable HIGH 500Ω V OUT VIN Pulse Generator D.U.T. 50pF RT Switch Closed Open 3103 lnk 07 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 500Ω CL 3103 drw 04 TEST WAVEFORMS PACKAGE DELAY OUTPUT SKEW (SAME BANK) - tSK1(o) 3V 1.5V INPUT INPUT 0V tPLH tPLH1 tPHL1 tPHL 2.0V VOH OUTPUT 1 tSK1(o) 1.5V 0.8V OUTPUT tSK1(o) VOL OUTPUT 2 tPLH2 tF tR 3V 1.5V 0V VOH 1.5V VOL VOH 1.5V VOL tPHL2 3103 drw 05 tSK1(o) = |tPLH2 - tPLH1| or |tPHL2 - tPLH1| OUTPUT SKEW (ALL BANKS) - tSK2(o) INPUT tPLH1 3103 drw 06 PULSE SKEW - tSK(p) 3V 1.5V 0V tPHL1 VOH 1.5V VOL OUTPUT 1 tSK2(o) tSK2(o) tPHL2 INPUT OUTPUT tSK(p) = |tPHL - tPLH| 3103 drw 08 3103 drw 07 PACKAGE SKEW - tSK(t) INPUT ENABLE AND DISABLE TIMES tPD1a tPD1b PACKAGE 1 OUTPUT tSK2(o) PACKAGE 2 OUTPUT VOH 1.5V VOL tPLH2 tSK2(o) = |tPHL2 - tPLH1| or |tPLH2 - tPHL1| tPHL tPLH VOH 1.5V VOL OUTPUT 2 3V 1.5V 0V tSK2(o) 3V 1.5V 0V VOH 1.5V VOL VOH 1.5V VOL tPD2a tPD2b ENABLE Package 1 and Package 2 are same device type and speed grade 3103 drw 09 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: f ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns 3V 1.5V 0V CONTROL INPUT t PZL OUTPUT NORMALLY LOW SWITCH CLOSED t PLZ SWITCH OPEN 3.5V 3.5V 1.5V 0.3V t PZH OUTPUT NORMALLY HIGH tSK(t) = |tPD2a - tPD1a| or |tPD2b- tPD1b| DISABLE VOL t PHZ 0.3V 1.5V 0V VOH 0V 3103 drw 10 9.4 5 IDT54/74FCT810BT/CT FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDTXXFCT Temp. Range XXX Device Type XX Package X Process/ Temperature Range Blank B Commercial Military (-55°C to +125°C) Compliant to MIL-STD-883, Class B P D E L SO PY Q Plastic DIP CERDIP CERPACK Leadless Chip Carrier Small Outline IC Shrink Small Outline IC Quarter-size Small Outline IC 810BT 810CT 54 74 Inverting, Non-Inverting Buffer/Clock driver -55°C to +125°C 0°C to + 70°C 3103 drw 13 9.4 6