Microchip MCP4351T-503E/ML 7/8-bit quad spi digital pot with volatile memory Datasheet

MCP433X/435X
7/8-Bit Quad SPI Digital POT with Volatile Memory
MCP43X1 Quad Potentiometers
TSSOP
P2A
P2W
P2B
VDD
SDO
RESET
NC
P0B
P0W
P0A
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
P3A
P3W
P3B
CS
SCK
SDI
VSS
P1B
P1W
P1A
P2B
P2W
P2A
P3A
P3W
MCP43X1 Quad Potentiometers
4x4 QFN*
20 19 18 17 16
P3B
1
CS
2
SCK
3
SDI
4
VDD
5
NC
11
P0B
9 10
P0A
8
12
P0W
7
6
RESET
13
EP
21
P1A
VSS
15
14 SDO
P1B
• Quad Resistor Network
• Potentiometer or Rheostat Configuration Options
• Resistor Network Resolution:
- 7-bit: 128 Resistors (129 Taps)
- 8-bit: 256 Resistors (257 Taps)
• RAB Resistances Options of:
- 5 k
- 10 k
- 50 k
- 100 k
• Zero Scale to Full Scale Wiper Operation
• Low Wiper Resistance: 75  (typical)
• Low Tempco:
- Absolute (Rheostat): 50 ppm typical
(0°C to 70°C)
- Ratiometric (Potentiometer): 15 ppm typical
• SPI Serial Interface (10 MHz, Modes 0,0 and 1,1):
- High-Speed Read/Writes to wiper registers
• Resistor Network Terminal Disconnect Feature
via Terminal Control (TCON) Register
• Reset Input Pin
• Brown-out Reset Protection (1.5V typical)
• Serial Interface Inactive Current (2.5 µA typical)
• High-Voltage Tolerant Digital Inputs: Up to 12.5V
• Supports Split Rail Applications
• Internal Weak Pull-up on all Digital Inputs
• Wide Operating Voltage:
- 2.7V to 5.5V – Device Characteristics
Specified
- 1.8V to 5.5V – Device Operation
• Wide Bandwidth (-3 dB) Operation:
- 2 MHz (typical) for 5.0 k device
• Extended Temperature Range (-40°C to +125°C)
Package Types (Top View)
P1W
Features
MCP43X2 Quad Rheostat
TSSOP
P3W
P3B
CS
SCK
SDI
VSS
P1B
1
2
3
4
5
6
7
14
13
12
11
10
9
8
P2W
P2B
VDD
SDO
P0B
P0W
P1W
* Includes Exposed Thermal Pad (EP); see Table 3-1.
 2010 Microchip Technology Inc.
DS22242A-page 1
MCP433X/435X
Device Block Diagram
VDD
VSS
Power-up/
Brown-out
Control
Resistor
Network 0
(Pot 0)
CS
SCK
SDI
SDO
SPI Serial
Interface
Module and
Control
Logic
Wiper 0
and TCON0
Register
RESET
P0A
P0W
P0B
P1A
Resistor
Network 1
(Pot 1)
Memory (16x9)
Wiper0 (V)
Wiper1 (V)
Wiper2 (V)
Wiper3 (V)
P1W
Wiper 1
and TCON0
Register
TCON0
TCON1
P1B
P2A
Resistor
Network 2
(Pot 2)
P2W
Wiper 2
and TCON1
Register
P2B
P3A
Resistor
Network 3
(Pot 3)
P3W
Wiper 3
and TCON1
Register
P3B
Resistance (typical)
RAB Options (k)
Wiper
- RW
()
# of Taps
POR Wiper
Setting
WiperLock
Technology
Memory
Type
Wiper
Configuration
Control
Interface
Device
# of POTs
Device Features
VDD
Operating
Range (2)
MCP4331
4 Potentiometer (1) SPI
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
129 1.8V to 5.5V
MCP4332
4 Rheostat
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
129 1.8V to 5.5V
MCP4341
4 Potentiometer (1) SPI
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
129 2.7V to 5.5V
MCP4342
4 Rheostat
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
129 2.7V to 5.5V
Potentiometer (1)
MCP4351
4
MCP4352
4 Rheostat
MCP4361
MCP4362
Note 1:
2:
SPI
SPI
SPI
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
257 1.8V to 5.5V
SPI
RAM
No
Mid-Scale 5.0, 10.0, 50.0, 100.0
75
257 1.8V to 5.5V
4 Potentiometer (1) SPI
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
257 2.7V to 5.5V
4 Rheostat
EE
Yes
NV Wiper 5.0, 10.0, 50.0, 100.0
75
257 2.7V to 5.5V
SPI
Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor).
Analog characteristics only tested from 2.7V to 5.5V unless otherwise noted.
DS22242A-page 2
 2010 Microchip Technology Inc.
MCP433X/435X
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
Voltage on VDD with respect to VSS ..... -0.6V to +7.0V
Voltage on CS, SCK, SDI, SDI/SDO, and
RESET with respect to VSS ..................... -0.6V to 12.5V
Voltage on all other pins (PxA, PxW, PxB and
SDO) with respect to VSS ............... -0.3V to VDD + 0.3V
Input clamp current, IIK
(VI < 0, VI > VDD, VI > VPP ON HV pins) ........... ±20 mA
Output clamp current, IOK
(VO < 0 or VO > VDD) ....................................... ±20 mA
Maximum output current sunk by any Output pin
........................................................................... 25 mA
Maximum output current sourced by any Output pin
........................................................................... 25 mA
Maximum current out of VSS pin ...................... 100 mA
Maximum current into VDD pin ......................... 100 mA
Maximum current into PXA, PXW and PXB pins
±2.5 mA Storage temperature ........... -65°C to +150°C
Ambient temperature with power applied
.......................................................... -40°C to +125°C
Package power dissipation
(TA = +50°C, TJ = +150°C) TSSOP-14 ......... 1000 mW
TSSOP-20......................................................1110 mW
QFN-20 (4x4) ................................................ 2320 mW
Soldering temperature of leads
(10 seconds) .................................................... +300°C
ESD protection on all pins 4 kV (HBM),
................................................................ 300V (MM)
Maximum Junction Temperature (TJ) .............. +150°C
 2010 Microchip Technology Inc.
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification
is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
DS22242A-page 3
MCP433X/435X
AC/DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C  TA  +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Supply Voltage
VDD
2.7
—
5.5
V
1.8
—
2.7
V
Serial Interface only.
VSS
—
12.5V
V
VSS
—
VDD +
8.0V
V
VDD  4.5V The CS pin will be at one
VDD < 4.5V of three input levels
(VIL, VIH or VIHH). (Note 6)
—
—
1.65
V
RAM retention voltage (VRAM) < VBOR
CS, SDI, SDO,
SCK, RESET pin
Voltage Range
VHV
VDD Start Voltage
to ensure Wiper
Reset
VBOR
VDD Rise Rate to
ensure Power-on
Reset
VDDRR
Delay after device
exits the Reset
state
(VDD > VBOR)
TBORD
—
10
20
µs
IDD
—
—
450
µA
Serial Interface Active,
VDD = 5.5V, CS = VIL, SCK @ 5 MHz,
write all 0’s to volatile Wiper 0
(address 0h)
—
2.5
5
µA
Serial Interface Inactive,
CS = VIH, VDD = 5.5V
—
0.55
1
mA
Serial Interface Active,
VDD = 5.5V, CS = VIHH,
SCK @ 5 MHz,
decrement volatile Wiper 0
(address 0h)
Supply Current
(Note 10)
(Note 9)
V/ms
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP43X1 only.
MCP43X2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
DS22242A-page 4
 2010 Microchip Technology Inc.
MCP433X/435X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C  TA  +125°C (extended)
DC Characteristics
Parameters
Resistance
(± 20%)
Resolution
Step Resistance
Nominal
Resistance Match
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym
RAB
RS
(| RABWC RABMEAN |)/
RABMEAN
RW
Nominal
Resistance
Tempco
RAB/T
Ratiometeric
Tempco
VWB/T
Resistance
Tracking
RTRACK
Typ
Max
Units
Conditions
4.0
5
6.0
k
-502 devices(Note 1)
8.0
10
12.0
k
-103 devices(Note 1)
40.0
50
60.0
k
-503 devices(Note 1)
80.0
100
120.0
k
-104 devices(Note 1)
N
(| RBWWC RBWMEAN |)/
RBWMEAN
Wiper Resistance
(Note 3, Note 4)
Min
257
Taps
8-bit
No Missing Codes
129
Taps
7-bit
No Missing Codes
—
RAB/
(256)
—

8-bit
Note 6
—
RAB/
(128)
—

7-bit
Note 6
—
0.2
1.50
%
5 k
MCP43X1 devices only
—
0.2
1.25
%
10 k
—
0.2
1.0
%
50 k
—
0.2
1.0
%
100 k
—
0.25
1.75
%
5 k
—
0.25
1.50
%
10 k
—
0.25
1.25
%
50 k
—
0.25
1.25
%
100 k
—
75
160

VDD = 5.5 V, IW = 2.0 mA, code = 00h
—
75
300

VDD = 2.7 V, IW = 2.0 mA, code = 00h
—
50
—
ppm/°C TA = -20°C to +70°C
—
100
—
ppm/°C TA = -40°C to +85°C
—
150
—
ppm/°C TA = -40°C to +125°C
—
15
—
ppm/°C Code = Mid-scale (80h or 40h)
Section 2.0
Code = Full Scale
ppm/°C See Section 2.0 “Typical Performance
Curves”
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP43X1 only.
MCP43X2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
 2010 Microchip Technology Inc.
DS22242A-page 5
MCP433X/435X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C  TA  +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Resistor Terminal
Input Voltage
Range (Terminals
A, B and W)
VA,VW,VB
Vss
—
VDD
V
Maximum current
through A, W or B
IW
—
—
2.5
mA
Worst case current through wiper when
wiper is either Full Scale or Zero Scale.
(Note 6)
Leakage current
into A, W or B
IWL
—
100
—
nA
MCP43X1 PxA = PxW = PxB = VSS
—
100
—
nA
MCP43X2 PxB = PxW = VSS
Note 5, Note 6
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP43X1 only.
MCP43X2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
DS22242A-page 6
 2010 Microchip Technology Inc.
MCP433X/435X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C  TA  +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Full Scale Error
(MCP43X1 only)
(8-bit code = 100h,
7-bit code = 80h)
VWFSE
-6.0
-0.1
—
LSb
-4.0
-0.1
—
LSb
-3.5
-0.1
—
LSb
-2.0
-0.1
—
LSb
-0.8
-0.1
—
LSb
-0.5
-0.1
—
LSb
-0.5
-0.1
—
LSb
-0.5
-0.1
—
LSb
—
+0.1
+6.0
LSb
Zero Scale Error
(MCP43X1 only)
(8-bit code = 00h,
7-bit code = 00h)
VWZSE
Potentiometer
Integral
Non-linearity
INL
Potentiometer
Differential
Non-linearity
DNL
Bandwidth -3 dB
(See Figure 2-92,
load = 30 pF)
BW
—
+0.1
+3.0
LSb
—
+0.1
+3.5
LSb
—
+0.1
+2.0
LSb
—
+0.1
+0.8
LSb
—
+0.1
+0.5
LSb
—
+0.1
+0.5
LSb
—
+0.1
+0.5
LSb
Conditions
8-bit
3.0V  VDD  5.5V
7-bit
3.0V  VDD  5.5V
8-bit
3.0V  VDD  5.5V
7-bit
3.0V  VDD  5.5V
8-bit
3.0V  VDD  5.5V
7-bit
3.0V  VDD  5.5V
8-bit
3.0V  VDD  5.5V
7-bit
3.0V  VDD  5.5V
5 k
8-bit
3.0V  VDD  5.5V
7-bit
3.0V  VDD  5.5V
10 k
8-bit
3.0V  VDD  5.5V
5 k
10 k
50 k
100 k
7-bit
3.0V  VDD  5.5V
50 k
8-bit
3.0V  VDD  5.5V
7-bit
3.0V  VDD  5.5V
100 k
8-bit
3.0V  VDD  5.5V
7-bit
3.0V  VDD  5.5V
-1
±0.5
+1
LSb
8-bit
-0.5
±0.25
+0.5
LSb
7-bit
-0.5
±0.25
+0.5
LSb
8-bit
-0.25
±0.125
+0.25
LSb
7-bit
—
2
—
MHz
5 k
—
2
—
MHz
—
1
—
MHz
—
1
—
MHz
—
200
—
kHz
—
200
—
kHz
—
100
—
kHz
—
100
—
kHz
10 k
50 k
100 k
3.0V  VDD  5.5V
MCP43X1 devices only
(Note 2)
3.0V  VDD  5.5V
MCP43X1 devices only
(Note 2)
8-bit
Code = 80h
7-bit
Code = 40h
8-bit
Code = 80h
7-bit
Code = 40h
8-bit
Code = 80h
7-bit
Code = 40h
8-bit
Code = 80h
7-bit
Code = 40h
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP43X1 only.
MCP43X2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
 2010 Microchip Technology Inc.
DS22242A-page 7
MCP433X/435X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C  TA  +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Rheostat Integral
Non-linearity
MCP43X1
(Note 4, Note 8)
MCP43X2 devices
only (Note 4)
R-INL
Min
Typ
Max
Units
-1.5
±0.5
+1.5
LSb
-8.25
+4.5
+8.25
LSb
Conditions
5 k
8-bit
3.0V, IW = 480 µA
(Note 7)
Section 2.0
1.8V, IW = 190 µA
-1.125
±0.5
+1.125
LSb
-6.0
+4.5
+6.0
LSb
-1.5
±0.5
+1.5
LSb
-5.5
+2.5
+5.5
LSb
7-bit
5.5V, IW = 900 µA
3.0V, IW = 480 µA
(Note 7)
Section 2.0
1.8V, IW = 190 µA
10 k
8-bit
5.5V, IW = 450 µA
3.0V, IW = 240 µA
(Note 7)
Section 2.0
1.8V, IW = 150 µA
-1.125
±0.5
+1.125
LSb
-4.0
+2.5
+4.0
LSb
-1.5
±0.5
+1.5
LSb
-2.0
+1
+2.0
LSb
7-bit
5.5V, IW = 450 µA
3.0V, IW = 240 µA
(Note 7)
Section 2.0
1.8V, IW = 150 µA
50 k
8-bit
5.5V, IW = 90 µA
3.0V, IW = 48 µA
(Note 7)
Section 2.0
1.8V, IW = 30 µA
-1.125
±0.5
+1.125
LSb
-1.5
+1
+1.5
LSb
-1.0
±0.5
+1.0
LSb
-1.5
+0.25
+1.5
LSb
7-bit
5.5V, IW = 90 µA
3.0V, IW = 48 µA
(Note 7)
Section 2.0
1.8V, IW = 30 µA
100 k
8-bit
5.5V, IW = 45 µA
3.0V, IW = 24 µA
(Note 7)
Section 2.0
1.8V, IW = 15 µA
-0.8
±0.5
+0.8
LSb
-1.125
+0.25
+1.125
LSb
Section 2.0
5.5V, IW = 900 µA
7-bit
5.5V, IW = 45 µA
3.0V, IW = 24 µA
(Note 7)
1.8V, IW = 15 µA
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP43X1 only.
MCP43X2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
DS22242A-page 8
 2010 Microchip Technology Inc.
MCP433X/435X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C  TA  +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Rheostat
Differential
Non-linearity
MCP43X1
(Note 4, Note 8)
MCP43X2 devices
only
(Note 4)
R-DNL
Min
Typ
Max
Units
-0.5
-1.0
±0.25
+0.5
LSb
+0.5
+1.0
LSb
Conditions
5 k
8-bit
3.0V, IW = 480 µA
(Note 7)
Section 2.0
1.8V, IW = 190 µA
-0.375
±0.25
+0.375
LSb
-0.75
+0.5
+0.75
LSb
-0.5
±0.25
+0.5
LSb
-1.0
+0.25
+1.0
LSb
7-bit
5.5V, IW = 900 µA
3.0V, IW = 480 µA
(Note 7)
Section 2.0
1.8V, IW = 190 µA
10 k
8-bit
5.5V, IW = 450 µA
3.0V, IW = 240 µA
(Note 7)
Section 2.0
1.8V, IW = 150 µA
-0.375
±0.25
+0.375
LSb
-0.75
+0.5
+0.75
LSb
-0.5
±0.25
+0.5
LSb
-0.5
±0.25
+0.5
LSb
7-bit
5.5V, IW = 450 µA
3.0V, IW = 240 µA
(Note 7)
Section 2.0
1.8V, IW = 150 µA
50 k
8-bit
5.5V, IW = 90 µA
3.0V, IW = 48 µA
(Note 7)
Section 2.0
1.8V, IW = 30 µA
-0.375
±0.25
+0.375
LSb
-0.375
±0.25
+0.375
LSb
-0.5
±0.25
+0.5
LSb
-0.5
±0.25
+0.5
LSb
7-bit
5.5V, IW = 90 µA
3.0V, IW = 48 µA
(Note 7)
Section 2.0
1.8V, IW = 30 µA
100 k
8-bit
5.5V, IW = 45 µA
3.0V, IW = 24 µA
(Note 7)
Section 2.0
1.8V, IW = 15 µA
-0.375
±0.25
+0.375
LSb
-0.375
±0.25
+0.375
LSb
Section 2.0
5.5V, IW = 900 µA
7-bit
5.5V, IW = 45 µA
3.0V, IW = 24 µA
(Note 7)
1.8V, IW = 30 µA
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP43X1 only.
MCP43X2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
 2010 Microchip Technology Inc.
DS22242A-page 9
MCP433X/435X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C  TA  +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Capacitance (PA)
CAW
—
75
—
pF
f =1 MHz, Code = Full Scale
Capacitance (Pw)
CW
—
120
—
pF
f =1 MHz, Code = Full Scale
Capacitance (PB)
CBW
—
75
—
pF
f =1 MHz, Code = Full Scale
—
V
2.7V  VDD  5.5V
(Allows 2.7V Digital VDD with
5V Analog VDD)
1.8V  VDD  2.7V
Digital Inputs/Outputs (CS, SDI, SDO, SCK, WP, RESET)
0.45 VD
—
Schmitt Trigger
High Input
Threshold
VIH
0.5 VDD
—
—
V
Schmitt Trigger
Low Input
Threshold
VIL
—
—
0.2VDD
V
Hysteresis of
Schmitt Trigger
Inputs
VHYS
—
0.1VDD
—
V
High Voltage Input
Entry Voltage
VIHH
8.5
—
12.5 (6)
V
High Voltage Input
Exit Voltage
VIHH
—
—
VDD +
0.8V
V
High Voltage Limit
VMAX
—
—
12.5 (6)
V
Pin can tolerate VMAX or less.
Output Low
Voltage (SDO)
VOL
VSS
—
0.3VDD
V
IOL = 5 mA, VDD = 5.5V
VSS
—
0.3VDD
V
IOL = 1 mA, VDD = 1.8V
Output High
Voltage (SDO)
VOH
0.7VDD
—
VDD
V
IOH = -2.5 mA, VDD = 5.5V
0.7VDD
—
VDD
V
IOL = -1 mA, VDD = 1.8V
D
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP43X1 only.
MCP43X2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
DS22242A-page 10
 2010 Microchip Technology Inc.
MCP433X/435X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C  TA  +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Weak Pull-up
Current
IPU
—
—
1.75
mA
Internal VDD pull-up, VIHH pull-down,
VDD = 5.5V, VCS = 12.5V
—
170
—
µA
CS pin, VDD = 5.5V, VCS = 3V
CS Pull-up/
Pull-down
Resistance
RCS
—
16
—
k
VDD = 5.5V, VCS = 3V
RESET Pull-up
Resistance
RRESET
—
16
—
k
VDD = 5.5V, VRESET = 0V
Input Leakage
Current
IIL
-1
—
1
µA
VIN = VDD (all pins) and
VIN = VSS (all pins except RESET)
CIN, COUT
—
10
—
pF
fC = 20 MHz
0h
—
1FFh
hex
8-bit device
—
1FFh
hex
7-bit device
hex
All terminals connected
Pin Capacitance
Conditions
RAM (Wiper, TCON) Value
Value Range
N
0h
TCON POR/BOR
Setting
Wiper POR/BOR
Setting
1FF
N
080h
hex
8-bit
040h
hex
7-bit
Power Requirements
Power Supply
Sensitivity
(MCP43X1)
PSS
—
0.0015
0.0035
%/%
8-bit
VDD = 2.7V to 5.5V,
VA = 2.7V, Code = 80h
—
0.0015
0.0035
%/%
7-bit
VDD = 2.7V to 5.5V,
VA = 2.7V, Code = 40h
Note 1:
2:
3:
4:
5:
6:
7:
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS.
MCP43X1 only.
MCP43X2 only, includes VWZSE and VWFSE.
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design.
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP43X1 is externally connected to match the configurations of the MCP43X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
 2010 Microchip Technology Inc.
DS22242A-page 11
MCP433X/435X
1.1
SPI Mode Timing Waveforms and Requirements
RESET
tRST
tRSTD
SCK
Wx
FIGURE 1-1:
TABLE 1-1:
Reset Waveforms.
RESET TIMING
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C  TA  +125°C (extended)
Timing Characteristics
Parameters
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym
Min
Typ
Max
Units
RESET pulse width
tRST
50
—
—
ns
RESET rising edge
normal mode (Wiper
driving and SPI
interface operational)
tRSTD
—
—
20
ns
DS22242A-page 12
Conditions
 2010 Microchip Technology Inc.
MCP433X/435X
VIHH
VIH
CS
VIH
VIL
84
70
72
SCK
83
71
78
79
80
MSb
SDO
LSb
BIT6 - - - - - -1
77
75, 76
SDI
MSb IN
BIT6 - - - -1
LSb IN
74
73
FIGURE 1-2:
TABLE 1-2:
#
SPI Timing Waveform (Mode = 11).
SPI REQUIREMENTS (MODE = 11)
Characteristic
SCK Input Frequency
70
CS Active (VIL or VIHH) to SCK input
71
SCK input high time
72
73
SCK input low time
Setup time of SDI input to SCK edge
Symbol
Min
FSCK
—
TcsA2scH
TscH
TscL
TDIV2scH
Max Units
10
MHz VDD = 2.7V to 5.5V
—
1
MHz VDD = 1.8V to 2.7V
60
—
ns
45
—
ns
VDD = 2.7V to 5.5V
500
—
ns
VDD = 1.8V to 2.7V
45
—
ns
VDD = 2.7V to 5.5V
500
—
ns
VDD = 1.8V to 2.7V
10
—
ns
VDD = 2.7V to 5.5V
20
—
ns
VDD = 1.8V to 2.7V
74
Hold time of SDI input from SCK edge
TscH2DIL
20
—
ns
77
CS Inactive (VIH) to SDO output high-impedance
TcsH2DOZ
—
50
ns
80
SDO data output valid after SCK edge
TscL2DOV
—
83
CS Inactive (VIH) after SCK edge
TscH2csI
100
Hold time of CS Inactive (VIH) to
CS Active (VIL or VIHH)
Note 1:
TcsA2csI
50
Note 1
70
ns
VDD = 2.7V to 5.5V
170
ns
VDD = 1.8V to 2.7V
ns
VDD = 2.7V to 5.5V
ms
VDD = 1.8V to 2.7V
—
1
84
Conditions
—
ns
This specification by design.
 2010 Microchip Technology Inc.
DS22242A-page 13
MCP433X/435X
VIH
VIHH
VIH
82
CS
VIL
84
70
SCK
83
71
MSb
SDO
BIT6 - - - - - -1
LSb
75, 76
73
SDI
80
72
MSb IN
77
BIT6 - - - -1
LSb IN
74
FIGURE 1-3:
TABLE 1-3:
#
SPI Timing Waveform (Mode = 00).
SPI REQUIREMENTS (MODE = 00)
Characteristic
SCK Input Frequency
Symbol
FSCK
Min
Max Units
Conditions
—
10
MHz VDD = 2.7V to 5.5V
—
1
MHz VDD = 1.8V to 2.7V
70
CS Active (VIL or VIHH) to SCK input
TcsA2scH
60
—
ns
71
SCK input high time
TscH
45
—
ns
72
SCK input low time
TscL
500
—
ns
VDD = 1.8V to 2.7V
73
Setup time of SDI input to SCK edge
TDIV2scH
10
—
ns
VDD = 2.7V to 5.5V
20
—
ns
VDD = 1.8V to 2.7V
74
Hold time of SDI input from SCK edge
TscH2DIL
20
—
ns
77
CS Inactive (VIH) to SDO output high-impedance
TcsH2DOZ
—
50
ns
Note 1
80
SDO data output valid after SCK edge
TscL2DOV
—
70
ns
VDD = 2.7V to 5.5V
170
ns
VDD = 1.8V to 2.7V
82
SDO data output valid after
CS Active (VIL or VIHH)
TssL2doV
—
85
ns
83
CS Inactive (VIH) after SCK edge
TscH2csI
100
—
500
—
ns
VDD = 1.8V to 2.7V
45
—
ns
VDD = 2.7V to 5.5V
1
84
Hold time of CS Inactive (VIH) to
CS Active (VIL or VIHH)
Note 1:
TcsA2csI
VDD = 2.7V to 5.5V
50
—
ns
VDD = 2.7V to 5.5V
ms
VDD = 1.8V to 2.7V
ns
This specification by design.
DS22242A-page 14
 2010 Microchip Technology Inc.
MCP433X/435X
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 14L-TSSOP
JA
—
100
—
°C/W
Thermal Resistance, 20L-QFN
JA
—
43
—
°C/W
Thermal Resistance, 20L-TSSOP
JA
—
90
—
°C/W
Conditions
Temperature Ranges
Thermal Package Resistances
 2010 Microchip Technology Inc.
DS22242A-page 15
MCP433X/435X
NOTES:
DS22242A-page 16
 2010 Microchip Technology Inc.
MCP433X/435X
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
250
2.7V -40°C
2.7V 25°C
2.7V 85°C
2.7V 125°C
5.5V -40°C
5.5V 25°C
5.5V 85°C
5.5V 125°C
200
ICS
150
100
50
RCS
0
2.00
4.00
6.00
8.00
fSCK (MHz)
10.00
2
12.00
FIGURE 2-1:
Device Current (IDD) vs. SPI
Frequency (fSCK) and Ambient Temperature
(VDD = 2.7V and 5.5V).
3
4
5
6
7
VCS (V)
8
9
10
FIGURE 2-3:
CS Pull-up/Pull-down
Resistance (RCS) and Current (ICS) vs. CS Input
Voltage (VCS) (VDD = 5.5V).
3.0
12
2.5
CS VPP Threshold (V)
Standby Current (Istby) (μA)
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
ICS (μA)
700
650
600
550
500
450
400
350
300
250
200
150
100
50
0
0.00
RCS (kOhms)
Operating Current (IDD) (μA)
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
5.5V
2.0
1.5
1.0
2.7V
0.5
0.0
10
5.5V Entry
8
2.7V Entry
5.5V Exit
6
4
2.7V Exit
2
0
-40
25
85
125
Ambient Temperature (°C)
FIGURE 2-2:
Device Current (ISHDN) and
VDD. (CS = VDD) vs. Ambient Temperature.
 2010 Microchip Technology Inc.
-40
-20
0
20
40
60
80 100
Ambient Temperature (°C)
120
FIGURE 2-4:
CS High Input Entry/Exit
Threshold vs. Ambient Temperature and VDD.
DS22242A-page 17
MCP433X/435X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
0.1
80
0
60
-0.1
20
0
100
-0.2
RW
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
32
-40C Rw
-40C INL
-40C DNL
260
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
INL
220
0.1
180
0
140
RW
100
-0.1
125°C
60
-40°C
20
0
32
25°C
-0.2
85°C
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
0.5
0.2
1500
0.1
0
1000
DNL
RW
0
0
Note:
64
128
192
Wiper Setting (decimal)
-0.2
FIGURE 2-7:
5 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
-0.75
RW
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
6
INL
4
180
2
140
RW
100
0
-40°C
60
125°C
20
0
32
85°C
25°C
DNL
-2
64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-9:
5 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V, IW = 480 µA).
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
118
98
INL
78
1500
58
1000
38
500
RW
-0.3
256
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
DS22242A-page 18
DNL
-40°C
-1.25
64 96 128 160 192 224 256
Wiper Setting (decimal)
2000
-0.1
500
32
2500
0.4
0.3
INL
2000
125C Rw
125C INL
125C DNL
Error (LSb)
Wiper Resistance (RW)
(ohms)
-40C Rw
-40C INL
-40C DNL
85°C 25°C
FIGURE 2-8:
5 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V, IW = 900 µA).
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-6:
5 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
2500
40
220
DNL
0.75
-0.25
260
0.2
1.25
60
300
0.3
125C Rw
125C INL
125C DNL
0.25
0
Error (LSb)
Wiper Resistance (RW)
(ohms)
300
85C Rw
85C INL
85C DNL
80
20
FIGURE 2-5:
5 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
25C Rw
25C INL
25C DNL
INL
125°C
Wiper Resistance (RW)
(ohms)
125°C
-40°C 25°C
85°C
-40C Rw
-40C INL
-40C DNL
Error (LSb)
0.2
INL
DNL
40
120
Error (LSb)
0.3
125C Rw
125C INL
125C DNL
DNL
0
0
Note:
64
128
192
Wiper Setting (decimal)
Error (LSb)
85C Rw
85C INL
85C DNL
Wiper Resistance (RW)
(ohms)
100
25C Rw
25C INL
25C DNL
Wiper Resistance (RW)
(ohms)
-40C Rw
-40C INL
-40C DNL
Error (LSb)
Wiper Resistance (RW)
(ohms)
120
18
-2
256
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-10:
5 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V, IW = 260 µA).
 2010 Microchip Technology Inc.
MCP433X/435X
5300
6000
5250
5000
Resistance ()
Nominal Resistance (RAB)
(Ohms)
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
2.7V
5200
5150
5.5V
4000
3000
2000
-40C
+25C
+85C
+125C
1.8V
5100
1000
5050
-40
0
40
80
Ambient Temperature (°C)
0
120
FIGURE 2-11:
5 k – Nominal Resistance
(RAB) () vs. Ambient Temperature and VDD.
0
32
64
96
128
160
Wiper Code
192
224
256
FIGURE 2-12:
5 k – RWB () vs. Wiper
Setting and Ambient Temperature
(VDD = 5.5V, IW = 190 µA).
6000
Resistance ()
5000
4000
3000
2000
-40C
+25C
+85C
+125C
1000
0
0
32
64
96
128
160
Wiper Code
192
224
256
FIGURE 2-13:
5 k – RWB () vs. Wiper
Setting and Ambient Temperature
(VDD = 3.0V, IW = 190 µA).
7000
Resistance ()
6000
5000
4000
3000
-40C
+25C
+85C
+125C
2000
1000
0
0
Note:
32
64
96
128
160
Wiper Code
192
224
256
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-14:
5 k – RWB () vs. Wiper
Setting and Ambient Temperature
(VDD = 1.8V, IW = 190 µA).
 2010 Microchip Technology Inc.
DS22242A-page 19
MCP433X/435X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
2.50%
CH0
CH2
52
50
PPM / °C
1.50%
Error %
54
-40C
+25C
+85C
+125C
0.50%
-0.50%
CH1
CH3
48
46
44
-1.50%
42
40
-2.50%
0
32
64
96
128
160
192
224
0
256
32
64
96 128 160
Wiper Code
Wiper Code
FIGURE 2-15:
5 k – Worst Case RBW
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 5.5V, IW = 190 µA).
2.50%
256
100
CH0
CH2
95
90
PPM / °C
Error %
224
FIGURE 2-18:
5 k – RWB PPM/°C vs.
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n,
-40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 5.5V, IW = 190 µA).
-40C
+25C
+85C
+125C
1.50%
192
0.50%
-0.50%
CH1
CH3
85
80
75
70
-1.50%
65
60
-2.50%
0
32
64
96
128
160
192
224
0
256
32
64
Wiper Code
FIGURE 2-16:
5 k – Worst Case RBW
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 3.0V, IW = 190 µA).
96
128 160
Wiper Code
192
224
256
FIGURE 2-19:
5 k – RWB PPM/°C vs.
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n,
-40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 3.0V, IW = 190 µA).
500
2.00%
1.00%
0
0.00%
PPM / °C
Error %
-1.00%
-2.00%
-3.00%
-4.00%
-40C
+25C
+85C
+125C
-5.00%
-6.00%
-7.00%
0
32
64
96
128
160
192
224
-500
-1000
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-17:
5 k – Worst Case RBW
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 1.8V, IW = 190 µA).
DS22242A-page 20
CH1
CH3
-2000
256
0
Wiper Code
Note:
CH0
CH2
-1500
Note:
32
64
96
128 160
Wiper Code
192
224
256
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-20:
5 k – RWB PPM/°C vs.
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n,
-40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 1.8V, IW = 190 µA).
 2010 Microchip Technology Inc.
MCP433X/435X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-21:
5 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-24:
5 k – Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-22:
5 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-25:
5 k – Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-23:
5 k – Power-Up Wiper
Response Time (20 ms/Div).
 2010 Microchip Technology Inc.
DS22242A-page 21
MCP433X/435X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
0.1
80
0
60
-0.1
25°C -40°C
125°C 85°C
-0.2
RW
20
0
100
-0.3
256
64
128
192
Wiper Setting (decimal)
-40C Rw
-40C INL
-40C DNL
260
220
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
INL
DNL
0.1
180
0
140
100
60
25°C
125°C 85°C
20
0
32
-0.2
-40°C
85C Rw
85C INL
85C DNL
3000
125C Rw
125C INL
125C DNL
INL
2500
0.4
0.3
0.2
2000
DNL
0.1
1500
0
1000
-0.1
500
RW
0
0
Note:
64
128
192
Wiper Setting (decimal)
-0.2
FIGURE 2-28:
10 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
DS22242A-page 22
260
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
4
3
INL
220
2
180
1
140
0
100
-40°C
60
0
DNL
RW
-1
-2
256
64
128
192
Wiper Setting (decimal)
FIGURE 2-30:
10 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V, IW = 240 µA).
-40C Rw
125C Rw
85C INL
25C DNL
3500
3000
25C Rw
-40C INL
125C INL
85C DNL
INL
2000
1500
1000
RW
500
DNL
0
0
Note:
98
88
78
68
58
48
38
28
18
8
-2
256
85C Rw
25C INL
-40C DNL
125C DNL
2500
-0.3
256
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
-0.5
DNL
-1
64 96 128 160 192 224 256
Wiper Setting (decimal)
-40C Rw
-40C INL
-40C DNL
4000
0.5
Error (LSb)
Wiper Resistance
(RW)(ohms)
3500
25C Rw
25C INL
25C DNL
RW
-40°C
20
0.6
-40C Rw
-40C INL
-40C DNL
32
85°C 25°C
125°C 85°C 25°C
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-27:
10 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
4000
40
300
-0.1
RW
0
60
FIGURE 2-29:
10 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V, IW = 450 µA).
0.3
0.2
1
125C Rw
125C INL
125C DNL
80
0
Error (LSb)
Wiper Resistance (RW)
(ohms)
300
85C Rw
85C INL
85C DNL
0.5
20
FIGURE 2-26:
10 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
25C Rw
25C INL
25C DNL
INL
125°C
Wiper Resistance (RW)
(ohms)
40
-40C Rw
-40C INL
-40C DNL
Error (LSb)
0.2
INL
DNL
120
Error (LSb)
0.3
125C Rw
125C INL
125C DNL
64
128
192
Wiper Setting (decimal)
Error (LSb)
85C Rw
85C INL
85C DNL
Wiper Resistance (RW)
(ohms)
100
25C Rw
25C INL
25C DNL
Wiper Resistance (RW)
(ohms)
-40C Rw
-40C INL
-40C DNL
Error (LSb)
Wiper Resistance (RW)
(ohms)
120
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-31:
10 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V, IW = 125 µA).
 2010 Microchip Technology Inc.
MCP433X/435X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
12000
10250
10000
10200
Resistance ()
Nominal Resistance (RAB)
(Ohms)
10300
10150
10100
2.7V
10050
10000
5.5V
9950
1.8V
9850
0
40
80
Ambient Temperature (°C)
6000
4000
-40C
+25C
+85C
+125C
2000
9900
-40
8000
0
120
FIGURE 2-32:
10 k – Nominal Resistance
(RAB) () vs. Ambient Temperature and VDD.
0
32
64
96
128 160
Wiper Code
192
224
256
FIGURE 2-33:
10 k – RWB () vs. Wiper
Setting and Ambient Temperature
(VDD = 5.5V, IW = 150 µA).
12000
Resistance ()
10000
8000
6000
4000
-40C
+25C
+85C
+125C
2000
0
0
32
64
96
128 160
Wiper Code
192
224
256
FIGURE 2-34:
10 k – RWB () vs. Wiper
Setting and Ambient Temperature
(VDD = 3.0V, IW = 150 µA).
12000
Resistance ()
10000
8000
6000
4000
-40C
+25C
+85C
+125C
2000
0
0
Note:
32
64
96
128 160
Wiper Code
192
224
256
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-35:
10 k – RWB () vs. Wiper
Setting and Ambient Temperature
(VDD = 1.8V, IW = 150 µA).
 2010 Microchip Technology Inc.
DS22242A-page 23
MCP433X/435X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
1.50%
-40C
+85C
1.00%
45
40
PPM / °C
0.50%
Error %
50
+25C
+125C
0.00%
-0.50%
35
30
25
20
-1.00%
CH0
CH2
15
10
-1.50%
0
32
64
96
128
160
192
224
0
256
32
64
Wiper Code
FIGURE 2-36:
10 k – Worst Case RBW
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 5.5V, IW = 150 µA).
1.50%
-40C
+85C
1.00%
224
256
55
50
PPM / °C
Error %
192
60
0.00%
-0.50%
45
40
35
30
-1.00%
CH0
CH2
25
CH1
CH3
20
-1.50%
0
32
64
96
128
160
192
224
0
256
32
64
Wiper Code
FIGURE 2-37:
10 k – Worst Case RBW
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 3.0V, IW = 150 µA).
1.50%
-40C
+85C
1.00%
96 128 160
Wiper Code
192
224
256
FIGURE 2-40:
10 k – RWB PPM/°C vs.
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n,
-40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 3.0V, IW = 150 µA).
200
+25C
+125C
0
-200
PPM / °C
0.50%
Error %
96 128 160
Wiper Code
FIGURE 2-39:
10 k – RWB PPM/°C vs.
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n,
-40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 5.5V, IW = 150 µA).
+25C
+125C
0.50%
0.00%
-0.50%
-400
-600
-800
-1000
-1.00%
CH0
CH2
-1200
CH1
CH3
-1400
-1.50%
0
32
64
96
128
160
192
224
0
256
Wiper Code
Note:
CH1
CH3
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-38:
10 k – Worst Case RBW
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 1.8V, IW = 150 µA).
DS22242A-page 24
Note:
32
64
96 128 160 192 224 256
Wiper Code
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-41:
10 k – RWB PPM/°C vs.
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n,
-40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 1.8V, IW = 150 µA).
 2010 Microchip Technology Inc.
MCP433X/435X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-42:
10 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-44:
10 k – Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-43:
10 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-45:
10 k – Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
 2010 Microchip Technology Inc.
DS22242A-page 25
MCP433X/435X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
0.1
80
0
60
-0.1
40
25°C
85°C
125°C
20
0
-40°C
100
-0.2
RW
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
32
260
220
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
0.1
180
0
140
-0.1
RW
100
-0.2
-40°C
60
-0.1
40
32
85C Rw
85C INL
85C DNL
DNL
INL
RW
0
Note:
25C Rw
25C INL
25C DNL
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
256
125C Rw
125C INL
125C DNL
64
128
192
Wiper Setting (decimal)
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-48:
50 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
DS22242A-page 26
RW
-0.2
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
1
125C Rw
125C INL
125C DNL
0.75
INL
0.5
DNL
0.25
180
0
140
-0.25
RW
100
-0.5
-40°C
60
125°C
Error (LSb)
Wiper Resistance (RW)
(ohms)
-40C Rw
-40C INL
-40C DNL
-40°C
FIGURE 2-49:
50 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V, IW = 90 µA).
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-47:
50 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
15000
14000
13000
12000
11000
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
32
0
32
-0.75
85°C 25°C
20
64
-1
96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-50:
50 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V, IW = 48 µA).
15000
14000
13000
12000
11000
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
-40C Rw
-40C INL
-40C DNL
Wiper Resistance (Rw)
(ohms)
0
85°C 25°C
125°C
125°C 85°C 25°C
20
0.1
0
220
INL
DNL
0.2
60
260
0.2
0.3
125C Rw
125C INL
125C DNL
DNL
300
0.3
125C Rw
125C INL
125C DNL
85C Rw
85C INL
85C DNL
80
0
Error (LSb)
Wiper Resistance (RW)
(ohms)
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
INL
20
FIGURE 2-46:
50 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
300
-40C Rw
-40C INL
-40C DNL
Error (LSb)
0.2
INL
DNL
120
Error (LSb)
0.3
125C Rw
125C INL
125C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
RW
INL
DNL
0
64
128
192
78.5
73.5
68.5
63.5
58.5
53.5
48.5
43.5
38.5
33.5
28.5
23.5
18.5
13.5
8.5
3.5
-1.5
Error (LSb)
85C Rw
85C INL
85C DNL
Wiper Resistance (RW)
(ohms)
100
25C Rw
25C INL
25C DNL
Wiper Resistance (RW)
(ohms)
-40C Rw
-40C INL
-40C DNL
Error (LSb)
Wiper Resistance (RW)
(ohms)
120
256
Wiper Setting (decimal)
Note:
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-51:
50 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V, IW = 25 µA).
 2010 Microchip Technology Inc.
MCP433X/435X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
60000
52000
50000
51500
1.8V
Resistance ()
Nominal Resistance (RAB)
(Ohms)
52500
51000
50500
50000
2.7V
49500
0
40
80
Ambient Temperature (°C)
30000
20000
-40C
+25C
+85C
+125C
10000
5.5V
49000
-40
40000
0
120
FIGURE 2-52:
50 k – Nominal Resistance
(RAB) () vs. Ambient Temperature and VDD.
0
32
64
96
128 160
Wiper Code
192
224
256
FIGURE 2-53:
50 k – RWB () vs. Wiper
Setting and Ambient Temperature
(VDD = 5.5V, IW = 90 µA).
60000
Resistance ()
50000
40000
30000
-40C
+25C
+85C
+125C
20000
10000
0
0
32
64
96
128 160
Wiper Code
192
224
256
FIGURE 2-54:
50 k – RWB () vs. Wiper
Setting and Ambient Temperature
(VDD = 3.0V, IW = 48 µA).
60000
Resistance ()
50000
40000
30000
-40C
+25C
+85C
+125C
20000
10000
0
0
Note:
32
64
96
128 160
Wiper Code
192
224
256
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-55:
50 k – RWB () vs. Wiper
Setting and Ambient Temperature
(VDD = 1.8V, IW = 30 µA).
 2010 Microchip Technology Inc.
DS22242A-page 27
MCP433X/435X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
7.00%
-40C
+85C
6.00%
+25C
+125C
4.00%
PPM / °C
Error %
5.00%
3.00%
2.00%
1.00%
0.00%
-1.00%
0
32
64
96
128
160
192
224
7
6
5
4
3
2
1
0
-1
-2
-3
CH0
CH2
0
256
CH1
CH3
32
64
96 128 160
Wiper Code
Wiper Code
FIGURE 2-56:
50 k – Worst Case RBW
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 5.5V, IW = 90 µA).
+25C
+125C
10
8
PPM / °C
2.00%
Error %
256
12
-40C
+85C
3.00%
1.00%
0.00%
6
4
2
CH0
CH2
0
-1.00%
CH1
CH3
-2
-2.00%
0
32
64
96
128
160
192
224
0
256
32
64
Wiper Code
FIGURE 2-57:
50 k – Worst Case RBW
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 3.0V, IW = 48 µA).
3.50%
-40C
+85C
0.50%
224
256
0
-200
-400
-600
-800
-1000
-0.50%
192
200
+25C
+125C
1.50%
96 128 160
Wiper Code
FIGURE 2-60:
50 k – RWB PPM/°C vs.
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n,
-40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 3.0V, IW = 48 µA).
PPM / °C
2.50%
Error %
224
FIGURE 2-59:
50 k – RWB PPM/°C vs.
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n,
-40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 5.5V, IW = 90 µA).
4.00%
CH0
CH2
-1200
CH1
CH3
-1400
-1.50%
0
32
64
96
128
160
192
224
0
256
Wiper Code
Note:
192
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-58:
50 k – Worst Case RBW
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 1.8V, IW = 30 µA).
DS22242A-page 28
Note:
32
64
96 128 160 192 224 256
Wiper Code
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-61:
50 k – RWB PPM/°C vs.
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n,
-40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 1.8V, IW = 30 µA).
 2010 Microchip Technology Inc.
MCP433X/435X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-62:
50 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-64:
50 k – Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-63:
50 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-65:
50 k – Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
 2010 Microchip Technology Inc.
DS22242A-page 29
MCP433X/435X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
DNL
0
60
-0.1
40
25°C -40°C
-40C Rw
-40C INL
-40C DNL
100
0.1
INL
80
120
RW
-0.2
64 96 128 160 192 224 256
Wiper Setting (decimal)
-40C Rw
-40C INL
-40C DNL
260
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
-0.1
40
-40°C
220
DNL
260
0
140
RW
60
-0.1
-40°C
-0.15
125°C 85°C 25°C
20
0
32
0.25
0.05
15000
-0.05
10000
-0.15
5000
RW
INL
0
Note:
-0.25
64
128
192
Wiper Setting (decimal)
DS22242A-page 30
-0.2
RW
100
60
-0.4
-40°C
125°C 85°C 25°C
32
-0.6
64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-70:
100 k Rheo Mode – RW
(), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V, IW = 24 µA).
-40C Rw
-40C INL
-40C DNL
25000
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
20000
15000
10000
5000
0
256
FIGURE 2-68:
100 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
0.4
0.2
DNL
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
0.6
0
-0.35
0
125C Rw
125C INL
125C DNL
140
0.35
0.15
DNL
20000
125C Rw
125C INL
125C DNL
85C Rw
85C INL
85C DNL
DNL
0
Error (LSb)
Wiper Resistance (RW)
(ohms)
25000
85C Rw
85C INL
85C DNL
25C Rw
25C INL
25C DNL
INL
20
FIGURE 2-67:
100 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
25C Rw
25C INL
25C DNL
-40C Rw
-40C INL
-40C DNL
180
-0.2
64 96 128 160 192 224 256
Wiper Setting (decimal)
-40C Rw
-40C INL
-40C DNL
-0.3
64 96 128 160 192 224 256
Wiper Setting (decimal)
220
-0.05
100
32
-0.2
FIGURE 2-69:
100 k Rheo Mode – RW
(), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V, IW = 45 µA).
0.15
0.05
180
RW
125°C 85°C 25°C
300
0.1
INL
0.1
0
0.2
Error (LSb)
Wiper Resistance (RW)
(ohms)
300
0.2
60
0
FIGURE 2-66:
100 k Pot Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
0.3
125C Rw
125C INL
125C DNL
DNL
80
20
Wiper Resistance (Rw)
(ohms)
32
Wiper Resistance (RW)
(ohms)
0
85C Rw
85C INL
85C DNL
INL
125°C 85°C
20
25C Rw
25C INL
25C DNL
Error (LSb)
0.2
125C Rw
125C INL
125C DNL
Error (LSb)
85C Rw
85C INL
85C DNL
0
Note:
64
128
192
Wiper Setting (decimal)
59
54
49
RW
44
39
INL
34
29
24
19
14
9
4
-1
256
125C Rw
125C INL
125C DNL
Error (LSb)
100
25C Rw
25C INL
25C DNL
Wiper Resistance (RW)
(ohms)
-40C Rw
-40C INL
-40C DNL
Error (LSb)
Wiper Resistance (RW)
(ohms)
120
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-71:
100 k Rheo Mode – RW
(), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V, IW = 10 µA).
 2010 Microchip Technology Inc.
MCP433X/435X
103500
103000
102500
102000
101500
101000
100500
100000
99500
99000
98500
120000
100000
Resistance ()
Nominal Resistance (RAB)
(Ohms)
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
1.8V
2.7V
0
40
80
Ambient Temperature (°C)
60000
-40C
+25C
+85C
+125C
40000
20000
5.5V
-40
80000
0
120
FIGURE 2-72:
100 k – Nominal
Resistance (RAB) () vs. Ambient Temperature
and VDD .
0
32
64
96
128 160
Wiper Code
192
224
256
FIGURE 2-73:
100 k – RWB () vs. Wiper
Setting and Ambient Temperature
(VDD = 5.5V, IW = 45 µA).
120000
Resistance ()
100000
80000
60000
40000
-40C
+25C
+85C
+125C
20000
0
0
32
64
96
128 160
Wiper Code
192
224
256
FIGURE 2-74:
100 k – RWB () vs. Wiper
Setting and Ambient Temperature
(VDD = 3.0V, IW = 24 µA).
120000
Resistance ()
100000
80000
60000
40000
-40C
+25C
+85C
+125C
20000
0
0
Note:
32
64
96
128 160
Wiper Code
192
224
256
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-75:
100 k – RWB () vs. Wiper
Setting and Ambient Temperature
(VDD = 1.8V, IW = 15 µA).
 2010 Microchip Technology Inc.
DS22242A-page 31
MCP433X/435X
14.00%
13.00%
12.00%
11.00%
10.00%
9.00%
8.00%
7.00%
6.00%
5.00%
4.00%
3.00%
2.00%
1.00%
0.00%
-1.00%
-40C
+85C
16
+25C
+125C
14
12
PPM / °C
Error %
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
10
8
6
4
CH0
CH2
2
0
0
32
64
96
128
160
192
224
0
256
32
64
Wiper Code
FIGURE 2-76:
100 k – Worst Case RBW
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 5.5V, IW = 45 µA).
7.00%
-40C
+85C
6.00%
2.00%
256
14
12
10
8
6
1.00%
4
0.00%
2
CH0
CH2
CH1
CH3
0
-1.00%
0
32
64
96
128
160
192
224
0
256
32
64
96
128 160
Wiper Code
Wiper Code
FIGURE 2-77:
100 k – Worst Case RBW
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 3.0V, IW = 24 µA).
192
224
256
FIGURE 2-80:
100 k – RWB PPM/°C vs.
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n,
-40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 3.0V, IW = 24 µA).
200
6.00%
-40C
+85C
5.00%
+25C
+125C
0
-200
PPM / °C
4.00%
Error %
224
16
PPM / °C
Error %
3.00%
192
18
+25C
+125C
4.00%
96 128 160
Wiper Code
FIGURE 2-79:
100 k – RWB PPM/°C vs.
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n,
-40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 5.5V, IW = 45 µA).
5.00%
3.00%
2.00%
-400
-600
1.00%
-800
0.00%
-1000
CH0
CH2
CH1
CH3
-1200
-1.00%
0
32
64
96
128
160
192
224
0
256
Wiper Code
Note:
CH1
CH3
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-78:
100 k – Worst Case RBW
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 1.8V, IW = 15 µA).
DS22242A-page 32
Note:
32
64
96 128 160 192 224 256
Wiper Code
See Appendix B: for additional information of RW resistance variation characteristics for VDD > 2.7V.
FIGURE 2-81:
100 k – RWB PPM/°C vs.
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n,
-40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 1.8V, IW = 15 µA).
 2010 Microchip Technology Inc.
MCP433X/435X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-82:
100 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-84:
100 k – Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
FIGURE 2-83:
100 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
FIGURE 2-85:
100 k – Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
 2010 Microchip Technology Inc.
DS22242A-page 33
MCP433X/435X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
2.4
0
2.2
-5
-10
5.5V
IOH (mA)
VIH (V)
2
1.8
1.6
1.4
2.7V
2.7V
-15
-20
5.5V
-25
-30
-35
1.2
-40
1
-45
-40
0
40
80
120
-40
0
Temperature (°C)
FIGURE 2-86:
VIH (SDI, SCK, CS, and
RESET) vs. VDD and Temperature.
1.3
5.5V
IOL (mA)
VIL (V)
1.1
1
0.9
0.8
2.7V
0.7
0.6
-40
0
40
80
120
50
45
40
35
30
25
20
15
10
5
0
120
5.5V
2.7V
-40
Temperature (°C)
FIGURE 2-87:
VIL (SDI, SCK, CS, and
RESET) vs. VDD and Temperature.
DS22242A-page 34
80
IOH (SDO) vs. VDD and
FIGURE 2-88:
Temperature.
1.4
1.2
40
Temperature (°C)
0
40
80
120
Temperature (°C)
FIGURE 2-89:
Temperature.
IOL (SDO) vs. VDD and
 2010 Microchip Technology Inc.
MCP433X/435X
Note: Unless otherwise indicated, TA = +25°C,
VDD = 5V, VSS = 0V.
2.1
Test Circuits
+5V
2
VDD (V)
A
VIN
1.6
1.2
B
Offset
GND
0.8
W
+
VOUT
-
0.4
2.5V DC
0
-40
0
40
80
120
Temperature (°C)
FIGURE 2-90:
and Temperature.
POR/BOR Trip point vs. VDD
14.2
14.1
5.5V
FIGURE 2-92:
Measurement.
floating
VA
A
fsck (MHz)
14.0
-3 db Gain vs. Frequency
VW
W
13.9
IW
2.7V
13.8
13.7
B
13.6
VB
RBW = VW / IW
RW = (VW - VA) / IW
13.5
13.4
-40
0
40
80
120
FIGURE 2-93:
RBW and RW Measurement.
Temperature (°C)
FIGURE 2-91:
SCK Input Frequency vs.
Voltage and Temperature.
 2010 Microchip Technology Inc.
DS22242A-page 35
MCP433X/435X
NOTES:
DS22242A-page 36
 2010 Microchip Technology Inc.
MCP433X/435X
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
Additional descriptions of the device pins follows.
TABLE 3-1:
PINOUT DESCRIPTION FOR THE MCP433X/435X
Pin
TSSOP
QFN
Symbol
I/O
Buffer
Type
Weak
Pull-up/
down
(Note 1)
Standard Function
14L
20L
20L
—
1
19
P3A
A
Analog
No
Potentiometer 3 Terminal A
1
2
20
P3W
A
Analog
No
Potentiometer 3 Wiper Terminal
2
3
1
P3B
A
Analog
No
Potentiometer 3 Terminal B
3
4
2
CS
I
HV w/ST
“smart”
SPI Chip Select Input
4
5
3
SCK
I
HV w/ST
“smart”
SPI Clock Input
5
6
4
SDI
I
HV w/ST
“smart”
SPI Serial Data Input
6
7
5
VSS
—
P
—
Ground
7
8
6
P1B
A
Analog
No
Potentiometer 1 Terminal B
8
9
7
P1W
A
Analog
No
Potentiometer 1 Wiper Terminal
—
10
8
P1A
A
Analog
No
Potentiometer 1 Terminal A
—
11
9
P0A
A
Analog
No
Potentiometer 0 Terminal A
9
12
10
P0W
A
Analog
No
Potentiometer 0 Wiper Terminal
10
13
11
P0B
A
Analog
No
Potentiometer 0 Terminal B
—
14
12
NC
I
I
—
No Connect
—
15
13
RESET
I
HV w/ST
Yes
Hardware Reset Pin
11
16
14
SDO
O
O
No
SPI Serial Data Output
12
17
15
VDD
—
P
—
Positive Power Supply Input
13
18
16
P2B
A
Analog
No
Potentiometer 2 Terminal B
14
19
17
P2W
A
Analog
No
Potentiometer 2 Wiper Terminal
—
20
18
P2A
A
Analog
No
Potentiometer 2 Terminal A
—
—
21
EP
—
—
—
Exposed Pad. (Note 2)
Legend:
Note 1:
2:
HV w/ST = High Voltage tolerant input (with Schmitt trigger input)
A = Analog pins (Potentiometer terminals)
I = digital input (high Z)
O = digital output
I/O = Input / Output
P = Power
The pin’s “smart” pull-up shuts off while the pin is forced low. This is done to reduce the standby and
shutdown current.
The QFN package has a contact on the bottom of the package. This contact is conductively connected to
the die substrate, and therefore should be unconnected or connected to the same ground as the device’s
VSS pin.
 2010 Microchip Technology Inc.
DS22242A-page 37
MCP433X/435X
3.1
Chip Select (CS)
The CS pin is the serial interface’s chip select input.
Forcing the CS pin to VIL enables the serial commands.
Forcing the CS pin to VIHH enables the high-voltage
serial commands.
3.2
Serial Clock (SCK)
The SCK pin is the serial interface's Serial Clock pin.
This pin is connected to the host controllers SCK pin.
The MCP43XX is an SPI slave device, so it’s SCK pin
is an input only pin.
3.3
Serial Data In (SDI)
The SDI pin is the serial interfaces Serial Data In pin.
This pin is connected to the host controllers SDO pin.
3.4
Ground (VSS)
The VSS pin is the device ground reference.
3.5
Potentiometer Terminal B
The terminal B pin is connected to the internal
potentiometer’s terminal B.
The potentiometer’s terminal B is the fixed connection
to the zero scale wiper value of the digital
potentiometer. This corresponds to a wiper value of
0x00 for both 7-bit and 8-bit devices.
The terminal B pin does not have a polarity relative to
the terminal W or A pins. The terminal B pin can
support both positive and negative current. The voltage
on terminal B must be between VSS and VDD.
MCP43XX devices have four terminal B pins, one for
each resistor network.
3.6
Potentiometer Wiper (W) Terminal
The terminal W pin is connected to the internal
potentiometer’s terminal W (the wiper). The wiper
terminal is the adjustable terminal of the digital
potentiometer. The terminal W pin does not have a
polarity relative to terminals A or B pins. The terminal
W pin can support both positive and negative current.
The voltage on terminal W must be between VSS and
VDD.
MCP43XX devices have four terminal W pins, one for
each resistor network.
DS22242A-page 38
3.7
Potentiometer Terminal A
The terminal A pin is available on the MCP43X1
devices, and is connected to the internal
potentiometer’s terminal A.
The potentiometer’s terminal A is the fixed connection
to the full scale wiper value of the digital potentiometer.
This corresponds to a wiper value of 0x100 for 8-bit
devices or 0x80 for 7-bit devices.
The terminal A pin does not have a polarity relative to
the terminal W or B pins. The terminal A pin can
support both positive and negative current. The voltage
on terminal A must be between VSS and VDD.
The terminal A pin is not available on the MCP43X2
devices, and the internally terminal A signal is floating.
MCP43X1 devices have four terminal A pins, one for
each resistor network.
3.8
Not Connected (NC)
The NC pin is not used.
3.9
Reset (RESET)
The RESET pin is used to force the device into the
POR/BOR state.
3.10
Serial Data Out (SDO)
The SDO pin is the serial interfaces Serial Data Out pin.
This pin is connected to the host controllers SDI pin.
This pin allows the host controller to read the digital
potentiometers registers, or monitor the state of the
command error bit.
3.11
Positive Power Supply Input (VDD)
The VDD pin is the device’s positive power supply input.
The input power supply is relative to VSS.
While the devices VDD is less than Vmin (2.7V), the
electrical performance of the device may not meet the
data sheet specifications.
3.12
Exposed Pad (EP)
This pad is conductively connected to the device's
substrate. This pad should be tied to the same potential
as the VSS pin (or left unconnected). This pad could be
used to assist as a heat sink for the device when
connected to a PCB heat sink.
 2010 Microchip Technology Inc.
MCP433X/435X
4.0
FUNCTIONAL OVERVIEW
4.1.2
BROWN-OUT RESET
This data sheet covers a family of four volatile Digital
Potentiometer and Rheostat devices that will be
referred to as MCP43XX. The MCP43X1 devices are
the Potentiometer configuration, while the MCP43X2
devices are the Rheostat configuration.
When the device powers down, the device VDD will
cross the VPOR/VBOR voltage.
As the Device Block Diagram shows, there are four
main functional blocks. These are:
If the VDD voltage decreases below the VRAM voltage,
the following happens:
•
•
•
•
• Volatile wiper registers may become corrupted
• TCON registers may become corrupted
POR/BOR and Reset Operation
Memory Map
Resistor Network
Serial Interface (SPI)
The POR/BOR operation and the Memory Map are
discussed in this section and the Resistor Network and
SPI operation are described in their own sections. The
Device Commands are discussed in Section 7.0.
4.1
POR/BOR and Reset Operation
The Power-on Reset is the case where the device is
having power applied to it from VSS. The Brown-out
Reset occurs when a device had power applied to it,
and that power (voltage) drops below the specified
range.
The devices RAM retention voltage (VRAM) is lower
than the POR/BOR voltage trip point (VPOR/VBOR). The
maximum VPOR/VBOR voltage is less than 1.8V.
When VPOR/VBOR < VDD < 2.7V, the analog electrical
performance may not meet the data sheet
specifications. In this region, the device is capable of
incrementing, decrementing, reading and writing to its
volatile memory, if the proper serial command is
executed.
When VDD < VPOR/VBOR or the RESET pin is Low, the
pin weak pull-ups are enabled.
4.1.1
POWER-ON RESET
When the device powers up, the device VDD will cross
the VPOR/VBOR voltage. Once the VDD voltage crosses
the VPOR/VBOR voltage, the following happens:
• Volatile wiper register is loaded with the default
value
• The TCON registers are loaded with their default
value
• The device is capable of digital operation
 2010 Microchip Technology Inc.
Once the VDD voltage decreases below the VPOR/VBOR
voltage the following happens:
• Serial Interface is disabled
As the voltage recovers above the VPOR/VBOR voltage,
the operation is the same as Power-on Reset (see
Section 4.1.1 “Power-on Reset”).
Serial commands not completed due to a brown-out
condition may cause the memory location to become
corrupted.
4.1.3
RESET PIN
The RESET pin can be used to force the device into
the POR/BOR state of the device. When the RESET
pin is forced Low, the device is forced into the Reset
state. This means that the TCON registers are forced
to their default values and the volatile wiper registers
are loaded with the default value. Also the SPI
interface is disabled.
This feature allows a hardware method for all registers
to be updated to the default value at the same time.
4.1.4
INTERACTION OF RESET PIN AND BOR/
POR CIRCUITRY
Figure 4-1 shows how the RESET pin signal and the
POR/BOR signal interact to control the hardware Reset
state of the device.
RESET (from pin)
Device Reset
POR/BOR signal
FIGURE 4-1:
POR/BOR Signal and
RESET Pin Interaction.
DS22242A-page 39
MCP433X/435X
4.2
Memory Map
The device memory supports 16 locations that are
9-bits wide (16x9 bits). This memory space contains
only volatile locations (see Table 4-2).
4.2.1
VOLATILE MEMORY (RAM)
Volatile Wiper 0
Volatile Wiper 1
Volatile Wiper 2
Volatile Wiper 3
Terminal Control (TCON0) Register 0
Terminal Control (TCON)1 Register 1
TABLE 4-2:
Address
TABLE 4-1:
STANDARD SETTINGS
Resistance
Typical
Code
RAB Value
There are six volatile memory locations. These are:
•
•
•
•
•
•
The volatile memory starts functioning at the RAM
retention voltage (VRAM). The POR/BOR Wiper code is
shown in Table 4-1.
Wiper
Default
Code
POR Wiper
Setting
8-bit 7-bit
-502
5.0 k
Mid scale
80h
40h
-103
10.0 k
Mid scale
80h
40h
-503
50.0 k
Mid scale
80h
40h
-104
100.0 k
Mid scale
80h
40h
MEMORY MAP AND THE SUPPORTED COMMANDS
Function
Memory
Type
Allowed Commands
Disallowed Commands (1)
Factory
Initialization
00h
Volatile Wiper 0
RAM
Read, Write,
Increment, Decrement
—
7-bit
040h
8-bit
080h
01h
Volatile Wiper 1
RAM
Read, Write,
Increment, Decrement
—
7-bit
040h
02h
Reserved
—
None
All
03h
Reserved
04h
Volatile
TCON0 Register
05h
Reserved
06h
Volatile Wiper 2
07h
Volatile Wiper 3
08h
Reserved
09h
Reserved
0Ah
Volatile
TCON1 Register
0Bh-0Fh Reserved
Note 1:
8-bit
080h
—
—
None
All
—
RAM
Read, Write
Increment, Decrement
1FFh
—
None
All
RAM
Read, Write,
Increment, Decrement
—
7-bit
040h
8-bit
080h
RAM
Read, Write,
Increment, Decrement
—
7-bit
040h
—
None
All
—
8-bit
080h
—
—
None
All
—
RAM
Read, Write
Increment, Decrement
1FFh
—
None
All
—
This command on this address will generate an error condition. To exit the error condition, the user must
take the CS pin to the VIH level and then back to the active state (VIL or VIHH).
DS22242A-page 40
 2010 Microchip Technology Inc.
MCP433X/435X
4.2.1.1
Terminal Control (TCON) Registers
disconnected from the resistor network. This allows the
system to minimize the currents through the digital
potentiometer.
There are two Terminal Control (TCON) Registers.
These are called TCON0 and TCON1. Each register
contains 8 control bits. Four bits for each Wiper.
Register 4-1 describes each bit of the TCON0 register,
while Register 4-2 describes each bit of the TCON1
register.
The value that is written to the specified TCON register
will appear on the appropriate resistor network
terminals when the serial command has completed.
On a POR/BOR these registers are loaded with
1FFh (9-bits), for all terminals connected. The host
controller needs to detect the POR/BOR event and
then update the volatile TCON register values.
The state of each resistor network terminal connection
is individually controlled. That is, each terminal
connection (A, B and W) can be individually connected/
REGISTER 4-1:
TCON0 BITS (1)
R-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
D8
R1HW
R1A
R1W
R1B
R0HW
R0A
R0W
R0B
bit 8
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 8
D8: Reserved. Forced to “1”
bit 7
R1HW: Resistor 1 Hardware Configuration Control bit
This bit forces Resistor 1 into the “shutdown” configuration of the Hardware pin
1 = Resistor 1 is NOT forced to the hardware pin “shutdown” configuration
0 = Resistor 1 is forced to the hardware pin “shutdown” configuration
bit 6
R1A: Resistor 1 Terminal A (P1A pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Terminal A to the Resistor 1 Network
1 = P1A pin is connected to the Resistor 1 Network
0 = P1A pin is disconnected from the Resistor 1 Network
bit 5
R1W: Resistor 1 Wiper (P1W pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Wiper to the Resistor 1 Network
1 = P1W pin is connected to the Resistor 1 Network
0 = P1W pin is disconnected from the Resistor 1 Network
bit 4
R1B: Resistor 1 Terminal B (P1B pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Terminal B to the Resistor 1 Network
1 = P1B pin is connected to the Resistor 1 Network
0 = P1B pin is disconnected from the Resistor 1 Network
bit 3
R0HW: Resistor 0 Hardware Configuration Control bit
This bit forces Resistor 0 into the “shutdown” configuration of the Hardware pin
1 = Resistor 0 is NOT forced to the hardware pin “shutdown” configuration
0 = Resistor 0 is forced to the hardware pin “shutdown” configuration
bit 2
R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network
1 = P0A pin is connected to the Resistor 0 Network
0 = P0A pin is disconnected from the Resistor 0 Network
bit 1
R0W: Resistor 0 Wiper (P0W pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network
1 = P0W pin is connected to the Resistor 0 Network
0 = P0W pin is disconnected from the Resistor 0 Network
bit 0
R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network
1 = P0B pin is connected to the Resistor 0 Network
0 = P0B pin is disconnected from the Resistor 0 Network
Note 1:
These bits do not affect the wiper register values.
 2010 Microchip Technology Inc.
DS22242A-page 41
MCP433X/435X
REGISTER 4-2:
TCON1 BITS (1)
R-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
D8
R3HW
R3A
R3W
R3B
R2HW
R2A
R2W
R2B
bit 8
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 8
D8: Reserved. Forced to “1”
bit 7
R3HW: Resistor 3 Hardware Configuration Control bit
This bit forces Resistor 3 into the “shutdown” configuration of the Hardware pin
1 = Resistor 3 is NOT forced to the hardware pin “shutdown” configuration
0 = Resistor 3 is forced to the hardware pin “shutdown” configuration
bit 6
R3A: Resistor 3 Terminal A (P3A pin) Connect Control bit
This bit connects/disconnects the Resistor 3 Terminal A to the Resistor 3 Network
1 = P3A pin is connected to the Resistor 3 Network
0 = P3A pin is disconnected from the Resistor 3 Network
bit 5
R3W: Resistor 3 Wiper (P3W pin) Connect Control bit
This bit connects/disconnects the Resistor 3 Wiper to the Resistor 3 Network
1 = P3W pin is connected to the Resistor 3 Network
0 = P3W pin is disconnected from the Resistor 3 Network
bit 4
R3B: Resistor 3 Terminal B (P3B pin) Connect Control bit
This bit connects/disconnects the Resistor 3 Terminal B to the Resistor 3 Network
1 = P3B pin is connected to the Resistor 3 Network
0 = P3B pin is disconnected from the Resistor 3 Network
bit 3
R2HW: Resistor 2 Hardware Configuration Control bit
This bit forces Resistor 2 into the “shutdown” configuration of the Hardware pin
1 = Resistor 2 is NOT forced to the hardware pin “shutdown” configuration
0 = Resistor 2 is forced to the hardware pin “shutdown” configuration
bit 2
R2A: Resistor 2 Terminal A (P0A pin) Connect Control bit
This bit connects/disconnects the Resistor 2 Terminal A to the Resistor 2 Network
1 = P2A pin is connected to the Resistor 2 Network
0 = P2A pin is disconnected from the Resistor 2 Network
bit 1
R2W: Resistor 2 Wiper (P0W pin) Connect Control bit
This bit connects/disconnects the Resistor 2 Wiper to the Resistor 2 Network
1 = P2W pin is connected to the Resistor 2 Network
0 = P2W pin is disconnected from the Resistor 2 Network
bit 0
R2B: Resistor 2 Terminal B (P2B pin) Connect Control bit
This bit connects/disconnects the Resistor 2 Terminal B to the Resistor 2 Network
1 = P2B pin is connected to the Resistor 2 Network
0 = P2B pin is disconnected from the Resistor 2 Network
Note 1:
These bits do not affect the wiper register values.
DS22242A-page 42
 2010 Microchip Technology Inc.
MCP433X/435X
5.0
RESISTOR NETWORK
5.1
The Resistor Network has either 7-bit or 8-bit
resolution. Each Resistor Network allows zero scale to
full scale connections. Figure 5-1 shows a block
diagram for the resistive network of a device.
The Resistor Network is made up of several parts.
These include:
• Resistor Ladder
• Wiper
• Shutdown (Terminal Connections)
Devices have either four resistor networks. These are
referred to as Pot 0, Pot 1, Pot 2 and Pot 3.
A
RW
RS
RW
RS
RW
R
RAB S
8-Bit
N=
257
(1) (100h)
7-Bit
N=
128
(80h)
256
(1) (FFh)
127
(7Fh)
255
(FEh)
126
(7Eh)
(1)
RW
RS
RW
1
(01h)
0
(00h)
0
(00h)
(1)
The resistor ladder is a series of equal value resistors
(RS) with a connection point (tap) between the two
resistors. The total number of resistors in the series
(ladder) determines the RAB resistance (see
Figure 5-1). The end points of the resistor ladder are
connected to analog switches which are connected to
the device terminal A and terminal B pins. The RAB
(and RS) resistance has small variations over voltage
and temperature.
For an 8-bit device, there are 256 resistors in a string
between terminal A and terminal B. The wiper can be
set to tap onto any of these 256 resistors thus providing
257 possible settings (including terminal A and
terminal B).
For a 7-bit device, there are 128 resistors in a string
between terminal A and terminal B. The wiper can be
set to tap onto any of these 128 resistors thus providing
129 possible settings (including terminal A and
terminal B).
Equation 5-1 shows the calculation for the step
resistance.
EQUATION 5-1:
W
1
(1) (01h)
Resistor Ladder Module
RS CALCULATION
RAB
RS = ------------ 256 
8-bit Device
R AB
R S = ------------- 128 
7-bit Device
Analog Mux
B
Note 1:
The wiper resistance is dependent on
several factors including, wiper code,
device VDD, Terminal voltages (on A, B
and W), and temperature.
Also for the same conditions, each tap
selection resistance has a small variation.
This RW variation has greater effects on
some specifications (such as INL) for the
smaller resistance devices (5.0 k)
compared to larger resistance devices
(100.0 k).
FIGURE 5-1:
Resistor Block Diagram.
 2010 Microchip Technology Inc.
DS22242A-page 43
MCP433X/435X
5.2
Wiper
TABLE 5-1:
Each tap point (between the RS resistors) is a
connection point for an analog switch. The opposite
side of the analog switch is connected to a common
signal which is connected to the Terminal W (Wiper)
pin.
A value in the volatile wiper register selects which
analog switch to close, connecting the W terminal to
the selected node of the resistor ladder.
The wiper can connect directly to Terminal B or to
Terminal A. A zero scale connection, connects the
Terminal W (wiper) to Terminal B (wiper setting of
000h). A full scale connection, connects the Terminal W
(wiper) to Terminal A (wiper setting of 100h or 80h). In
these configurations the only resistance between the
Terminal W and the other Terminal (A or B) is that of the
analog switches.
A wiper setting value greater than full scale (wiper
setting of 100h for 8-bit device or 80h for 7-bit devices)
will also be a full scale setting (Terminal W (wiper) connected to Terminal A). Table 5-1 illustrates the full wiper
setting map.
VOLATILE WIPER VALUE VS.
WIPER POSITION MAP
Wiper Setting
Properties
7-bit
8-bit
3FFh081h
3FFh101h
Reserved (Full Scale (W = A)),
Increment and Decrement
commands ignored
080h
100h
Full Scale (W = A),
Increment commands ignored
07Fh041h
0FFh081h
W=N
040h
080h
W = N (Mid Scale)
03Fh001h
07Fh001h
W=N
000h
000h
Zero Scale (W = B)
Decrement command ignored
Equation 5-2 illustrates the calculation used to
determine the resistance between the wiper and
terminal B.
EQUATION 5-2:
RWB CALCULATION
R AB N
R WB = -------------- + R W
 256 
8-bit Device
N = 0 to 256 (decimal)
R AB N
R WB = -------------- + R W
 128 
7-bit Device
N = 0 to 128 (decimal)
DS22242A-page 44
 2010 Microchip Technology Inc.
MCP433X/435X
Shutdown
Shutdown is used to minimize the device’s current
consumption. The MCP43XX has one method to
achieve this:
• Terminal Control Register (TCON)
This is different from the MCP42XXX devices in that the
Hardware Shutdown pin (SHDN) has been replaced by
a RESET pin. The Hardware Shutdown pin function is
still available via software commands to the TCON
register.
5.3.1
TERMINAL CONTROL REGISTER
(TCON)
The Terminal Control (TCON) register is a volatile
register used to configure the connection of each
resistor network terminal pin (A, B and W) to the
Resistor Network. These registers are shown in
Register 4-1 and Register 4-2.
The RxHW bit does NOT corrupt the values in the
Volatile Wiper Registers nor the TCON register. When
the Shutdown mode is exited (RxHW bit = 1):
• The device returns to the Wiper setting specified
by the Volatile Wiper value
• The TCON register bits return to controlling the
terminal connection state
A
Resistor Network
5.3
W
B
FIGURE 5-2:
Resistor Network Shutdown
State (RxHW = 0).
The RxHW bit forces the selected resistor network into
the same state as the MCP42X1’s SHDN pin. Alternate
low-power configurations may be achieved with the
RxA, RxW and RxB bits.
When the RxHW bit is “0”:
• The P0A, P1A, P2A and P3A terminals are
disconnected
• The P0W, P1W, P2W and P3W terminals are
simultaneously connect to the P0B, P1B, P2B and
P3B terminals, respectively (see Figure 5-2)
Note:
When the RxHW bit forces the resistor
network into the hardware SHDN state,
the state of the TCON0 or TCON1
register’s RxA, RxW and RxB bits is
overridden (ignored). When the state of
the RxHW bit no longer forces the resistor
network into the hardware SHDN state,
the TCON0 or TCON1 register’s RxA,
RxW and RxB bits return to controlling the
terminal connection state. In other words,
the RxHW bit does not corrupt the state of
the RxA, RxW and RxB bits.
 2010 Microchip Technology Inc.
DS22242A-page 45
MCP433X/435X
NOTES:
DS22242A-page 46
 2010 Microchip Technology Inc.
MCP433X/435X
6.0
SERIAL INTERFACE (SPI)
The MCP43XX devices support the SPI serial protocol.
This SPI operates in the Slave mode (does not
generate the serial clock).
The SPI interface uses up to four pins. These are:
•
•
•
•
CS – Chip Select
SCK – Serial Clock
SDI – Serial Data In
SDO – Serial Data Out
Typical SPI Interface is shown in Figure 6-1. In the SPI
interface, the Master’s Output pin is connected to the
Slave’s Input pin and the Master’s Input pin is
connected to the Slave’s Output pin.
The MCP4XXX SPI’s module supports two (of the four)
standard SPI modes. These are Mode 0,0 and 1,1. The
SPI mode is determined by the state of the SCK pin
(VIH or VIL) on the when the CS pin transitions from
inactive (VIH) to active (VIL or VIHH).
All SPI interface signals are high-voltage tolerant.
Typical SPI Interface Connections
Host
Controller
MCP4XXX
SDO
(Master Out – Slave In (MOSI))
SDI
SDI
(Master In – Slave Out (MISO))
SDO
SCK
SCK
I/O (1)
CS
Note 1: If high voltage commands are desired, some type of external circuitry needs to be implemented.
FIGURE 6-1:
Typical SPI Interface Block Diagram.
 2010 Microchip Technology Inc.
DS22242A-page 47
MCP433X/435X
6.1
SDI, SDO, SCK, and CS Operation
The operation of the four SPI interface pins are
discussed in this section. These pins are:
•
•
•
•
SDI (Serial Data In)
SDO (Serial Data Out)
SCK (Serial Clock)
CS (Chip Select)
SERIAL DATA IN (SDI)
The Serial Data In (SDI) signal is the data signal into
the device. The value on this pin is latched on the rising
edge of the SCK signal.
6.1.2
SERIAL DATA OUT (SDO)
The Serial Data Out (SDO) signal is the data signal out
of the device. The value on this pin is driven on the
falling edge of the SCK signal.
Once the CS pin is forced to the active level (VIL or
VIHH), the SDO pin will be driven. The state of the SDO
pin is determined by the serial bit’s position in the
command, the command selected, and if there is a
command error state (CMDERR).
6.1.3
THE CS SIGNAL
The Chip Select (CS) signal is used to select the device
and frame a command sequence. To start a command,
or sequence of commands, the CS signal must
transition from the inactive state (VIH) to an active state
(VIL or VIHH).
After the CS signal has gone active, the SDO pin is
driven and the clock bit counter is reset.
The serial interface works on either 8-bit or 16-bit
boundaries depending on the selected command. The
Chip Select (CS) pin frames the SPI commands.
6.1.1
6.1.4
SERIAL CLOCK (SCK)
(SPI FREQUENCY OF OPERATION)
The SPI interface is specified to operate up to 10 MHz.
The actual clock rate depends on the configuration of
the system and the serial command used. Table 6-1
shows the SCK frequency.
Note:
There is a required delay after the CS pin
goes active to the 1st edge of the SCK pin.
If an error condition occurs for an SPI command, then
the command byte’s Command Error (CMDERR) bit
(on the SDO pin) will be driven low (VIL). To exit the
error condition, the user must take the CS pin to the VIH
level.
When the CS pin returns to the inactive state (VIH) the
SPI module resets (including the Address Pointer).
While the CS pin is in the inactive state (VIH), the serial
interface is ignored. This allows the host controller to
interface to other SPI devices using the same SDI,
SDO and SCK signals.
The CS pin has an internal pull-up resistor. The resistor
is disabled when the voltage on the CS pin is at the VIL
level. This means that when the CS pin is not driven,
the internal pull-up resistor will pull this signal to the VIH
level. When the CS pin is driven low (VIL), the
resistance becomes very large to reduce the device
current consumption.
The high voltage capability of the CS pin allows High
Voltage commands. Support of High Voltage
commands allows circuit compatibility with the
corresponding nonvolatile device.
SCK FREQUENCY (1)
TABLE 6-1:
Command
Memory Type Access
Volatile
Memory
Note 1:
SDI, SDO
Read
Write,
Increment,
Decrement
10 MHz
10 MHz
This is the maximum clock frequency
without an external pull-up resistor.
DS22242A-page 48
 2010 Microchip Technology Inc.
MCP433X/435X
6.2
The SPI Modes
6.2.2
In Mode 1,1: SCK Idle state = high (VIH), data is
clocked in on the SDI pin on the rising edge of SCK and
clocked out on the SDO pin on the falling edge of SCK.
The SPI module supports two (of the four) standard SPI
modes. These are Mode 0,0 and 1,1. The mode is
determined by the state of the SDI pin on the rising
edge of the 1st clock bit (of the 8-bit byte).
6.2.1
6.3
MODE 0,0
VIH
SPI Waveforms
Figure 6-2 through Figure 6-5 show the different SPI
command waveforms. Figure 6-2 and Figure 6-3 are
read and write commands. Figure 6-4 and Figure 6-5
are Increment and Decrement commands. Support of
High Voltage commands allows circuit compatibility
with the corresponding nonvolatile device.
In Mode 0,0: SCK Idle state = low (VIL), data is clocked
in on the SDI pin on the rising edge of SCK and clocked
out on the SDO pin on the falling edge of SCK.
CS
MODE 1,1
VIHH
VIL
SCK
Write to
SSPBUF
CMDERR bit
SDO
bit15 bit14 bit13 bit12 bit11
SDI
AD3 AD2 AD1 AD0
bit15 bit14 bit13 bit12
C1
bit10 bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
X
bit9
D8
bit8
D7
bit7
D6
bit6
D5
bit5
D4
bit4
D3
bit3
D2
D1
bit2 bit1
D0
bit0
C0
Input
Sample
FIGURE 6-2:
VIH
CS
16-Bit Commands (Write, Read) – SPI Waveform (Mode 1,1).
VIHH
VIL
SCK
Write to
SSPBUF
SDO
SDI
CMDERR bit
bit15
bit14 bit13 bit12 bit11
AD3 AD2 AD1 AD0
bit15 bit14 bit13 bit12
C1
bit10 bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
X
bit9
D8
bit8
D7
bit7
D6
bit6
D5
bit5
D4
bit4
D3
bit3
D2
D1
bit2 bit1
C0
bit1
bit0
D0
bit0
Input
Sample
FIGURE 6-3:
16-Bit Commands (Write, Read) – SPI Waveform (Mode 0,0).
 2010 Microchip Technology Inc.
DS22242A-page 49
MCP433X/435X
CS
VIH
VIHH
VIL
SCK
Write to
SSPBUF
CMDERR bit
“1” = Valid Command
“0” = Invalid Command
SDO
bit7
SDI
AD3
bit6
AD2
bit5
AD1
bit4
AD0
bit3
C1
bit2
C0
bit1
X
bit0
X
bit0
bit7
Input
Sample
FIGURE 6-4:
VIH
CS
8-Bit Commands (Increment, Decrement) – SPI Waveform with PIC MCU (Mode 1,1).
VIHH
VIL
SCK
Write to
SSPBUF
SDO
SDI
CMDERR bit
“1” = Valid Command
“0” = Invalid Command
bit7
AD3
bit7
bit6
AD2
bit5
AD1
bit4
AD0
bit3
C1
bit2
C0
bit1
X
bit0
X
bit0
Input
Sample
FIGURE 6-5:
DS22242A-page 50
8-Bit Commands (Increment, Decrement) – SPI Waveform with PIC MCU (Mode 0,0).
 2010 Microchip Technology Inc.
MCP433X/435X
7.0
DEVICE COMMANDS
7.1
Command Byte
The command byte has three fields, the address, the
command, and 2 data bits, see Figure 7-1. Currently
only one of the data bits is defined (D8). This is for the
Write command.
The MCP43XX’s SPI command format supports
16 memory address locations and four commands.
Each command has two modes:
• Normal Serial Commands
• High-Voltage Serial Commands
The device memory is accessed when the master
sends a proper command byte to select the desired
operation. The memory location getting accessed is
contained in the command byte’s AD3:AD0 bits. The
action desired is contained in the command byte’s
C1:C0 bits, see Table 7-1. C1:C0 determines if the
desired memory location will be read, written,
incremented (wiper setting +1) or decremented (wiper
setting -1). The Increment and Decrement commands
are only valid on the volatile wiper registers.
Normal serial commands are those where the CS pin is
driven to VIL. With high-voltage serial commands, the
CS pin is driven to VIHH. In each mode, there are four
possible commands. These commands are shown in
Table 7-1.
The 8-bit commands (Increment Wiper and
Decrement Wiper commands) contain a command
byte, see Figure 7-1, while 16-bit commands (Read
Data and Write Data commands) contain a command
byte and a data byte. The command byte contains two
data bits, see Figure 7-1.
As the command byte is being loaded into the device
(on the SDI pin), the device’s SDO pin is driving. The
SDO pin will output high bits for the first six bits of that
command. On the 7th bit, the SDO pin will output the
CMDERR bit state (see Section 7.3 “Error
Condition”). The 8th bit state depends on the
command selected.
Table 7-2 shows the supported commands for each
memory location and the corresponding values on the
SDI and SDO pins.
Table 7-3 shows an overview of all the SPI commands
and their interaction with other device features.
TABLE 7-1:
COMMAND BIT OVERVIEW
C1:C0
Bit
Command
States
A A A A C C D D
D D D D 1 0 9 8
3 2 1 0
Memory
Address
Data
Bits
Command
Bits
FIGURE 7-1:
11
Read Data
16-Bits
Both
00
Write Data
16-Bits
Both
01
Increment
8-Bits
Volatile Only
10
Decrement
8-Bits
Volatile Only
16-bit Command
8-bit Command
Command Byte
Operates on
Volatile/
Nonvolatile
memory
# of
Bits
Command Byte
Data Byte
A A A A C C D D D D D D D D D D
D D D D 1 0 9 8 7 6 5 4 3 2 1 0
3 2 1 0
Data
Bits
Memory
Address
Command
Bits
Command
Bits
CC
1 0
0 0 = Write Data
0 1 = INCR
1 0 = DECR
1 1 = Read Data
General SPI Command Formats.
 2010 Microchip Technology Inc.
DS22242A-page 51
MCP433X/435X
TABLE 7-2:
MEMORY MAP AND THE SUPPORTED COMMANDS
Address
Value
Function
00h
Volatile Wiper 0
01h
Volatile Wiper 1
SPI String (Binary)
Data
(10-bits) (1)
Command
MOSI (SDI pin)
MISO (SDO pin) (2)
Write Data
nn nnnn nnnn
0000 00nn
nnnn nnnn 1111 1111
1111 1111
Read Data
nn nnnn nnnn
0000 11nn
nnnn nnnn 1111 111n
nnnn nnnn
Increment Wiper
—
0000 0100
1111 1111
Decrement Wiper
—
0000 1000
1111 1111
Write Data
nn nnnn nnnn
0001 00nn
nnnn nnnn 1111 1111
1111 1111
Read Data
nn nnnn nnnn
0001 11nn
nnnn nnnn 1111 111n
nnnn nnnn
Increment Wiper
—
0001 0100
1111 1111
Decrement Wiper
—
0001 1000
1111 1111
02h
Reserved
None
—
—
—
03h
Reserved
None
—
—
—
nn nnnn nnnn
0100 00nn
nnnn nnnn 1111 1111
1111 1111
nn nnnn nnnn
0100 11nn
nnnn nnnn 1111 111n
nnnn nnnn
None
—
—
Write Data
nn nnnn nnnn
0110 00nn
nnnn nnnn 1111 1111
1111 1111
Read Data
nn nnnn nnnn
0110 11nn
nnnn nnnn 1111 111n
nnnn nnnn
Increment Wiper
—
0110 0100
1111 1111
04h
(3)
Volatile
Write Data
TCON 0 Register Read Data
05h
Reserved
06h
Volatile Wiper 2
07h
Volatile Wiper 3
—
Decrement Wiper
—
0110 1000
1111 1111
Write Data
nn nnnn nnnn
0111 00nn
nnnn nnnn 1111 1111
1111 1111
Read Data
nn nnnn nnnn
0111 11nn
nnnn nnnn 1111 111n
nnnn nnnn
Increment Wiper
—
0111 0100
1111 1111
Decrement Wiper
—
0111 1000
1111 1111
08h
Reserved
None
—
—
—
09h
Reserved
None
0Ah (3)
0Bh-0Fh
Note 1:
2:
3:
Volatile
Write Data
TCON 1 Register Read Data
Reserved
None
—
—
nn nnnn nnnn
1010 00nn
nnnn nnnn 1111 1111
—
1111 1111
nn nnnn nnnn
1010 11nn
nnnn nnnn 1111 111n
nnnn nnnn
—
—
—
The data memory is only 9-bits wide, so the MSb is ignored by the device.
All these address/command combinations are valid, so the CMDERR bit is set. Any other address/command combination is a command error state and the CMDERR bit will be clear.
Increment or Decrement commands are invalid for these addresses.
DS22242A-page 52
 2010 Microchip Technology Inc.
MCP433X/435X
7.2
Data Byte
Only the Read command and the Write command use
the data byte, see Figure 7-1. These commands
concatenate the 8 bits of the data byte with the one
data bit (D8) contained in the command byte to form
9-bits of data (D8:D0). The command byte format
supports up to 9-bits of data so that the 8-bit resistor
network can be set to full scale (100h or greater). This
allows wiper connections to Terminal A and to
Terminal B.
The D9 bit is currently unused, and corresponds to the
position on the SDO data of the CMDERR bit.
7.3
Error Condition
The CMDERR bit indicates if the four address bits
received (AD3:AD0) and the two command bits
received (C1:C0) are a valid combination (see
Table 4-2). The CMDERR bit is high if the combination
is valid and low if the combination is invalid.
The command error bit will also be low if a write to a
nonvolatile address has been specified and another
SPI command occurs before the CS pin is driven
inactive (VIH).
SPI commands that do not have a multiple of 8 clocks
are ignored.
Once an error condition has occurred, any following
commands are ignored. All following SDO bits will be
low until the CMDERR condition is cleared by forcing
the CS pin to the inactive state (VIH).
 2010 Microchip Technology Inc.
7.3.1
ABORTING A TRANSMISSION
All SPI transmissions must have the correct number of
SCK pulses to be executed. The command is not
executed until the complete number of clocks have
been received. Some commands also require the CS
pin to be forced inactive (VIH). If the CS pin is forced to
the inactive state (VIH) the serial interface is reset.
Partial commands are not executed.
SPI is more susceptible to noise than other bus
protocols. The most likely case is that this noise
corrupts the value of the data being clocked into the
MCP43XX or the SCK pin is injected with extra clock
pulses. This may cause data to be corrupted in the
device, or a command error to occur, since the address
and command bits were not a valid combination. The
extra SCK pulse will also cause the SPI data (SDI) and
clock (SCK) to be out of sync. Forcing the CS pin to the
inactive state (VIH) resets the serial interface. The SPI
interface will ignore activity on the SDI and SCK pins
until the CS pin transition to the active state is detected
(VIH to VIL or VIH to VIHH).
Note 1: When data is not being received by the
MCP43XX, It is recommended that the
CS pin be forced to the inactive level (VIL)
2: It is also recommended that long
continuous command strings should be
broken down into single commands or
shorter continuous command strings.
This reduces the probability of noise on
the SCK pin corrupting the desired SPI
commands.
DS22242A-page 53
MCP433X/435X
7.4
Continuous Commands
The device supports the ability to execute commands
continuously. While the CS pin is in the active state (VIL
or VIHH). Any sequence of valid commands may be
received.
The following example is a valid sequence of events:
1.
2.
3.
4.
5.
6.
7.
2: It is also recommended that long
command strings should be broken down
into shorter command strings. This
reduces the probability of noise on the
SCK pin corrupting the desired SPI
command string.
CS pin driven active (VIL or VIHH).
Read Command.
Increment Command (Wiper 0).
Increment Command (Wiper 0).
Decrement Command (Wiper 1).
Write Command (volatile memory).
CS pin driven inactive (VIH).
TABLE 7-3:
Note 1: It is recommended that while the CS pin is
active, only one type of command should
be issued. When changing commands, it
is recommended to take the CS pin
inactive then force it back to the active
state.
COMMANDS
# of
Bits
High
Voltage
(VIHH) on
CS pin?
Write Data
16-Bits
—
Read Data
16-Bits
—
Increment Wiper
8-Bits
—
Decrement Wiper
8-Bits
—
High-Voltage Write Data
16-Bits
Yes
High-Voltage Read Data
16-Bits
Yes
Command Name
High-Voltage Increment Wiper
8-Bits
Yes
High-Voltage Decrement Wiper
8-Bits
Yes
DS22242A-page 54
 2010 Microchip Technology Inc.
MCP433X/435X
7.5
Write Data
Normal and High Voltage
7.5.1
SINGLE WRITE TO VOLATILE
MEMORY
The write operation requires that the CS pin be in the
active state (VILor VIHH). Typically, the CS pin will be in
the inactive state (VIH) and is driven to the active state
(VIL). The 16-bit Write command (command byte and
data byte) is then clocked in on the SCK and SDI pins.
Once all 16 bits have been received, the specified
volatile address is updated. A write will not occur if the
write command isn’t exactly 16 clocks pulses. This
protects against system issues from corrupting the
nonvolatile memory locations.
The Write command is a 16-bit command. The format
of the command is shown in Figure 7-2.
A Write command to a volatile memory location
changes that location after a properly formatted Write
command (16-clock) have been received.
Figure 6-2 and Figure 6-3 show possible waveforms
for a single write.
COMMAND BYTE
A
D
3
1
SDO
1
SDI
A
D
2
1
1
A
D
1
1
1
A
D
0
1
1
DATA BYTE
0
0
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1 Valid Address/Command combination
0 Invalid Address/Command combination (1)
Note 1: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR
condition is cleared (the CS pin is forced to the inactive state).
FIGURE 7-2:
Write Command – SDI and SDO States.
 2010 Microchip Technology Inc.
DS22242A-page 55
MCP433X/435X
7.5.2
CONTINUOUS WRITES TO
VOLATILE MEMORY
Continuous writes are possible only when writing to the
volatile memory registers (address 00h, 01h and 04h).
Figure 7-3 shows the sequence for three continuous
writes. The writes do not need to be to the same volatile
memory address.
COMMAND BYTE
SDI
SDO
A
D
3
1
A
D
2
1
A
D
1
1
A
D
0
1
A
D
3
1
A
D
2
1
A
D
1
1
A
D
0
1
A
D
3
1
A
D
2
1
A
D
1
1
A
D
0
1
DATA BYTE
0
0 D9 D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1 1* 1
1
1
1
1
1
1
1
1
0
0 D9 D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1 1* 1
1
1
1
1
1
1
1
1
0
0 D9 D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1 1* 1
1
1
1
1
1
1
1
1
Note 1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be
driven low until the CS pin is driven inactive (VIH).
FIGURE 7-3:
DS22242A-page 56
Continuous Write Sequence.
 2010 Microchip Technology Inc.
MCP433X/435X
7.6
Read Data
Normal and High Voltage
7.6.1
SINGLE READ
The read operation requires that the CS pin be in the
active state (VILor VIHH). Typically, the CS pin will be in
the inactive state (VIH) and is driven to the active state
(VILor VIHH). The 16-bit Read command (command
byte and data byte) is then clocked in on the SCK and
SDI pins. The SDO pin starts driving data on the 7th bit
(CMDERR bit) and the addressed data comes out on
the 8th through 16th clocks. Figure 6-2 through
Figure 6-3 show possible waveforms for a single read.
The Read command is a 16-bit command. The format
of the command is shown in Figure 7-4.
The first 6 bits of the Read command determine the
address and the command. The 7th clock will output
the CMDERR bit on the SDO pin. The remaining
9-clocks the device will transmit the 9 data bits (D8:D0)
of the specified address (AD3:AD0).
Figure 7-4 shows the SDI and SDO information for a
Read command.
COMMAND BYTE
SDI
SDO
DATA BYTE
A
D
3
1
A
D
2
1
A
D
1
1
A
D
0
1
1
1
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
1
0
D
8
0
D
7
0
D
6
0
D
5
0
D
4
0
D
3
0
D
2
0
D
1
0
D Valid Address/Command combination
0
0 Attempted Memory Read of Reserved
Memory location
READ DATA
FIGURE 7-4:
Read Command – SDI and SDO States.
 2010 Microchip Technology Inc.
DS22242A-page 57
MCP433X/435X
7.6.2
CONTINUOUS READS
Figure 7-5 shows the sequence for three continuous
reads. The reads do not need to be to the same
memory address.
Continuous reads allow the devices memory to be read
quickly. Continuous reads are possible to all memory
locations.
COMMAND BYTE
SDI
SDO
A
D
3
1
A
D
2
1
A
D
1
1
A
D
0
1
A
D
3
1
A
D
2
1
A
D
1
1
A
D
0
1
A
D
3
1
A
D
2
1
A
D
1
1
A
D
0
1
X
DATA BYTE
1
1
X
X
X
X
X
X
X
X
X
1
1 1* D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1
X
X
X
X
X
X
X
X
X
1
1 1* D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
1
X
X
X
X
X
X
X
X
X
1
1 1* D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
X
X
Note 1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be
driven low until the CS pin is driven inactive (VIH).
FIGURE 7-5:
DS22242A-page 58
Continuous Read Sequence.
 2010 Microchip Technology Inc.
MCP433X/435X
7.7
Increment Wiper
Normal and High Voltage
The Increment command is an 8-bit command. The
Increment command can only be issued to volatile
memory locations. The format of the command is
shown in Figure 7-6.
An Increment command to the volatile memory location
changes that location after a properly formatted command (8-clocks) have been received.
Increment commands provide a quick and easy
method to modify the value of the volatile wiper location
by +1 with minimal overhead.
COMMAND BYTE
(INCR COMMAND (n+1))
A
D
3
1
SDO
1
SDI
A
D
2
1
1
A
D
1
1
1
A
D
0
1
1
0
1
X
X
1
1
1 1* 1 Note 1, 2
1 0 0 Note 1, 3
Note 1: Only functions when writing the volatile
wiper registers (AD3:AD0) 0h and 1h.
2: Valid Address/Command combination.
3: Invalid Address/Command combination
all following SDO bits will be low until the
CMDERR condition is cleared. (the CS
pin is forced to the inactive state).
4: If a Command Error (CMDERR) occurs
at this bit location (*), then all following
SDO bits will be driven low until the CS
pin is driven inactive (VIH).
FIGURE 7-6:
Increment Command –
SDI and SDO States.
Note:
Table 7-2 shows the valid addresses for
the Increment Wiper command. Other
addresses are invalid.
 2010 Microchip Technology Inc.
7.7.1
SINGLE INCREMENT
Typically, the CS pin starts at the inactive state (VIH),
but may already be in the active state due to the
completion of another command.
Figure 6-4 through Figure 6-5 show possible
waveforms for a single increment. The increment
operation requires that the CS pin be in the active state
(VILor VIHH). Typically, the CS pin will be in the inactive
state (VIH) and is driven to the active state (VILor VIHH).
The 8-bit Increment command (command byte) is then
clocked in on the SDI pin by the SCK pins. The SDO pin
drives the CMDERR bit on the 7th clock.
The wiper value will increment up to 100h on 8-bit
devices and 80h on 7-bit devices. After the wiper value
has reached full scale (8-bit = 100h, 7-bit = 80h), the
wiper value will not be incremented further. If the wiper
register has a value between 101h and 1FFh, the
Increment command is disabled. See Table 7-4 for
additional information on the Increment command
versus the current volatile wiper value.
The increment operations only require the Increment
command byte while the CS pin is active (VILor VIHH)
for a single increment.
After the wiper is incremented to the desired position,
the CS pin should be forced to VIH to ensure that
unexpected transitions on the SCK pin do not cause
the wiper setting to change. Driving the CS pin to VIH
should occur as soon as possible (within device
specifications) after the last desired increment occurs.
TABLE 7-4:
Current Wiper
Setting
INCREMENT OPERATION VS.
VOLATILE WIPER VALUE
Increment
Command
Operates?
Wiper (W)
Properties
7-bit
Pot
8-bit
Pot
3FFh
081h
3FFh
101h
Reserved
(Full Scale (W = A))
No
No
080h
100h
Full Scale (W = A)
07Fh
041h
0FFh
081
W=N
040h
080h
W = N (Mid-scale)
03Fh
001h
07Fh
001
W=N
000h
000h
Zero Scale (W = B)
Yes
Yes
DS22242A-page 59
MCP433X/435X
7.7.2
CONTINUOUS INCREMENTS
Increment commands can be sent repeatedly without
raising CS until a desired condition is met.
Continuous increments are possible only when writing
to the volatile memory registers (address 00h, 01h, 06h
and 07h).
When executing a continuous command string, the
Increment command can be followed by any other valid
command.
Figure 7-7 shows a continuous increment sequence for
three continuous writes. The writes do not need to be
to the same volatile memory address.
The wiper terminal will move after the command has
been received (8th clock).
After the wiper is incremented to the desired position,
the CS pin should be forced to VIH to ensure that
unexpected transitions (on the SCK pin do not cause
the wiper setting to change). Driving the CS pin to VIH
should occur as soon as possible (within device
specifications) after the last desired increment occurs.
When executing an continuous Increment commands,
the selected wiper will be altered from n to n+1 for each
Increment command received. The wiper value will
increment up to 100h on 8-bit devices and 80h on 7-bit
devices. After the wiper value has reached full scale
(8-bit = 100h, 7-bit = 80h), the wiper value will not be
incremented further. If the wiper register has a value
between 101h and 1FFh, the Increment command is
disabled.
(INCR COMMAND (n+1))
A
D
3
1
1
SDO
1
1
SDI
A
D
2
1
1
1
1
A
D
1
1
1
1
1
A
D
0
1
1
1
1
X
COMMAND BYTE
COMMAND BYTE
COMMAND BYTE
(INCR COMMAND (n+2))
0
1
X
1
1
1
1
1 1* 1
1 0 0
1 1 1
1 1 1
A
D
3
1
0
1
1
A
D
2
1
0
1
1
A
D
1
1
0
1
1
A
D
0
1
0
1
1
X
(INCR COMMAND (n+3))
0
1
X
1
0
1
1
1 1* 1
0 0 0
1 0 0
1 1 1
A
D
3
1
0
0
1
A
D
2
1
0
0
1
A
D
1
1
0
0
1
A
D
0
1
0
0
1
0
1
X
X
1
0
0
1
1 1* 1 Note 1, 2
0 0 0 Note 3, 4
0 0 0 Note 3, 4
1 0 0 Note 3, 4
Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h.
2: Valid Address/Command combination.
3: Invalid Address/Command combination.
4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR
condition is cleared (the CS pin is forced to the inactive state).
FIGURE 7-7:
DS22242A-page 60
Continuous Increment Command – SDI and SDO States.
 2010 Microchip Technology Inc.
MCP433X/435X
7.8
Decrement Wiper
Normal and High Voltage
The Decrement command is an 8-bit command. The
Decrement command can only be issued to volatile
memory locations. The format of the command is
shown in Figure 7-6.
A Decrement command to the volatile memory location
changes that location after a properly formatted
command (8 clocks) have been received.
Decrement commands provide a quick and easy
method to modify the value of the volatile wiper location
by -1 with minimal overhead.
COMMAND BYTE
(DECR COMMAND (n+1))
A
D
3
1
SDO
1
SDI
A
D
2
1
1
A
D
1
1
1
A
D
0
1
1
1
0
X
X
1
1
1 1* 1 Note 1, 2
1 0 0 Note 1, 3
Note 1: Only functions when writing the volatile
wiper registers (AD3:AD0) 0h and 1h.
2: Valid Address/Command combination.
3: Invalid Address/Command combination
all following SDO bits will be low until the
CMDERR condition is cleared.
(the CS pin is forced to the inactive
state).
4: If a Command Error (CMDERR) occurs
at this bit location (*), then all following
SDO bits will be driven low until the CS
pin is driven inactive (VIH).
FIGURE 7-8:
Decrement Command –
SDI and SDO States.
Note:
Table 7-2 shows the valid addresses for
the Decrement Wiper command. Other
addresses are invalid.
 2010 Microchip Technology Inc.
7.8.1
SINGLE DECREMENT
Typically, the CS pin starts at the inactive state (VIH),
but may already be in the active state due to the
completion of another command.
Figure 6-4 through Figure 6-5 show possible
waveforms for a single decrement. The decrement
operation requires that the CS pin be in the active state
(VILor VIHH). Typically, the CS pin will be in the inactive
state (VIH) and is driven to the active state (VILor VIHH).
Then the 8-bit Decrement command (command byte) is
clocked in on the SDI pin by the SCK pins. The SDO pin
drives the CMDERR bit on the 7th clock.
The wiper value will decrement from the wiper’s full
scale value (100h on 8-bit devices and 80h on 7-bit
devices). Above the wiper’s full scale value (8-bit =
101h to 1FFh, 7-bit = 81h to FFh), the Decrement command is disabled. If the wiper register has a zero scale
value (000h), then the wiper value will not decrement.
See Table 7-5 for additional information on the Decrement command vs. the current volatile wiper value.
The Decrement commands only require the Decrement
command byte, while the CS pin is active (VILor VIHH)
for a single decrement.
After the wiper is decremented to the desired position,
the CS pin should be forced to VIH to ensure that
unexpected transitions on the SCK pin do not cause
the wiper setting to change. Driving the CS pin to VIH
should occur as soon as possible (within device
specifications) after the last desired decrement occurs.
TABLE 7-5:
Current Wiper
Setting
DECREMENT OPERATION VS.
VOLATILE WIPER VALUE
Decrement
Command
Operates?
Wiper (W)
Properties
7-bit
Pot
8-bit
Pot
3FFh
081h
3FFh
101h
Reserved
(Full Scale (W = A))
No
Yes
080h
100h
Full Scale (W = A)
07Fh
041h
0FFh
081
W=N
040h
080h
W = N (Mid-scale)
03Fh
001h
07Fh
001
W=N
000h
000h
Zero Scale (W = B)
Yes
No
DS22242A-page 61
MCP433X/435X
7.8.2
CONTINUOUS DECREMENTS
Decrement commands can be sent repeatedly without
raising CS until a desired condition is met.
Continuous decrements are possible only when writing
to the volatile memory registers (address 00h, 01h, and
04h).
When executing a continuous command string, the
Decrement command can be followed by any other
valid command.
Figure 7-9 shows a continuous decrement sequence
for three continuous writes. The writes do not need to
be to the same volatile memory address.
The wiper terminal will move after the command has
been received (8th clock).
After the wiper is decremented to the desired position,
the CS pin should be forced to VIH to ensure that
“unexpected” transitions (on the SCK pin do not cause
the wiper setting to change). Driving the CS pin to VIH
should occur as soon as possible (within device
specifications) after the last desired decrement occurs.
When executing continuous Decrement commands,
the selected wiper will be altered from n to n-1 for each
Decrement command received. The wiper value will
decrement from the wiper’s full scale value (100h on
8-bit devices and 80h on 7-bit devices). Above the
wiper’s full scale value (8-bit = 101h to 1FFh,
7-bit = 81h to FFh), the Decrement command is
disabled. If the Wiper register has a zero scale value
(000h), then the wiper value will not decrement. See
Table 7-5 for additional information on the Decrement
command vs. the current volatile wiper value.
(DECR COMMAND (n-1))
A
D
3
1
1
SDO
1
1
SDI
A
D
2
1
1
1
1
A
D
1
1
1
1
1
A
D
0
1
1
1
1
X
COMMAND BYTE
COMMAND BYTE
COMMAND BYTE
(DECR COMMAND (n-1))
1
0
X
1
1
1
1
1 1* 1
1 0 0
1 1 1
1 1 1
A
D
3
1
0
1
1
A
D
2
1
0
1
1
A
D
1
1
0
1
1
A
D
0
1
0
1
1
X
(DECR COMMAND (n-1))
1
0
X
1
0
1
1
1 1* 1
0 0 0
1 0 0
1 1 1
A
D
3
1
0
0
1
A
D
2
1
0
0
1
A
D
1
1
0
0
1
A
D
0
1
0
0
1
1
0
X
X
1
0
0
1
1 1* 1 Note 1, 2
0 0 0 Note 3, 4
0 0 0 Note 3, 4
1 0 0 Note 3, 4
Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h.
2: Valid Address/Command combination.
3: Invalid Address/Command combination.
4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR
condition is cleared (the CS pin is forced to the inactive state).
FIGURE 7-9:
DS22242A-page 62
Continuous Decrement Command – SDI and SDO States.
 2010 Microchip Technology Inc.
MCP433X/435X
8.0
APPLICATIONS EXAMPLES
5V
Digital potentiometers have a multitude of practical
uses in modern electronic circuits. The most popular
uses include precision calibration of set point thresholds, sensor trimming, LCD bias trimming, audio attenuation, adjustable power supplies, motor control
overcurrent trip setting, adjustable gain amplifiers and
offset trimming. The MCP433X/435X devices can be
used to replace the common mechanical trim pot in
applications where the operating and terminal voltages
are within CMOS process limitations (VDD = 2.7V to
5.5V).
8.1
Split Rail Applications
All inputs that would be used to interface to a host
controller support high voltage on their input pin. This
allows the MCP43XX device to be used in split power
rail applications.
PIC® MCU
Figure 8-1 through Figure 8-2 show three example split
rail systems. In this system, the MCP43XX interface
input signals need to be able to support the PIC MCU
output high voltage (VOH).
In Example #1 (Figure 8-1), the MCP43XX interface
input signals need to be able to support the PIC MCU
output high voltage (VOH). If the split rail voltage delta
becomes too large, then the customer may be required
to do some level shifting due to MCP43XX VOH levels
related to host controller VIH levels.
In Example #2 (Figure 8-2), the MCP43XX interface
input signals need to be able to support the lower
voltage of the PIC MCU output high voltage level (VOH).
Table 8-1 shows an example PIC microcontroller I/O
voltage
specifications
and
the
MCP43XX
specifications. So this PIC MCU operating at 3.3V will
drive a VOH at 2.64V, and for the MCP43XX operating
at 5.5V, the VIH is 2.47V. Therefore, the interface
signals meet specifications.
I/O
SDO
RESET
SDO
Example Split Rail
5V
3V
PIC® MCU
MCP4XXX
SDI
CS
SCK
SDI
CS
SCK
RESET
I/O
SDO
SDO
FIGURE 8-2:
System 2.
Example Split Rail
TABLE 8-1:
VOH – VIH COMPARISONS
PIC® MCU (1)
VDD
VIH
MCP4XXX (2)
VOH VDD
VIH
VOH
5.5
4.4
4.4
2.7
1.215 — (3)
5.0
4.0
4.0
3.0
1.35
4.5
3.6
3.6
3.3
1.485 — (3)
3.3
2.64 2.64 4.5
2.025 — (3)
3.0
2.4
2.25
2.7
2.16 2.16 5.5
Note 1:
2:
3:
 2010 Microchip Technology Inc.
SDI
CS
SCK
Voltage
Regulator
For SPI applications, these inputs are:
CS
SCK
SDI (or SDI/SDO)
RESET
MCP4XXX
SDI
CS
SCK
FIGURE 8-1:
System 1.
An example of this is a battery application where the
PIC® MCU is directly powered by the battery supply
(4.8V) and the MCP43XX device is powered by the
3.3V regulated voltage.
•
•
•
•
3V
Voltage
Regulator
2.4
5.0
Comment
— (3)
— (3)
2.475 — (3)
VOH minimum = 0.8 * VDD;
VOL maximum = 0.6V
VIH minimum = 0.8 * VDD;
VIL maximum = 0.2 * VDD;
VOH minimum (SDA only) =;
VOL maximum = 0.2 * VDD
VIH minimum = 0.45 * VDD;
VIL maximum = 0.2 * VDD
The only MCP4XXX output pin is SDO,
which is open-drain (or open-drain with
internal pull-up) with high voltage support
DS22242A-page 63
MCP433X/435X
8.2
Techniques to Force the CS Pin to
VIHH
PIC10F206
The circuit in Figure 8-3 shows a method using the
TC1240A doubling charge pump. When the SHDN pin
is high, the TC1240A is off, and the level on the CS pin
is controlled by the PIC® microcontrollers (MCUs) IO2
pin.
When the SHDN pin is low, the TC1240A is on and the
VOUT voltage is 2 * VDD. The resistor R1 allows the CS
pin to go higher than the voltage such that the PIC
MCU’s IO2 pin “clamps” at approximately VDD.
PIC® MCU
TC1240A
C+
VIN
CSHDN
VOUT
IO1
IO2
C1
MCP4XXX
R1
CS
C2
FIGURE 8-3:
Using the TC1240A to
Generate the VIHH Voltage.
The circuit in Figure 8-4 shows the method used on the
MCP402X Nonvolatile Digital Potentiometer Evaluation
Board (Part Number: MCP402XEV). This method
requires that the system voltage be approximately 5V.
This ensures that when the PIC10F206 enters a
brown-out condition, there is an insufficient voltage
level on the CS pin to change the stored value of the
wiper.
The
“MCP402X
Nonvolatile
Digital
Potentiometer Evaluation Board User’s Guide”
(DS51546) contains a complete schematic.
R1
GP0
MCP4XXX
GP2
CS
C1
FIGURE 8-4:
MCP4XXX Nonvolatile
Digital Potentiometer Evaluation Board
(MCP402XEV) implementation to generate the
VIHH voltage.
8.3
Using Shutdown Modes
Figure 8-5 shows a possible application circuit where
the independent terminals could be used.
Disconnecting the wiper allows the transistor input to
be taken to the bias voltage level (disconnecting A and
or B may be desired to reduce system current).
Disconnecting Terminal A modifies the transistor input
by the RBW rheostat value to the Common B.
Disconnecting Terminal B modifies the transistor input
by the RAW rheostat value to the Common A. The
Common A and Common B connections could be
connected to VDD and VSS.
Common A
Input
A
GP0 is a general purpose I/O pin, while GP2 can either
be a general purpose I/O pin or it can output the internal
clock.
To base
of Transistor
(or Amplifier)
W
For the serial commands, configure the GP2 pin as an
input (high-impedance). The output state of the GP0
pin will determine the voltage on the CS pin (VIL or VIH).
For high-voltage serial commands, force the GP0
output pin to output a high level (VOH) and configure the
GP2 pin to output the internal clock. This will form a
charge pump and increase the voltage on the CS pin
(when the system voltage is approximately 5V).
C2
B
Input
Common B
Balance
Bias
FIGURE 8-5:
Example Application Circuit
using Terminal Disconnects.
DS22242A-page 64
 2010 Microchip Technology Inc.
MCP433X/435X
8.4
Design Considerations
8.4.2
In the design of a system with the MCP43XX devices,
the following considerations should be taken into
account:
LAYOUT CONSIDERATIONS
Several layout considerations may be applicable to
your application. These may include:
• Power Supply Considerations
• Layout Considerations
• Noise
• Footprint Compatibility
• PCB Area Requirements
8.4.1
8.4.2.1
POWER SUPPLY
CONSIDERATIONS
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply’s traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity. Figure 8-6 illustrates an
appropriate bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 µF. This capacitor should be placed as
close (within 4 mm) to the device power pin (VDD) as
possible.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.
VDD
Noise
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP43XX’s performance.
Careful board layout minimizes these effects and
increases the Signal-to-Noise Ratio (SNR). Multi-layer
boards utilizing a low-inductance ground plane,
isolated inputs, isolated outputs and proper decoupling
are critical to achieving the performance that the
silicon is capable of providing. Particularly harsh
environments may require shielding of critical signals.
If low noise is desired, breadboards and wire-wrapped
boards are not recommended.
8.4.2.2
Footprint Compatibility
The specification of the MCP43XX pinouts was done to
allow systems to be designed to easily support the use
of either the dual (MCP42XX) or quad (MCP43XX)
device.
Figure 8-7 shows how the dual pinout devices fit on the
quad device footprint. For the Rheostat devices, the
dual device is in the MSOP package, so the footprints
would need to be offset from each other.
0.1 µF
VDD
MCP43X1 Quad Potentiometers
W
B
VSS
FIGURE 8-6:
Connections.
U/D
PIC® Microcontroller
A
MCP433X/435X
0.1 µF
P3A
P3W
P3B
CS
SCK
SDI
VSS
P1B
P1W
P1A
Typical Microcontroller
20
19
18
17
16
15
14
12
12
11
P2A
P2W
P2B
VDD
SDO
RESET
WP
P0B
P0W
P0A
MCP42X1 Pinout (1)
TSSOP
MCP43X2 Quad Rheostat
CS
VSS
1
2
3
4
5
6
7
8
9
10
P3W
P3B
CS
SCK
SDI
VSS
P1B
1
2
3
4
5
6
7
14
13
12
11
10
9
8
P2W
P2B
VDD
SDO
P0B
P0W
P1W
MCP42X2 Pinout
TSSOP
Note 1: Pin 15 (RESET) is the Shutdown
(SHDN) pin on the MCP42x1 device.
FIGURE 8-7:
Quad Pinout (TSSOP
Package) vs. Dual Pinout.
 2010 Microchip Technology Inc.
DS22242A-page 65
MCP433X/435X
Figure 8-8 shows possible layout implementations for
an application to support the quad and dual options on
the same PCB.
Potentiometers Devices
MCP43X1
8.4.2.3
PCB Area Requirements
In some applications, PCB area is a criteria for device
selection. Table 8-2 shows the package dimensions
and area for the different package options. The table
also shows the relative area factor compared to the
smallest area. For space critical applications, the QFN
package would be the suggested package.
PACKAGE FOOTPRINT (1)
TABLE 8-2:
MCP42X1
Type
Area (mm2)
Relative Area
MCP43X2
Package Footprint
Pins
Rheostat Devices
MCP42X2
Package
14
TSSOP
ST
5.10
6.40
32.64
2.04
QFN
ML
4.00
4.00
16.00
1
TSSOP
ST
6.60
6.40
42.24
2.64
20
Dimensions
(mm)
Code
X
Y
Note 1: Does not include recommended land
pattern dimensions.
8.4.3
FIGURE 8-8:
Dual Devices.
Layout to support Quad and
RESISTOR TEMPCO
Characterization curves of the resistor temperature
coefficient (Tempco) are shown in Figure 2-11,
Figure 2-32, Figure 2-52, and Figure 2-72.
These curves show that the resistor network is
designed to correct for the change in resistance as
temperature increases. This technique reduces the
end to end change is RAB resistance.
8.4.4
HIGH VOLTAGE TOLERANT PINS
High voltage support (VIHH) on the Serial Interface pins
supports in-circuit accommodation of split rail
applications and power supply sync issues.
DS22242A-page 66
 2010 Microchip Technology Inc.
MCP433X/435X
9.0
DEVELOPMENT SUPPORT
9.1
Development Tools
9.2
Technical Documentation
Several additional technical documents are available to
assist you in your design and development. These
technical documents include Application Notes,
Technical Briefs, and Design Guides. Table 9-2 shows
some of these documents.
Several development tools are available to assist in
your design and evaluation of the MCP43XX devices.
The currently available tools are shown in Table 9-1.
These boards may be purchased directly from the
Microchip web site at www.microchip.com.
TABLE 9-1:
DEVELOPMENT TOOLS
Board Name
Part #
Supported Devices
20-pin TSSOP and SSOP Evaluation Board
TSSOP20EV
MCP43XX
MCP4361 Evaluation Board (1)
MCP43XXEV
MCP4361
MCP42XX Digital Potentiometer PICtail™ Plus Demo MCP42XXDM-PTPLS
Board
MCP42XX
MCP4XXX Digital Potentiometer Daughter Board (2)
MCP42XXX, MCP42XX, MCP4021
and MCP4011
MCP4XXXDM-DB
Note 1: This Evaluation Board is planned to be available by March 2010. This board uses the TSSOP20EV PCB
and requires the PICkit™ Serial Analyzer (see User’s Guide for details). This kit also includes 1 blank
TSSOP20EV PCB.
2: Requires the use of a PICDEM™ Demo board (see User’s Guide for details).
TABLE 9-2:
TECHNICAL DOCUMENTATION
Application
Note Number
Title
Literature #
AN1080
Understanding Digital Potentiometers Resistor Variations
DS01080
AN737
Using Digital Potentiometers to Design Low-Pass Adjustable Filters
DS00737
AN692
Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect
DS00692
AN691
Optimizing the Digital Potentiometer in Precision Circuits
DS00691
AN219
Comparing Digital Potentiometers to Mechanical Potentiometers
DS00219
—
Digital Potentiometer Design Guide
DS22017
—
Signal Chain Design Guide
DS21825
 2010 Microchip Technology Inc.
DS22242A-page 67
MCP433X/435X
NOTES:
DS22242A-page 68
 2010 Microchip Technology Inc.
MCP433X/435X
10.0
PACKAGING INFORMATION
10.1
Package Marking Information
14-Lead TSSOP
Example
4352502E
XXXXXXXX
1004
YYWW
NNN
256
20-Lead QFN (4x4)
4351
502EML
e3 1004
^^
256
XXXXX
XXXXXX
XXXXXX
YYWWNNN
Example
20-Lead TSSOP
XXXXXXXX
4351502
XXXXX NNN
YYWW
EST ^^
e3 256
1004
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
 2010 Microchip Technology Inc.
DS22242A-page 69
MCP433X/435X
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 2010 Microchip Technology Inc.
MCP433X/435X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2010 Microchip Technology Inc.
DS22242A-page 71
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 2010 Microchip Technology Inc.
MCP433X/435X
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DS22242A-page 74
 2010 Microchip Technology Inc.
MCP433X/435X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
 2010 Microchip Technology Inc.
DS22242A-page 75
MCP433X/435X
NOTES:
DS22242A-page 76
 2010 Microchip Technology Inc.
MCP433X/435X
APPENDIX A:
REVISION HISTORY
Revision A (March 2010)
• Original Release of this Document.
Note: Original TSSOP-20 device samples used the
example marking shown in Figure A-1. Future device
samples will usE the part marking shown in Section 10.
Figure A-1: Old example TSSOP-20 device marking.
Example
MCP4351
e3 256
EST ^^
1004
 2010 Microchip Technology Inc.
DS22242A-page 77
MCP433X/435X
NOTES:
DS22242A-page 78
 2010 Microchip Technology Inc.
MCP433X/435X
CHARACTERIZATION
DATA ANALYSIS
Some designers may desire to understand the device
operational characteristics outside of the specified
operating conditions of the device.
Applications where the knowledge of the resistor
network characteristics could be useful include battery
powered devices and applications that experience
brown-out conditions.
In battery applications the application voltage decays
over time until new batteries are installed. As the
voltage decays, the system will continue to operate. At
some voltage level, the application will be below its
specified operating voltage range. This is dependent
on the individual components used in the design. It is
still useful to understand the device characteristics to
expect when this low-voltage range is encountered.
Unlike a microcontroller which can use an external
supervisor device to force the controller into the Reset
state, a digital potentiometer’s resistance characteristic
is not specified. But understanding the operational
characteristics can be important in the design of the
applications circuit for this low-voltage condition.
Other application system scenarios where understanding the low-voltage characteristics of the resistor network could be important is for system brown out
conditions.
For the MCP433X/435X devices, the analog operation
is specified at a minimum of 2.7V. Device testing has
Terminal A connected to the device VDD (for
potentiometer configuration only) and Terminal B
connected to VSS.
B.1
Low-Voltage Operation
This appendix gives an overview of CMOS
semiconductor characteristics at lower voltages. This is
important so that the 1.8V resistor network
characterization graphs of the MCP433X/435X devices
can be better understood.
For this discussion, we will use the 5 k device data.
This data was chosen since the variations of wiper
resistance has much greater implications for devices
with smaller RAB resistances.
Figure B-1 shows the worst case RBW error from the
average RBW as a percentage, while Figure B-2 shows
the RBW resistance verse wiper code graph. Nonlinear
behavior occurs at approximately wiper code 160. This
is better shown in Figure B-2, where the RBW
resistance changes from a linear slope. This change is
due to the change in the wiper resistance.
2.00%
1.00%
0.00%
-1.00%
Error %
APPENDIX B:
-2.00%
-3.00%
-4.00%
-40C
+25C
+85C
+125C
-5.00%
-6.00%
-7.00%
0
32
64
96
128
160
192
224
256
Wiper Code
FIGURE B-1:
1.8V Worst Case RBW Error
from Average RBW (RBW0-RBW3) vs. Wiper Code
and Temperature (VDD = 1.8V, IW = 190 µA).
7000
Resistance ()
6000
5000
4000
3000
-40C
+25C
+85C
+125C
2000
1000
0
0
32
64
96
128
160
Wiper Code
192
224
256
FIGURE B-2:
RBW vs. Wiper Code And
Temperature (VDD = 1.8V, IW = 190 µA).
 2010 Microchip Technology Inc.
DS22242A-page 79
MCP433X/435X
Figure B-3 and Figure B-4 show the wiper resistance
for VDD voltages of 5.5, 3.0, 1.8 Volts. These graphs
show that as the resistor ladder wiper node voltage
(VWCn) approaches the VDD/2 voltage, the wiper
resistance increases. These graphs also show the
different resistance characteristics of the NMOS and
PMOS transistors that make up the wiper switch. This
is demonstrated by the wiper code resistance curve,
which does not mirror itself around the mid-scale code
(wiper code = 128).
So why is the RW graphs showing the maximum
resistance at about mid-scale (wiper code = 128) and
the RBW graphs showing the issue at code 160?
This requires understanding low-voltage transistor
characteristics as well as how the data was measured.
220
200
Resistance ()
180
-40C @ 3.0V
+25C @ 3.0V
+85C @ 3.0V
+125C @ 3.0V
-40C @5.5V
+25C @ 5.5V
+85C @ 5.5V
+125C @ 5.5V
160
floating
VA
A
120
VW
W
IW
B
140
VB
RBW = VW/IW
RW = (VW-VA)/IW
100
80
FIGURE B-5:
60
40
20
0
64
128
192
256
Wiper Code
FIGURE B-3:
Wiper Resistance (RW) vs.
Wiper Code and Temperature
(VDD = 5.5V, IW = 900 UA; VDD = 3.0V,
IW = 480 µA).
2020
+25C @ 1.8V
1520
+125C @ 1.8V
1020
520
20
0
64
128
192
256
Wiper Code
FIGURE B-4:
Wiper Resistance (RW) vs.
Wiper Code and Temperature
(VDD = 1.8V, IW = 260 µA).
DS22242A-page 80
RBW and RW Measurement.
Figure B-6 shows a block diagram of the resistor
network where the RAB resistor is a series of 256 RS
resistors. These resistors are polysilicon devices. Each
wiper switch is an analog switch made up of an NMOS
and PMOS transistor. A more detailed figure of the
wiper switch is shown in Figure B-7. The wiper
resistance is influenced by the voltage on the wiper
switches nodes (VG, VW and VWCn). Temperature also
influences the characteristics of the wiper switch, see
Figure B-4.
The NMOS transistor and PMOS transistor have
different characteristics. These characteristics as well
as the wiper switch node voltages determine the RW
resistance at each wiper code. The variation of each
wiper switch’s characteristics in the resistor network is
greater then the variation of the RS resistors.
-40C @ 1.8V
+85C @ 1.8V
Resistance ()
The method in which the data was collected is
important to understand. Figure B-5 shows the
technique that was used to measure the RBW and RW
resistance. In this technique Terminal A is floating and
Terminal B is connected to ground. A fixed current is
then forced into the wiper (IW) and the corresponding
wiper voltage (VW) is measured. Forcing a known
current through RBW (IW) and then measuring the
voltage difference between the wiper (VW) and
Terminal A (VA), the wiper resistance (RW) can be
calculated, see Figure B-5. Changes in IW current will
change the wiper voltage (VW). This may effect the
device’s wiper resistance (RW).
The voltage on the resistor network node (VWCn) is
dependent upon the wiper code selected and the
voltages applied to VA, VB and VW. The wiper switch VG
voltage to VW or VWCn voltage determines how strongly
the transistor is turned on. When the transistor is
weakly turned on the wiper resistance RW will be high.
When the transistor is strongly turned on, the wiper
resistance (RW) will be in the typical range.
 2010 Microchip Technology Inc.
MCP433X/435X
So looking at the wiper voltage (VW) for the
3.0V and 1.8V data gives the graphs in Figure B-8 and
Figure B-9. In the 1.8V graph, as the VW approaches
0.8V, the voltage increases nonlinearly. Since V = I * R,
and the current (IW) is constant, it means that the
device resistance increased nonlinearly at around
wiper code 160.
A
VA
RS
Nn-1
RS
Nn-2
RS
RW (1)
DVG
RW (1)
VWC(n-2)
RAB
Nn-3
1.2
1.0
NMOS
PMOS
RW (1)
VW
W
Wiper Voltage (V)
Nn
0.8
0.6
0.4
-40C
+25C
+85C
+125C
0.2
0.0
RS
RW
(1)
RW
(1)
N0
B
Note 1:
0
32
64
96 128 160
Wiper Code
192
224
256
FIGURE B-8:
Wiper Voltage (VW) vs.
Wiper Code (VDD = 3.0V, IW = 190 µA).
VB
1.4
1.2
The wiper resistance is dependent on
several factors including, wiper code,
device VDD, Terminal voltages (on A, B
and W), and temperature.
FIGURE B-6:
Diagram.
Resistor Network Block
Wiper Voltage (V)
N1
1.0
0.8
0.6
-40C
+25C
+85C
+125C
0.4
0.2
The characteristics of the wiper is determined by the
characteristics of the wiper switch at each of the
resistor networks tap points. Figure B-7 shows an
example of a wiper switch. As the device operational
voltage becomes lower, the characteristics of the wiper
switch change due to a lower voltage on the VG signal.
0.0
0
32
64
96
128 160
Wiper Code
192
224
256
FIGURE B-9:
Wiper Voltage (VW) vs.
Wiper Code (VDD = 1.8V, IW = 190 µA).
Figure B-7 shows an implementation of a wiper switch.
When the transistor is turned off, the switch resistance
is in the Giga s. When the transistor is turned on, the
switch resistance is dependent on the VG, VW and
VWCn voltages. This resistance is referred to as RW.
RW (1)
VG (VDD/VSS)
“gate”
NMOS
NWC
VWCn
PMOS
Wiper
VW
“gate”
Note 1: Wiper Resistance (RW) depends on the
voltages at the wiper switch nodes
(VG, VW and VWCn).
FIGURE B-7:
Wiper Switch.
 2010 Microchip Technology Inc.
DS22242A-page 81
MCP433X/435X
RW
RPMOS
140
RW
120
5.00E+09
100
4.00E+09
3.00E+09
80
NMOS
PMOS Theshold
Theshold
2.00E+09
60
40
1.00E+09
Wiper Resistance ()
6.00E+09
20
0.00E+00
0
0.0
0.6
1.2
1.8
VIN Voltage
2.4
3.0
FIGURE B-12:
NMOS and PMOS
Transistor Resistance (RNMOS, RPMOS) and
Wiper Resistance (RW) VS. VIN
(VDD = 1.8V).
300
NMOS
250
Resistance ()
VOUT
PMOS
“gate”
FIGURE B-10:
160
RNMOS
VG (VDD/VSS)
“gate”
VIN
7.00E+09
NMOS and PMOS Resistance
()
Using the simulation models of the NMOS and PMOS
devices for the MCP43XX analog switch (Figure B-10),
we plot the device resistance when the devices are
turned on. Figure B-11 and Figure B-12 show the
resistances of the NMOS and PMOS devices as the
VIN voltage is increased. The wiper resistance (RW) is
simply the parallel resistance on the NMOS and PMOS
devices (RW = RNMOS || RPMOS). Below the threshold
voltage for the NMOS ad PMOS devices, the
resistance becomes very large (Giga s). In the
transistors active region, the resistance is much lower.
For these graphs, the resistances are on different
scales. Figure B-13 and Figure B-14 only plots the
NMOS and PMOS device resistance for their active
region and the resulting wiper resistance. For these
graphs, all resistances are on the same scale.
Analog Switch.
200
RNMOS
RPMOS
150
100
RW
50
RW
2500
RNMOS
0
2.50E+10
2000
RPMOS
2.00E+10
1500
1.50E+10
1000
1.00E+10
NMOS
500
Theshold
PMOS
Theshold
5.00E+09
0.00E+00
0.0
Wiper Resistance ()
0
0.0
0.3
0.6
0.9
1.2
VIN Voltage
1.5
1.2
1.8
VIN Voltage
2.4
3.0
5000
1.8
FIGURE B-11:
NMOS and PMOS
Transistor Resistance (RNMOS, RPMOS) and
Wiper Resistance (RW) VS. VIN
(VDD = 3.0V).
0.6
FIGURE B-13:
NMOS and PMOS
Transistor Resistance (RNMOS, RPMOS) and
Wiper Resistance (RW) VS. VIN
(VDD = 3.0V).
4500
4000
Resistance ()
NMOS and PMOS Resistance
()
3.00E+10
3500
3000
RNMOS
2500
RPMOS
2000
RW
1500
1000
500
0
0.0
0.3
0.6
0.9
1.2
VIN Voltage
1.5
1.8
FIGURE B-14:
NMOS and PMOS
Transistor Resistance (RNMOS, RPMOS) and
Wiper Resistance (RW) VS. VIN
(VDD = 1.8V).
DS22242A-page 82
 2010 Microchip Technology Inc.
MCP433X/435X
B.2
Optimizing Circuit Design for LowVoltage Characteristics
R1
The low-voltage nonlinear characteristics can be
minimized by application design. The section will show
two application circuits that can be used to control a
programmable reference voltage (VOUT).
A
In example implementation #1 (Figure B-15) we
window the digital potentiometer using resistors R1 and
R2. When the wiper code is at full scale the VOUT
voltage will be  0.6 * VDD, and when the wiper code is
at zero scale the VOUT voltage will be  0.5 * VDD.
Remember that the digital potentiometers RAB variation
must be included. Table B-1 shows that the VOUT voltage can be selected to be between 0.455 * VDD and
0.727 * VDD, which includes the desired range. With
respect to the voltages on the resistor network node, at
1.8V the VA voltage would range from 1.29V to 1.31V
while the VB voltage would range from 0.82V to 0.86V.
These voltages cause the wiper resistance to be in the
nonlinear region (see Figure B-12). In Potentiometer
mode, the variation of the wiper resistance is typically
not an issue, as shown by the INL/DNL graph
(Figure 2-7).
VW
W
Minimizing the low-voltage nonlinear characteristics is
done by keeping the voltages on the wiper switch
nodes at a voltage where either the NMOS or PMOS
transistor is turned on.
An example of this is if we are using a digital potentiometer for a voltage reference (VOUT). Lets say that we
want VOUT to range from 0.5 * VDD to 0.6 * VDD.
VA
B
VOUT
VB
R2
FIGURE B-15:
TABLE B-1:
Example Implementation #1.
EXAMPLE #1 VOLTAGE
CALCULATIONS
Variation
Min
Typ
Max
R1
12,000
12,000
12,000
R2
20,000
20,000
20,000
RAB
8,000
10,000
12,000
VOUT (@ FS) 0.714 VDD
VOUT (@ ZS) 0.476 VDD
0.70 VDD
0.727 VDD
0.50 VDD
0.455 VDD
VA
0.714 VDD
0.70 VDD
0.727 VDD
VB
0.476 VDD
0.50 VDD
0.455 VDD
Legend: FS – Full Scale, ZS – Zero Scale
In example implementation #2 (Figure B-16) we use
the digital potentiometer in Rheostat mode. The resistor ladder uses resistors R1 and R2 with RBW at the
bottom of the ladder. When the wiper code is at full
scale, the VOUT voltage will be  0.6 * VDD and when
the wiper code is at full scale the VOUT voltage will be
 0.5 * VDD. Remember that the digital potentiometers
RAB variation must be included. Table B-2 shows that
the VOUT voltage can be selected to be between 0.50 *
VDD and 0.687 * VDD, which includes the desired
range. With respect to the voltages on the resistor network node, at 1.8V the VW voltage would range from
0.29V to 0.38V. These voltages cause the wiper
resistance to be in the linear region (see Figure B-12).
 2010 Microchip Technology Inc.
DS22242A-page 83
MCP433X/435X
R1
VOUT
R2
A VA
W
B
FIGURE B-16:
TABLE B-2:
VW
VB
Example Implementation #2.
EXAMPLE #2 VOLTAGE
CALCULATIONS
Variation
Min
Typ
Max
R1
10,000
10,000
10,000
R2
10,000
10,000
10,000
RBW (max)
8,000
10,000
12,000
VOUT (@ FS) 0.667 VDD
VOUT(@ ZS) 0.50 VDD
0.643 VDD
0.687 VDD
0.50 VDD
0.50 VDD
VW (@ FS)
0.333 VDD
0.286 VDD
0.375 VDD
VW (@ ZS)
VSS
VSS
VSS
Legend: FS – Full Scale, ZS – Zero Scale
DS22242A-page 84
 2010 Microchip Technology Inc.
MCP433X/435X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
-XXX
X
/XX
Device
Resistance
Version
Temperature
Range
Package
Device:
MCP4331:
MCP4331T:
MCP4332:
MCP4332T:
MCP4351:
MCP4351T:
MCP4352:
MCP4352T:
Quad Volatile 7-bit Potentiometer
Quad Volatile 7-bit Potentiometer
(Tape and Reel)
Quad Volatile 7-bit Rheostat
Quad Volatile 7-bit Rheostat
(Tape and Reel)
Quad Volatile 8-bit Potentiometer
Quad Volatile 8-bit Potentiometer
(Tape and Reel)
Quad Volatile 8-bit Rheostat
Quad Volatile 8-bit Rheostat
(Tape and Reel)
Resistance
Version:
502
103
503
104
=
=
=
=
5 k
10 k
50 k
100 k
Temperature
Range:
E
= -40C to +125C (Extended)
Package:
ST
= Plastic Thin Shrink Small Outline (TSSOP),
14/20-lead
ML = Plastic Quad Flat No-lead (4x4 QFN), 20-lead
 2010 Microchip Technology Inc.
Examples:
a)
b)
c)
d)
e)
f)
g)
h)
MCP4331-502E/XX:
MCP4331T-502E/XX:
MCP4331-103E/XX:
MCP4331T-103E/XX:
MCP4331-503E/XX:
MCP4331T-503E/XX:
MCP4331-104E/XX:
MCP4331T-104E/XX:
5 k 20-LD Device
T/R, 5 k20-LD Device
10 k, 20-LD Device
T/R, 10 k, 20-LD Device
50 k, 20-LD Device
T/R, 50 k, 20-LD Device
100 k, 20-LD Device
T/R, 100 k,
20-LD Device
a)
b)
c)
d)
e)
f)
g)
h)
MCP4332-502E/XX:
MCP4332T-502E/XX:
MCP4332-103E/XX:
MCP4332T-103E/XX:
MCP4332-503E/XX:
MCP4332T-503E/XX:
MCP4332-104E/XX:
MCP4332T-104E/XX:
5 k 14-LD Device
T/R, 5 k14-LD Device
10 k, 14-LD Device
T/R, 10 k, 14-LD Device
50 k, 8LD Device
T/R, 50 k, 14-LD Device
100 k, 14-LD Device
T/R, 100 k,
14-LD Device
a)
b)
c)
d)
e)
f)
g)
h)
MCP4351-502E/XX:
MCP4351T-502E/XX:
MCP4351-103E/XX:
MCP4351T-103E/XX:
MCP4351-503E/XX:
MCP4351T-503E/XX:
MCP4351-104E/XX:
MCP4351T-104E/XX:
5 k 20-LD Device
T/R, 5 k20-LD Device
10 k, 20-LD Device
T/R, 10 k, 20-LD Device
50 k, 20-LD Device
T/R, 50 k, 20-LD Device
100 k, 20-LD Device
T/R, 100 k,
20-LD Device
a)
b)
c)
d)
e)
f)
g)
h)
MCP4352-502E/XX:
MCP4352T-502E/XX:
MCP4352-103E/XX:
MCP4352T-103E/XX:
MCP4352-503E/XX:
MCP4352T-503E/XX:
MCP4352-104E/XX:
MCP4352T-104E/XX:
5 k 14-LD Device
T/R, 5 k14-LD Device
10 k, 14-LD Device
T/R, 10 k, 14-LD Device
50 k, 14-LD Device
T/R, 50 k, 14-LD Device
100 k, 14-LD Device
T/R, 100 k,
14-LD Device
XX
= ST for 14/20-lead TSSOP
= ML for 20-lead QFN
DS22242A-page 85
MCP433X/435X
NOTES:
DS22242A-page 86
 2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
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dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
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SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-061-4
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
 2010 Microchip Technology Inc.
DS22242A-page 87
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Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
01/05/10
DS22242A-page 88
 2010 Microchip Technology Inc.