NB6L239 2.5 V / 3.3 V Any Differential Clock IN to Differential LVPECL OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider http://onsemi.com Features The NB6L239 is a high−speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; 1/2/4/8 and 2/4/8/16. Both divider circuits drive a pair of differential LVPECL outputs. (More device information on page 7). • Maximum Clock Input Frequency, 3.0 GHz • Input Compatibility with LVDS/LVPECL/CML/HSTL • Rise/Fall Time 70 ps Typical • < 10 ps Typical Output−to−Output Skew • Ex. 622 MHz Input Generates 38.8 MHz to 622 MHz Outputs • Internal 50 Termination Provided • Random Clock Jitter < 1 ps RMS • Divide−by−1 Edge of QA Aligned to QB Divided Output • Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V • Master Reset for Synchronization of Multiple Chips • VBBAC Reference Output • Synchronous Output Enable/Disable MARKING DIAGRAM* Bottom View QFN−16 MN SUFFIX CASE 485G XXXX A L Y W XXXX XXXX ALYW = Device Code = Assembly Location = Wafer Lot = Year = Work Week *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. SELA0 SELA1 QA CLK QA VT CLK QB QB EN SELB0 SELB1 + MR Figure 1. Simplified Logic Diagram Semiconductor Components Industries, LLC, 2004 April, 2004 − Rev. 0 1 Publication Order Number: NB6L239/D NB6L239 MR 16 VT 1 CLK 2 SELA0 SELA1 VCC 15 14 13 12 QA 11 QA NB6L239 CLK 3 10 QB VBBAC 4 9 QB 5 EN 6 7 8 SELB0 SELB1 VEE Exposed Pad (EP) Figure 2. Pinout: QFN−16 (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 VT 2 CLK LVPECL, CML, LVDS, HSTL Input Noninverted Differential CLOCK Input. 3 CLK LVPECL, CML, LVDS, HSTL Input Inverted Differential CLOCK Input. 4 VBBAC 5 EN* LVCMOS/LVTTL Input Synchronous Output Enable 6 SELB0* LVCMOS/LVTTL Input Clock Divide Select Pin 7 SELB1* LVCMOS/LVTTL Input Clock Divide Select Pin 8 VEE Power Supply Negative Supply Voltage 9 QB LVPECL Output Inverted Differential Output. Typically terminated with 50 resistor to VTT. 10 QB LVPECL Output Noninverted Differential Output. Typically terminated with 50 resistor to VTT. 11 QA LVPECL Output Inverted Differential Output. Typically terminated with 50 resistor to VTT. 12 QA LVPECL Output Noninverted Differential Output. Typically terminated with 50 resistor to VTT. 13 VCC Power Supply Positive Supply Voltage. 14 SELA1* LVCMOS/LVTTL Input Clock Divide Select Pin 15 SELA0* LVCMOS/LVTTL Input Clock Divide Select Pin 16 MR** LVCMOS/LVTTL Input Master Reset Asynchronous, Default Open High, Asserted LOW EP Power Supply (OPT) Internal 100 Center−Tapped Termination Pin for CLK and CLK. Output Voltage Reference for Capacitor Coupled Inputs, Only. The Exposed Pad on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to VEE on the PC board. *Pins will default LOW when left OPEN. **Pins will default HIGH when left OPEN. http://onsemi.com 2 NB6L239 + SELA0 VCC SELA1 A 4 CLK VT 1 2 50 R 8 QA QA 50 CLK R 2 4 B 8 QB QB 16 EN SELB0 SELB1 VEE + MR VBBAC Figure 3. Logic Diagram Table 2. FUNCTION TABLES CLK EN* MR** X L H X H H L FUNCTION Divide Hold Q Reset Q Table 3. CLOCK DIVIDE SELECT, QA OUTPUTS SELA1* SELA0* L L H H L H L H QA Outputs Divide by 1 Divide by 2 Divide by 4 Divide by 8 Table 4. CLOCK DIVIDE SELECT, QB OUTPUTS SELB1* SELB0* L L H H L H L H QB Outputs Divide by 2 Divide by 4 Divide by 8 Divide by 16 = Low−to−High Transition = High−to−Low Transition X = Don’t Care *Pins will default LOW when left OPEN. **Pins will default HIGH when left OPEN. http://onsemi.com 3 NB6L239 Table 5. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection 75 k 75 k Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating > 1500 V > 150 V > 1000 V Level 1 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 367 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Units 3.6 V 3.6 V 50 100 mA mA ± 0.5 mA −40 to +85 °C VCC Positive Mode Power Supply VEE = 0 V VI Input Voltage VEE = 0 V Iout Output Current Continuous Surge IBB VBBAC Sink/Source TA Operating Temperature Range Tstg Storage Temperature Range −65 to +150 °C JA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm 41.6 35.2 °C/W °C/W JC Thermal Resistance (Junction−to−Case) Standard Board 4.0 °C/W Tsol Wave Solder < 3 sec @ 248°C 265 °C VEE VI VCC Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. http://onsemi.com 4 NB6L239 Table 6. DC CHARACTERISTICS, CLOCK INPUTS, LVPECL OUTPUTS (VCC = 2.375 V to 3.465 V, VEE = 0 V) −40C Symbol 85°C Min Typ Max Min Typ Max Min Typ Max Unit 30 40 50 30 40 50 30 40 50 mA Output HIGH Voltage (Notes 2, 3) VCC = 3.3 V VCC = 2.5 V VCC−1150 VCC−1060 VCC−950 VCC−1100 VCC−1015 VCC − 900 VCC−1050 VCC −980 VCC − 850 mV 2150 1350 2240 1440 2350 1550 2200 1400 2285 1485 2400 1600 2250 1450 2320 1520 2450 1650 Output LOW Voltage (Notes 2, 3) VCC = 3.3 V VCC = 2.5 V VCC−1870 VCC−1760 VCC−1630 VCC−1820 VCC−1700 VCC−1580 VCC−1770 VCC−1660 VCC−1530 1430 630 1540 740 1670 870 1480 680 1600 800 1720 920 1530 730 1640 840 1770 970 Characteristic IEE Power Supply Current VOH VOL 25C mV DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 7, 10) Vth Input Threshold Reference Voltage (Note 4) 100 VCC − 100 100 VCC − 100 100 VCC − 100 mV VIH Single−ended Input HIGH Voltage Vth + 100 VCC Vth + 100 VCC Vth + 100 VCC mV VIL Single−ended Input LOW Voltage VEE Vth − 100 VEE Vth − 100 VEE Vth − 100 mV VBBAC Output Voltage Reference @ 100 A (Note 7) VCC = 3.3 V VCC = 2.5 V mV VCC−1460 VCC−1330 VCC−1200 VCC−1460 VCC−1340 VCC−1200 VCC−1460 VCC−1350 VCC−1200 1840 1040 1970 1170 2100 1300 1840 1040 1960 1160 2100 1300 1840 1040 1950 1150 2100 1300 DIFFERENTIAL INPUT DRIVEN DIFFERENTIALLY (Figures 8, 9, 11) (Note 6) VIHD Differential Input HIGH Voltage 100 VCC 100 VCC 100 VCC mV VILD Differential Input LOW Voltage VEE VCC – 100 VEE VCC – 100 VEE VCC – 100 mV VCMR Input Common Mode Range (Differential Cross−point Voltage) (Note 5) 50 VCC – 50 50 VCC – 50 50 VCC – 50 mV VID Differential Input Voltage (VIHD(CLK) − VILD(CLK)) and (VIHD(CLK)−VILD(CLK)) 100 VCC − VEE 100 VCC − VEE 100 VCC − VEE mV RTIN Internal Input Termination Resistor 45 55 45 55 45 55 50 50 50 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. 3. Outputs loaded with 50 to VCC – 2.0 V for proper operation. 4. Vth is applied to the complementary input when operating in single−ended mode. 5. VCMRMIN varies 1:1 with VEE, VCMRMAX varies 1:1 with VCC. 6. Input and output voltage swing is a single−ended measurement operating in differential mode. 7. VBBAC used to rebias capacitor−coupled inputs only (see Figures 16 and 17). http://onsemi.com 5 NB6L239 Table 7. DC CHARACTERISTICS, LVTTL/LVCMOS INPUTS (VCC = 2.375 V to 3.465 V, VEE = 0 V, TA = −40°C to +85°C) Symbol Characteristic Min Typ Max Unit VIH Input HIGH Voltage (LVCMOS/LVTTL) 2.0 VCC V VIL Input LOW Voltage (LVCMOS/LVTTL) VEE 0.8 V IIH Input HIGH Current −150 150 A IIL Input LOW Current −150 150 A NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. Table 8. AC CHARACTERISTICS VCC = 2.375 V to 3.465 V; VEE = 0 V (Note 8) −40°C Symbol Min Characteristic 25°C Typ fin Maximum Input CLOCK Frequency VOUTPP Output Voltage Amplitude (Notes 10, 11) QA(2, 4, 8), QB(n) fin 3.0 GHz QA(1), QB(n) fin 2.5 GHz QA(1), QB(n) 2.5 GHz < fin 3.0 GHz 450 450 300 650 650 650 tPLH, tPHL Propagation Delay to Output Differential @ 50 MHz 370 330 470 370 tRR Reset Recovery 0 ts Setup Time @ 50 MHz EN, CLK SELA/B, CLK th Hold Time @ 50 MHz CLK, EN CLK, SELA/B tskew Within−Device Skew @ 50 MHz Device−to−Device Skew Duty Cycle Skew tPW Minimum Pulse Width tJITTER RMS Random Clock Jitter (See Figure 20. Fmax/JITTER) VINPP Input Voltage Swing (Differential Configuration) (Note 10) 100 tr tf Output Rise/Fall Times @ 50 MHz (20% − 80%) 30 Max Min Typ 3.0 CLK, Qn MR, Qn Min Typ Max Unit 3.0 GHz mV 650 630 650 370 330 470 380 −90 0 0 0 −60 −300 150 700 65 200 570 430 5 25 25 450 450 200 650 610 650 400 330 500 400 −90 0 −90 ps 0 0 −60 −300 0 0 −60 −300 ps 150 700 65 200 150 700 65 200 ps 30 80 40 550 5 30 30 570 430 30 90 45 550 100 120 30 35 90 45 65 VCC −VEE 100 120 30 ps ps ps <1 VCC −VEE 60 6 30 30 600 480 550 <1 Qn, Qn Max 3.0 450 450 250 (Note 9) (Note 9) (Note 9) MR 85°C 70 <1 ps VCC −VEE mV 120 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Measured using a 750 mV, 50% duty cycle clock source. All loading with 50 to VCC − 2.0 V. 9. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. 10. Input and output voltage swing is a single−ended measurement operating in differential mode. 11. Output Voltage Amplitude (VOHCLK − VOLCLK) at input CLOCK frequency, fin. The output frequency, fout, is the input CLOCK frequency divided by n, fout = fin n. Input CLOCK frequency is 3.0 GHz. http://onsemi.com 6 NB6L239 Application Information single−ended input CLOCK signals. For the The NB6L239 is a high−speed, low skew clock divider capacitor−coupled CLK and/or CLK inputs, VBBAC should with two divider circuits, each having selectable clock divide ratios; 1/2/4/8 and 2/4/8/16. Both divider be connected to the VT pin and bypassed to ground with a circuits drive a pair of differential LVPECL outputs. The 0.01 F capacitor. Inputs CLK and CLK must be signal internal dividers are synchronous to each other. Therefore, driven or auto oscillation may result. the common output edges are precisely aligned. The common enable (EN) is synchronous so that the The NB6L239 clock inputs can be driven by a variety of internal divider flip−flops will only be enabled/disabled differential signal level technologies including LVDS, when the internal clock is in the LOW state. This avoids any LVPECL, HSTL, or CML. The differential clock input chance of generating a runt pulse on the internal clock when buffer employs a pair of internal 50 termination resistors the device is enabled/disabled, as can happen with an in a 100 center−tapped configuration and accessible via asynchronous control. The internal enable flip−flop is the VT pin. This feature provides transmission line clocked on the falling edge of the input clock. Therefore, all termination on−chip, at the receiver end, eliminating associated specification limits are referenced to the negative external components. The VBBAC reference output can be edge of the clock input. used to rebias capacitor−coupled differential or MR CLK Q (÷1) Q (÷2) Q (÷4) Q (÷8) Q (÷16) Figure 4. Timing Diagram CLK tRR tRR MR Q (÷n) Figure 5. Master Reset Timing Diagram NOTE: On the rising edge of MR, Q goes HIGH after the first rising edge of CLK. Internal Clock Disabled Internal Clock Enabled CLK Q (÷n) EN Figure 6. Output Enable Timing Diagrams The EN signal will “freeze” the internal divider flip−flops on the first falling edge of CLK after its assertion. The internal divider flip−flops will maintain their state during the freeze. When EN is deasserted (LOW), and after the next falling edge of CLK, then the internal divider flip−flops will “unfreeze” and continue to their next state count with proper phase relationships. http://onsemi.com 7 NB6L239 CLK CLK VIH Vth VIL CLK CLK Figure 8. Differential Inputs Driven Differentially Vth Figure 7. Differential Input Driven Single−Ended CLK CLK VID = |VIHD(CLK) − VILD(CLK)| VIHD VILD Figure 9. Differential Inputs Driven Differentially VCC Vthmax VIHmax CLK VCC VCMmax VILmax VIHDmax VILDmax VCMR Vth VIHmin Vthmin VEE CLK VCMmin VILmin VEE Figure 10. Vth Diagram VIHDmin VILDmin Figure 11. VCMR Diagram http://onsemi.com 8 NB6L239 VCC VCC VCC Zo = 50 LVPECL Driver VT = VCC − 2.0 V NB6L239 CLK Zo = 50 50 LVDS Driver VEE 50 VEE Figure 13. LVDS Interface VCC VCC NB6L239 CLK VCC Zo = 50 50 CML Driver 50 VEE 50 VEE Figure 15. Standard 50 Load HSTL Interface VCC VCC NB6L239 CLK VCC Zo = 50 50 Differential Driver VEE NB6L239 CLK 50 Single−Ended Driver VT = VBBAC* 50 Zo = 50 CLK VEE Figure 14. Standard 50 Load CML Interface Zo = 50 VT =VEE Zo = 50 CLK VEE VCC NB6L239 CLK 50 HSTL Driver VT = VCC Zo = 50 CLK VEE Figure 12. LVPECL Interface Zo = 50 VT = OPEN Zo = 50 CLK VEE VCC NB6L239 CLK 50 50 Zo = 50 VCC CLK VT = VBBAC* 50 CLK VEE VEE Figure 16. Capacitor−Coupled Differential Interface (VT Connected to VBBAC) VEE Figure 17. Capacitor−Coupled Single−Ended Interface (VT Connected to VBBAC) *VBBAC bypassed to ground with a 0.01 F capacitor. http://onsemi.com 9 800 8 700 7 600 6 500 5 400 4 300 3 200 2 100 1 JITTEROUT ps (RMS) VOUTPP, OUTPUT VOLTAGE AMPLITUDE (mV) (TYPICAL) NB6L239 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 0 0 1 2 3 0 fout, CLOCK OUTPUT FREQUENCY (GHz) Figure 18. Output Voltage Amplitude (VOUTPP)/RMS Jitter versus Clock Output Frequency at Ambient Temperature (Typical) (fout = fin n). CLK VINPP = VIH(CLK) − VIL(CLK) CLK Q VOUTPP = VOH(Q) − VOL(Q) Q tPHL tPLH Figure 19. AC Reference Measurement NB6L239 Q Zo = 50 D Receiver Device Driver Device Q Zo = 50 D 50 50 VTT VTT = VCC − 2.0 V Figure 20. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) http://onsemi.com 10 NB6L239 ORDERING INFORMATION Package Shipping† NB6L239MN QFN−16 123 Units / Rail NB6L239MNR2 QFN−16 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPS I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1642/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 11 NB6L239 PACKAGE DIMENSIONS QFN−16 CASE 485G−01 ISSUE A −X− A NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION D APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. M −Y− DIM A B C D E F G H J K L M N P R B N 0.25 (0.010) T 0.25 (0.010) T MILLIMETERS MIN MAX 3.00 BSC 3.00 BSC 0.80 1.00 0.23 0.28 1.75 1.85 1.75 1.85 0.50 BSC 0.875 0.925 0.20 REF 0.00 0.05 0.35 0.45 1.50 BSC 1.50 BSC 0.875 0.925 0.60 0.80 INCHES MIN MAX 0.118 BSC 0.118 BSC 0.031 0.039 0.009 0.011 0.069 0.073 0.069 0.073 0.020 BSC 0.034 0.036 0.008 REF 0.000 0.002 0.014 0.018 0.059 BSC 0.059 BSC 0.034 0.036 0.024 0.031 J R C 0.08 (0.003) T −T− K SEATING PLANE E H G L 5 8 4 9 1 12 F 16 D 13 P NOTE 3 0.10 (0.004) M T X Y ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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