AD ADS8365 ® S8 36 5 www.ti.com.................................................................................................................................................... SBAS362C – AUGUST 2006 – REVISED MARCH 2008 16-Bit, 250kSPS, 6-Channel, Simultaneous Sampling SAR ANALOG-TO-DIGITAL CONVERTERS FEATURES 1 • • • • • 2 • DESCRIPTION Six Input Channels Fully Differential Inputs Six Independent 16-Bit ADCs 4µs Total Throughput per Channel Low Power: 200mW in Normal Mode 5mW in Nap Mode 50µW in Power-Down Mode TQFP-64 Package Package The ADS8365 includes six, 16-bit, 250kSPS analog-to-digital converters (ADCs) with six fully differential input channels grouped into three pairs for high-speed simultaneous signal acquisition. Inputs to the sample-and-hold amplifiers are fully differential and are maintained differential to the input of the ADC. This architecture provides excellent common-mode rejection of 80dB at 50kHz, which is important in high-noise environments. The ADS8365 offers a flexible, high-speed parallel interface with a direct address mode, a cycle, and a FIFO mode. The output data for each channel is available as a 16-bit word. APPLICATIONS • • • Motor Control Multi-Axis Positioning Systems 3-Phase Power Control CH A0+ CH A0- CDAC S/H Amp Comp SAR HOLDA CH A1+ Interface CDAC CH A1S/H Amp A0 A1 A2 Comp Conversion and Control CH B0+ ADD NAP CDAC CH B0S/H Amp RD WR CS Comp FD EOC CLK SAR FIFO Register and 6x HOLDB CH B1+ 16 CDAC CH B1- RESET BYTE Comp S/H Amp Data Input/Output CH C0+ CDAC CH C0S/H Amp Comp SAR HOLDC CH C1+ CH C1- CDAC Comp S/H Amp REFIN REFOUT Internal 2.5V Reference 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2008, Texas Instruments Incorporated ADS8365 SBAS362C – AUGUST 2006 – REVISED MARCH 2008.................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT MAXIMUM NO INTEGRAL MISSING LINEARITY CODES ERROR ERROR PACKAGEPACKAGE (LSB) (LSB) LEAD DESIGNATOR ADS8365 (1) ±4 14 TQFP-64 PAG SPECIFIED TEMPERATURE RANGE PACKAGE MARKING –40°C to +85°C ADS8365AI ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS8365IPAG Tray, 160 ADS8365IPAGR Tape and Reel, 1500 For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) Supply voltage, AGND to AVDD Supply voltage, BGND to BVDD ADS8365 UNIT –0.3 to 6 V –0.3 to 6 V Analog input voltage range AGND – 0.3 to AVDD + 0.3 V Reference input voltage range AGND – 0.3 to AVDD + 0.3 V Digital input voltage range BGND – 0.3 to BVDD + 0.3 V ±0.3 V Ground voltage differences, AGND to BGND Voltage differences, BVDD to AGND –0.3 to 6 V Input current to any pin except supply –20 to 20 mA Power dissipation See Dissipation Ratings Table Operating virtual junction temperature range, TJ –40 to +150 °C Operating free-air temperature range, TA –40 to +85 °C Storage temperature range, TSTG –65 to +150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability. DISSIPATION RATINGS BOARD PACKAGE RθJC RθJA DERATING FACTOR ABOVE TA = +25°C Low-K (1) PAG 8.6°C/W 68.5°C/W 14.598mW/°C 1824mW 1168mW 949mW High-K (2) PAG 8.6°C/W 42.8°C/W 23.364mW/°C 2920mW 1869mW 1519mW (1) (2) 2 TA ≤ +25°C POWER RATING TA = +70°C POWER RATING TA = +85°C POWER RATING The JEDEC Low K (1s) board design used to derive this data was a 3-inch x 3-inch, two-layer board with 2-ounce copper traces on top of the board. The JEDEC High K (2s2p) board design used to derive this data was a 3-inch x 3-inch, multilayer board with 1-ounce internal power and ground planes, and 2-ounce copper traces on the top and bottom of the board. Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 ADS8365 www.ti.com.................................................................................................................................................... SBAS362C – AUGUST 2006 – REVISED MARCH 2008 RECOMMENDED OPERATING CONDITIONS Supply voltage, AVDD to AGND MIN NOM MAX UNIT 4.75 5 5.25 V 3.6 V Low-voltage levels 2.7 5V logic levels 4.5 5 5.5 V Reference input voltage 1.5 2.5 2.6 V Operating common-mode signal, –IN 2.2 2.5 2.8 V 0 ±VREF V –40 +125 °C Supply voltage, BVDD to BGND Analog inputs, +IN – (–IN) Operating junction temperature range, TJ ELECTRICAL CHARACTERISTICS: 100kSPS Over recommended operating free-air temperature range at –40°C to +85°C, AVDD = 5V, BVDD = 3V, VREF = internal +2.5V, fCLK = 2MHz, and fSAMPLE = 100kSPS, unless otherwise noted. ADS8365 PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT ±VREF V ANALOG INPUT Full-scale range FSR +IN – (–IN) Operating common-mode signal 2.2 2.8 V Ω Input resistance –IN = VREF 750 Input capacitance –IN = VREF 25 pF Input leakage current –IN = VREF ±1 nA Differential input resistance –IN = VREF 1500 Ω Differential input capacitance –IN = VREF 15 pF At dc 84 dB VIN = ±1.25VPP at 50kHz 80 dB 10 MHz 16 Bits Common-mode rejection ratio Bandwidth CMRR BW FS sinewave, –3dB DC ACCURACY Resolution No missing codes Integral linearity error NMC 14 Bits INL ±1.5 Differential nonlinearity DNL ±1.5 Bipolar offset error VOS ±1 ±2.3 0.2 1 Bipolar offset error match Bipolar offset error drift Gain error Only pair-wise matching TCVOS Gain error drift Only pair-wise matching TCGERR Noise Power-supply rejection ratio PSRR 4.75V < AVDD < 5.25V LSB LSB 0.8 GERR Referenced to VREF Gain error match ±4 mV mV ppm/°C ±0.05 ±0.25 0.005 0.05 %FSR %FSR 2 ppm/°C 60 µVrms –87 dB SAMPLING DYNAMICS Conversion time per ADC Acquisition time tCONV 50kHz ≤ fCLK ≤ 5MHz tAQ fCLK = 5MHz 3.2 320 800 ns Aperture delay 5 Aperture delay matching 100 Aperture jitter (1) 0.05 ns ps 50 Clock frequency µs ps 5 MHz All typical values are at +25°C. Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 3 ADS8365 SBAS362C – AUGUST 2006 – REVISED MARCH 2008.................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: 100kSPS (continued) Over recommended operating free-air temperature range at –40°C to +85°C, AVDD = 5V, BVDD = 3V, VREF = internal +2.5V, fCLK = 2MHz, and fSAMPLE = 100kSPS, unless otherwise noted. ADS8365 PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT AC ACCURACY Total harmonic distortion Spurious-free dynamic range THD VIN = ±2.5VPP at 50kHz –94 dB SFDR VIN = ±2.5VPP at 50kHz 95 dB SNR VIN = ±2.5VPP at 10kHz 88 dB SINAD VIN = ±2.5VPP at 10kHz 87 dB Signal-to-noise ratio Signal-to-noise + distortion Channel-to-channel isolation Effective number of bits ENOB 95 dB 14.3 Bits VOLTAGE REFERENCE OUTPUT Reference voltage output VOUT 2.475 2.5 Initial accuracy Output voltage temperature drift dVOUT/dT f = 0.1Hz to 10Hz, CL = 10µF Output voltage noise Power-supply rejection ratio f = 10Hz to 10kHz, CL = 10µF 2.525 V ±1 % ±20 ppm/°C 40 µVPP 8 µVrms PSRR 60 dB ROUT 2 kΩ 1.25 mA 100 µs Output impedance Short-circuit current ISC Turn-on settling time to 0.1% at CL = 0pF VOLTAGE REFERENCE INPUT Reference voltage input VIN 1.5 Reference input resistance 2.5 2.6 100 Reference input capacitance V MΩ 5 Reference input current pF 1 µA V DIGITAL INPUTS (2) Logic family CMOS High-level input voltage VIH 0.7 × BVDD BVDD + 0.3 Low-level input voltage VIL –0.3 0.3 × BVDD V Input current IIN VI = BVDD or GND ±50 nA Input capacitance CI 5 pF DIGITAL OUTPUTS (2) Logic family CMOS High-level output voltage VOH BVDD = 4.5V, IOH = –100µA Low-level output voltage VOL BVDD = 4.5V, IOL = 100µA High-impedance state output current IOZ CS = BVDD, VI = BVDD or GND Output capacitance CO Load capacitance CL 4.44 V 0.5 V ±50 nA 5 pF 30 pF V DIGITAL INPUTS (3) Logic family LVCMOS High-level input voltage VIH BVDD = 3.6V 2 BVDD + 0.3 Low-level input voltage VIL BVDD = 2.7V –0.3 0.8 V Input current IIN VI = BVDD or GND ±50 nA Input capacitance CI (2) (3) 4 5 pF Applies for 5.0V nominal supply: BVDD (min) = 4.5V and BVDD (max) = 5.5V. Applies for 3.0V nominal supply: BVDD (min) = 2.7V and BVDD (max) = 3.6V. Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 ADS8365 www.ti.com.................................................................................................................................................... SBAS362C – AUGUST 2006 – REVISED MARCH 2008 ELECTRICAL CHARACTERISTICS: 100kSPS (continued) Over recommended operating free-air temperature range at –40°C to +85°C, AVDD = 5V, BVDD = 3V, VREF = internal +2.5V, fCLK = 2MHz, and fSAMPLE = 100kSPS, unless otherwise noted. ADS8365 PARAMETER DIGITAL OUTPUTS TEST CONDITIONS MIN TYP (1) MAX UNIT (4) Logic family LVCMOS High-level output voltage VOH BVDD = 2.7V, IOH = –100µA Low-level output voltage VOL BVDD = 2.7V, IOL = 100µA High-impedance state output current IOZ CS = BVDD, VI = BVDD or GND Output capacitance CO Load capacitance CL BVDD – 0.2 V 0.2 V ±50 nA 5 pF 30 pF 4.75 5.25 V Low-voltage levels 2.7 3.6 V 5V logic levels 4.5 5.5 V 45 mA µA DATA FORMAT Data format Bit DB4 = 1 Binary two's complement Bit DB4 = 0 Straight binary coding POWER SUPPLY Analog supply voltage AVDD Buffer I/O supply voltage BVDD Analog operating supply current AIDD Buffer I/O operating supply current BIDD Power dissipation (4) 38 BVDD = 3V 60 90 BVDD = 5V 100 150 µA BVDD = 3V 190 225 mW BVDD = 5V 190 225 mW Nap mode enabled 5 mW Powerdown enabled 50 µW Applies for 3.0V nominal supply: BVDD (min) = 2.7V and BVDD (max) = 3.6V. Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 5 ADS8365 SBAS362C – AUGUST 2006 – REVISED MARCH 2008.................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: 250kSPS Over recommended operating free-air temperature range at –40°C to +85°C, AVDD = 5V, BVDD = 3V, VREF = internal +2.5V, fCLK = 5MHz, and fSAMPLE = 250kSPS, unless otherwise noted ADS8365 PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT ±VREF V ANALOG INPUT Full-scale range FSR +IN – (–IN) Operating common-mode signal 2.2 2.8 V Ω Input resistance –IN = VREF 750 Input capacitance –IN = VREF 25 pF Input leakage current –IN = VREF ±1 nA Differential input resistance –IN = VREF 1500 Ω Differential input capacitance –IN = VREF 15 pF At dc 84 dB VIN = ±1.25VPP at 50kHz 80 dB 10 MHz 16 Bits Common-mode rejection ratio CMRR Bandwidth BW FS sinewave, –3dB DC ACCURACY Resolution No missing codes NMC Integral linearity error 14 INL Differential nonlinearity DNL Specified for 14 bit Bipolar offset error VOS Bipolar offset error match Bipolar offset error drift TCVOS Gain error drift Only pair-wise matching TCGERR Noise Power-supply rejection ratio PSRR 4.75V < AVDD < 5.25V LSB LSB ±1 ±2.3 0.2 1 0.8 GERR Referenced to VREF Gain error match ±8 ±1.5 Only pair-wise matching Gain error Bits ±3 mV mV ppm/°C ±0.05 ±0.25 0.005 0.05 %FSR %FSR 2 ppm/°C 60 µVrms –87 dB SAMPLING DYNAMICS tCONV 50kHz ≤ fCLK ≤ 5MHz Conversion time per ADC Acquisition time tAQ fCLK = 5MHz 3.2 320 µs 250 kSPS 800 ns Throughput rate Aperture delay 5 Aperture delay matching 100 Aperture jitter ps 50 Clock frequency 0.05 ns ps 5 MHz AC ACCURACY Total harmonic distortion Spurious-free dynamic range THD VIN = ±2.5VPP at 50kHz –94 dB SFDR VIN = ±2.5VPP at 50kHz 95 dB SNR VIN = ±2.5VPP at 10kHz 88 dB SINAD VIN = ±2.5VPP at 10kHz 87 dB Signal-to-noise ratio Signal-to-noise + distortion Channel-to-channel isolation Effective number of bits (1) 6 ENOB 95 dB 14.3 Bits All typical values are at +25°C. Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 ADS8365 www.ti.com.................................................................................................................................................... SBAS362C – AUGUST 2006 – REVISED MARCH 2008 ELECTRICAL CHARACTERISTICS: 250kSPS (continued) Over recommended operating free-air temperature range at –40°C to +85°C, AVDD = 5V, BVDD = 3V, VREF = internal +2.5V, fCLK = 5MHz, and fSAMPLE = 250kSPS, unless otherwise noted ADS8365 PARAMETER TEST CONDITIONS MIN TYP (1) MAX 2.475 2.5 2.525 V ±1 % UNIT VOLTAGE REFERENCE OUTPUT Reference voltage output VOUT Initial accuracy Output voltage temperature drift dVOUT/dT Output voltage noise Power-supply rejection ratio Output impedance Short-circuit current ±20 ppm/°C f = 0.1Hz to 10Hz, CL = 10µF 40 µVPP f = 10Hz to 10kHz, CL = 10µF 8 µVrms PSRR 60 dB ROUT 2 kΩ 1.25 mA 100 µs ISC Turn-on settling time to 0.1% at CL = 0pF VOLTAGE REFERENCE INPUT Reference voltage input VIN 1.5 Reference input resistance 2.5 2.6 100 Reference input capacitance V MΩ 5 Reference input current pF 1 µA V DIGITAL INPUTS (2) Logic family CMOS High-level input voltage VIH 0.7 × BVDD BVDD + 0.3 Low-level input voltage VIL –0.3 0.3 × BVDD V Input current IIN VI = BVDD or GND ±50 nA Input capacitance CI 5 pF DIGITAL OUTPUTS (2) Logic family CMOS High-level output voltage VOH BVDD = 4.5V, IOH = –100µA Low-level output voltage VOL BVDD = 4.5V, IOL = 100µA High-impedance state output current IOZ CS = BVDD, VI = BVDD or GND Output capacitance CO Load capacitance CL 4.44 V 0.5 V ±50 nA 5 pF 30 pF DIGITAL INPUTS (3) Logic family LVCMOS High-level input voltage VIH BVDD = 3.6V 2 BVDD + 0.3 V Low-level input voltage VIL BVDD = 2.7V –0.3 0.8 V Input current IIN VI = BVDD or GND ±50 nA Input capacitance CI 5 pF DIGITAL OUTPUTS (3) Logic family LVCMOS High-level output voltage VOH BVDD = 2.7V, IOH = –100µA Low-level output voltage VOL BVDD = 2.7V, IOL = 100µA High-impedance state output current IOZ CS = BVDD, VI = BVDD or GND Output capacitance CO Load capacitance CL (2) (3) BVDD – 0.2 V 0.2 V ±50 nA 5 pF 30 pF Applies for 5.0V nominal supply: BVDD (min) = 4.5V and BVDD (max) = 5.5V. Applies for 3.0V nominal supply: BVDD (min) = 2.7V and BVDD (max) = 3.6V. Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 7 ADS8365 SBAS362C – AUGUST 2006 – REVISED MARCH 2008.................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: 250kSPS (continued) Over recommended operating free-air temperature range at –40°C to +85°C, AVDD = 5V, BVDD = 3V, VREF = internal +2.5V, fCLK = 5MHz, and fSAMPLE = 250kSPS, unless otherwise noted ADS8365 PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT DATA FORMAT Data format Bit DB4 = 1 Binary two's complement Bit DB4 = 0 Straight binary coding POWER SUPPLY Analog supply voltage AVDD Buffer I/O supply voltage BVDD Analog operating supply current AIDD Buffer I/O operating supply current BIDD Power dissipation 4.75 5.25 V Low-voltage levels 2.7 3.6 V 5V logic levels 4.5 5.5 V 40 48 mA BVDD = 3V 150 225 µA BVDD = 5V 250 375 µA BVDD = 3V 200 240 mW BVDD = 5V 201 241 mW Nap mode enabled 5 mW Powerdown enabled 50 µW EQUIVALENT INPUT CIRCUIT AVDD BVDD RON 750W AIN AGND Equivalent Analog Input Circuit 8 Diode Turn-on Voltage: 0.35V C(SAMPLE) 20pF DIN BGND Equivalent Digital Input Circuit Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 ADS8365 www.ti.com.................................................................................................................................................... SBAS362C – AUGUST 2006 – REVISED MARCH 2008 PIN CONFIGURATION BVDD BGND 54 RESET 55 A2 56 ADD 57 A0 58 A1 59 HOLDB 60 HOLDA HOLDC 61 AGND 62 AVDD 63 REFIN 64 REFOUT CH A0- CH A0+ PAG PACKAGE TQFP-64 (TOP VIEW) 53 52 51 50 49 CH A1- 1 48 D0 CH A1+ 2 47 D1 AVDD 3 46 D2 AGND 4 45 D3 SGND 5 44 D4 CH B0+ 6 43 D5 CH B0- 7 42 D6 AVDD 8 41 D7 AGND 9 40 D8 ADS8365 34 D14 33 D15 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 BGND 17 CS 15 16 WR SGND CH C0+ RD D13 CLK 35 FD 14 EOC D12 AGND BVDD D11 36 BGND 37 13 BYTE 12 AVDD AVDD CH B1+ AGND D10 NAP D9 38 CH C1+ 39 11 CH C0- 10 CH C1- SGND CH B1- TERMINAL FUNCTIONS TERMINAL NO. I/O (1) CH A1– 1 AI Inverting input channel A1 CH A1+ 2 AI Noninverting input channel A1 AVDD 3 P Analog power supply AGND 4 P Analog ground SGND 5 P Signal Ground CH B0+ 6 AI Noninverting input channel B0 CH B0– 7 AI Inverting input channel B0 AVDD 8 P Analog power supply AGND 9 P Analog ground SGND 10 P Signal ground CH B1– 11 AI Inverting input channel B1 CH B1+ 12 AI Noninverting input channel B1 AVDD 13 P Analog power supply AGND 14 P Analog ground SGND 15 P Signal ground CH C0+ 16 AI Noninverting input channel C0 CH C0– 17 AI Inverting input channel C0 CH C1– 18 AI Inverting input channel C1 NAME (1) DESCRIPTION AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, DIO = Digital Input/Output, and P = Power Supply Connection. Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 9 ADS8365 SBAS362C – AUGUST 2006 – REVISED MARCH 2008.................................................................................................................................................... www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL NO. I/O (1) CH C1+ 19 AI Noninverting input channel C1 NAP 20 DI Nap mode.Low level or unconnected = normal operation; high level = Nap mode. AGND 21 P Analog ground AVDD 22 P +5V power supply BYTE 23 DI 2 x 8 output capability (active high) BVDD 24 P Power supply for digital interface from 3V to 5V BGND 25 P Buffer digital ground FD 26 DO First data (A0 data) EOC 27 DO End of conversion (active low) CLK 28 DI An external CMOS compatible clock can be applied to the CLK input to synchronize the conversion process to an external source. RD 29 DI Read (active low) WR 30 DI Write (active low) CS 31 DI Chip select (active low) BGND 32 P Buffer digital ground D15 33 DO Data bit 15 (MSB) D14 34 DO Data bit 14 D13 35 DO Data bit 13 D12 36 DO Data bit 12 D11 37 DO Data bit 11 D10 38 DO Data bit 10 D9 39 DO Data bit 9 D8 40 DO Data bit 8 D7 41 DIO Data bit 7 (software input 7) D6 42 DIO Data bit 6 (software input 6) D5 43 DIO Data bit 5 (software input 5) D4 44 DIO Data bit 4 (software input 4) D3 45 DIO Data bit 3 (software input 3) D2 46 DIO Data bit 2 (software input 2) D1 47 DIO Data bit 1 (software input 1) D0 48 DIO Data bit 0 (software input 0) (LSB) BGND 49 P Buffer digital ground BVDD 50 P Power supply for digital interface from 3V to 5V RESET 51 DI Global reset (active low) ADD 52 DI Address mode select A2 53 DI Address line 3 A1 54 DI Address line 2 A0 55 DI Address line 1 HOLDA 56 DI Hold command A (active low) HOLDB 57 DI Hold command B (active low) HOLDC 58 DI Hold command C (active low) AVDD 59 P Analog power supply AGND 60 P Analog ground REFOUT 61 AO Reference output; attach 0.1µF and 10µF capacitors REFIN 62 AI Reference input CH A0+ 63 AI Noninverting input channel A0 CH A0– 64 AI Inverting input channel A0 NAME 10 DESCRIPTION Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 ADS8365 www.ti.com.................................................................................................................................................... SBAS362C – AUGUST 2006 – REVISED MARCH 2008 TIMING INFORMATION tC1 CLK 1 2 16 17 18 20 19 1 2 tW1 CONVERSION tCONV tD1 ACQUISITION tACQ HOLDX tW3 tW2 EOC CS tD4 tD5 tW6 RD tW5 tD7 tD6 D15–D8 Bits 15–8 Bits 15–8 D7–D0 Bits 7–0 Bits 7–0 BYTE Figure 1. Read and Convert Timing CS WR WR or CS DB7:0 tD10 tW6 tD11 Figure 2. Write Timing Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 11 ADS8365 SBAS362C – AUGUST 2006 – REVISED MARCH 2008.................................................................................................................................................... www.ti.com TIMING CHARACTERISTICS (1) (2) (3) (4) Over recommended operating free-air temperature range, TMIN to TMAX, AVDD = 5V, REFIN = REFOUT, VREF = internal +2.5V, fCLK = 5MHz, fSAMPLE = 250kSPS, and BVDD = 2.7 to 5V, unless otherwise noted, SYMBOL DESCRIPTION MAX UNIT tACQ Acquisition time 0.8 µs tCONV Conversion time 3.2 µs tC1 tD1 Cycle time of CLK (5) ns 10 ns BVDD = 5V 20 ns BVDD = 3V 40 ns tD4 Delay time of falling edge of RD after falling edge of CS 0 ns tD5 Delay time of rising edge of CS after rising edge of RD 0 ns BVDD = 5V 40 ns BVDD = 3V 60 ns BVDD = 5V 5 ns BVDD = 3V 10 ns BVDD = 5V 50 ns BVDD = 3V 60 ns BVDD = 5V 10 ns BVDD = 3V 20 ns BVDD = 5V 10 ns BVDD = 3V 20 ns BVDD = 5V 10 ns BVDD = 3V 20 ns 60 ns BVDD = 5V 15 ns BVDD = 3V 30 ns BVDD = 5V 20 ns BVDD = 3V 30 ns BVDD = 5V 20 ns BVDD = 3V 40 ns BVDD = 5V 30 ns BVDD = 3V 40 ns BVDD = 5V 50 ns BVDD = 3V 70 ns Delay time of data valid after falling edge of RD Delay time of data hold from rising edge of RD tD8 Delay time of RD high after CS low tD9 Delay time of RD low after address setup tD10 Delay time of data valid to WR low tD11 Delay time of WR or CS high to data release tW1 Pulse width CLK high time or low time tW2 Pulse width of HOLDX high time to be recognized again tW3 Pulse width of HOLDX low time tW4 12 200 Delay time of first hold after RESET tD7 (5) Delay time of rising edge of CLK after falling edge of HOLDX TYP tD2 tD6 (1) (2) (3) (4) MIN Pulse width of RESET tW5 Pulse width of RD high time tW6 Pulse width of RD and CS both low time Assured by design. All input signals are specified with rise time and fall time = 5ns (10% to 90% of BVDD ) and timed from a voltage level of (VIL + VIH )/2. See Figure 1. BYTE is asynchronous; when BYTE is 0, bits 15 to 0 appear at DB15 to DB0. When BYTE is 1, bits 15 to 8 appear on DB7 to DB0. RD may remain LOW between changes in BYTE. Only important when synchronization to clock is important. Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 ADS8365 www.ti.com.................................................................................................................................................... SBAS362C – AUGUST 2006 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS At TA = +25°C, AVDD = +5V, BVDD = +3V, VREF = internal +2.5V, fCLK = 5MHz, and fSAMPLE = 250kSPS, unless otherwise noted. INTEGRAL LINEARITY ERROR vs CODE (100kSPS) DIFFERENTIAL LINEARITY ERROR vs CODE (100kSPS) 2.0 4 3 1.5 1.0 1 DNL (LSB) INL (LSB) 2 0 1 0.5 0 2 -0.5 3 4 -1.0 0 Figure 4. MINIMUM AND MAXIMUM INL OF ALL CHANNELS vs TEMPERATURE (100kSPS) MINIMUM AND MAXIMUM INL OF ALL CHANNELS vs TEMPERATURE (250kSPS) 1.5 1.5 1.0 1.0 Max INL (LSB) 0 -0.5 -1.0 Max 0.5 Min 0 -0.5 -1.0 -1.5 -1.5 -2.0 -2.0 -2.5 Min -2.5 -50 -25 0 25 50 Temperature (°C) 75 100 -50 -25 0 25 50 Temperature (°C) 75 100 Figure 5. Figure 6. MINIMUM AND MAXIMUM DNL OF ALL CHANNELS vs TEMPERATURE (100kSPS) MINIMUM AND MAXIMUM DNL OF ALL CHANNELS vs TEMPERATURE (250kSPS) 3.0 3.0 2.5 2.5 Max 2.0 Max 2.0 1.5 DNL (LSB) 1.5 DNL (LSB) 8192 16384 24576 32768 40960 49152 57344 65535 Code Figure 3. 0.5 INL (LSB) 0 8192 16384 24576 32768 40960 49152 57344 65535 Code 1.0 0.5 0 -0.5 0.5 0 -0.5 Min -1.0 1.0 Min -1.0 -1.5 -1.5 -2.0 -2.0 -50 -25 0 25 50 Temperature (°C) 75 100 -50 Figure 7. -25 0 25 50 Temperature (°C) 75 100 Figure 8. Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 13 ADS8365 SBAS362C – AUGUST 2006 – REVISED MARCH 2008.................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +5V, BVDD = +3V, VREF = internal +2.5V, fCLK = 5MHz, and fSAMPLE = 250kSPS, unless otherwise noted. FREQUENCY SPECTRUM (16384 point FFT, fIN = 45kHz, –0.2dB) 0 0 -20 -20 -40 -40 Amplitude (dB) Amplitude (dB) FREQUENCY SPECTRUM (16384 point FFT, fIN = 10kHz, –0.2dB) -60 -80 -100 -80 -100 -120 -120 -140 -140 -160 -160 0 25 50 75 Frequency (kHz) 100 125 0 25 50 75 Frequency (kHz) 100 Figure 9. Figure 10. SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY (ALL CHANNELS) SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (ALL CHANNELS) 100 125 120 115 SFDR and THD (dB) 95 SNR and SINAD (dB) -60 90 SNR 85 SINAD 80 75 110 SFDR 105 THD 100 95 90 85 70 80 1 10 Frequency (kHz) 100 1 10 Frequency (kHz) 100 Figure 11. Figure 12. SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-NOISE + DISTORTION vs TEMPERATURE (ALL CHANNELS) SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs TEMPERATURE (ALL CHANNELS) 90.0 107 89.5 105 SFDR and THD (dB) SINAD and SNR (dB) 89.0 88.5 88.0 87.5 SNR 87.0 86.5 SINAD 86.0 SFDR 103 101 THD 99 97 85.5 85.0 95 -50 -25 0 25 50 Temperature (°C) 75 100 -50 Figure 13. 14 -25 0 25 50 Temperature (°C) 75 100 Figure 14. Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 ADS8365 www.ti.com.................................................................................................................................................... SBAS362C – AUGUST 2006 – REVISED MARCH 2008 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, AVDD = +5V, BVDD = +3V, VREF = internal +2.5V, fCLK = 5MHz, and fSAMPLE = 250kSPS, unless otherwise noted. OFFSET OF ALL CHANNELS vs TEMPERATURE OFFSET MATCHING OF CHANNEL PAIRS vs TEMPERATURE 0.25 -0.8 0.20 0.15 C0 A0 A1 -1.0 C1 -1.1 Offset Matching (mV) Offset (mV) -0.9 B0 -1.2 B1 0.10 0.05 B 0 A -0.05 -0.10 -0.15 -1.3 C -0.20 -1.4 -0.25 -50 -25 0 25 50 Temperature (°C) 75 -50 0 -25 25 50 Temperature (°C) 75 100 Figure 15. Figure 16. GAIN ERROR OF ALL CHANNELS vs TEMPERATURE GAIN-ERROR MATCHING OF CHANNEL PAIRS vs TEMPERATURE 100 100 B1 A0 B0 A1 50 Gain Match (ppm FSR) Gain Error (ppm FSR) 100 0 C1 C0 -50 -100 -150 50 B C 0 A -50 -100 -150 -50 -25 0 25 50 Temperature (°C) 75 100 -50 -25 0 25 50 Temperature (°C) Figure 17. Figure 18. REFERENCE VOLTAGE OUTPUT vs TEMPERATURE ANALOG SUPPLY CURRENT vs TEMPERATURE 2.498 75 100 42 40 250kSPS 38 IDDA (mA) VREFOUT (V) 2.496 2.494 36 100kSPS 34 2.492 32 2.490 30 -50 -25 0 25 50 Temperature (°C) 75 100 -50 Figure 19. -25 0 25 50 Temperature (°C) 75 100 Figure 20. Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 15 ADS8365 SBAS362C – AUGUST 2006 – REVISED MARCH 2008.................................................................................................................................................... www.ti.com INTRODUCTION The ADS8365 is a high-speed, low-power, six-channel simultaneous sampling and converting, 16-bit ADC that operates from a single +5V supply. The input channels are fully differential with a typical common-mode rejection of 80dB. The ADS8365 contains six 4µs successive approximation ADCs, six differential sample-and-hold amplifiers, an internal +2.5V reference with REFIN and REFOUT pins, and a high-speed parallel interface. There are six analog inputs that are grouped into three channel pairs (A, B, and C). There are six ADCs, one for each input that can be sampled and converted simultaneously, thus preserving the relative phase information of the signals on both analog inputs. Each pair of channels has a hold signal (HOLDA, HOLDB, and HOLDC) to allow simultaneous sampling on each channel pair, on four or on all six channels. The part accepts a differential analog input voltage in the range of –VREF to +VREF, centered on the common-mode voltage (see the Analog Input section). The ADS8365 also accepts bipolar input ranges when a level shift circuit is used at the front end (see Figure 26). A conversion is initiated on the ADS8365 by bringing the HOLDX pin low for a minimum of 20ns. HOLDX low places the sample-and-hold amplifiers of the X channels in the hold state simultaneously and the conversion process is started on each channel. The EOC output goes low for half a clock cycle when the conversion is latched into the output register. The data can be read from the parallel output bus following the conversion by bringing both RD and CS low. Conversion time for the ADS8365 is 3.2µs when a 5MHz external clock is used. The corresponding acquisition time is 0.8µs. To achieve the maximum output data rate (250kSPS), the read function can be performed during the next conversion. NOTE: This mode of operation is described in more detail in the Timing and Control section of this data sheet. 5ns. The average delta of repeated aperture delay values (also known as aperture jitter) is typically 50ps. These specifications reflect the ability of the ADS8365 to capture ac input signals accurately at the exact same moment in time. REFERENCE Under normal operation, REFOUT (pin 61) can be directly connected to REFIN (pin 62) to provide an internal +2.5V reference to the ADS8365. The ADS8365 can operate, however, with an external reference in the range of 1.5V to 2.6V, for a corresponding full-scale range of 3.0V to 5.2V, as long as the input does not exceed the AVDD + 0.3V limit. The reference output of the ADS8365 has an impedance of 2kΩ. The high impedance reference input can be driven directly. For an external resistive load, an additional buffer is required. A load capacitance of 0.1µF to 10µF should be applied to the reference output to minimize noise. If an external reference is used, the three input buffers provide isolation between the external reference and the CDACs. These buffers are also used to recharge all the capacitors of all CDACs during conversion. ANALOG INPUT The analog input is bipolar and fully differential. There are two general methods of driving the analog input of the ADS8365: single-ended or differential, as shown in Figure 21 and Figure 22. When the input is single-ended, the –IN input is held at the common-mode voltage. The +IN input swings around the same common voltage and the peak-to-peak amplitude is the (common-mode + VREF) and the (common-mode –VREF). The value of VREF determines the range over which the common-mode voltage may vary (see Figure 23). SAMPLE AND HOLD Single-Ended Input The sample-and-hold amplifiers on the ADS8365 allow the ADCs to accurately convert an input sine wave of full-scale amplitude to 16-bit resolution. The input bandwidth of the sample-and-hold amplifiers is greater than the Nyquist rate (Nyquist = 1/2 of the sampling rate) of the ADC, even when the ADC is operated at its maximum throughput rate of 250kSPS. The typical small-signal bandwidth of the sample-and-hold amplifiers is 10MHz. Typical aperture delay time (or the time it takes for the ADS8365 to switch from the sample to the hold mode following the negative edge of the HOLDX signal) is -VREF to +VREF peak-to-peak ADS8365 Common Voltage Differential Input VREF peak-to-peak Common Voltage ADS8365 VREF peak-to-peak Figure 21. Methods of Driving the ADS8365 Single-Ended or Differential 16 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 ADS8365 www.ti.com.................................................................................................................................................... SBAS362C – AUGUST 2006 – REVISED MARCH 2008 +IN CM +VREF +VREF CM Voltage -IN = CM Voltage -VREF t CM -VREF CM +1/2VREF Single-Ended Inputs +IN +VREF CM Voltage -VREF CM -1/2VREF -IN t Differential Inputs NOTES: Common−mode voltage (Differential mode) = (+IN) ) (−IN) . Common−mode voltage (Single−ended mode) = −IN 2 The maximum differential voltage between +IN and –IN of the ADS8365 is VREF. See Figure 23 and Figure 24 for a further explanation of the common voltage range for single-ended and differential inputs. Figure 22. Using the ADS8365 in the Single-Ended and Differential Input Modes 5 AVDD = 5V Common-Mode Voltage Range (V) Common-Mode Voltage Range (V) 5 3.8 4 3 2.7 Single-Ended Input 2.3 2 1.2 1 0 -1 1.0 1.5 2.0 VREF (V) 2.6 2.5 AVDD = 5V 4.55 4 4.0 3 Differential Input 2 1 1.0 0.45 0 -1 3.0 1.0 1.5 2.0 VREF (V) 2.6 2.5 3.0 Figure 23. Single-Ended Input: Common-Mode Voltage Range vs VREF Figure 24. Differential Input: Common-Mode Voltage Range vs VREF When the input is differential, the amplitude of the input is the difference between the +IN and –IN input, or: (+IN) – (–IN). The peak-to-peak amplitude of each input is ±1/2VREF around this common voltage. However, since the inputs are 180° out-of-phase, the peak-to-peak amplitude of the differential voltage is +VREF to –VREF. The value of VREF also determines the range of the voltage that may be common to both inputs, as shown in Figure 24. In each case, care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are matched. Often, a small capacitor (20pF) between the positive and negative input helps to match the impedance. Otherwise, a mismatch may result in offset error, which will change with both temperature and input voltage. The input current on the analog inputs depends on a number of factors, such as sample rate or input Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 17 ADS8365 SBAS362C – AUGUST 2006 – REVISED MARCH 2008.................................................................................................................................................... www.ti.com voltage. Essentially, the current into the ADS8365 charges the internal capacitor array during the sampling period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (25pF) to a 16-bit settling level within three clock cycles if the minimum acquisition time is used. When the converter goes into the hold mode, the input impedance is greater than 1GΩ. Care must be taken regarding the absolute analog input voltage. The +IN and –IN inputs should always remain within the range of AGND – 0.3V to AVDD + 0.3V. BIPOLAR INPUTS The differential inputs of the ADS8365 were designed to accept bipolar inputs (–VREF and +VREF) around the common-mode voltage (2.5V), which corresponds to a 0V to 5V input range with a 2.5V reference. By using a simple op amp circuit featuring four, high-precision external resistors, the ADS8365 can be configured to accept a bipolar input range. The conventional ±2.5V, ±5V, and ±10V input ranges could be interfaced to the ADS8365 using the resistor values shown in Figure 26. R1 The OPA365 is a good choice for driving the analog inputs in a 5V, single-supply application. 4kW TRANSITION NOISE 20kW 1.2kW The transition noise of the ADS8365 itself is low, as shown in Figure 25 These histograms were generated by applying a low-noise dc input and initiating 8000 conversions. The digital output of the ADC will vary in output code due to the internal noise of the ADS8365; this feature is true for all 16-bit, successive approximation register (SAR) type ADCs. Using a histogram to plot the output codes, the distribution should appear bell-shaped, with the peak of the bell curve representing the nominal code for the input value. The ±1σ , ±2σ , and ±3σ distributions represent the 68.3%, 95.5%, and 99.7%, respectively, of all codes. The transition noise can be calculated by dividing the number of codes measured by 6, yielding the ±3σ distribution, or 99.7%, of all codes. Statistically, up to three codes could fall outside the distribution when executing 1000 conversions. Remember, in order to achieve this low-noise performance, the peak-to-peak noise of the input signal and reference must be < 50µV. 4000 3500 3290 Bipolar Input +IN OPA227 1.2kW -IN R2 ADS8365 OPA227 BIPOLAR INPUT R1 R2 ±10V ±5V ±2.5V 1kW 2kW 4kW 5kW 10kW 20kW REFOUT (pin 61) 2.5V Figure 26. Level Shift Circuit for Bipolar Input Ranges TIMING AND CONTROL The ADS8365 uses an external clock (CLK, pin 28) that controls the conversion rate of the CDAC. With a 5MHz external clock, the ADC sampling rate is 250kSPS which corresponds to a 4µs maximum throughput time. Acquisition and conversion take a total of 20 clock cycles. 3379 Occurrences 3000 2500 2000 1500 1000 603 649 5 00 37 42 0 32782 32783 32784 32785 Code 32786 32787 Figure 25. 8000 Conversion Histogram of a DC Input 18 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 ADS8365 www.ti.com.................................................................................................................................................... SBAS362C – AUGUST 2006 – REVISED MARCH 2008 THEORY OF OPERATION and all the output registers, aborts any conversion in process, and closes the sampling switches. The reset signal must stay low for at least 20ns (see Figure 27, tW4). The reset signal should be back high for at least 20ns (Figure 27, tD2) before starting the next conversion (negative hold edge). The ADS8365 contains six 16-bit ADCs that can operate simultaneously in pairs. The three hold signals (HOLDA, HOLDB, and HOLDC) initiate the conversion on the specific channels. A simultaneous hold on all six channels can occur with all three hold signals strobed together. The converted values are saved in six registers. For each read operation, the ADS8365 outputs 16 bits of information (16 data or 3 channel address, data valid, and some synchronization information). The address/mode signals (A0, A1, and A2) select how the data are read from the ADS8365. These address/mode signals can define a selection of a single channel, a cycle mode that cycles through all channels, or a FIFO mode that sequences the data determined by the order of the hold signals. The FIFO mode will allow the six registers to be used by a single-channel pair; therefore, three locations for CH X0 and three locations for CH X1 can be updated before they are read from the device. EOC End of conversion goes low when new data from the internal ADC are latched into the output registers, which usually happens 16.5 clock cycles after hold initiated the conversion. It remains low for half a clock cycle. If more than one channel pair is converted simultaneously, the A-channels get stored to the registers first (16.5 clock cycles after hold), followed by the B-channels one clock cycle later, and finally the C-channels another clock cycle later. If a reading (both RD and CS are low) is in process, then the latch process is delayed until the read operation is finished. FD EXPLANATION OF CLOCK, RESET, FD, AND EOC PINS First data or A0 data are high if channel A0 is chosen to be read next. In FIFO mode, the channel (X0) that is written to the FIFO first is latched into the A0 register. For example, when the FIFO is empty, FD is 0. The first result latched into the FIFO register A0 is, therefore, chosen to be read next, and FD rises. After the first channel is read (one to three read cycles, depending on BYTE and ADD), FD goes low again. Clock An external clock has to be provided for the ADS8365. The maximum clock frequency is 5MHz. The minimum clock cycle is 200ns (see Figure 1, tC1), and the clock has to remain high (Figure 1, tW1) or low for at least 60ns. RESET Bringing the RESET signal low will reset the ADS8365. Resetting clears the control register tC1 CLK tW1 tD1 HOLD A tW3 HOLD B tD2 tW2 HOLD C tW4 RESET Figure 27. Start of the Conversion Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 19 ADS8365 SBAS362C – AUGUST 2006 – REVISED MARCH 2008.................................................................................................................................................... www.ti.com START OF A CONVERSION AND READING DATA The ADS8365 can also convert one channel continuously (see Figure 28). Therefore, HOLDA and HOLDC are kept high all the time. To gain acquisition time, the falling edge of HOLDB takes place just before the rising edge of clock. One conversion requires 20 clock cycles. Here, data are read after the next conversion is initiated by HOLDB. To read data from channel B, A1 is set high and A2 is low. Since A0 is low during the first reading (A2 A1 A0 = 010), data B0 are put to the output. Before the second RD, A0 switches high (A2 A1 A0 = 011) so that data from channel B1 are read, as shown in Table 1. However, reading data during the conversion or on a falling hold edge might cause a loss in performance. By bringing one, two, or all three of the HOLDX signals low, the input data of the corresponding channel X are immediately placed in the hold mode (5ns). The conversion of this channel X follows with the next rising edge of clock. If it is important to detect a hold command during a certain clock-cycle, then the falling edge of the hold signal has to occur at least 10ns before the rising edge of clock, as shown in Figure 27, tD1. The hold signal can remain low without initiating a new conversion. The hold signal must be high for at least 15ns (as shown in Figure 27, tW2) before it is brought low again, and hold must stay low for at least 20ns (Figure 27, tW3). Table 1. Address Control for RD Functions Once a particular hold signal goes low, further impulses of this hold signal are ignored until the conversion is finished or the device is reset. When the conversion is finished (after 16 clock cycles) the sampling switches close and sample the selected channel. The start of the next conversion must be delayed to allow the input capacitor of the ADS8365 to be fully charged. This delay time depends on the driving amplifier, but should be at least 800ns. CONVERSION CLK 1 2 A2 A1 A0 CHANNEL TO BE READ 0 0 0 CH A0 0 0 1 CH A1 0 1 0 CH B0 0 1 1 CH B1 1 0 0 CH C0 1 0 1 CH C1 1 1 0 Cycle mode reads registers CH A0 to CH C1 on successive transitions of the read line 1 1 1 FIFO mode ACQUISITION 16 17 18 19 20 1 2 HOLD B EOC CS RD A0 Figure 28. Timing of One Conversion Cycle 20 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 ADS8365 www.ti.com.................................................................................................................................................... SBAS362C – AUGUST 2006 – REVISED MARCH 2008 Reading data (RD and CS) CS being low tells the ADS8365 that the bus on the board is assigned to the ADS8365. If an ADC shares a bus with digital gates, there is a possibility that digital (high-frequency) noise will be coupled into the ADC. If the bus is just used by the ADS8365, CS can be hardwired to ground. Reading data at the falling edge of one of the HOLDX signals might cause noise. In general, the channel/data outputs are in tri-state. Both CS and RD must be low to enable these outputs. RD and CS must stay low together for at least 40ns (see Figure 1, tD6) before the output data are valid. RD must remain HIGH for at least 30ns (see Figure 1, tW5) before bringing it back low for a subsequent read command. BYTE The new data are latched into its output register 16.5 clock cycles after the start of a conversion (next rising edge of clock after the falling edge of HOLDX). Even if the ADS8365 is forced to wait until the read process is finished (RD signal going high) before the new data are latched into its output register, the possibility still exists that the new data was latched to the output register just before the falling edge of RD. If a read process is initiated around 16.5 clock cycles after the conversion started, RD and CS should stay low for at least 50ns (see Figure 1, tW6) to get the new data stored to its register and switched to the output. If there is only an 8-bit bus available on a board, then BYTE can be set high (see Figure 29). In this case, the lower eight bits can be read at the output pins D15 to D8 or D7 to D0 at the first RD signal, and the higher bits after the second RD signal. If the ADS8365 is used in the cycle or the FIFO mode, then the address and data valid information is added to the data (if ADD is high). In this case, the address will be read first, then the lower eight bits, and finally the higher eight bits. If BYTE is low, then the ADS8365 operates in the 16-bit output mode. Here, data are read between pins DB15 and DB0. As long as ADD is low, with every RD impulse, data from a new channel are brought to the output. If ADD is high and the cycle or the FIFO mode is chosen; the first output word contains the address, while the second output word contains the 16-bit data. CS RD BYTE A0 A0 A1 A1 B0 B0 LOW HIGH LOW HIGH LOW HIGH B1 C0 C1 A0 D7 – D0 Figure 29. Reading Data in Cycling Mode Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 21 ADS8365 SBAS362C – AUGUST 2006 – REVISED MARCH 2008.................................................................................................................................................... www.ti.com ADD Signal In the cycle and the FIFO mode, it might be desirable to have address information with the 16-bit output data. Therefore, ADD can be set high. In this case, two RD signals (or three readings if the part is operated with BYTE being high) are necessary to read data of one channel, while the ADS8365 provides channel information on the first RD signal (see Table 2 and Table 3). Soft Trigger Mode Signals NAP, ADD, A0, A1, A2, RESET, HOLDA, HOLDB, and HOLDC are accessible through the data bus and control word. Bits NAP, ADD, A0, A1 and A2 are in an OR configuration with hardware pins. When software configuration is used, these pins must be connected to ground. Conversely, the RESET, HOLDA, HOLDB, and HOLDC bits are in a NAND configuration with the hardware pins. When software configuration is used, these pins must be connected to BVDD. If conversion timing between ADCs is not critical, Soft Trigger mode can allow all three HOLDX signals to be triggered simultaneously. This simultaneous triggering can be done by tying all three HOLDX pins high, and issuing a write (CS and WR low) with the DB0, DB1, DB2, and DB7 bits low, and the reset bit (DB3) high. Writing a low to the reset bit (DB3) while the RESET pin is high forces a device reset, and all HOLDX signals that occur during that time are ignored. The HOLDX signals start conversion automatically on the next clock cycle. The format of the two words that can be written to the ADS8365 are shown in Table 4. Bits DB5 and DB4 do not have corresponding hardware pins. Bit DB5 = 1 enables Powerdown mode. Bit DB4 = 1 inverts the MSB of the output data, putting the output data in two's complement format. When DB4 is low, the data is in straight binary format. Table 2. Overview of the Output Formats Depending on Mode When ADD = 0 ADD = 0 BYTE = 0 BYTE = 1 A2 A1 A0 1st RD 2nd RD 1st RD 2nd RD 3rd RD 000 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD 001 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD 010 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD 011 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD 100 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD 101 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD 110 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD 111 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD Table 3. Overview of the Output Formats Depending on Mode When ADD = 1 ADD = 1 BYTE = 0 BYTE = 1 A2 A1 A0 1st RD 2nd RD 1st RD 2nd RD 3rd RD 000 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD 001 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD 010 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD 011 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD 100 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD 101 DB15...DB0 No 2nd RD DB7...DB0 DB15...DB8 No 3rd RD 110 1000 0000 0000 DV A2 A1 A0 DB15...DB0 DV A2 A1 A0 DB3 DB2 DB0 DB7...DB0 DB15...DB8 111 1000 0000 0000 DV A2 A1 A0 DB15...DB0 DV A2 A1 A0 DB3 DB2 DB0 DB7...DB0 DB15...DB8 DB0 (LSB) Table 4. Control Register Bits 22 DB7 (MSB) DB6 DB5 DB4 DB3 DB2 DB1 1 NAP PD Invert MSB ADD A2 A1 A0 0 X X X RESET HOLDA HOLDB HOLDC Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 ADS8365 www.ti.com.................................................................................................................................................... SBAS362C – AUGUST 2006 – REVISED MARCH 2008 NAP AND POWERDOWN MODE CONTROL In order to minimize power consumption when the ADS8365 is not in use, two low-power options are available. Nap mode minimizes power without shutting down the biasing circuitry and internal reference, allowing immediate recovery after it is disabled. It can be enabled by either the NAP pin going high, or setting DB6 in the data register high. Enabling Powerdown mode results in lower power consumption than Nap mode, but requires a short recovery period after disabling. It can only be enabled by setting DB5 in the data register high. GETTING DATA Flexible Output Modes: A0 A1, and A2. The ADS8365 has three different output modes that are selected with A2, A1, and A0. The A2, A1 and A0 pins are held with a transparent latch that triggers on a falling edge of the RD pin negative-ANDed with the CS pin (that is, if either RD or CS is low, the falling edge of the other will latch A0-2). When (A2, A1, A0) = 000 to 101, a particular channel can be directly addressed (see Table 1 and Figure 30). The channel address should be set at least 10ns (see Figure 30, tD9) before the falling edge of RD and should not change as long as RD is low. In this standard address mode, ADD will be ignored, but should be connected to either ground or supply. When (A2, A1, A0) = 110, the interface is running in a cycle mode (see Figure 29). Here, data 7 down to data 0 of channel A0 is read on the first RD signal, and data 15 down to data 8 on the second as BYTE is high. Then A1 on the second RD, followed by B0, CLK 16 17 18 19 B1, C0, and finally, C1 before reading A0 again. Data from channel A0 are brought to the output first after a reset signal, or after powering up the device. The third mode is a FIFO mode that is addressed with (A2, A1, A0 = 111). Data of the channel that is converted first is read first. So, if a particular channel pair is most interesting and is converted more frequently (for example, to get a history of a particular channel pair), then there are three output registers per channel available to store data. If all the output registers are filled up with unread data and new data from an additional conversion must be latched in, then the oldest data is discarded. If a read process is going on (RD signal low) and new data must be stored, then the ADS8365 waits until the read process is finished (RD signal going high) before the new data gets latched into its output register. Again, with the ADD signal, it can be chosen whether the address should be added to the output data. New data is always written into the next available register. At t0 (see Figure 31), the reset deletes all the existing data. At t1, the new data of the channels A0 and A1 are put into registers 0 and 1. At t2, a dummy read (RD low) is performed to latch the address data correctly. At t3, the read process of channel A0 data is finished; therefore, these data are dumped and A1 data are shifted to register 0. At t4, new data are available, this time from channels B0, B1, C0, and C1. These data are written into the next available registers (registers 1, 2, 3, and 4). 20 1 2 tD1 HOLD X tACQ EOC CS tD8 tD7 RD tD9 A0 Figure 30. Timing for Reading Data Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 23 ADS8365 SBAS362C – AUGUST 2006 – REVISED MARCH 2008.................................................................................................................................................... www.ti.com RESET EOC Conversion Channels B and C Conversion Channel A Conversion Channel C RD Register 5 empty empty empty empty empty CH C1 Register 4 empty empty empty CH C1 empty CH C0 Register 3 empty empty empty CH C0 CH C1 CH C1 Register 2 empty empty empty CH B1 CH C0 CH C0 Register 1 empty CH A1 empty CH B0 CH B1 CH B1 Register 0 empty CH A0 CH A1 CH A1 CH B0 CH B0 t0 t2 t1 t3 t4 t5 t6 Figure 31. Functionality Diagram of the FIFO Registers On t5, the new read process of channel A1 data is finished. The new data of channel C0 and C1 at t6 are put on top (registers 4 and 5). In Cycle mode and in FIFO mode, the ADS8365 offers the ability to add the address of the channel to the output data. Since there is only a 16-bit bus available (or 8-bit bus in the case BYTE is high), an additional RD signal is necessary to get the information (see Table 2 and Table 3). In FIFO mode, a dummy read signal (RD) is required after a reset signal to set the address bits appropriately; otherwise, the first conversion will not be valid. This is only necessary in FIFO mode. The Output Code (DB15 …DB0) In the standard address mode (A2 A1 A0 = 000…101), the ADS8365 has a 16-bit output word on pins DB15…DB0, if BYTE = 0. If BYTE = 1, then two RD impulses are necessary to first read the lower bits, and then the higher bits on either DB7…DB0 or DB15...DB8. If the ADS8365 operates in Cycle or in FIFO mode and ADD is set high, then the address of the channel (A2A1A0) and a data valid (DV) bit are added to the data. If BYTE = 0, then the data valid and the address of the channel is active during the first RD impulse (1000 0000 0000 DV A2 A1 A0). During the 24 second RD, the 16-bit data word can be read (DB15…DB0). If BYTE = 1, then three RD impulses are needed. On the first RD impulse, data valid, the three address bits, and data bits DB3…DB0 (DV, A2, A1, A0, DB3, DB2, DB1, DB0) are read, followed by the eight lower bits of the 16-bit data word (db7…db0), and finally the higher eight data bits (DB15…DB8). 1000 0000 0000 is added before the address in case BYTE = 0, and DB3…DB0 is added after the address if BYTE = 1. This provides the possibility to check if the counting of the RD signals inside the ADS8365 are still tracking with the external interface (see Table 2 and Table 3). The data valid bit is useful for the FIFO mode. Valid data can simply be read until the data valid bit equals 0. The three address bits are listed in Table 5. If the FIFO is empty, 16 zeroes are loaded to the output. Table 5. Address Bit in the Output Data DATA FROM ... A2 A1 A0 Channel A0 0 0 0 Channel A1 0 0 1 Channel B0 0 1 0 Channel B1 0 1 1 Channel C0 1 0 0 Channel C1 1 0 1 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 ADS8365 www.ti.com.................................................................................................................................................... SBAS362C – AUGUST 2006 – REVISED MARCH 2008 0111111111111111 65535 0111111111111110 65534 0111111111111101 65533 0000000000000001 32769 0000000000000000 32768 1111111111111111 32767 1000000000000010 Step Digital Output Code Binary Two's Complement (BTC) 2 1000000000000001 1 1000000000000000 0 2.499962V VNFS = VCM - VREF = 0V 0.000038V 2.500038V VPFS = VCM + VREF = 5V VPFS - 1LSB = 4.999924V VBPZ = 2.5V 0.000076V 4.999848V Unipolar Analog Input Voltage 0.000152V 1LSB = 76V VCM = 2.5V 16-BIT VREF = 2.5V Bipolar Input, Binary Two’s Complement Output: (BTC) Negative Full-Scale Code = VNFS = 8000H, Vcode = VCM - VREF Bipolar Zero Code = VBPZ = 0000H, Vcode = VCM Positive Full-Scale Code = VPFS = 7FFFH, Vcode = (VCM + VREF) - 1LSB Figure 32. Ideal Conversion Characteristics (Condition: Single-Ended, VCM = chXX– = 2.5V, VREF = 2.5V) Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 25 ADS8365 SBAS362C – AUGUST 2006 – REVISED MARCH 2008.................................................................................................................................................... www.ti.com LAYOUT For optimum performance, care should be taken with the physical layout of the ADS8365 circuitry. This recommendation is particularly true if the CLK input is approaching the maximum throughput rate. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving any single conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic, or high-power devices. The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external event. Their error can change if the external event changes in time with respect to the CLK input. capacitor and a 5Ω or 10Ω series resistor may be used to low-pass filter a noisy supply. On average, the ADS8365 draws very little current from an external reference because the reference voltage is internally buffered. A bypass capacitor of 0.1µF and 10µF are suggested when using the internal reference (tie pin 61 directly to pin 62). GROUNDING The AGND pins should be connected to a clean ground point. In all cases, this point should be the analog ground. Avoid connections that are too close to the grounding point of a microcontroller or digital signal processor. If required, run a ground trace directly from the converter to the power-supply entry point. The ideal layout includes an analog ground plane dedicated to the converter and associated analog circuitry. Three signal ground pins (SGND) are the input signal grounds that are on the same potential as analog ground. With this information in mind, power to the ADS8365 should be clean and well-bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. In addition, a 1µF to 10µF capacitor is recommended. If needed, an even larger 26 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 ADS8365 www.ti.com.................................................................................................................................................... SBAS362C – AUGUST 2006 – REVISED MARCH 2008 APPLICATION INFORMATION Different connection diagrams to DSPs or microcontrollers are shown in Figure 33 through Figure 39. 5V 5V 2.048V REF3220 AVDD REFIN 100nF 5V V+ -IN REFOUT 100kW 20kW OPA343 SENSE OUT 100W 0.5V to 4.5V CH A0+ VIN A0 +IN 100kW 40kW REF 2 100W 1nF CH A02.5V 40kW ±10V VREF REF 1 INA159 ADS8365 100W VIN A1 CH A1+ OUT -IN INA159 +IN 100W 1nF CH A1- REF 1/2 CH B0+ CH B0CH B1+ CH B1CH C0+ CH C0100W VIN C1 INA159 +IN CH C1+ OUT -IN 100W 1nF CH C1- REF 1/2 SGND AGND Figure 33. ±10V Input Range By Using the INA159 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 27 ADS8365 SBAS362C – AUGUST 2006 – REVISED MARCH 2008.................................................................................................................................................... www.ti.com 3.3V ADS8365 BVDD BVDD HOLDA HOLDB 26 30 23 55 HOLDC FD WR A0 ADD A1 BYTE A2 CS DVDD 56 PWM1 57 PWM2 58 PWM3 54 EA0 53 EA1 52 31 EA2 EA3 8:1 OE RD EOC CLK RESET IS 29 RE 27 EXT_INT1 28 MCLKX 51 DATA [0] ... DATA [15] C28xx ADC_RST (MFSX) D0 ... D15 48 ... 33 VSS BGND Figure 34. Typical C28xx Connection (Hardware Control) BVDD 3.3V ADS8365 56 57 58 26 23 55 54 HOLDA C28xx DVDD BVDD HOLDB A2 HOLDC A1 FD 8:1 ADD BYTE CS A0 RD 53 A1 WR 52 A2 EOC CLK DATA [0] ... DATA [15] 31 OE 29 A0 IS RE 30 WE 27 EXT_INT1 28 MCLKX 48 ... 33 BGND D0 ... D15 VSS Figure 35. Typical C28xx Connection (Software Control) 28 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 ADS8365 www.ti.com.................................................................................................................................................... SBAS362C – AUGUST 2006 – REVISED MARCH 2008 3.3V ADS8365 BVDD BVDD HOLDA 30 53 52 23 54 WR HOLDB A1 HOLDC DVDD 56 TOUT1 57 A2 58 A1 8:1 A2 ADD CS BYTE A0 RD EOC CLK RESET 31 A0 IS OE 55 BE0 29 RE 27 INT0 28 TOUT0 51 DATA [0] ... DATA [15] C67xx DB_CNTL0 (ED27) D0 ... D15 48 ... 33 VSS BGND Figure 36. Typical C67xx Connection (Cycle Mode—Hardware Control) BVDD 3.3V ADS8365 56 57 58 26 23 55 54 HOLDA C67xx DVDD BVDD HOLDB HOLDC A2 A1 FD 8:1 ADD BYTE CS A0 RD 31 OE 29 RE 30 53 A1 WR 52 A2 EOC CLK DATA [0] ... DATA [15] A0 IS WE 27 INT0 28 TOUT0 48 ... 33 BGND D0 ... D15 VSS Figure 37. Typical C67xx Connection (Software Control) Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 29 ADS8365 SBAS362C – AUGUST 2006 – REVISED MARCH 2008.................................................................................................................................................... www.ti.com 3.3V ADS8365 BVDD BVDD HOLDA HOLDB 26 54 53 52 30 23 55 HOLDC FD DVDD 56 TOUT0 57 A2 58 A1 8:1 A0 CS A1 C54xx 31 A0 OE IS 29 A2 RD WR 30 27 ADD EOC BYTE CLK <1 I/OSTRB (1G32) 28 INT0 51 BCLKX1 RESET XF DATA [0] ... DATA [15] D0 ... D15 48 ... 33 VSS BGND Figure 38. Typical C54xx Connection (FIFO Mode—Hardware Control) 3.3V ADS8365 BVDD BVDD HOLDA 30 52 54 53 23 55 29 WR HOLDB ADD HOLDC A1 CS A2 RESET BYTE EOC A0 CLK RD DATA [0] ... DATA [7] MSP430x1xx DVDD 56 TACLK (P1.0) 57 58 31 P1.1 51 P1.2 27 P1.3 (ADC_INT) 28 SMCLK (P1.4) 48 ... 41 BGND P2.0 ... P2.7 VSS Figure 39. Typical MSP430x1xx Connection (Cycle Mode—Hardware Control) 30 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 ADS8365 www.ti.com.................................................................................................................................................... SBAS362C – AUGUST 2006 – REVISED MARCH 2008 Part Change Notification # 20071210003 The ADS8365 device underwent a silicon change under Texas Instruments Part Change Notification (PCN) number 20071210003. Details of this change can be obtained from the Product Information Center at Texas Instruments or by contacting your local sales/distribution office. Devices with a date code of 81x and higher are covered by this PCN. Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 31 ADS8365 SBAS362C – AUGUST 2006 – REVISED MARCH 2008.................................................................................................................................................... www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (November 2006) to Revision C ........................................................................................... Page • 32 Added Part Change Notification information........................................................................................................................ 31 Submit Documentation Feedback Copyright © 2006–2008, Texas Instruments Incorporated Product Folder Link(s): ADS8365 PACKAGE OPTION ADDENDUM www.ti.com 21-May-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ADS8365IPAG ACTIVE TQFP PAG 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR ADS8365IPAGG4 ACTIVE TQFP PAG 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR ADS8365IPAGR ACTIVE TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR ADS8365IPAGRG4 ACTIVE TQFP PAG 64 1500 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADS8365IPAGR Package Package Pins Type Drawing TQFP PAG 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1500 330.0 24.4 Pack Materials-Page 1 13.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 1.5 16.0 24.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8365IPAGR TQFP PAG 64 1500 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. 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