ON MMDF1N05ER2G Power mosfet 1 amp, 50 volts n-channel so-8, dual Datasheet

MMDF1N05E
Power MOSFET
1 Amp, 50 Volts
N−Channel SO−8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain−to−source diode has a low reverse recovery time. MiniMOSt
devices are designed for use in low voltage, high speed switching
applications where power efficiency is important. Typical applications
are dc−dc converters, and power management in portable and battery
powered products such as computers, printers, cellular and cordless
phones. They can also be used for low voltage motor controls in mass
storage products such as disk drives and tape drives. The avalanche
energy is specified to eliminate the guesswork in designs where
inductive loads are switched and offer additional safety margin against
unexpected voltage transients.
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1 AMPERE, 50 VOLTS
RDS(on) = 300 mW
N−Channel
D
G
S
Features
•
•
•
•
•
•
•
•
•
Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive − Can Be Driven by Logic ICs
Miniature SO−8 Surface Mount Package − Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed
Avalanche Energy Specified
Mounting Information for SO−8 Package Provided
IDSS Specified at Elevated Temperature
Pb−Free Package is Available
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain−to−Source Voltage
VDS
50
V
Gate−to−Source Voltage − Continuous
VGS
± 20
V
ID
A
IDM
2.0
10
EAS
300
mJ
Rating
Drain Current − Continuous
Drain Current − Pulsed
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 V, VGS = 10 V, IL = 2 Apk)
Operating and Storage Temperature Range
Total Power Dissipation @ TA = 25°C
Thermal Resistance, Junction−to−Ambient
(Note 1)
Maximum Temperature for Soldering,
Time in Solder Bath
TJ, Tstg
−55 to 150
°C
PD
2.0
W
RqJA
62.5
°C/W
TL
260
10
°C
Sec
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided) with
one die operating, 10 sec. max.
© Semiconductor Components Industries, LLC, 2006
February, 2006 − Rev. 8
1
MARKING
DIAGRAM
8
SO−8
CASE 751
STYLE 11
8
1
F1N05
AYWWG
G
1
F1N05 = Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN ASSIGNMENT
Source−1
1
8
Drain−1
Gate−1
2
7
Drain−1
Source−2
3
6
Drain−2
Gate−2
4
5
Drain−2
Top View
ORDERING INFORMATION
Device
Package
Shipping†
MMDF1N05ER2
SO−8
2,500/Tape & Reel
MMDF1N05ER2G
SO−8
2,500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
MMDF1N05E/D
MMDF1N05E
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
V(BR)DSS
50
−
−
Vdc
Zero Gate Voltage Drain Current
(VDS = 50 V, VGS = 0)
IDSS
−
−
2
mAdc
Gate−Body Leakage Current
(VGS = 20 Vdc, VDS = 0)
IGSS
−
−
100
nAdc
Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc)
VGS(th)
1.0
−
3.0
Vdc
Drain−to−Source On−Resistance
(VGS = 10 Vdc, ID = 1.5 Adc)
(VGS = 4.5 Vdc, ID = 0.6 Adc)
RDS(on)
RDS(on)
−
−
−
−
0.30
0.50
gFS
−
1.5
−
mhos
Ciss
−
330
−
pF
Coss
−
160
−
Crss
−
50
−
td(on)
−
−
20
tr
−
−
30
td(off)
−
−
40
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(VGS = 0, ID = 250 mA)
ON CHARACTERISTICS (Note 2)
W
Forward Transconductance (VDS = 15 V, ID = 1.5 A)
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 V, VGS = 0,
f = 1.0 MHz)
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 10 V, ID = 1.5 A, RL = 10 W,
VG = 10 V, RG = 50 W)
Fall Time
Total Gate Charge
Gate−Source Charge
(VDS = 10 V, ID = 1.5 A,
VGS = 10 V)
Gate−Drain Charge
ns
tf
−
−
25
Qg
−
12.5
−
Qgs
−
1.9
−
Qgd
−
3.0
−
VSD
−
−
1.6
V
trr
−
45
−
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS (TC = 25°C)
Forward Voltage (Note 2)
Reverse Recovery Time
(IS = 1.5 A, VGS = 0 V)
(dIS/dt = 100 A/ms)
2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2.0%.
3. Switching characteristics are independent of operating junction temperature.
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2
MMDF1N05E
TYPICAL ELECTRICAL CHARACTERISTICS
6V
8V
10 V
TJ = 25°C
10
8
4.5 V
6
4V
4
VGS = 3.5 V
2
−55 °C
VDS ≥ 10 V
5V
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
10
8
100°C
6
4
25°C
2
100°C
0
0
2
4
6
8
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0
10
0
1
RDS(on) , DRAIN−TO−SOURCE ON−RESISTANCE
(NORMALIZED)
RDS(on) , DRAIN−TO−SOURCE ON−RESISTANCE (OHMS)
VGS = 10 V
0.4
0.3
100°C
25°C
0.1
−55°C
0
2
4
6
ID, DRAIN CURRENT (AMPS)
8
0.5
ID = 1.5 A
VGS = 0
0.3
0.2
0.1
0
2
3
4
5
6
7
8
TJ, JUNCTION TEMPERATURE
4
5
6
7
8
125
150
9
1.8
1.6
1.4
VGS = 10 V
ID = 1.5 A
1.2
1
0.8
0.6
0.4
0.2
0
−50
−25
25
75
0
50
100
TJ, JUNCTION TEMPERATURE (°C)
Figure 4. On−Resistance Variation with Temperature
V GS(th), GATE THRESHOLD VOLTAGE (NORMALIZED)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
Figure 3. On−Resistance versus Drain Current
0.4
−55 °C
3
Figure 2. Transfer Characteristics
0.5
0
2
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
0.2
25°C
10
1.2
VDS = VGS
ID = 1 mA
1.1
1
0.9
0.8
0.7
−50
Figure 5. On Resistance versus
Gate−To−Source Voltage
−25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 6. Gate Threshold Voltage Variation
with Temperature
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3
150
MMDF1N05E
VGS
1200
VDS
12
VGS , GATE−TO−SOURCE VOLTAGE (VOLTS)
TJ = 25°C
Crss
1000
C, CAPACITANCE (pF)
0
Ciss
800
VDS = 0
VGS = 0
600
Ciss
400
Coss
200
Crss
0
VDS = 25 V
ID = 1.2 A
10
8
6
4
2
0
20
10
0
20
25
15
5
5
10
15
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0
2
Figure 7. Capacitance Variation
4
6
8
10
12
Qg, TOTAL GATE CHARGE (nC)
14
16
Figure 8. Gate Charge versus
Gate−To−Source Voltage
100
SAFE OPERATING AREA INFORMATION
I D , DRAIN CURRENT (AMPS)
Forward Biased Safe Operating Area
The FBSOA curves define the maximum drain−to−source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned
on. Because these curves include the limitations of
simultaneous high voltage and high current, up to the rating
of the device, they are especially useful to designers of linear
systems. The curves are based on a case temperature of 25°C
and a maximum junction temperature of 150°C. Limitations
for repetitive pulses at various case temperatures can be
determined by using the thermal response curves. ON
Semiconductor Application Note, AN569, “Transient
Thermal Resistance − General Data and Its Use” provides
detailed instructions.
10
VGS = 20 V
SINGLE PULSE
TC = 25°C
Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″
thick single sided) with one die operating, 10s max.
100 ms
10 ms
1
10 ms
dc
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1
10
1
100
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 9. Maximum Rated Forward Biased
Safe Operating Area
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE
10
1
0.1
D = 0.5
0.2
0.1
0.05
0.02
Normalized to qja at 10s.
Chip
0.0175 W
0.0710 W
0.2706 W
0.5776 W
0.7086 W
0.0154 F
0.0854 F
0.3074 F
1.7891 F
107.55 F
0.01
0.01
SINGLE PULSE
0.001
1.0E−05
1.0E−04
1.0E−03
1.0E−02
1.0E−01
t, TIME (s)
1.0E+00
Figure 10. Thermal Response
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4
1.0E+01
1.0E+02
Ambient
1.0E+03
MMDF1N05E
PACKAGE DIMENSIONS
SOIC−8
CASE 751−07
ISSUE AG
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
STYLE 11:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
SOLDERING FOOTPRINT*
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
SOURCE 1
GATE 1
SOURCE 2
GATE 2
DRAIN 2
DRAIN 2
DRAIN 1
DRAIN 1
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MiniMOS is a trademark of Semiconductor Components Industries, LLC (SCILLC). Company.
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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MMDF1N05E/D
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