16-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) AD9268 FEATURES APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications Ultrasound equipment FUNCTIONAL BLOCK DIAGRAM SDIO/ SCLK/ DCS DFS AVDD CSB DRVDD SPI AD9268 PROGRAMMING DATA VIN+A 16 CMOS/LVDS OUTPUT BUFFER ADC VIN–A D15A (MSB) TO D0A (LSB) CLK+ DIVIDE 1 TO 8 VREF ORA CLK– SENSE VCM DUTY CYCLE STABILIZER REF SELECT DCO GENERATION RBIAS DCOA DCOB ORB VIN–B 16 CMOS/LVDS OUTPUT BUFFER ADC VIN+B D15B (MSB) TO D0B (LSB) MULTICHIP SYNC AGND SYNC PDWN OEB NOTES 1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 7 FOR LVDS PIN NAMES. 08123-001 SNR = 78.2 dBFS @ 70 MHz and 125 MSPS SFDR = 88 dBc @ 70 MHz and 125 MSPS Low power: 750 mW @ 125 MSPS 1.8 V analog supply operation 1.8 V CMOS or LVDS output supply Integer 1-to-8 input clock divider IF sampling frequencies to 300 MHz −153.6 dBm/Hz small-signal input noise with 200 Ω input impedance @ 70 MHz and 125 MSPS Optional on-chip dither Programmable internal ADC voltage reference Integrated ADC sample-and-hold inputs Flexible analog input range: 1 V p-p to 2 V p-p Differential analog inputs with 650 MHz bandwidth ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk Serial port control User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes Figure 1. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. On-chip dither option for improved SFDR performance with low power analog input. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 300 MHz. Operation from a single 1.8 V supply and a separate digital output driver supply accommodating 1.8 V CMOS or LVDS outputs. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltage reference mode. Pin compatibility with the AD9258, allowing a simple migration from 16 bits to 14 bits. The AD9268 is also pin compatible with the AD9251, AD9231, and AD9204 family of products for lower sample rate, low power applications. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. AD9268* PRODUCT PAGE QUICK LINKS Last Content Update: 09/27/2017 COMPARABLE PARTS TOOLS AND SIMULATIONS View a parametric search of comparable parts. • Visual Analog • AD9268 IBIS Models EVALUATION KITS • AD9268 Evaluation Board REFERENCE DESIGNS • CN0171 DOCUMENTATION Application Notes REFERENCE MATERIALS • AN-1142: Techniques for High Speed ADC PCB Layout Solutions Bulletins & Brochures • AN-1211: Powering the AD9268 Dual Channel 16-Bit, 125 MSPS Analog-to-Digital Converter with the ADP2114 Synchronous Step-Down DC-to-DC Regulator for Increased Efficiency • Test & Instrumentation Solutions Bulletin, Volume 10, Issue 3 Technical Articles • AN-586: LVDS Outputs for High Speed A/D Converters • Improve The Design Of Your Passive Wideband ADC Front-End Network • AN-742: Frequency Domain Response of SwitchedCapacitor ADCs • MS-2210: Designing Power Supplies for High Speed ADC • AN-807: Multicarrier WCDMA Feasibility DESIGN RESOURCES • AN-808: Multicarrier CDMA2000 Feasibility • AD9268 Material Declaration • AN-812: MicroController-Based Serial Port Interface (SPI) Boot Circuit • PCN-PDN Information • AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs • Symbols and Footprints • AN-878: High Speed ADC SPI Control Software • AN-905: Visual Analog Converter Evaluation Tool Version 1.0 User Manual • Quality And Reliability DISCUSSIONS View all AD9268 EngineerZone Discussions. • AN-935: Designing an ADC Transformer-Coupled Front End SAMPLE AND BUY Data Sheet Visit the product page to see pricing options. • AD9268: 16-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) Data Sheet TECHNICAL SUPPORT User Guides • UG-003: Evaluating the AD9650/AD9268/AD9258/ AD9251/AD9231/AD9204 Analog-to-Digital Converters Submit a technical question or find your regional support number. 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AD9268 TABLE OF CONTENTS Features .............................................................................................. 1 Clock Input Considerations ...................................................... 30 Applications ....................................................................................... 1 Channel/Chip Synchronization ................................................ 31 Functional Block Diagram .............................................................. 1 Power Dissipation and Standby Mode .................................... 32 Product Highlights ........................................................................... 1 Digital Outputs ........................................................................... 32 Revision History ............................................................................... 2 Timing ......................................................................................... 33 General Description ......................................................................... 3 Built-In Self-Test (BIST) and Output Test .................................. 34 Specifications..................................................................................... 4 Built-In Self-Test (BIST) ............................................................ 34 ADC DC Specifications ............................................................... 4 Output Test Modes ..................................................................... 34 ADC AC Specifications ................................................................. 6 Serial Port Interface (SPI) .............................................................. 35 Digital Specifications ................................................................... 7 Configuration Using the SPI ..................................................... 35 Switching Specifications ................................................................ 9 Hardware Interface..................................................................... 36 Timing Specifications ................................................................ 10 Configuration Without the SPI ................................................ 36 Absolute Maximum Ratings.......................................................... 12 SPI Accessible Features .............................................................. 36 Thermal Characteristics ............................................................ 12 Memory Map .................................................................................. 37 ESD Caution ................................................................................ 12 Reading the Memory Map Register Table............................... 37 Pin Configurations and Function Descriptions ......................... 13 Memory Map Register Table ..................................................... 38 Typical Performance Characteristics ........................................... 17 Memory Map Register Descriptions ........................................ 40 Equivalent Circuits ......................................................................... 25 Applications Information .............................................................. 41 Theory of Operation ...................................................................... 26 Design Guidelines ...................................................................... 41 ADC Architecture ...................................................................... 26 Outline Dimensions ....................................................................... 42 Analog Input Considerations.................................................... 26 Ordering Guide .......................................................................... 42 Voltage Reference ....................................................................... 29 REVISION HISTORY 9/09—Rev. 0 to Rev. A Changes to Features List .................................................................. 1 Changes to Specifications Section .................................................. 4 Changes to Table 5 .......................................................................... 10 Changes to Typical Performance Characteristics Section ......... 17 5/09—Revision 0: Initial Version Rev. A | Page 2 of 44 AD9268 GENERAL DESCRIPTION The AD9268 is a dual, 16-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC). The AD9268 is designed to support communications applications where high performance, combined with low cost, small size, and versatility, is desired. The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth, differential sample-and-hold analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The ADC output data can be routed directly to the two external 16-bit output ports. These outputs can be set to either 1.8 V CMOS or LVDS. Flexible power-down options allow significant power savings, when desired. Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. The AD9268 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. Rev. A | Page 3 of 44 AD9268 SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) 1 Integral Nonlinearity (INL)1 MATCHING CHARACTERISTIC Offset Error Gain Error TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Load Regulation @ 1.0 mA INPUT REFERRED NOISE VREF = 1.0 V ANALOG INPUT Input Span, VREF = 1.0 V Input Capacitance 2 Input CommonMode Voltage REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltage AVDD DRVDD Supply Current IAVDD1 IDRVDD1 (1.8 V CMOS) IDRVDD1 (1.8 V LVDS) Temperature Full Full Full Full Full Min 16 AD9268BCPZ-80 Typ Max Guaranteed ±0.2 ±0.4 −1.0 ±0.4 ±2.5 +1.4 AD9268BCPZ-105 Min Typ Max 16 Guaranteed ±0.2 ±0.4 −1.0 ±0.5 ±2.5 +1.3 Min 16 AD9268BCPZ-125 Typ Max Guaranteed ±0.4 ±0.4 −1.0 ±0.65 ±2.5 +1.2 % FSR % FSR LSB ±5.5 LSB LSB 25°C Full ±0.65 25°C ±2.0 Full Full ±0.1 ±0.3 Full Full ±2 ±15 Full ±5 Full 5 5 5 mV 25°C 2.17 2.23 2.27 LSB rms Full 2 2 2 V p-p Full Full 8 0.9 8 0.9 8 0.9 pF V Full 6 6 6 kΩ Full Full ±0.7 Unit Bits ±4.5 1.7 1.7 ±0.7 ±5.1 ±3.0 ±0.4 ±1.3 ±0.1 ±0.3 ±3.0 ±0.4 ±1.3 ±0.2 ±0.3 ±2 ±15 ±12 1.8 1.8 1.9 1.9 Full Full 234 35 240 Full 89 ±5 1.7 1.7 Rev. A | Page 4 of 44 ±0.45 ±1.3 ±2 ±15 ±12 1.8 1.8 1.9 1.9 293 45 300 89 LSB ±5 1.7 1.7 % FSR % FSR ppm/°C ppm/°C ±12 mV 1.8 1.8 1.9 1.9 V V 390 55 400 mA mA 94 mA AD9268 Parameter POWER CONSUMPTION DC Input Sine Wave Input1 (DRVDD = 1.8 V CMOS Output Mode) Sine Wave Input1 (DRVDD = 1.8 V LVDS Output Mode) Standby Power 3 Power-Down Power Temperature Min AD9268BCPZ-80 Typ Max Full Full 420 485 Full 582 Full Full 45 0.5 AD9268BCPZ-105 Min Typ Max 450 565 608 590 685 2.5 1 45 0.5 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. Input capacitance refers to the effective capacitance between one differential input pin and AGND. 3 Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND). 2 Rev. A | Page 5 of 44 Min AD9268BCPZ-125 Typ Max 750 800 777 870 2.5 45 0.5 Unit mW mW mW 2.5 mW mW AD9268 ADC AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz SIGNAL-TO-NOISE-AND-DISTORTION (SINAD) fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz WORST SECOND OR THIRD HARMONIC fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) Without Dither (AIN@ −23 dBFS) fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz With On-Chip Dither (AIN @ −23 dBFS) fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz Temp 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C AD9268BCPZ-80 Min Typ Max 78.3 78.0 79.7 79.0 AD9268BCPZ-105 Min Typ Max 77.2 77.1 77.4 75.5 78.9 78.8 AD9268BCPZ-125 Min Typ Max 77.2 76.5 76.9 75.0 dBFS dBFS dBFS dBFS dBFS 77.1 75.5 75.4 74.3 75.9 72.2 75.8 74.0 dBFS dBFS dBFS dBFS dBFS 25°C 25°C 25°C 25°C 12.9 12.8 12.2 12.0 12.7 12.7 12.3 11.7 12.7 12.6 12.3 12.0 Bits Bits Bits Bits 25°C 25°C Full 25°C 25°C −92 −91 25°C 25°C Full 25°C 25°C 78.1 77.7 79.4 78.5 78.8 78.2 77.1 76.8 −87 −93 −88 −87 −80 −82 76.8 76.2 −90 −88 −87 −87 −84 −77 −83 −79 dBc dBc dBc dBc dBc 84 77 83 79 25°C 25°C 25°C 25°C 93 95 98 102 100 96 96 100 88 89 90 89 dBFS dBFS dBFS dBFS 25°C 25°C 25°C 25°C 107 107 106 104 106 109 104 108 106 106 104 105 dBFS dBFS dBFS dBFS Rev. A | Page 6 of 44 85 84 90 88 −85 −84 80 82 87 87 87 93 78.3 77.7 dBc dBc dBc dBc dBc 88 87 92 91 78.3 78.6 Unit AD9268 Parameter 1 WORST OTHER (HARMONIC OR SPUR) Without Dither fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz With On-Chip Dither fIN = 2.4 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz TWO-TONE SFDR, WITHOUT DITHER fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS) fIN = 169 MHz (−7 dBFS ), 172 MHz (−7 dBFS) CROSSTALK 2 ANALOG INPUT BANDWIDTH 1 2 AD9268BCPZ-80 Min Typ Max AD9268BCPZ-105 Min Typ Max AD9268BCPZ-125 Min Typ Max 25°C 25°C Full 25°C 25°C −99 −100 −100 −99 −100 −100 25°C 25°C Full 25°C 25°C −108 −106 −105 −102 −104 −102 −103 −99 dBc dBc dBc dBc dBc 25°C 25°C Full 25°C 93 81 −95 650 92 80 −95 650 90 82 −95 650 dBc dBc dB MHz Temp −96 −96 −98 −96 −94 −94 −98 −94 −96 −96 −107 −107 −94 −94 −98 −96 −95 −95 −108 −106 −95 −95 Unit dBc dBc dBc dBc dBc See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Crosstalk is measured at 100 MHz with −1 dBFS on one channel and no input on the alternate channel. DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range High Level Input Current Low Level Input Current Input Capacitance Input Resistance SYNC INPUT Logic Compliance Internal Bias Input Voltage Range High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance Input Resistance Temperature Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Min Typ Max CMOS/LVDS/LVPECL 0.9 0.3 AGND 0.9 −100 −100 8 3.6 AVDD 1.4 +100 +100 4 10 12 CMOS 0.9 AGND 1.2 AGND −100 −100 12 Rev. A | Page 7 of 44 AVDD AVDD 0.6 +100 +100 1 16 20 Unit V V p-p V V μA μA pF kΩ V V V V μA μA pF kΩ AD9268 Parameter LOGIC INPUT (CSB) 1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUT (SCLK/DFS) 2 High Level Input Voltage Low Level Input Voltage High Level Input Current (VIN = 1.8 V) Low Level Input Current Input Resistance Input Capacitance LOGIC INPUT/OUTPUT (SDIO/DCS)1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (OEB, PDWN)2 High Level Input Voltage Low Level Input Voltage High Level Input Current (VIN = 1.8 V) Low Level Input Current Input Resistance Input Capacitance DIGITAL OUTPUTS CMOS Mode—DRVDD = 1.8 V High Level Output Voltage IOH = 50 μA IOH = 0.5 mA Low Level Output Voltage IOL = 1.6 mA IOL = 50 μA LVDS Mode—DRVDD = 1.8 V Differential Output Voltage (VOD), ANSI Mode Output Offset Voltage (VOS), ANSI Mode Differential Output Voltage (VOD), Reduced Swing Mode Output Offset Voltage (VOS), Reduced Swing Mode 1 2 Temperature Min Full Full Full Full Full Full 1.22 0 −10 40 Full Full Full Full Full Full 1.22 0 −92 −10 Full Full Full Full Full Full 1.22 0 −10 38 Full Full Full Full Full Full 1.22 0 −90 −10 Full Full 1.79 1.75 Typ Unit 2.1 0.6 +10 132 V V μA μA kΩ pF 2.1 0.6 −135 +10 V V μA μA kΩ pF 2.1 0.6 +10 128 V V μA μA kΩ pF 2.1 0.6 −134 +10 V V μA μA kΩ pF 26 2 26 2 26 5 26 5 V V Full Full Full Full Full Full Max 290 1.15 160 1.15 Pull up. Pull down. Rev. A | Page 8 of 44 345 1.25 200 1.25 0.2 0.05 V V 400 1.35 230 1.35 mV V mV V AD9268 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock Rate Conversion Rate1 DCS Enabled DCS Disabled CLK Period—Divide-by-1 Mode (tCLK) CLK Pulse Width High (tCH) Divide-by-1 Mode, DCS Enabled Divide-by-1 Mode, DCS Disabled Divide-by-2 Mode Through Divideby-8 Mode Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) DATA OUTPUT PARAMETERS CMOS Mode Data Propagation Delay (tPD) DCO Propagation Delay (tDCO)2 DCO to Data Skew (tSKEW) LVDS Mode Data Propagation Delay (tPD) DCO Propagation Delay (tDCO)2 DCO to Data Skew (tSKEW) CMOS Mode Pipeline Delay (Latency) LVDS Mode Pipeline Delay (Latency) Channel A/Channel B Wake-Up Time3 Out-of-Range Recovery Time Temperature AD9268BCPZ-80 Min Typ Max Full AD9268BCPZ-105 Min Typ Max 625 Full Full Full 20 10 12.5 Full Full Full 3.75 5.95 6.25 6.25 625 80 80 20 10 9.5 8.75 6.55 2.85 4.5 Full Full 1.0 0.07 Full Full Full 2.8 Full Full Full Full 2.9 4.75 4.75 105 105 20 10 8 6.65 5.0 2.4 3.8 0.8 0.8 0.8 −0.6 −0.1 AD9268BCPZ-125 Min Typ Max 1.0 0.07 3.5 3.1 −0.4 4.2 2.8 0 −0.6 3.7 3.9 +0.2 12 4.5 2.9 +0.5 −0.1 3.5 3.1 −0.4 3.7 3.9 +0.2 12 4 4 625 MHz 125 125 MSPS MSPS ns 5.6 4.2 ns ns ns 1.0 0.07 4.2 2.8 0 −0.6 4.5 2.9 +0.5 −0.1 3.5 3.1 −0.4 3.7 3.9 +0.2 12 Unit ns ps rms 4.2 0 4.5 +0.5 ns ns ns ns ns ns Cycles Full 12/12.5 12/12.5 12/12.5 Cycles Full Full 500 2 500 2 500 2 μs Cycles 1 Conversion rate is the clock rate after the divider. Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see Table 17). 3 Wake-up time is defined as the time required to return to normal operation from power-down mode. 2 Rev. A | Page 9 of 44 AD9268 TIMING SPECIFICATIONS Table 5. Parameter SYNC TIMING REQUIREMENTS tSSYNC tHSYNC SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Conditions Limit SYNC to rising edge of CLK+ setup time SYNC to rising edge of CLK+ hold time 0.3 ns typ 0.40 ns typ Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK SCLK pulse width high SCLK pulse width low Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 2 ns min 2 ns min 40 ns min 2 ns min 2 ns min 10 ns min 10 ns min 10 ns min 10 ns min Timing Diagrams N–1 N+4 tA N+5 N N+3 VIN N+1 tCH N+2 tCLK CLK+ CLK– tDCO DCOA/DCOB CH A/CH B DATA N – 13 N – 12 N – 11 N – 10 N–9 N–8 tPD 08123-002 tSKEW Figure 2. CMOS Default Output Mode Data Output Timing N–1 N+4 tA N+5 N N+3 VIN N+1 tCH N+2 tCLK CLK+ CLK– tDCO DCOA/DCOB tSKEW CH A/CH B DATA CH A CH B CH A N – 12 N – 12 N – 11 CH B CH A CH B N – 11 N – 10 N – 10 Figure 3. CMOS Interleaved Output Mode Data Output Timing Rev. A | Page 10 of 44 CH A N–9 CH B N–9 CH A N–8 08123-057 tPD AD9268 N–1 N+4 tA N+5 N N+3 VIN N+1 tCH N+2 tCLK CLK+ CLK– tDCO DCOA/DCOB CH A CH B CH A N – 12 N – 12 N – 11 CH A/CH B DATA CH B CH A CH B N – 11 N – 10 N – 10 CH A N–9 CH B N–9 Figure 4. LVDS Mode Data Output Timing CLK+ tHSYNC 08123-004 tSSYNC SYNC Figure 5. SYNC Input Timing Requirements Rev. A | Page 11 of 44 CH A N–8 08123-003 tSKEW tPD AD9268 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter ELECTRICAL1 AVDD to AGND DRVDD to AGND VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND VCM to AGND RBIAS to AGND CSB to AGND SCLK/DFS to AGND SDIO/DCS to AGND OEB PDWN D0A/D0B through D15A/D15B to AGND DCOA/DCOB to AGND ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Under Bias Storage Temperature Range (Ambient) 1 Rating −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to DRVDD + 0.2 V −0.3 V to DRVDD + 0.2 V −0.3 V to DRVDD + 0.2 V −0.3 V to DRVDD + 0.2 V −0.3 V to DRVDD + 0.2 V −0.3 V to DRVDD + 0.2 V The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the PCB increases the reliability of the solder joints and maximizes the thermal capability of the package. Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown in Table 7, airflow improves heat dissipation, which reduces θJA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes, reduces θJA. Table 7. Thermal Resistance Package Type 64-Lead LFCSP (CP-64-6) 1 −0.3 V to DRVDD + 0.2 V θJA1, 2 18.5 16.1 14.5 θJC1, 3 1.0 θJB1, 4 9.2 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). 2 −40°C to +85°C ESD CAUTION 150°C Airflow Velocity (m/sec) 0 1.0 2.5 −65°C to +150°C The inputs and outputs are rated to the supply voltage (AVDD or ARVDD) + 0.2 V but should not exceed 2.1 V. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. A | Page 12 of 44 Unit °C/W °C/W °C/W AD9268 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD AVDD VIN+B VIN–B AVDD AVDD RBIAS VCM SENSE VREF AVDD AVDD VIN–A VIN+A AVDD AVDD PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR AD9268 PARALLEL CMOS TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PDWN OEB CSB SCLK/DFS SDIO/DCS ORA D15A (MSB) D14A D13A D12A D11A DRVDD D10A D9A D8A D7A NOTES 1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. 08123-005 D12B D13B DRVDD D14B D15B (MSB) ORB DCOB DCOA D0A (LSB) D1A D2A DRVDD D3A D4A D5A D6A 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CLK+ CLK– SYNC D0B (LSB) D1B D2B D3B D4B D5B DRVDD D6B D7B D8B D9B D10B D11B Figure 6. LFCSP Parallel CMOS Pin Configuration (Top View) Table 8. Pin Function Descriptions (Parallel CMOS Mode) Pin No. ADC Power Supplies 10, 19, 28, 37 49, 50, 53, 54, 59, 60, 63, 64 0 ADC Analog 51 52 62 61 55 56 58 57 1 2 Digital Input 3 Digital Outputs 25 26 27 29 30 31 32 Mnemonic Type Description DRVDD AVDD Supply Supply Digital Output Driver Supply (1.8 V Nominal). Analog Power Supply (1.8 V Nominal). AGND, Exposed Pad Ground The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to ground for proper operation. VIN+A VIN−A VIN+B VIN−B VREF SENSE RBIAS VCM CLK+ CLK− Input Input Input Input Input/Output Input Input/Output Output Input Input Differential Analog Input Pin (+) for Channel A. Differential Analog Input Pin (−) for Channel A. Differential Analog Input Pin (+) for Channel B. Differential Analog Input Pin (−) for Channel B. Voltage Reference Input/Output. Voltage Reference Mode Select. See Table 11 for details. External Reference Bias Resistor. Common-Mode Level Bias Output for Analog Inputs. ADC Clock Input—True. ADC Clock Input—Complement. SYNC Input Digital Synchronization Pin. Slave mode only. D0A (LSB) D1A D2A D3A D4A D5A D6A Output Output Output Output Output Output Output Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Rev. A | Page 13 of 44 AD9268 Pin No. 33 34 35 36 38 39 40 41 42 43 4 5 6 7 8 9 11 12 13 14 15 16 17 18 20 21 22 24 23 SPI Control 45 44 46 ADC Configuration 47 48 Mnemonic D7A D8A D9A D10A D11A D12A D13A D14A D15A (MSB) ORA D0B (LSB) D1B D2B D3B D4B D5B D6B D7B D8B D9B D10B D11B D12B D13B D14B D15B (MSB) ORB DCOA DCOB Type Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Description Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A Overrange Output. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B Overrange Output Channel A Data Clock Output. Channel B Data Clock Output. SCLK/DFS SDIO/DCS CSB Input Input/Output Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. SPI Chip Select (Active Low). OEB PDWN Input Input Output Enable Input (Active Low) in External Pin Mode. Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby. Rev. A | Page 14 of 44 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD AVDD VIN+B VIN–B AVDD AVDD RBIAS VCM SENSE VREF AVDD AVDD VIN–A VIN+A AVDD AVDD AD9268 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR AD9268 PARALLEL LVDS TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PDWN OEB CSB SCLK/DFS SDIO/DCS OR+ OR– D15+ (MSB) D15– (MSB) D14+ D14– DRVDD D13+ D13– D12+ D12– NOTES 1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. 08123-006 D6– D6+ DRVDD D7– D7+ D8– D8+ DCO– DCO+ D9– D9+ DRVDD D10– D10+ D11– D11+ 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CLK+ CLK– SYNC D0– (LSB) D0+ (LSB) D1– D1+ D2– D2+ DRVDD D3– D3+ D4– D4+ D5– D5+ Figure 7. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View) Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode) Pin No. ADC Power Supplies 10, 19, 28, 37 49, 50, 53, 54, 59, 60, 63, 64 0 ADC Analog 51 52 62 61 55 56 58 57 1 2 Digital Input 3 Digital Outputs 5 4 7 6 9 8 12 Mnemonic Type Description DRVDD AVDD Supply Supply Digital Output Driver Supply (1.8 V Nominal). Analog Power Supply (1.8 V Nominal). AGND, Exposed Pad Ground The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to ground for proper operation. VIN+A VIN−A VIN+B VIN−B VREF SENSE RBIAS VCM CLK+ CLK− Input Input Input Input Input/Output Input Input/Output Output Input Input Differential Analog Input Pin (+) for Channel A. Differential Analog Input Pin (−) for Channel A. Differential Analog Input Pin (+) for Channel B. Differential Analog Input Pin (−) for Channel B. Voltage Reference Input/Output. Voltage Reference Mode Select. See Table 11 for details. External Reference Bias Resistor. Common-Mode Level Bias Output for Analog Inputs. ADC Clock Input—True. ADC Clock Input—Complement. SYNC Input Digital Synchronization Pin. Slave mode only. D0+ (LSB) D0− (LSB) D1+ D1− D2+ D2− D3+ Output Output Output Output Output Output Output Channel A/Channel B LVDS Output Data 0—True. Channel A/Channel B LVDS Output Data 0—Complement. Channel A/Channel B LVDS Output Data 1—True. Channel A/Channel B LVDS Output Data 1—Complement. Channel A/Channel B LVDS Output Data 2—True. Channel A/Channel B LVDS Output Data 2—Complement. Channel A/Channel B LVDS Output Data 3—True. Rev. A | Page 15 of 44 AD9268 Pin No. 11 14 13 16 15 18 17 21 20 23 22 27 26 30 29 32 31 34 33 36 35 39 38 41 40 43 42 25 24 SPI Control 45 44 46 ADC Configuration 47 48 Mnemonic D3− D4+ D4− D5+ D5− D6+ D6− D7+ D7− D8+ D8− D9+ D9− D10+ D10− D11+ D11− D12+ D12− D13+ D13− D14+ D14− D15+ (MSB) D15− (MSB) OR+ OR− DCO+ DCO− Type Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Description Channel A/Channel B LVDS Output Data 3—Complement. Channel A/Channel B LVDS Output Data 4—True. Channel A/Channel B LVDS Output Data 4—Complement. Channel A/Channel B LVDS Output Data 5—True. Channel A/Channel B LVDS Output Data 5—Complement. Channel A/Channel B LVDS Output Data 6—True. Channel A/Channel B LVDS Output Data 6—Complement. Channel A/Channel B LVDS Output Data 7—True. Channel A/Channel B LVDS Output Data 7—Complement. Channel A/Channel B LVDS Output Data 8—True. Channel A/Channel B LVDS Output Data 8—Complement. Channel A/Channel B LVDS Output Data 9—True. Channel A/Channel B LVDS Output Data 9—Complement. Channel A/Channel B LVDS Output Data 10—True. Channel A/Channel B LVDS Output Data 10—Complement. Channel A/Channel B LVDS Output Data 11—True. Channel A/Channel B LVDS Output Data 11—Complement. Channel A/Channel B LVDS Output Data 12—True. Channel A/Channel B LVDS Output Data 12—Complement. Channel A/Channel B LVDS Output Data 13—True. Channel A/Channel B LVDS Output Data 13—Complement. Channel A/Channel B LVDS Output Data 14—True. Channel A/Channel B LVDS Output Data 14—Complement. Channel A/Channel B LVDS Output Data 15—True. Channel A/Channel B LVDS Output Data 15—Complement. Channel A/Channel B LVDS Overrange Output—True. Channel A/Channel B LVDS Overrange Output—Complement. Channel A/Channel B LVDS Data Clock Output—True. Channel A/Channel B LVDS Data Clock Output—Complement. SCLK/DFS SDIO/DCS CSB Input Input/Output Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. SPI Chip Select (Active Low). OEB PDWN Input Input Output Enable Input (Active Low) in External Pin Mode. Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby. Rev. A | Page 16 of 44 AD9268 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, DCS enabled, 1.0 V internal reference, 2 V p-p differential input, VIN = −1.0 dBFS, and 32k sample, TA = 25°C, unless otherwise noted. 0 0 80MSPS 2.4MHz @ –1dBFS SNR = 79.0dB (80.0dBFS) SFDR = 98dBc –20 –20 –40 –60 AMPLITUDE (dBFS) SECOND HARMONIC –80 THIRD HARMONIC –100 SECOND HARMONIC THIRD HARMONIC –80 –100 0 10 20 FREQUENCY (MHz) 30 40 –140 08123-062 –140 0 10 Figure 8. AD9268-80 Single-Tone FFT with fIN = 2.4 MHz 30 40 Figure 11. AD9268-80 Single-Tone FFT with fIN = 200.1 MHz 0 0 80MSPS 70.1MHz @ –1dBFS SNR = 77.5dB (78.5dBFS) SFDR = 89.2dBc –20 20 FREQUENCY (MHz) 08123-065 –120 –120 80MSPS 70.1MHz @ –6dBFS SNR = 73.0dB (79.0dBFS) SFDR = 98dBc –20 –40 AMPLITUDE (dBFS) –40 –60 THIRD HARMONIC –80 SECOND HARMONIC –100 –120 –60 THIRD HARMONIC –80 SECOND HARMONIC –100 –120 0 10 20 FREQUENCY (MHz) 30 40 –140 08123-063 –140 Figure 9. AD9268-80 Single-Tone FFT with fIN = 70.1 MHz 0 SNR/SFDR (dBc AND dBFS) THIRD HARMONIC SECOND HARMONIC –80 –100 80 60 40 SNR (dBFS) SFDR (dBc) SNR (dBc) SFDR (dBFS) 20 –140 20 FREQUENCY (MHz) 30 Figure 10. AD9268-80 Single-Tone FFT with fIN = 140.1 MHz 40 08123-064 –120 10 40 100 –40 0 30 120 80MSPS 140.1MHz @ –1dBFS SNR = 76.0dB (77.0dBFS) SFDR = 81.1dBc –60 20 FREQUENCY (MHz) Figure 12. AD9268-80 Single-Tone FFT with fIN = 70.1 MHz with Dither Enabled 0 –20 10 08123-066 AMPLITUDE (dBFS) –60 0 –100 –90 –80 –70 –60 –50 –40 –30 INPUT AMPLITUDE (dBFS) –20 –10 0 08123-067 AMPLITUDE (dBFS) –40 AMPLITUDE (dBFS) 80MSPS 200.3MHz @ –1dBFS SNR = 74.3dB (75.3dBFS) SFDR = 83dBc Figure 13. AD9268-80 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 98.12 MHz Rev. A | Page 17 of 44 AD9268 200,000 120 2.17 LSB rms 180,000 110 160,000 NUMBER OF HITS SNR/SFDR (dBFS) 140,000 100 90 SNRFS (DITHER ON) SNRFS (DITHER OFF) SFDRFS (DITHER ON) SFDRFS (DITHER OFF) 120,000 100,000 80,000 60,000 40,000 80 20,000 –70 –60 –50 –40 –30 INPUT AMPLITUDE (dBFS) –20 –10 0 0 08123-071 –80 N – 11 N – 10 N–9 N–8 N –7 N –6 N–5 N–4 N–3 N–2 N–1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 –90 08123-068 70 –100 OUTPUT CODE Figure 14. AD9268-80 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 30 MHz with and without Dither Enabled Figure 17. AD9268-80 Grounded Input Histogram 100 4 SNR @ –40°C SFDR @ –40°C SNR @ +25°C SFDR @ +25°C SNR @ +85°C SFDR @ +85°C 90 2 INL ERROR (LSB) SNR/SFDR (dBFS/dBc) 95 DITHER ENABLED DITHER DISABLED 85 80 75 0 –2 0 50 100 150 200 INPUT FREQUENCY (MHz) 250 300 –4 08123-069 65 0 20,000 30,000 40,000 OUTPUT CODE 50,000 60,000 Figure 18. AD9268-80 INL with fIN = 9.7 MHz Figure 15. AD9268-80 Single-Tone SNR/SFDR vs. Input Frequency (fIN) with 2 V p-p Full Scale 1.00 105 SNR, CHANNEL B SFDR, CHANNEL B SNR, CHANNEL A SFDR, CHANNEL A 100 0.75 0.50 95 DNL ERROR (LSB) SNR/SFDR (dBFS AND dBc) 10,000 08123-072 70 90 85 0.25 0 –0.25 –0.50 80 30 35 40 45 50 55 60 65 SAMPLE RATE (MSPS) 70 75 80 –1.00 08123-070 75 25 0 10,000 20,000 30,000 40,000 OUTPUT CODE 50,000 Figure 19. AD9268-80 DNL with fIN = 9.7 MHz Figure 16. AD9268-80 Single-Tone SNR/SFDR vs. Sample Rate (fS) with fIN = 70.1 MHz Rev. A | Page 18 of 44 60,000 08123-073 –0.75 AD9268 0 0 105MSPS 2.4MHz @ –6dBFS SNR = 78.2dB (79.2dBFS) SFDR = 90dBc –20 –40 AMPLITUDE (dBFS) SECOND HARMONIC –60 THIRD HARMONIC –80 –100 –120 THIRD HARMONIC –80 –100 –120 10 20 30 FREQUENCY (MHz) 40 50 –140 0 Figure 20. AD9268-105 Single-Tone FFT with fIN = 2.4 MHz 10 20 30 FREQUENCY (MHz) 40 08123-077 0 08123-074 –140 50 Figure 23. AD9268-105 Single-Tone FFT with fIN = 200.3 MHz 0 0 105MSPS 70.1MHz @ –1dBFS SNR = 77.5dB (78.5dBFS) SFDR = 93.0dBc –20 105MSPS 70.1MHz @ –6dBFS SNR = 72.7dB (78.7dBFS) SFDR = 97.6dBc –20 –40 –60 AMPLITUDE (dBFS) –40 SECOND HARMONIC THIRD HARMONIC –80 –100 –120 –60 SECOND HARMONIC THIRD HARMONIC –80 –100 –120 0 10 20 30 FREQUENCY (MHz) 40 50 –140 08123-075 –140 Figure 21. AD9268-105 Single-Tone FFT with fIN = 70.1 MHz 0 10 20 30 FREQUENCY (MHz) 40 08123-078 AMPLITUDE (dBFS) SECOND HARMONIC –60 50 Figure 24. AD9268-105 Single-Tone FFT with fIN = 70.1 MHz with Dither Enabled 120 0 105MSPS 140.1MHz @ –1dBFS SNR = 75.7dB (76.7dBFS) SFDR = 85.5dBc 100 SNR/SFDR (dBc AND dBFS) –20 –40 SECOND HARMONIC –60 THIRD HARMONIC –80 –100 80 60 40 SNR (dBFS) SFDR (dBc) SNR (dBc) SFDR (dBFS) 20 –120 0 10 20 30 FREQUENCY (MHz) 40 50 Figure 22. AD9268-105 Single-Tone FFT with fIN = 140.1 MHz 0 –100 08123-076 –140 –90 –80 –70 –60 –50 –40 –30 INPUT AMPLITUDE (dBFS) –20 –10 0 08123-079 AMPLITUDE (dBFS) –40 AMPLITUDE (dBFS) 105MSPS 200.3MHz @ –1dBFS SNR = 74.0dB (75.0dBFS) SFDR = 79dBc –20 Figure 25. AD9268-105 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 98.12 MHz Rev. A | Page 19 of 44 AD9268 250,000 120 2.23 LSB rms 200,000 NUMBER OF HITS 100 90 SNRFS (DITHER ON) SNRFS (DITHER OFF) SFDRFS (DITHER ON) SFDRFS (DITHER OFF) 150,000 100,000 50,000 80 –80 –70 –60 –50 –40 –30 INPUT AMPLITUDE (dBFS) –20 –10 0 0 N – 11 N – 10 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 –90 08123-080 70 –100 08123-083 SNR/SFDR (dBFS) 110 OUTPUT CODE Figure 26. AD9268-105 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 30 MHz with and without Dither Enabled Figure 29. AD9268-105 Grounded Input Histogram 6 100 SNR @ –40°C SFDR @ –40°C SNR @ +25°C SFDR @ +25°C SNR @ +85°C SFDR @ +85°C 90 4 INL ERROR (LSB) 85 80 2 0 –2 75 –4 70 0 50 100 150 200 INPUT FREQUENCY (MHz) 250 300 –6 08123-081 65 0 105 30,000 40,000 OUTPUT CODE 50,000 60,000 1.00 SNR, CHANNEL B SFDR, CHANNEL B SNR, CHANNEL A SFDR, CHANNEL A 0.75 0.50 95 DNL ERROR (LSB) SNR/SFDR (dBFS AND dBc) 20,000 Figure 30. AD9268-105 INL with fIN = 9.7 MHz Figure 27. AD9268-105 Single-Tone SNR/SFDR vs. Input Frequency (fIN) with 2 V p-p Full Scale 100 10,000 08123-084 SNR/SFDR (dBFS AND dBc) 95 DITHER ENABLED DITHER DISABLED 90 85 0.25 0 –0.25 –0.50 80 08123-082 –1.00 0 Figure 28. AD9268-105 Single-Tone SNR/SFDR vs. Sample Rate (fS) with fIN = 70.1 MHz 10,000 20,000 30,000 40,000 OUTPUT CODE 50,000 Figure 31. AD9268-105 DNL with fIN = 9.7 MHz Rev. A | Page 20 of 44 60,000 08123-073 –0.75 75 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 SAMPLE RATE (MSPS) AD9268 0 0 125MSPS 2.4MHz @ –1dBFS SNR = 77.7dB (78.7dBFS) SFDR = 90dBc –20 –40 –60 AMPLITUDE (dBFS) SECOND HARMONIC THIRD HARMONIC –80 –100 –120 THIRD HARMONIC SECOND HARMONIC –80 –100 10 20 30 40 FREQUENCY (MHz) 50 60 –140 08123-016 0 0 10 20 30 40 FREQUENCY (MHz) 50 60 08123-019 –120 –140 Figure 35. AD9268-125 Single-Tone FFT with fIN = 140.1 MHz Figure 32. AD9268-125 Single-Tone FFT with fIN = 2.4 MHz 0 0 125MSPS 30.3MHz @ –1dBFS SNR = 77.4dB (78.4dBFS) SFDR = 91.2dBc –20 125MSPS 200.3MHz @ –1dBFS SNR = 74.7dB (75.7dBFS) SFDR = 80dBc –20 –40 AMPLITUDE (dBFS) –40 –60 THIRD HARMONIC –80 SECOND HARMONIC –100 –60 THIRD HARMONIC SECOND HARMONIC –80 –100 –120 –120 –140 0 10 20 30 40 FREQUENCY (MHz) 50 60 0 08123-017 –140 10 20 30 40 FREQUENCY (MHz) 50 60 08123-020 AMPLITUDE (dBFS) –60 Figure 36. AD9268-125 Single-Tone FFT with fIN = 200.3 MHz Figure 33. AD9268-125 Single-Tone FFT with fIN = 30.3 MHz 0 0 125MSPS 70.1MHz @ –1dBFS SNR = 77.2dB (78.2dBFS) SFDR = 87.8dBc –20 125MSPS 220.1MHz @ –1dBFS SNR = 74.3dB (75.3dBFS) SFDR = 78.5dBc –20 –40 –60 AMPLITUDE (dBFS) –40 THIRD HARMONIC SECOND HARMONIC –80 –100 THIRD HARMONIC –60 SECOND HARMONIC –80 –100 –120 –120 –140 0 10 20 30 40 FREQUENCY (MHz) 50 60 0 08123-018 –140 10 20 30 40 FREQUENCY (MHz) 50 60 Figure 37. AD9268-125 Single-Tone FFT with fIN = 220.1 MHz Figure 34. AD9268-125 Single-Tone FFT with fIN = 70.1 MHz Rev. A | Page 21 of 44 08123-021 AMPLITUDE (dBFS) –40 AMPLITUDE (dBFS) 125MSPS 140.1MHz @ –1dBFS SNR = 76.0dB (77.0dBFS) SFDR = 84.0dBc –20 AD9268 0 120 125MSPS 70.1MHz @ –6dBFS SNR = 72.2dB (78.2dBFS) SFDR = 97dBc SFDR (dBFS) 100 SNR/SFDR (dBc AND dBFS) –20 –60 –80 SECOND HARMONIC THIRD HARMONIC –100 60 SFDR (dBc) 40 SNR (dBc) 20 –120 0 10 20 30 40 FREQUENCY (MHz) 50 60 0 –100 08123-022 –140 Figure 38. AD9268-125 Single-Tone FFT with fIN = 70.1 MHz @ −6 dBFS with Dither Enabled –90 –80 –70 –60 –50 –40 –30 INPUT AMPLITUDE (dBFS) –20 –10 0 Figure 41. AD9268-125 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 2.4 MHz 120 0 SFDR (dBFS) 125MSPS 70.1MHz @ –23dBFS SNR = 56.8dB (79.8dBFS) SFDR = 67.7dBc –30 100 SNR/SFDR (dBc AND dBFS) –15 AMPLITUDE (dBFS) SNR (dBFS) 80 08123-023 AMPLITUDE (dBFS) –40 –45 –60 THIRD HARMONIC –75 SECOND HARMONIC –90 –105 –120 SNR (dBFS) 80 60 SFDR (dBc) 40 SNR (dBc) 20 0 6 12 18 24 30 36 42 FREQUENCY (MHz) 48 54 60 0 –100 08123-088 –150 Figure 39. AD9268-125 Single-Tone FFT with fIN = 70.1 MHz @ −23 dBFS with Dither Disabled, 1M Sample –80 –70 –60 –50 –40 –30 INPUT AMPLITUDE (dBFS) –20 –10 0 Figure 42. AD9268-125 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 98.12 MHz 120 0 125MSPS 70.1MHz @ –23dBFS SNR = 56.2dB (57.2dBFS) SFDR = 86.6dBc –15 –30 SFDR (DITHER ON) 110 –45 SNR/SFDR (dBFS) AMPLITUDE (dBFS) –90 08123-024 –135 –60 –75 SECOND HARMONIC THIRD HARMONIC –90 100 SFDR (DITHER OFF) 90 –105 SNR (DITHER OFF) 80 –120 SNR (DITHER ON) 0 6 12 18 24 30 36 42 FREQUENCY (MHz) 48 54 60 70 –100 08123-089 –150 Figure 40. AD9268-125 Single-Tone FFT with fIN = 70.1 MHz @ −23 dBFS with Dither Enabled, 1M Sample –90 –80 –70 –60 –50 –40 –30 INPUT AMPLITUDE (dBFS) –20 –10 0 08123-061 –135 Figure 43. AD9268-125 Single Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 30 MHz with and without Dither Enabled Rev. A | Page 22 of 44 AD9268 0 100 SNR @ –40°C SFDR @ –40°C SNR @ +25°C SFDR @ +25°C SNR @ +85°C SFDR @ +85°C 90 –20 SFDR/IMD3 (dBc AND dBFS) SNR/SFDR (dBFS AND dBc) 95 85 80 75 SFDR (dBc) –40 –60 IMD3 (dBc) –80 SFDR (dBFS) –100 70 100 150 200 INPUT FREQUENCY (MHz) 250 300 Figure 44. AD9268-125 Single-Tone SNR/SFDR vs. Input Frequency (fIN) with 2 V p-p Full Scale 0 90 –20 AMPLITUDE (dBFS) 80 SNR (dBFS) 125MSPS 29.1MHz @ –7dBFS 32.1MHz @ –7dBFS SFDR = 89dBc (96dBFS) –80 –100 65 –120 60 100 150 200 INPUT FREQUENCY (MHz) 250 300 –140 0 Figure 45. AD9268-125 Single-Tone SNR/SFDR vs. Input Frequency (fIN) with 1 V p-p Full Scale 10 20 30 40 FREQUENCY (MHz) 50 60 Figure 48. AD9268-125 Two-Tone FFT with fIN1 = 29.1 MHz and fIN2 = 32.1 MHz 0 0 125MSPS 169.1MHz @ –7dBFS 172.1MHz @ –7dBFS SFDR = 81.8dBc (88.8dBFS) –20 –20 SFDR (dBc) –40 AMPLITUDE (dBFS) SFDR/IMD3 (dBc AND dBFS) –6 –60 70 50 –18 –40 08123-026 SNR/SFDR (dBFS/dBc) SFDR (dBc) 85 0 –66 –54 –42 –30 INPUT AMPLITUDE (dBFS) Figure 47. AD9268-125 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 169.1 MHz, fIN2 = 172.1 MHz, fS = 125 MSPS 95 75 –78 08123-029 50 08123-025 0 –120 –90 08123-028 IMD3 (dBFS) 65 –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 –60 –80 –100 –120 –66 –54 –42 –30 INPUT AMPLITUDE (dBFS) –18 –6 Figure 46. AD9268-125 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 29.1 MHz, fIN2 = 32.1 MHz, fS = 125 MSPS Rev. A | Page 23 of 44 –140 0 10 20 30 40 FREQUENCY (MHz) 50 60 Figure 49. AD9268-125 Two-Tone FFT with fIN1 = 169.1 MHz and fIN2 = 172.1 MHz 08123-030 –78 08123-027 IMD3 (dBFS) –120 –90 AD9268 1.00 100 SFDR (dBc), CHANNEL B 0.75 95 DNL ERROR (LSB) SNR/SFDR (dBFS/dBc) 0.50 90 85 SFDR (dBc), CHANNEL A SNR (dBFS), CHANNEL B 0.25 0 –0.25 –0.50 80 35 45 55 65 75 85 95 SAMPLE RATE (MSPS) 105 115 125 –1.00 08123-031 0 Figure 50. AD9268-125 Single-Tone SNR/SFDR vs. Sample Rate (fS) with fIN = 70.1 MHz 16,384 90 2500 80 SNR/SFDR (dBFS/dBc) NUMBER OF HITS SFDR (dBc) 3000 2000 1500 1000 SNR (dBFS) 70 60 50 40 OUTPUT CODE 30 0.75 08123-059 N – 10 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 500 Figure 51. AD9268-125 Grounded Input Histogram DITHER ENABLED DITHER DISABLED 2 0 –4 32,768 OUTPUT CODE 49,152 65,536 08123-032 –2 16,384 0.80 0.85 0.90 0.95 1.00 1.05 1.10 INPUT COMMON-MODE VOLTAGE (V) 1.15 Figure 54. SNR/SFDR vs. Input Common Mode (VCM) with fIN = 30 MHz 4 INL ERROR (LSB) 65,536 100 2.27LSB rms 0 49,152 Figure 53. AD9268-125 DNL with fIN = 9.7 MHz 3500 0 32,768 OUTPUT CODE Figure 52. AD9268-125 INL with fIN = 9.7 MHz Rev. A | Page 24 of 44 1.20 08123-053 75 25 08123-033 –0.75 SNR (dBFS), CHANNEL A AD9268 EQUIVALENT CIRCUITS AVDD VIN 350Ω 08123-012 08123-007 SENSE Figure 55. Equivalent Analog Input Circuit Figure 60. Equivalent SENSE Circuit AVDD DRVDD 0.9V 26kΩ 10kΩ CLK– CSB 08123-008 CLK+ 350Ω 08123-013 10kΩ Figure 61. Equivalent CSB Input Circuit Figure 56. Equivalent Clock Input Circuit AVDD DRVDD VREF PAD 08123-009 08123-014 6kΩ Figure 62. Equivalent VREF Circuit Figure 57. Digital Output DRVDD 26kΩ 350Ω SDIO/DCS PDWN 350Ω 08123-010 08123-015 26kΩ Figure 63. Equivalent PDWN Input Circuit Figure 58. Equivalent SDIO/DCS Circuit DRVDD SCLK/DFS OR OEB 350Ω 08123-011 26kΩ Figure 59. Equivalent SCLK/DFS or OEB Input Circuit Rev. A | Page 25 of 44 AD9268 THEORY OF OPERATION The AD9268 dual-core analog-to-digital converter (ADC) design can be used for diversity reception of signals, in which the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample any fS/2 frequency segment from dc to 200 MHz, using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance. Operation to 300 MHz analog input is permitted, but it occurs at the expense of increased ADC noise and distortion. In nondiversity applications, the AD9268 can be used as a baseband or direct downconversion receiver, in which one ADC is used for I input data, and the other is used for Q input data. Synchronization capability is provided to allow synchronized timing between multiple devices. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC input; therefore, the precise values are dependent on the application. In intermediate frequency (IF) undersampling applications, any shunt capacitors should be reduced. In combination with the driving source impedance, the shunt capacitors limit the input bandwidth. Refer to the AN-742 Application Note, Frequency Domain Response of Switched-Capacitor ADCs; the AN-827 Application Note, A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs; and the Analog Dialogue article, “Transformer-Coupled Front-End for Wideband A/D Converters,” for more information on this subject (refer to www.analog.com). Programming and control of the AD9268 are accomplished using a 3-wire SPI-compatible serial interface. BIAS S S ADC ARCHITECTURE CFB CS Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residue amplifier (MDAC). The MDAC magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage of each channel contains a differential sampling circuit that can be ac- or dc-coupled in differential or singleended modes. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing digital output noise to be separated from the analog core. During power-down, the output buffers go into a high impedance state. ANALOG INPUT CONSIDERATIONS The analog input to the AD9268 is a differential switchedcapacitor circuit that has been designed for optimum performance while processing a differential input signal. The clock signal alternatively switches the input between sample mode and hold mode (see Figure 64). When the input is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within ½ of a clock cycle. CPAR1 CPAR2 H S S CS VIN– CPAR1 CPAR2 S S BIAS CFB 08123-034 The AD9268 architecture consists of a dual front-end sampleand-hold circuit, followed by a pipelined, switched-capacitor ADC. The quantized outputs from each stage are combined into a final 16-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. Sampling occurs on the rising edge of the clock. VIN+ Figure 64. Switched-Capacitor Input For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched, and the inputs should be differentially balanced. An internal differential reference buffer creates positive and negative reference voltages that define the input span of the ADC core. The span of the ADC core is set by this buffer to 2 × VREF. Input Common Mode The analog inputs of the AD9268 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = 0.5 × AVDD (or 0.9 V) is recommended for optimum performance, but the device functions over a wider range with reasonable performance (see Figure 54). An on-board common-mode voltage reference is included in the design and is available from the VCM pin. Optimum performance is achieved when the common-mode voltage of the analog input is set by the VCM pin voltage (typically 0.5 × AVDD). The VCM pin must be decoupled to ground by a 0.1 μF capacitor, as described in the Applications Information section. Rev. A | Page 26 of 44 AD9268 Common-Mode Voltage Servo In applications where there may be a voltage loss between the VCM output of the AD9268 and the analog inputs, the common-mode voltage servo can be enabled. When the inputs are ac-coupled and a resistance of >100 Ω is placed between the VCM output and the analog inputs, a significant voltage drop can occur and the common-mode voltage servo should be enabled. Setting Bit 0 in Register 0x0F to a logic high enables the VCM servo mode. In this mode, the AD9268 monitors the common-mode input level at the analog inputs and adjusts the VCM output level to keep the common-mode input voltage at an optimal level. If both channels are operational, Channel A is monitored. However, if Channel A is in power-down or standby mode, then the Channel B input is monitored. Dither The AD9268 has an optional dither mode that can be selected for one or both channels. Dithering is the act of injecting a known but random amount of white noise, commonly referred to as dither, into the input of the ADC. Dithering has the effect of improving the local linearity at various points along the ADC transfer function. Dithering can significantly improve the SFDR when quantizing small-signal inputs, typically when the input level is below −6 dBFS. As shown in Figure 65, the dither that is added to the input of the ADC through the dither DAC is precisely subtracted out digitally to minimize SNR degradation. When dithering is enabled, the dither DAC is driven by a pseudorandom number generator (PN gen). In the AD9268, the dither DAC is precisely calibrated to result in only a very small degradation in SNR and SINAD. The typical SNR and SINAD degradation values, with dithering enabled, are only 1 dB and 0.8 dB, respectively. typically at very low levels and do not limit SFDR when the ADC is quantizing large-signal inputs, dithering converts these tones to noise and produces a whiter noise floor. Small-Signal FFT For small-signal inputs, the front-end sampling circuit typically contributes very little distortion, and, therefore, the SFDR is likely to be limited by tones caused by DNL errors due to random component mismatches. Therefore, for small-signal inputs (typically, those below −6 dBFS), dithering can significantly improve SFDR by converting these DNL tones to white noise. Static Linearity Dithering also removes sharp local discontinuities in the INL transfer function of the ADC and reduces the overall peak-topeak INL. In receiver applications, utilizing dither helps to reduce DNL errors that cause small-signal gain errors. Often this issue is overcome by setting the input noise 5 dB to 10 dB above the converter noise. By utilizing dither within the converter to correct the DNL errors, the input noise requirement can be reduced. Differential Input Configurations Optimum performance is achieved while driving the AD9268 in a differential input configuration. For baseband applications, the AD8138, ADA4937-2, and ADA4938-2 differential drivers provide excellent performance and a flexible interface to the ADC. The output common-mode voltage of the ADA4938-2 is easily set with the VCM pin of the AD9268 (see Figure 66), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. 15pF AD9268 200Ω VIN ADC CORE DOUT 76.8Ω VIN 33Ω 90Ω 15Ω VIN– AVDD 5pF AD9268 ADA4938-2 0.1µF DITHER DAC 33Ω 15Ω 120Ω VIN+ VCM 08123-035 15pF Figure 65. Dither Block Diagram Large-Signal FFT In most cases, dithering does not improve SFDR for large-signal inputs close to full scale, for example, with a −1 dBFS input. For large-signal inputs, the SFDR is typically limited by front-end sampling distortion, which dithering cannot improve. However, even for such large-signal inputs, dithering may be useful for certain applications because it makes the noise floor whiter. As is common in pipeline ADCs, the AD9268 contains small DNL errors caused by random component mismatches that produce spurs or tones that make the noise floor somewhat randomly colored part-to-part. Although these tones are Figure 66. Differential Input Configuration Using the ADA4938-2 For baseband applications in which SNR is a key parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 67. To bias the analog input, the VCM voltage can be connected to the center tap of the secondary winding of the transformer. C2 R2 VIN+ R1 2V p-p 49.9Ω AD9268 C1 R1 0.1µF R2 VIN– VCM C2 Figure 67. Differential Transformer-Coupled Configuration Rev. A | Page 27 of 44 08123-036 DITHER ENABLE 08123-058 200Ω PN GEN AD9268 achieved by using a ferrite bead in series with a resistor and removing the capacitors. However, these values are dependent on the input signal and should be used only as a starting guide. The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz (MHz). Excessive signal power can also cause core saturation, which leads to distortion. Table 10. Example RC Network At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9268. For applications in which SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 68). In this configuration, the input is ac-coupled, and the CML is provided to each input through a 33 Ω resistor. These resistors compensate for losses in the input baluns to provide a 50 Ω impedance to the driver. Frequency Range (MHz) 0 to 100 100 to 200 100 to 300 1 R1 Series (Ω Each) 33 10 101 C1 Differential (pF) 5 5 Remove R2 Series (Ω Each) 15 10 66 In this configuration, R1 is a ferrite bead with a value of 10 Ω @ 100 MHz. An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use the AD8352 differential driver. An example is shown in Figure 69. See the AD8352 data sheet for more information. In the double balun and transformer configurations, the value of the input capacitors and resistors is dependent on the input frequency and source impedance and may need to be reduced or removed. Table 10 displays recommended values to set the RC network. At higher input frequencies, good performance can be C2 0.1µF 0.1µF R1 R2 2V p-p VIN+ 33Ω S S P AD9268 C1 0.1µF 33Ω 0.1µF R1 R2 VCM VIN– 08123-038 PA C2 Figure 68. Differential Double Balun Input Configuration VCC 0Ω ANALOG INPUT 16 1 8, 13 11 0.1µF 2 CD RD RG 3 ANALOG INPUT 0.1µF 0Ω R VIN+ 200Ω C AD8352 10 4 5 0.1µF 0.1µF AD9268 200Ω R 14 0.1µF 0.1µF Figure 69. Differential Input Configuration Using the AD8352 Rev. A | Page 28 of 44 VIN– VCM 08123-039 0.1µF C2 Shunt (pF Each) 15 10 Remove AD9268 VOLTAGE REFERENCE A stable and accurate voltage reference is built into the AD9268. The input range can be adjusted by varying the reference voltage applied to the AD9268, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The various reference modes are summarized in the sections that follow. The Reference Decoupling section describes the best practices PCB layout of the reference. If a resistor divider is connected external to the chip, as shown in Figure 71, the switch again sets to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output, defined as follows: R2 ⎞ VREF = 0.5 × ⎛⎜1 + ⎟ R1 ⎠ ⎝ The input range of the ADC always equals twice the voltage at the reference pin (VREF) for either an internal or an external reference. Internal Reference Connection VIN+A/VIN+B A comparator within the AD9268 detects the potential at the SENSE pin and configures the reference into four possible modes, which are summarized in Table 11. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 70), setting VREF to 1.0 V for a 2.0 V p-p fullscale input. In this mode, with SENSE grounded, the full scale can also be adjusted through the SPI port by adjusting Bit 6 and Bit 7 of Register 0x18. These bits can be used to change the full scale to 1.25 V p-p, 1.5 V p-p, 1.75 V p-p, or to the default of 2.0 V p-p, as shown in Table 17. VIN–A/VIN–B ADC CORE VREF 1.0µF 0.1µF R2 SELECT LOGIC SENSE Connecting the SENSE pin to the VREF pin switches the reference amplifier output to the SENSE pin, completing the loop and providing a 0.5 V reference output for a 1 V p-p full-scale input. VIN+A/VIN+B 08123-041 0.5V R1 AD9268 Figure 71. Programmable Reference Configuration If the internal reference of the AD9268 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 72 shows how the internal reference voltage is affected by loading. VIN–A/VIN–B ADC CORE 0 0.1µF SELECT LOGIC SENSE AD9268 08123-040 0.5V Figure 70. Internal Reference Configuration –0.5 VREF = 0.5V –1.0 VREF = 1V –1.5 –2.0 –2.5 –3.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 LOAD CURRENT (mA) 1.6 1.8 2.0 Figure 72. Reference Voltage Accuracy vs. Load Current Table 11. Reference Configuration Summary Selected Mode External Reference Internal Fixed Reference SENSE Voltage AVDD VREF Programmable Reference 0.2 V to VREF Internal Fixed Reference AGND to 0.2 V Resulting VREF (V) N/A 0.5 R2 ⎞ ⎛ 0.5 × ⎜ 1 + ⎟ (see Figure 71) R1 ⎠ ⎝ 1.0 Rev. A | Page 29 of 44 Resulting Differential Span (V p-p) 2 × external reference 1.0 2 × VREF 2.0 08123-054 1.0µF REFERENCE VOLTAGE ERROR (%) VREF AD9268 External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 73 shows the typical drift characteristics of the internal reference in 1.0 V mode. When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 6 kΩ load (see Figure 62). The internal buffer generates the positive and negative full-scale references for the ADC core. Therefore, the external reference must be limited to a maximum of 1.0 V. The RF balun configuration is recommended for clock frequencies between 125 MHz and 625 MHz, and the RF transformer is recommended for clock frequencies from 10 MHz to 200 MHz. The back-to-back Schottky diodes across the transformer/balun secondary limit clock excursions into the AD9268 to approximately 0.8 V p-p differential. This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9268 while preserving the fast rise and fall times of the signal that are critical to a low jitter performance. Mini-Circuits® ADT1-1WT, 1:1Z 0.1µF XFMR 2.0 CLOCK INPUT 1.5 VREF = 1.0V ADC AD9268 CLK+ 100Ω 50Ω 0.1µF 1.0 CLK– 0.5 SCHOTTKY DIODES: HSMS2822 0.1µF 0 08123-045 REFERENCE VOLTAGE ERROR (mV) 0.1µF Figure 75. Transformer-Coupled Differential Clock (Up to 200 MHz) –0.5 ADC –1.0 CLOCK INPUT –1.5 1nF AD9268 0.1µF CLK+ 50Ω 20 40 TEMPERATURE (°C) 60 80 0.1µF 1nF CLK– SCHOTTKY DIODES: HSMS2822 Figure 73. Typical VREF Drift Figure 76. Balun-Coupled Differential Clock (Up to 625 MHz) CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9268 sample clock inputs, CLK+ and CLK−, should be clocked with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally (see Figure 74) and require no external bias. If the inputs are floated, the CLK− pin is pulled low to prevent spurious clocking. If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 77. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516/AD9517/AD9518 clock drivers offer excellent jitter performance. AVDD 0.1µF 0.1µF CLOCK INPUT CLK+ AD951x 0.9V 0.1µF CLOCK INPUT CLK– 100Ω PECL DRIVER 0.1µF ADC AD9268 CLK– 50kΩ 240Ω 50kΩ 08123-047 CLK+ 240Ω 4pF Figure 77. Differential PECL Sample Clock (Up to 625 MHz) 08123-044 4pF 08123-046 0 Figure 74. Equivalent Clock Input Circuit Clock Input Options The AD9268 has a very flexible clock input structure. Clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations section. Figure 75 and Figure 76 show two preferred methods for clocking the AD9268 (at clock rates up to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF balun or an RF transformer. A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 78. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/ AD9518 clock drivers offer excellent jitter performance. 0.1µF 0.1µF CLOCK INPUT CLK+ AD951x 0.1µF CLOCK INPUT Rev. A | Page 30 of 44 LVDS DRIVER 100Ω 0.1µF ADC AD9268 CLK– 50kΩ 50kΩ Figure 78. Differential LVDS Sample Clock (Up to 625 MHz) 08123-048 –20 08123-055 –2.0 –40 AD9268 In some applications, it may be acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, the CLK+ pin should be driven directly from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 μF capacitor (see Figure 79). Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. For inputs near full scale, the degradation in SNR from the low frequency SNR (SNRLF) at a given input frequency (fINPUT) due to jitter (tJRMS) can be calculated by SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10 ( − SNRLF /10) ] VCC 1kΩ AD951x CLK+ CMOS DRIVER 50Ω1 ADC 1kΩ AD9268 CLK– 08123-049 0.1µF 150Ω RESISTOR IS OPTIONAL. In the equation, the rms aperture jitter represents the clock input jitter specification. IF undersampling applications are particularly sensitive to jitter, as illustrated in Figure 80. The measured curve in Figure 80 was taken using an ADC clock source with approximately 65 fs of jitter, which combines with the 70 fs of jitter inherent in the AD9268 to produce the results shown. 80 Figure 79. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) Input Clock Divider 0.05ps 75 MEASURED The AD9268 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. For divide ratios of 1, 2, or 4, the duty cycle stabilizer (DCS) is optional. For other divide ratios, divide by 3, 5, 6, 7, and 8, the duty cycle stabilizer must be enabled for proper part operation. SNR (dBc) 70 The AD9268 clock divider can be synchronized using the external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the clock divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the clock divider to reset to its initial state. This synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling. Clock Duty Cycle Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. The AD9268 requires a tight tolerance on the clock duty cycle to maintain dynamic performance characteristics. The AD9268 contains a duty cycle stabilizer (DCS) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the perfor-mance of the AD9268. Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS enabled. Jitter in the rising edge of the input is still of paramount concern and is not easily reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates of less than 20 MHz, nominally. The loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. A wait time of 1.5 μs to 5 μs is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. During the time period that the loop is not locked, the DCS loop is bypassed, and internal device timing is dependent on the duty cycle of the input clock signal. In such applications, it may be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance. 0.20ps 65 60 0.50ps 55 1.00ps 1.50ps 50 1 10 100 INPUT FREQUENCY (MHz) 1k 08123-050 0.1µF CLOCK INPUT OPTIONAL 0.1µF 100Ω Figure 80. SNR vs. Input Frequency and Jitter The clock input should be treated as an analog signal in cases in which aperture jitter may affect the dynamic range of the AD9268. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock at the last step. Refer to the AN-501 Application Note and the AN-756 Application Note (see www.analog.com) for more information about jitter performance as it relates to ADCs. CHANNEL/CHIP SYNCHRONIZATION The AD9268 has a SYNC input that offers the user flexible synchronization options for synchronizing the clock divider. The clock divider sync feature is useful for guaranteeing synchronized sample clocks across multiple ADCs. The input clock divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence. The SYNC input is internally synchronized to the sample clock; however, to ensure that there is no timing uncertainty between multiple parts, the SYNC input signal should be externally synchronized to the input clock signal, meeting the setup and hold times shown in Table 5. The SYNC input should be driven using a single-ended CMOS-type signal. Rev. A | Page 31 of 44 AD9268 1.0 POWER DISSIPATION AND STANDBY MODE where N is the number of output bits (32 plus two DCO outputs, in the case of the AD9268). Reducing the capacitive load presented to the output drivers reduces digital power consumption. The data in Figure 81 was taken in LVDS output mode, using the same operating conditions as those used for the Typical Performance Characteristics. 0.5 0.4 IAVDD 0.75 0.3 TOTAL POWER 0.50 0.2 0.25 SUPPLY CURRENT (A) TOTAL POWER (W) 1.00 0.1 08123-056 0 125 75 100 50 ENCODE FREQUENCY (MHz) Figure 81. AD9268-125 Power and Current vs. Encode Frequency (LVDS Output Mode) 1.0 0.5 0.8 0.2 IAVDD IDRVDD 0.2 SUPPLY CURRENT (A) 0.3 0 35 45 55 65 ENCODE FREQUENCY (MSPS) 75 Figure 83. AD9268-80 Power and Current vs. Encode Frequency (LVDS Output Mode) By asserting PDWN (either through the SPI port or by asserting the PDWN pin high), the AD9268 is placed in power-down mode. In this state, the ADC typically dissipates 3.3 mW. During power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the AD9268 to its normal operating mode. Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when entering powerdown mode and then must be recharged when returning to normal operation. When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. 45 55 65 75 85 ENCODE FREQUENCY (MSPS) 95 0 105 The AD9268 output drivers can be configured to interface with 1.8 V CMOS logic families. The AD9268 can also be configured for LVDS outputs (standard ANSI or reduced output swing mode) using a DRVDD supply voltage of 1.8 V. The default output mode is CMOS, with each channel output on separate busses as shown in Figure 2. The output can also be configured for interleaved CMOS via the SPI port. In interleaved CMOS mode, the data for both channels is output through the Channel A output bits, and the Channel B output is placed into high impedance mode. The timing diagram for interleaved CMOS output mode is shown in Figure 3. 0.1 35 0 25 0.05 Applications requiring the ADC to drive large capacitive loads or large fanouts may require external buffers or latches. 08123-086 TOTAL POWER (W) 0.6 0 25 IDRVDD In CMOS output mode, the output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies that may affect converter performance. 0.4 TOTAL POWER 0.4 0.10 DIGITAL OUTPUTS IDRVDD 0 25 0.15 0.4 0.2 This maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the Nyquist frequency of fCLK/2. In practice, the DRVDD current is established by the average number of output bits switching, which is determined by the sample rate and the characteristics of the analog input signal. 1.25 TOTAL POWER 0.6 SUPPLY CURRENT (A) IDRVDD = VDRVDD × CLOAD × fCLK × N 0.20 08123-087 The maximum DRVDD current (IDRVDD) can be calculated as IAVDD 0.8 TOTAL POWER (W) As shown in Figure 81, the power dissipated by the AD9268 varies with its sample rate. In CMOS output mode, the digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. 0.25 Figure 82. AD9268-105 Power and Current vs. Encode Frequency (LVDS Output Mode) The output data format can be selected for either offset binary or twos complement by setting the SCLK/DFS pin when operating in the external pin mode (see Table 12). Rev. A | Page 32 of 44 AD9268 As detailed in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, the data format can be selected for offset binary, twos complement, or gray code when using the SPI control. TIMING Table 12. SCLK/DFS Mode Selection (External Pin Mode) The AD9268 provides latched data with a pipeline delay of 12 clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Voltage at Pin AGND AVDD The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9268. These transients can degrade converter dynamic performance. SCLK/DFS Offset binary (default) Twos complement SDIO/DCS DCS disabled DCS enabled (default) The lowest typical conversion rate of the AD9268 is 10 MSPS. At clock rates below 10 MSPS, dynamic performance can degrade. Digital Output Enable Function (OEB) The AD9268 has a flexible three-state ability for the digital output pins. The three-state mode is enabled using the OEB pin or through the SPI. If the OEB pin is low, the output data drivers and DCOs are enabled. If the OEB pin is high, the output data drivers and DCOs are placed in a high impedance state. This OEB function is not intended for rapid access to the data bus. Note that OEB is referenced to the digital output driver supply (DRVDD) and should not exceed that supply voltage. When using the SPI, the data outputs and DCO of each channel can be independently three-stated by using the output enable bar bit (Bit 4) in Register 0x14. Data Clock Output (DCO) The AD9268 provides two data clock output (DCO) signals intended for capturing the data in an external register. In CMOS output mode, the data outputs are valid on the rising edge of DCO, unless the DCO clock polarity has been changed via the SPI. In LVDS output mode, the DCO and data output switching edges are closely aligned. Additional delay can be added to the DCO output using SPI Register 0x17 to increase the data setup time. In this case, the Channel A output data is valid on the rising edge of DCO, and the Channel B output data is valid on the falling edge of DCO. See Figure 2, Figure 3, and Figure 4 for a graphical timing description of the output modes. Table 13. Output Data Format Input (V) VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− Condition (V) < −VREF − 0.5 LSB = −VREF =0 = +VREF − 1.0 LSB > +VREF − 0.5 LSB Offset Binary Output Mode 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 Rev. A | Page 33 of 44 Twos Complement Mode 1000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0111 1111 1111 1111 0111 1111 1111 1111 OR 1 0 0 0 1 AD9268 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9268 includes built-in test features designed to enable verification of the integrity of each channel as well as facilitate board level debugging. A BIST (built-in self-test) feature is included that verifies the integrity of the digital datapath of the AD9268. Various output test options are also provided to place predictable values on the outputs of the AD9268. BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9268 signal path. When enabled, the test runs from an internal pseudorandom noise (PN) source through the digital datapath starting at the ADC block output. The BIST sequence runs for 512 cycles and stops. The BIST signature value for Channel A or Channel B is placed in Register 0x24 and Register 0x25. If one channel is chosen, its BIST signature is written to the two registers. If both channels are chosen, the results from Channel A are placed in the BIST signature registers. The outputs are not disconnected during this test, so the PN sequence can be observed as it runs. The PN sequence can be continued from its last value or reset from the beginning, based on the value programmed in Register 0x0E, Bit 2. The BIST signature result varies based on the channel configuration. OUTPUT TEST MODES The output test options are shown in Table 17. When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back end blocks and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting, and some are not. The seed value for the PN sequence tests can be forced if the PN reset bits are used to hold the generator in reset mode by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Rev. A | Page 34 of 44 AD9268 SERIAL PORT INTERFACE (SPI) The AD9268 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, which are documented in the Memory Map section. For detailed operational information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The falling edge of the CSB, in conjunction with the rising edge of the SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 84 and Table 5. CONFIGURATION USING THE SPI During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 and W1 bits. Other modes involving the CSB are available. When the CSB is held low indefinitely, which permanently enables the device, this is called streaming. The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in high impedance mode. This mode turns on any SPI pin secondary functions. Three pins define the SPI of this ADC: the SCLK/DFS pin, the SDIO/DCS pin, and the CSB pin (see Table 14). The SCLK/DFS (a serial clock) is used to synchronize the read and write data presented from and to the ADC. The SDIO/DCS (serial data input/output) is a dual-purpose pin that allows data to be sent to and read from the internal ADC memory map registers. The CSB (chip select bar) is an active-low control that enables or disables the read and write cycles. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. The first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Table 14. Serial Port Interface Pins Pin SCLK SDIO CSB Function Serial Clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. Serial Data Input/Output. A dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip Select Bar. An active-low control that gates the read and write cycles. tHIGH tDS tS tDH All data is composed of 8-bit words. Data can be sent in MSB-first mode or in LSB-first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. tCLK tH tLOW CSB SDIO DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 Figure 84. Serial Port Interface Timing Diagram Rev. A | Page 35 of 44 D4 D3 D2 D1 D0 DON’T CARE 08123-052 SCLK DON’T CARE AD9268 HARDWARE INTERFACE The pins described in Table 14 comprise the physical interface between the user programming device and the serial port of the AD9268. The SCLK pin and the CSB pin function as inputs when using the SPI. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9268 to prevent these signals from transitioning at the converter inputs during critical sampling periods. Some pins serve a dual function when the SPI is not being used. When the pins are strapped to AVDD or ground during device power-on, they are associated with a specific function. The Digital Outputs section describes the strappable functions supported on the AD9268. When the device is in SPI mode, the PDWN and OEB pins remain active. For SPI control of output enable and power-down, the OEB and PDWN pins should be set to their default states. Table 15. Mode Selection Pin SDIO/DCS SCLK/DFS OEB PDWN AGND (default) Configuration Duty cycle stabilizer enabled Duty cycle stabilizer disabled Twos complement enabled Offset binary enabled Outputs in high impedance Outputs enabled Chip in power-down or standby Normal operation SPI ACCESSIBLE FEATURES Table 16 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9268 part-specific features are described in detail following Table 17, the external memory map register table. Table 16. Features Accessible Using the SPI Feature Name Mode CONFIGURATION WITHOUT THE SPI In applications that do not interface to the SPI control registers, the SDIO/DCS pin, the SCLK/DFS pin, the OEB pin, and the PDWN pin serve as standalone CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer, output data format, output enable, and power-down feature control. In this mode, the CSB chip select bar should be connected to AVDD, which disables the serial port interface. External Voltage AVDD (default) AGND AVDD AGND (default) AVDD AGND (default) AVDD Clock Offset Test I/O Output Mode Output Phase Output Delay VREF Rev. A | Page 36 of 44 Description Allows the user to set either power-down mode or standby mode Allows the user to access the DCS, set the clock divider, set the clock divider phase, and enable the sync Allows the user to digitally adjust the converter offset Allows the user to set test modes to have known data on output bits Allows the user to set the output mode, including LVDS Allows the user to set the output clock polarity Allows the user to vary the DCO delay Allows the user to set the reference voltage AD9268 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Logic Levels Each row in the memory map register table has eight bit locations. The memory map is roughly divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02); the channel index and transfer registers (Address 0x05 and Address 0xFF); the ADC functions registers, including setup, control, and test (Address 0x08 to Address 0x30); and the digital feature control register (Address 0x100). An explanation of logic level terminology follows: The memory map register table (see Table 17) documents the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x18, the VREF select register, has a hexadecimal default value of 0xC0. This means that Bit 7 = 1, Bit 6 = 1, and the remaining bits are 0s. This setting is the default reference selection setting. The default value uses a 2.0 V p-p reference. For more information on this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This application note details the functions controlled by Register 0x00 to Register 0xFF. The remaining register, Register 0x100, is documented in the Memory Map Register Table section. Open Locations All address and bit locations that are not included in Table 17 are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written. • • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” Transfer Register Map Address 0x08 through Address 0x18 and Address 0x30 are shadowed. Writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to Address 0xFF, setting the transfer bit. This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes place when the transfer bit is set, and the bit autoclears. Channel-Specific Registers Some channel setup functions, such as the signal monitor thresholds, can be programmed differently for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Table 17 as local. These local registers and bits can be accessed by setting the appropriate Channel A or Channel B bits in Register 0x05. If both bits are set, the subsequent write affects the registers of both channels. In a read cycle, only Channel A or Channel B should be set to read one of the two registers. If both bits are set during an SPI read cycle, the part returns the value for Channel A. Registers and bits designated as global in Table 17 affect the entire part or the channel features for which independent settings are not allowed between channels. The settings in Register 0x05 do not affect the global registers and bits. Default Values After the AD9268 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 17. Rev. A | Page 37 of 44 AD9268 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 17 are not currently supported for this device. Table 17. Memory Map Registers Address Register Bit 7 (Hex) Name (MSB) Chip Configuration Registers 0x00 0 SPI port configuration (global) 0x01 Chip ID (global) 0x02 Chip grade (global) Open Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) LSB first Soft reset 1 1 Soft reset LSB first 0 8-bit Chip ID[7:0] (AD9268 = 0x32) (default) Speed grade ID Open 01 = 125 MSPS 10 = 105 MSPS 11 = 80 MSPS Open Default Value (Hex) Default Notes/ Comments 0x18 The nibbles are mirrored so LSB-first mode or MSBfirst mode registers correctly, regardless of shift mode Read only 0x32 Open Open Open Speed grade ID used to differentiate devices; read only Channel Index and Transfer Registers 0x05 Open Channel index Open Open Open Open Open Data Channel B (default) Data Channel A (default) 0x03 0xFF Open Open Open Open Open Open Open Transfer 0x00 ADC Functions 0x08 Power modes (local) 1 Open Open Open Open Internal power-down mode (local) 00 = normal operation 01 = full power-down 10 = standby 11 = normal operation 0x80 0x09 Global clock (global) Open Open External powerdown pin function (local) 0 = pdwn 1 = stndby Open Open Open Open Open 0x01 0x0B Clock divide (global) Open Open Open Open Open 0x0D Test mode (local) Open Open Reset PN long gen Reset PN short gen Transfer Open Rev. A | Page 38 of 44 Duty cycle stabilizer (default) Clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 Output test mode 000 = off (default) 001 = midscale short 010 = positive FS 011 = negative FS 100 = alternating checkerboard 101 = PN long sequence 110 = PN short sequence 111 = one/zero word toggle Bits are set to determine which device on the chip receives the next write command; applies to local registers only Synchronously transfers data from the master shift register to the slave Determines various generic modes of chip operation 0x00 Clock divide values other than 000 automatically cause the duty cycle stabilizer to become active 0x00 When this register is set, the test data is placed on the output pins in place of normal data AD9268 Address (Hex) 0x0E 0x0F 0x10 0x14 Register Name BIST enable (global) ADC input (global) Offset adjust (local) Output mode Bit 7 (MSB) Open Bit 6 Open Bit 5 Open Bit 4 Open Bit 3 Open Bit 2 Reset BIST sequence Bit 1 Open Open Open Open Open Open Open Open Commonmode servo enable Drive strength 0 = ANSI LVDS; 1= reduced swing LVDS (global) Invert DCO clock Output type 0 = CMOS 1 = LVDS (global) CMOS output interleave enable (global) Output enable bar (local) Open (must be written low) Open Open Open Open Open Open Clock phase control (global) 0x17 DCO output delay (global) Open 0x18 VREF select (global) Reference voltage selection 00 = 1.25 V p-p 01 = 1.5 V p-p 10 = 1.75 V p-p 11 = 2.0 V p-p (default) Open 0x24 Open Output invert (local) Default Value (Hex) 0x04 Default Notes/ Comments 0x00 0x00 Offset adjust in LSBs from +127 to −128 (twos complement format) 0x16 BIST signature LSB (local) 0x25 BIST signature MSB (local) 0x30 Dither enable (local) Digital Feature Control 0x100 Sync control (global) Bit 0 (LSB) BIST enable Output format 00 = offset binary 01 = twos complement 01 = gray code 11 = offset binary (local) Input clock divider phase adjust 000 = no delay 001 = 1 input clock cycle 010 = 2 input clock cycles 011 = 3 input clock cycles 100 = 4 input clock cycles 101 = 5 input clock cycles 110 = 6 input clock cycles 111 = 7 input clock cycles DCO clock delay (delay = 2500 ps × register value/31) 00000 = 0 ps 00001 = 81 ps 00010 = 161 ps … 11110 = 2419 ps 11111 = 2500 ps Open Open Open Open 0x00 Configures the outputs and the format of the data 0x00 Allows selection of clock delays into the input clock divider 0x00 0xC0 BIST signature[7:0] 0x00 Read only BIST signature[15:8] 0x00 Read only Open Open Open Dither enable Open Open Open Open 0x00 Open Open Open Open Open Clock divider next sync only Clock divider sync enable Master sync enable 0x00 Rev. A | Page 39 of 44 AD9268 MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. ignore the rest. The clock divider sync enable bit (Address 0x100, Bit 1) resets after it syncs. Bit 1—Clock Divider Sync Enable Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 1 gates the sync pulse to the clock divider. The sync signal is enabled when Bit 1 is high and Bit 0 is high. This is continuous sync mode. Bit 2—Clock Divider Next Sync Only Bit 0—Master Sync Enable If the master sync enable bit (Address 0x100, Bit 0) and the clock divider sync enable bit (Address 0x100, Bit 1) are high, Bit 2 allows the clock divider to sync to the first sync pulse it receives and to Bit 0 must be high to enable any of the sync functions. If the sync capability is not used this bit should remain low to conserve power. Rev. A | Page 40 of 44 AD9268 APPLICATIONS INFORMATION DESIGN GUIDELINES Before starting design and layout of the AD9268 as a system, it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements that are needed for certain pins. Power and Ground Recommendations When connecting power to the AD9268, it is recommended that two separate 1.8 V supplies be used. Use one supply for analog (AVDD); use a separate supply for the digital outputs (DRVDD). For both AVDD and DRVDD several different decoupling capacitors should be used to cover both high and low frequencies. Place these capacitors close to the point of entry at the PCB level and close to the pins of the part, with minimal trace length. A single PCB ground plane should be sufficient when using the AD9268. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be filled or plugged to prevent solder wicking through the vias, which can compromise the connection. To maximize the coverage and adhesion between the ADC and the PCB, a silkscreen should be overlaid to partition the continuous plane on the PCB into several uniform sections. This provides several tie points between the ADC and the PCB during the reflow process. Using one continuous plane with no partitions guarantees only one tie point between the ADC and the PCB. For detailed information about packaging and PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com. VCM The VCM pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 67. LVDS Operation RBIAS The AD9268 defaults to CMOS output mode on power-up. If LVDS operation is desired, this mode must be programmed, using the SPI configuration registers after power-up. When the AD9268 powers up in CMOS mode with LVDS termination resistors (100 Ω) on the outputs, the DRVDD current can be higher than the typical value until the part is placed in LVDS mode. This additional DRVDD current does not cause damage to the AD9268, but it should be taken into account when considering the maximum DRVDD current for the part. The AD9268 requires that a 10 kΩ resistor be placed between the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance. To avoid this additional DRVDD current, the AD9268 outputs can be disabled at power-up by taking the OEB pin high. After the part is placed in LVDS mode via the SPI port, the OEB pin can be taken low to enable the outputs. The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9268 to keep these signals from transitioning at the converter inputs during critical sampling periods. Exposed Paddle Thermal Heat Slug Recommendations It is mandatory that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance. A continuous, exposed (no solder mask) copper plane on the PCB should mate to the AD9268 exposed paddle, Pin 0. Reference Decoupling The VREF pin should be externally decoupled to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic capacitor. SPI Port Rev. A | Page 41 of 44 AD9268 OUTLINE DIMENSIONS 0.60 MAX 9.00 BSC SQ 0.60 MAX 64 1 49 PIN 1 INDICATOR 48 PIN 1 INDICATOR 8.75 BSC SQ 0.50 BSC 0.50 0.40 0.30 1.00 0.85 0.80 16 17 33 32 0.25 MIN 7.50 REF 0.80 MAX 0.65 TYP 12° MAX 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 7.65 7.50 SQ 7.35 EXPOSED PAD (BOTTOM VIEW) 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4 041509-A TOP VIEW Figure 85. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad (CP-64-6) Dimensions shown in millimeters ORDERING GUIDE Model AD9268BCPZ-80 1 AD9268BCPZRL7-801 AD9268BCPZ-1051 AD9268BCPZRL7-1051 AD9268BCPZ-1251 AD9268BCPZRL7-1251 AD9268-80EBZ1 AD9268-105EBZ1 AD9268-125EBZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Evaluation Board Evaluation Board Z = RoHS Compliant Part. Rev. A | Page 42 of 44 Package Option CP-64-6 CP-64-6 CP-64-6 CP-64-6 CP-64-6 CP-64-6 AD9268 NOTES Rev. A | Page 43 of 44 AD9268 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08123-0-9/09(A) Rev. A | Page 44 of 44