1+$+$"$ 64K x 16 HIGH-SPEED CMOS STATIC RAM FEATURES High-speed access time: 10, 12, 15, and 20 ns CMOS low power operation 1650 mW (max) @ -10ns Cycle 55 mW (max) CMOS Standby TTL compatible interface levels Single 5V ± 10% power supply Fully static operation: no clock or refresh required Three state outputs Industrial temperature available Available in 44-pin SOJ package and 44-pin TSOP-2 DESCRIPTION The 1+51 IC61C6416 is a high-speed, 1,048,576-bit static RAM organized as 65,536 words by 16 bits. It is fabricated using 1+51's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 10 ns with low power consumption. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IC61C6416 is packaged in the JEDEC standard 44-pin 400mil SOJ and 44-pin 400mil TSOP-2. FUNCTIONAL BLOCK DIAGRAM A0-A15 DECODER 64K x 16 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VCC GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte CE OE WE CONTROL CIRCUIT UB LB ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. Integrated Circuit Solution Inc. AHSR011-0A 05/23/2001 1 1+$+$"$ PIN CONFIGURATIONS 44-Pin TSOP-2 44-Pin SOJ A15 1 44 A0 A14 2 43 A1 A13 3 42 A2 A12 4 41 OE A11 5 40 UB CE 6 39 LB I/O0 7 38 I/O15 I/O1 8 37 I/O14 I/O2 9 36 I/O13 I/O3 10 35 I/O12 Vcc 11 34 GND GND 12 33 Vcc I/O4 13 32 I/O11 I/O5 14 31 I/O10 I/O6 15 30 I/O9 I/O7 16 29 I/O8 WE 17 28 NC A10 18 27 A3 A9 19 26 A4 A8 20 25 A5 A7 21 24 A6 NC 22 23 NC A15 A14 A13 A12 A11 CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A10 A9 A8 A7 NC 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A0 A1 A2 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC A3 A4 A5 A6 NC PIN DESCRIPTIONS A0-A15 Address Inputs LB Lower-byte Control (I/O0-I/O7) I/O0-I/O15 Data Inputs/Outputs UB Upper-byte Control (I/O8-I/O15) CE Chip Enable Input NC No Connection OE Output Enable Input Vcc Power WE Write Enable Input GND Ground TRUTH TABLE Mode Not Selected Output Disabled Read Write 2 WE CE OE LB UB X H X H H H L L L H L L L L L L L L X H X L L L X X X X X H L H L L H L X X H H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN Vcc Current ISB, ISB ICC, ICC ICC, ICC ICC, ICC Integrated Circuit Solution Inc. AHSR011-0A 05/23/2001 1+$+$"$ ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Storage Temperature Power Dissipation DC Output Current (LOW) Value 0.5 to +7.0 65 to +150 1.5 20 Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Unit V °C W mA OPERATING RANGE Range Commercial Ambient Temperature 0°C to +70°C Industrial Speed -10, -12 -15, -20 -12 -15, -20 40°C to +85°C ! VCC 5V ± 5% 5V ± 10% 5V ± 5% 5V ± 10% " # DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = 4.0 mA 2.4 V VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 V VIH Input HIGH Voltage(1) 2.2 VCC + 0.5 V VIL Input LOW Voltage(2) 0.5 0.8 V ILI Input Leakage GND ≤ VIN ≤ VCC 2 2 µA ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled 2 2 µA $ % Notes: 1. VIH=VCC +3.0V for pulse width less than 10ns. 2. VIL = 3.0V for pulse width less than 10 ns. & ' POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -10 Min. Max. -12 Min. Max. -15 Min. Max. -20 Min. Max. Symbol Parameter Test Conditions ICC Vcc Dynamic Operating Supply Current VCC = Max., IOUT = 0 mA, f = MAX Com. Ind. 300 280 300 260 290 235 255 mA ISB TTL Standby Current (TTL Inputs) VCC = Max., VIN = VIH or VIL CE ≥ VIH , f = 0 Com. Ind. 50 50 55 50 55 50 55 mA ISB CMOS Standby Current (CMOS Inputs) VCC = Max., CE ≥ VCC 0.2V, VIN ≥ VCC 0.2V, or VIN ≤ 0.2V, f = 0 Com. Ind. 10 10 15 10 15 10 15 mA Unit Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. Integrated Circuit Solution Inc. AHSR011-0A 05/23/2001 3 1+$+$"$ CAPACITANCE(1) Symbol Parameter CIN Input Capacitance COUT Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Note: 1. Tested initially and after any design or process changes that may affect these parameters. READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol -10 Min. Max. Parameter -12 Min. Max. -15 Min. Max. -20 Min. Max. Unit tRC tAA tOHA tACE tDOE tHZOE tLZOE tHZCE tLZCE tBA tHZB Read Cycle Time 10 12 15 20 ns Address Access Time 10 12 15 20 ns Output Hold Time 3 3 3 4 ns CE Access Time 10 12 15 20 ns OE Access Time 5 6 7 9 ns OE to High-Z Output 5 6 0 6 0 8 ns OE to Low-Z Output 0 0 0 0 ns CE to High-Z Output 0 5 0 6 0 6 0 8 ns CE to Low-Z Output 3 3 3 3 ns LB, UB Access Time 5 6 7 9 ns LB, UB to High-Z Output 0 5 0 6 0 6 0 8 ns tLZB LB, UB to Low-Z Output 0 0 0 0 ns Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2 AC TEST LOADS 480 Ω 480 Ω 5V 5V OUTPUT OUTPUT 30 pF Including jig and scope Figure 1 4 255 Ω 255 Ω 5 pF Including jig and scope Figure 2 Integrated Circuit Solution Inc. AHSR011-0A 05/23/2001 1+$+$"$ AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL) t RC ADDRESS t AA t OHA t OHA DOUT ! DATA VALID PREVIOUS DATA VALID " READ CYCLE NO. 2(1,3) t RC # ADDRESS t AA t OHA $ OE t HZOE t DOE % t LZOE CE t ACE t HZCE t LZCE & LB, UB DOUT HIGH-Z t LZB t BA t HZB ' DATA VALID Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition. Integrated Circuit Solution Inc. AHSR011-0A 05/23/2001 5 1+$+$"$ WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol Parameter -10 Min. Max. -12 Min. Max. -15 Min. Max. -20 Min. Max. Unit tWC Write Cycle Time 10 12 15 20 ns tSCE CE to Write End 8 9 10 12 ns tAW Address Setup Time to Write End 8 9 10 12 ns tHA Address Hold from Write End 0 0 0 0 ns tSA Address Setup Time 0 0 0 0 ns tPWB LB, UB Valid to End of Write 8 9 10 12 ns tPWE WE Pulse Width 8 9 10 12 ns tSD Data Setup to Write End 5 6 7 9 ns Data Hold from Write End 0 0 0 0 ns WE LOW to High-Z Output 5 6 7 9 ns tLZWE WE HIGH to Low-Z Output 3 3 3 3 ns tHD tHZWE Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 6 Integrated Circuit Solution Inc. AHSR011-0A 05/23/2001 1+$+$"$ AC WAVEFORMS WRITE CYCLE NO. 1 (WE WE Controlled)(1,2) t WC VALID ADDRESS ADDRESS t SA t SCE t HA CE ! t AW t PWE1 t PWE2 WE " t PBW UB, LB t HZWE DOUT DATA UNDEFINED t SD DIN # t LZWE HIGH-Z $ t HD DATAIN VALID % Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE). & ' Integrated Circuit Solution Inc. AHSR011-0A 05/23/2001 7 1+$+$"$ WRITE CYCLE NO. 2(OE is HIGH During Write Cycle) (1,2) t WC ADDRESS VALID ADDRESS t HA OE CE LOW t AW t PWE1 WE t SA t PBW UB, LB t HZWE DOUT t LZWE HIGH-Z DATA UNDEFINED t SD t HD DATAIN VALID DIN WRITE CYCLE NO. 3(OE is LOW During Write Cycle) (1) t WC ADDRESS VALID ADDRESS OE LOW CE LOW t HA t AW t PWE2 WE t SA t PBW UB, LB t HZWE DOUT DATA UNDEFINED t LZWE HIGH-Z t SD DIN t HD DATAIN VALID Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE > VIH. 8 Integrated Circuit Solution Inc. AHSR011-0A 05/23/2001 1+$+$"$ WRITE CYCLE NO. 4(UB/LB Back to Back Write) t WC ADDRESS t WC ADDRESS 1 ADDRESS 2 OE t SA CE LOW t HA t SA WE UB, LB t PBW t PBW WORD 1 WORD 2 t HZWE DOUT ! t HA " t LZWE HIGH-Z # DATA UNDEFINED t HD t SD DIN DATAIN VALID t HD t SD DATAIN VALID $ % & ' Integrated Circuit Solution Inc. AHSR011-0A 05/23/2001 9 1+$+$"$ ORDERING INFORMATION Commercial Range: 0°C to +70°C ORDERING INFORMATION Industrial Range: 40°C to +85°C Speed (ns) Order Part No. Package Speed (ns) Order Part No. Package 10 10 IC61C6416-10T IC61C6416-10K 400mil TSOP-2 400mil SOJ 12 12 IC61C6416-12TI IC61C6416-12KI 400mil TSOP-2 400mil SOJ 12 12 IC61C6416-12T IC61C6416-12K 400mil TSOP-2 400mil SOJ 15 15 IC61C6416-15TI IC61C6416-15KI 400mil TSOP-2 400mil SOJ 15 15 IC61C6416-15T IC61C6416-15K 400mil TSOP-2 400mil SOJ 20 20 IC61C6416-20TI IC61C6416-20KI 400mil TSOP-2 400mil SOJ 20 20 IC61C6416-20T IC61C6416-20K 400mil TSOP-2 400mil SOJ Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw 10 Integrated Circuit Solution Inc. AHSR011-0A 05/23/2001