ICX077AK
Diagonal 3.6mm (Type 1/5) CCD Image Sensor for PAL Color Video Cameras
Description
The ICX077AK is an interline CCD solid-state
image sensor suitable for PAL color video cameras.
This device possesses a number of pixels that is
compatible with both SIF and CIF, and offers
excellent cost performance due to the adoption of an
ultra-small image size and a 10 mm-square 14-pin
plastic package. High sensitivity and low dark current
are achieved through the use of Ye, Cy, Mg, and G
complementary color mosaic filters and through the
adoption of HAD (Hole-Accumulation Diode) sensors.
This chip features a field period readout system
and an electronic shutter with variable chargestorage time.
14 pin DIP (Plastic)
Features
• High sensitivity and low dark current
• Low smear
• Excellent antiblooming characteristics
• Ye, Cy, Mg, and G complementary color mosaic filters on chip
• Horizontal register:
5V drive (drive frequency: 6.75MHz)
• Reset gate:
5V drive (no adjustment of bias)
Device Structure
• Image size:
• Number of effective pixels:
• Total number of pixels:
• Interline CCD image sensor
• Chip size:
• Unit cell size:
• Optical black:
• Number of dummy bits:
• Substrate material:
Diagonal 3.6mm (Type 1/5)
358 (H) × 583 (V) approx. 210K pixels
379 (H) × 597 (V) approx. 230K pixels
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
Pin 1
2
V
2
Pin 8
H
12
19
Optical black position
(Top View)
3.75mm (H) × 3.30mm (V)
8.20µm (H) × 3.75µm (V)
Horizontal (H) direction: Front 2 pixels, rear 19 pixels
Vertical (V)
direction: Front 12 pixels, rear 2 pixels
Horizontal 14
Vertical
1 (even fields only)
Silicon
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95507D99
ICX077AK
GND
CGG
Vφ1
Vφ2
Vφ3
Vφ4
7
6
5
4
3
2
1
Vertical register
VOUT
Block Diagram and Pin Configuration
(Top View)
G
Mg
G
Mg
Cy
Ye
Cy
Ye
Cy
Ye
Cy
Ye
G
Mg
G
Mg
Cy
Ye
Cy
Ye
Mg
G
Mg
G
Note)
11
GND
SUB
VL
Pin Description
Pin No.
Symbol
Description
12
13
Pin No.
: Photo sensor
14
Hφ2
10
Hφ1
9
Note)
RG
8
VDD
Horizontal register
Symbol
Description
1
Vφ4
Vertical register transfer clock
8
VDD
Supply voltage
2
Vφ3
Vertical register transfer clock
9
GND
GND
3
Vφ2
Vertical register transfer clock
10
SUB
Substrate (overflow drain)
4
Vφ1
11
VL
Protective transistor bias
5
CGG
Vertical register transfer clock
Output amplifier gate∗1
12
RG
Reset gate clock
6
GND
GND
13
Hφ1
Horizontal register transfer clock
7
VOUT
Signal output
14
Hφ2
Horizontal register transfer clock
∗1 DC bias is applied within the CCD, so that this pin should be grounded externally through a capacitance of
1µF or more.
Absolute Maximum Ratings
Item
Ratings
Unit
–0.3 to +55
V
VDD, VOUT, CGG – GND
–0.3 to +18
V
VDD, VOUT, CGG – SUB
–55 to +12
V
Vφ1, Vφ2, Vφ3, Vφ4 – GND
–15 to +20
V
Vφ1, Vφ2, Vφ3, Vφ4 – SUB
to +12
V
Voltage difference between vertical clock input pins
to +15
V
Voltage difference between horizontal clock input pins
to +17
V
Hφ1, Hφ2 – Vφ4
–17 to +17
V
Hφ1, Hφ2 – GND
–10 to +15
V
Hφ1, Hφ2 – SUB
–55 to +10
V
VL – SUB
–65 to +0.3
V
Vφ1, Vφ3, VDD, VOUT – VL
–0.3 to +27.5
V
RG – GND
–0.3 to +22.5
V
Vφ2, Vφ4, CGG, Hφ1, Hφ2, GND – VL
–0.3 to +17.5
V
Storage temperature
–30 to +80
°C
Operating temperature
–10 to +60
°C
Substrate voltage SUB – GND
Supply voltage
Clock input
voltage
∗2 +27V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
∗3 When CGG or GND (Pin 6) are grounded.
–0.3 to + 17.5V when CGG and GND (Pin 6) are to be disconnected.
–2–
Remarks
∗2
∗3
ICX077AK
Bias Conditions
Item
Symbol
Min.
Typ.
Max.
Supply voltage
VDD
14.25
15.0
15.75
V
Substrate voltage adjustment range
VSUB
5.0
12.75
V
Indicated
voltage + 0.1
V
Indicated
voltage – 0.1
Substrate voltage adjustment precision
Protective transistor bias
Indicated
voltage
Unit Remarks
∗1
∗2
VL
DC Characteristics
Item
Symbol
Min.
Typ.
Max.
Unit
3
5
mA
Remarks
Supply current
IDD
Input current
IIN1
1
µA
∗3
Input current
IIN2
10
µA
∗4
∗1 Indications of substrate voltage (VSUB) setting value
The setting value of the substrate voltage is indicated on the back of image sensor by a special code.
Adjust the substrate voltage (VSUB) to the indicated voltage.
VSUB code – one character indication
↑
VSUB code
Code and optimal setting correspond to each other as follows.
VSUB code
Optimal setting
VSUB code
–
=
0
1
2
3
4
5.0
5.25
5.5
5.75
6.0
6.25
6.5
E
f
G
h
J
K
L
9.0
9.25
9.5
Y
Z
Optimal setting
8.5 8.75
VSUB code
W
Optimal setting
X
6
7
8
6.75 7.0 7.25
m
N
P
9
A
7.5
7.75
R
S
C
d
8.0 8.25
U
V
9.75 10.0 10.25 10.5 10.75 11.0 11.25 11.5 11.75
12.0 12.25 12.5 12.75
<Example> “L” → VSUB = 10.0V
∗2 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used.
∗3 1) Current to each pin when 16V is applied to VDD, VOUT, RG, CGG, GND (Pin 6), and SUB pins, while pins
that are not tested are grounded.
2) Current to each pin when 20V is applied sequentially to Vφ1, Vφ2, Vφ3, and Vφ4 pins, while pins that are
not tested are grounded. However, 20V is applied to SUB pin.
3) Current to each pin when 15V is applied sequentially to Hφ1 and Hφ2 pins, while pins that are not tested
are grounded. However, 15V is applied to SUB pin.
4) Current to VL pin when 25V is applied to Vφ1, Vφ3, VDD, and VOUT pins or when, 15V is applied to Vφ2,
Vφ4, Hφ1, and Hφ2 pins, while VL pin is grounded. However, GND and SUB pins are left open.
5) Current to GND pin when 20V is applied to the RG pin and the GND pin is grounded.
∗4 Current to SUB pin when 55V is applied to SUB pin, while all pins that are not tested are grounded.
–3–
ICX077AK
Clock Voltage Conditions
Item
Readout clock voltage
Vertical transfer clock
voltage
Horizontal transfer
clock voltage
Min.
Typ.
Max.
Unit
Waveform
diagram
VVT
14.25
15.0
15.75
V
1
VVH1, VVH2
–0.05
0
0.05
V
2
VVH3, VVH4
–0.2
0
0.05
V
2
VVL1, VVL2,
VVL3, VVL4
–8.5
–8.0
–7.5
V
2
VVL = (VVL3 + VVL4)/2
VφV
7.3
8.0
8.55
V
2
VφV = VVHn – VVLn
(n = 1 to 4)
Symbol
VVH = (VVH1 + VVH2)/2
VVH3 – VVH
–0.25
0.1
V
2
VVH4 – VVH
–0.25
0.1
V
2
VVHH
0.3
V
2
High-level coupling
VVHL
0.3
V
2
High-level coupling
VVLH
0.3
V
2
Low-level coupling
VVLL
0.3
V
2
Low-level coupling
VφH
4.75
5.0
5.25
V
3
VHL
–0.05
0
0.05
V
3
4.5
5.0
5.5
V
4
Input through 0.01µF
capacitance
0.8
V
4
Low-level coupling
V
4
V
5
VφRG
Reset gate clock
voltage
Remarks
VRGLH – VRGLL
VRGH
Substrate clock voltage VφSUB
VDD + 0.3 VDD + 0.6 VDD + 0.9
21.25
22.5
–4–
23.75
ICX077AK
Clock Equivalent Circuit Constant
Item
Min.
Symbol
Typ.
Max.
Unit
CφV1, CφV3
520
pF
CφV2, CφV4
390
pF
CφV12, CφV34
220
pF
CφV23, CφV41
150
pF
CφV13, CφV24
39
pF
Capacitance between horizontal
transfer clock and GND
CφH1, CφH2
24
pF
Capacitance between horizontal
transfer clocks
CφHH
18
pF
Capacitance between reset gate clock
and GND
CφRG
3
pF
Capacitance between substrate clock
and GND
CφSUB
170
pF
Vertical transfer clock series resistor
R1, R2, R3, R4
100
Ω
Vertical transfer clock ground resistor
RGND
15
Ω
Horizontal transfer clock series resistor
RφH
30
Ω
Reset gate clock series resistor
RφRG
39
Ω
Capacitance between vertical transfer
clock and GND
Capacitance between vertical transfer
clocks
Vφ1
Remarks
Vφ2
CφV12
R1
R2
RφH
RφH
Hφ1
CφV1
CφV41
CφV24
R4
Hφ2
CφHH
CφV2
CφV23
CφH1
CφH2
CφV13
CφV4 RGND CφV3
CφV34
Vφ4
R3
Vφ3
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
RφRG
RGφ
CφRG
Reset gate clock equivalent circuit
–5–
ICX077AK
Drive Clock Waveform Conditions
(1) Readout clock waveform
100%
90%
II
II
φM
VVT
φM
2
10%
0%
tr
twh
0V
tf
(2) Vertical transfer clock waveform
Vφ1
Vφ3
VVHH
VVH1
VVHH
VVH
VVHL
VVHL
VVH3
VVHL
VVL1
VVH
VVHH
VVHH
VVHL
VVL3
VVLH
VVLH
VVLL
VVLL
VVL
VVL
Vφ2
Vφ4
VVHH
VVHH
VVH
VVH
VVHH
VVHH
VVHL
VVH2 VVHL
VVHL
VVH4
VVL2
VVL
VVLH
VVLH
VVLL
VVLL
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)
VVHL
VVL4
–6–
VVL
ICX077AK
(3) Horizontal transfer clock waveform
tr
twh
tf
90%
twl
VφH
10%
VHL
(4) Reset gate clock waveform
tr
twh
tf
VRGH
twl
RG waveform
Point A
VφRG
VRGL + 0.5V
VRGLH
VRGL
VRGLL
Hφ1 waveform
10%
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period
from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of
VRGLH and VRGLL.
VRGL = (VRGLH + VRGLL) /2
Assuming VRGH is the minimum value during the interval twh, then:
VφRG = VRGH – VRGL
–7–
ICX077AK
(5) Substrate clock waveform
100%
90%
φM
VφSUB
VSUB
10%
0%
tr
twh
φM
2
tf
Clock Switching Characteristics
Item
Symbol
Readout clock
VT
Vertical transfer
clock
Vφ1, Vφ2,
Vφ3, Vφ4
Hφ
Horizontal
transfer clock
2.3 2.5
φSUB
tf
0.5
0.5
55
67
55
67
5.6
25
34
9
18
7
0.007
0.007
5.6
0.007
0.007
107
8
5
1.5 1.65
0.5
Unit
µs
Remarks
During
readout
250 ns ∗1
15
Hφ2
Substrate clock
tr
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Hφ1
Reset gate clock φRG
twl
twh
18
ns During imaging
µs During
parallel-serial
µs conversion
ns
During drain
0.5 µs charge
∗1 When vertical transfer clock driver CXD1267 is used. tr and tf are defined by the rise and fall times for 10%
to 90% of the interval between VVL and VVH.
–8–
ICX077AK
Image Sensor Characteristics
(Ta = 25°C)
Unit
Measurement
method
mV
1
mV
2
0.012
%
3
SHy
25
%
4
∆Sr
10
%
5
∆Sb
10
%
5
Dark signal
Ydt
2
mV
6
Ta = 60°C
Dark signal shading
∆Ydt
1
mV
7
Ta = 60°C
Flicker Y
Fy
5
%
8
Flicker R-Y
Fcr
5
%
8
Flicker B-Y
Fcb
5
%
8
Line crawl R
Lcr
3
%
9
Line crawl G
Lcg
3
%
9
Line crawl B
Lcb
5
%
9
Line crawl W
Lcw
3
%
9
Lag
Lag
0.5
%
10
Symbol
Min.
Typ.
Sensitivity
S
220
300
Saturation signal
Ysat
630
Smear
Sm
Video signal shading
Item
Uniformity between video
signal channels
0.007
Max.
Remarks
Ta = 60°C
Zone II’
Zone Definition of Video Signal Shading
358 (H)
4
4
8
583 (V)
7
Zone II'
Ignored region
Effective pixel region
Measurement System
[∗Y]
[∗A]
CCD signal output
Y signal output
LPF1
(3dB down 4MHz)
CCD
C.D.S
AMP
S
[∗C]
H
LPF2
S
H
Chroma signal output
(3dB down 1MHz)
Note) Adjust the amplifier gain so that the gain between [∗A] and [∗Y], and between [∗A] and [∗C] equals 1.
–9–
ICX077AK
Image Sensor Characteristics Measurement Method
Measurement conditions
1) In the following measurements, the substrate voltage is set to the value indicated on the device, and the
device drive conditions are at the typical values of the bias and clock voltage conditions.
2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black level (OB) is used as the reference for the signal output, which is taken as the value of Y signal
output or chroma signal output of the measurement system.
Color coding of this image sensor & Composition of luminance (Y) and chroma (color difference) signals
Cy
Ye
Cy
Ye
G
Mg
G
Mg
Cy
Ye
Cy
Ye
Mg
G
Mg
G
A1
B
A2
As shown in the left figure, fields are read out. The charge
is mixed by pairs such as A1 and A2 in the A field (pairs
such as B in the B field).
As a result, the sequence of charges output as signals from
the horizontal shift register (Hreg) is, for line A1, (G + Cy),
(Mg + Ye), (G + Cy), and (Mg + Ye).
Hreg
Color Coding Diagram
These signals are processed to form the Y signal and chroma (color difference) signal. The Y signal is formed
by adding adjacent signals, and the chroma signal is formed by subtracting adjacent signals. In other words,
the approximation:
Y = {(G + Cy) + (Mg + Ye)} × 1/2
= 1/2 {2B + 3G + 2R}
is used for the Y signal, and the approximation:
R – Y = {(Mg + Ye) – (G + Cy)}
= {2R – G}
is used for the chroma (color difference) signal. For line A2, the signals output from Hreg in sequence are
(Mg + Cy), (G + Ye), (Mg + Cy), (G + Ye).
The Y signal is formed from these signals as follows:
Y = {(G + Ye) + (Mg + Cy)} × 1/2
= 1/2 {2B + 3G + 2R}
This is balanced since it is formed in the same way as for line A1. In a like manner, the chroma (color
difference) signal is approximated as follows:
– (B – Y) = {(G + Ye) – (Mg + Cy)}
= – {2B – G}
In other words, the chroma signal can be retrieved according to the sequence of lines from R – Y and – (B – Y)
in alternation. This is also true for the B field.
– 10 –
ICX077AK
Definition of standard imaging conditions
1) Standard imaging condition I:
Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject.
(Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR
cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined
as the standard sensitivity testing luminous intensity.
2) Standard imaging condition II:
Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted
to the value indicated in each testing item by the lens diaphragm.
1. Sensitivity
Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of
1/250s, measure the Y signal (Ys) at the center of the screen and substitute the value into the following
formula.
S = Ys ×
250
[mV]
50
2. Saturation signal
Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with
average value of the Y signal output, 200mV, measure the minimum value of the Y signal.
3. Smear
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to
500 times the intensity with the average value of the Y signal output, 200mV. When the readout clock is
stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure
the maximum value (YSm [mV]) of the Y signal output and substitute the value into the following formula.
Sm =
1
YSm
1
×
×
× 100 [%] (1/10V method conversion value)
10
200
500
4. Video signal shading
Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity
so that the average value of the Y signal output is 200mV. Then measure the maximum (Ymax [mV]) and
minimum (Ymin [mV]) values of the Y signal and substitute the values into the following formula.
SHy = (Ymax – Ymin)/200 × 100 [%]
5. Uniformity between video signal channels
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, and then measure the maximum (Crmax, Cbmax [mV]) and minimum (Crmin, Cbmin
[mV]) values of the R – Y and B – Y channels of the chroma signal and substitute the values into the
following formula.
∆Sr = I (Crmax – Crmin)/200 I × 100 [%]
∆Sb = I (Cbmax – Cbmin)/200 I × 100 [%]
6. Dark signal
Measure the average value of the Y signal output (Ydt [mV]) with the device ambient temperature 60°C
and the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
– 11 –
ICX077AK
7. Dark signal shading
After measuring 6, measure the maximum (Ydmax [mV]) and minimum (Ydmin [mV]) values of the Y signal
output and substitute the values into the following formula.
∆Ydt = Ydmax – Ydmin [mV]
8. Flicker
1) Fy
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, and then measure the difference in the signal level between fields (∆Yf [mV]). Then
substitute the value into the following formula.
Fy = (∆Yf/200) × 100 [%]
2) Fcr, Fcb
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, insert an R or B filter, and then measure both the difference in the signal level between
fields of the chroma signal (∆Cr, ∆Cb) as well as the average value of the chroma signal output (CAr,
CAb). Substitute the values into the following formula.
Fci = (∆Ci/CAi) × 100 [%] (i = r, b)
9. Line crawls
Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal
output is 200mV, and then insert a white subject and R, G, and B filters and measure the difference
between Y signal lines for the same field (∆Ylw, ∆Ylr, ∆Ylg, ∆Ylb [mV]). Substitute the values into the
following formula.
Lci = (∆Yli/200) × 100 [%] (i = w, r, g, b)
10. Lag
Adjust the Y signal output value generated by strobe light to 200mV. After setting the strobe light so that it
strobes with the following timing, measure the residual signal (Ylag). Substitute the value into the following
formula.
Lag = (Ylag/200) × 100 [%]
FLD
SG1
Light
Strobe light
timing
Y signal output 200mV
Output
– 12 –
Ylag (lag)
5
XV2
CXD1267
17
4
XSUB
9
10
XSG2
XV4
RG
Hφ1
Hφ2
8
XV3
22/20V
14
13
7
XV1
XSG1
11
12
15
6
16
18
3
VSUB
22/16V
1/35V
0.1
1/20V
0.1
0.01
9
14 13 12 11 10
ICX077
( BOTTOM VIEW )
7
6
5
4
3
2
1/10V
1
100k
Hφ2
19
Vφ4
RG
2
Vφ3
Hφ1
100k
Vφ1
Vφ2
VL
20
CGG
SUB
1
GND
15V
VOUT
GND
– 13 –
8
3.3/20V
VDD
Drive Circuit
0.01
2SK523
1500p
3.9k
100
3.3/16V
1M
CCD OUT
[∗A]
–8V
ICX077AK
ICX077AK
Spectral Sensitivity Characteristics
(excludes lens characteristics and light source characteristics)
1.0
Ye
0.8
Cy
Relative Response
G
0.6
0.4
Mg
0.2
0.0
400
450
500
550
600
650
700
Wave Length [nm]
Sensor Readout Clock Timing Chart
HD
V1
2.5
V2
Odd Field
V3
V4
1.3
38.4
1.6
2.5 2.1
0.3
V1
V2
Even Field
V3
V4
Unit: µs
– 14 –
– 15 –
CLP1
CCD
OUT
V4
V3
V2
V1
SG2
SG1
HD
VD
FLD
581 583
582
Drive Timing Chart (Vertical Sync)
582
581 583
4 6
2
1 3 5 7
1 3 5 7 9
2 4 6 8 10
ICX077AK
– 16 –
SUB
CLP1
V4
V3
V2
V1
SHD
SHP
RG
H2
H1
HD
10
358
1
Drive Timing Chart (Horizontal Sync)
ICX077AK
10
1
10
1
20
ICX077AK
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an earth band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensor.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W
soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, use a thermal controller of the zero cross On/Off type and connect it to ground.
3) Dust and dirt protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dirt. Clean glass plates with the following operation as required, and use them.
a) Perform all assembly operations in a clean room (class 1000 or less).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Installing (attaching)
a) Remain within the following limits when applying a static load to the package. Do not apply any load more
than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited
portions. (This may cause cracks in the package.)
AAAA AAAA AAAA
AAAA AAAA AAAA
Cover glass
50N
50N
1.2Nm
Plastic package
Compressive strength
Torsional strength
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the
package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for
installation, use either an elastic load, such as a spring plate, or an adhesive.
– 17 –
ICX077AK
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated
voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area,
and indicated values should be transferred to the other locations as a precaution.
d) The notch of the package is used for directional index, and that can not be used for reference of fixing.
In addition, the cover glass and seal resin may overlap with the notch of the package.
e) If the lead bend repeatedly and the metal, etc., clash or rub against the package, the dust may be
generated by the fragments of resin.
f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference)
5) Others
a) Do not expose to strong light (sun rays) for long periods, color filters will be discolored. When high
luminance objects are imaged with the exposure level control by electronic-iris, the luminance of the
image-plane may become excessive and discolor of the color filter will possibly be accelerated. In such a
case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off
mode should be properly arranged. For continuous using under cruel condition exceeding the normal
using condition, consult our company.
b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
c) The brown stain may be seen on the bottom or side of the package. But this does not affect the CCD
characteristics.
d) This package has 2 kinds of internal structure. However, their package outline, optical size, and strength
are the same.
Structure A
Structure B
AAA
Package
Chip
Metal plate
(lead frame)
Cross section of
lead frame
The cross section of lead frame can be seen on the side of the package for structure A.
– 18 –
1.0
2.5
0.5
– 19 –
1.7
7
1
14
8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5.
9. The notch of the package is used only for directional index, that must not be used for reference
of fixing.
42 ALLOY
0.6g
LEAD MATERIAL
PACKAGE WEIGHT
7. The tilt of the effective image area relative to the bottom “C” is less than 40µm.
The tilt of the effective image area relative to the top “D” of the cover glass is less than 40µm.
6. The height from the bottom “C” to the effective image area is 1.41 ± 0.10mm.
The height from the top of the cover glass “D” to the effective image area is 1.94 ± 0.15mm.
5. The rotation angle of the effective image area relative to H and V is ± 1°.
4. The center of the effective image area relative to “B” and “B'” is (H, V) = (5.0, 5.0) ± 0.15mm.
3. The bottom “C” of the package, and the top of the cover glass “D” are the height reference.
2. The two points “B” of the package are the horizontal reference.
The point “B'” of the package is the vertical reference.
1. “A” is the center of the effective image area.
C
8
GOLD PLATING
0.46
0.3
B'
3.35 ± 0.15
LEAD TREATMENT
M
2.5
7
D
10.16
Plastic
0.3
7.0
8.9
10.0 ± 0.1
H
8
0° to 9°
0.25
14 pin DIP (400mil)
1.7
PACKAGE MATERIAL
1.27
1
V
14
5.0
1.0
2.5
7.0
A
8.9
10.0 ± 0.1
2.6
Unit: mm
5.0
PACKAGE STRUCTURE
B
~
1.27
3.5 ± 0.3
~
~
Package Outline
ICX077AK