LC87FBH08A 8-bit Microcontroller with 8K-byte Flash ROM and 256-byte RAM www.onsemi.com Overview The LC87FBH08A is an 8-bit microcontroller that, centered around a CPU running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 8K-byte flash ROM (On-boardprogrammable), 256-byte RAM, an On-chip-debugger (flash versions only), sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), two 8-bit timers with a prescaler, a base timer serving as a timeof-day clock, a high-speed clock counter, a synchronous SIO interface, an asynchronous/synchronous SIO interface, a UART interface (full duplex), two 12-bit PWM channels, a 12-bit/8-bit 11-channel AD converter, a highspeed clock counter, a system clock frequency divider, an internal highaccuracy oscillator, a reference voltage generator circuit, an internal reset and a 20-source 10-vector interrupt feature. LQFP36 7x7 / QFP36 VQLP32 4x4 [Build to order] Features Flash ROM 8192 8 bits Capable of On-board programming with wide range (2.2 to 5.5V) of voltage source. Block-erasable in 128 byte units Writable in 2-byte units RAM 256 9 bits Minimum Bus Cycle 83.3ns (12MHz at VDD=2.7V to 5.5V, Ta=40C to +85C) 100ns (10MHz at VDD=2.2V to 5.5V, Ta=40C to +85C) 250ns ( 4MHz at VDD=1.8V to 5.5V, Ta=40C to +85C) Note: The bus cycle time here refers to the ROM read speed. * This product is licensed from Silicon Storage Technology, Inc. (USA). ORDERING INFORMATION See detailed ordering and shipping information on page 32 of this data sheet. © Semiconductor Components Industries, LLC, 2016 June 2016 - Rev. 1 1 Publication Order Number : LC87FBH08A/D LC87FBH08A Minimum Instruction Cycle Time 250ns (12MHz at VDD=2.7V to 5.5V, Ta=40C to +85C) 300ns (10MHz at VDD=2.2V to 5.5V, Ta=40C to +85C) 750ns ( 4MHz at VDD=1.8V to 5.5V, Ta=40C to +85C) Ports Normal withstand voltage I/O ports Ports I/O direction can be designated in 1-bit units Ports I/O direction can be designated in 4-bit units Dedicated oscillator ports/input ports Reset pin Power pins 17 (P1n, P20, P21, P30, P31, P70 to P73 CF2/XT2) 8 (P0n) 1 (CF1/XT1) 1 (RES) 3 (VSS1, VSS2, VDD1) Timers Timer 0: 16-bit timer/counter with a capture register. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register) Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/ counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM) Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts are programmable in 5 different time schemes High-speed Clock Counter Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz). Can generate output real time. SIO SIO0: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle =4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of data transmission possible in 1 byte units) SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) ■UART1 Full duplex 7/8/9 bit data bits selectable 1 stop bit (2-bit in continuous data transmission) Built-in baudrate generator www.onsemi.com 2 LC87FBH08A AD converter: 12 bits/8 bits 11 channels Successive approximation 12 bits/8 bits AD converter resolution selectable Port input: 10 channels, Reference voltage input: 1 channel PWM: Multifrequency 12-bit PWM 2 channels Reference voltage generator circuit (VREF17) Capable of monitoring the power supply voltage by AD conversion of frequency variable RC oscillator circuit’s reference voltage. Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN) Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC) Clock Output Function Capable generating clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected as the system clock. Capable of generating the source clock for the subclock. Watchdog Timer Capable of generating an internal reset on an overflow of a timer running on the low-speed RC oscillator clock or subclock. Operating mode at standby is selectable from 3 modes (continue counting/stop operation/stop counting with a count value held). Interrupts 20 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level 1 00003H X or L Interrupt Source 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4 4 0001BH H or L INT3/INT5/base timer 5 00023H H or L T0H 6 0002BH H or L T1L/T1H 7 00033H H or L SIO0/UART1 receive 8 0003BH H or L SIO1/UART1 transmit 9 00043H H or L ADC/T6/T7/ PWM4, PWM5 10 0004BH H or L Port 0 INT0 Priority levels X > H > L Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 128levels (The stack is allocated in RAM.) High-speed Multiplication/Division Instructions 16 bits 8 bits (5 tCYC execution time) 24 bits 16 bits (12 tCYC execution time) 16 bits 8 bits (8 tCYC execution time) 24 bits 16 bits (12 tCYC execution time) www.onsemi.com 3 LC87FBH08A Oscillation Circuits Internal oscillation circuits Low-speed RC oscillation circuit (SRC): For system clock / For Watchdog timer (100kHz) Medium-speed RC oscillation circuit (RC): For system clock (1MHz) Frequency variable RC oscillation circuit (MRC): For system clock (8MHz 1.5%, Ta=10C to +85C) External oscillation circuits Hi-speed CF oscillation circuit (CF): For system clock, with internal Rf Low speed crystal oscillation circuit (X’tal): For low-speed system clock / For Watchdog timer, with internal Rf 1) The CF and crystal oscillation circuits share the same pins. The active circuit is selected under program control. 2) Both the CF and crystal oscillator circuits stop operation on a system reset. After reset is released, oscillation is stopped so start the oscillation operation by program. System Clock Divider Function Can run on low current. The minimum instruction cycle selectable from 300ns, 600ns, 1.2s, 2.4s, 4.8s, 9.6s, 19.2s, 38.4s, and 76.8s (at a main clock rate of 10MHz). Internal Reset Function Power-on reset (POR) function 1) POR reset is generated only at power-on time. 2) The POR release level can be selected from 8 levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V, and 4.35V) through option configuration. Low-voltage detection reset (LVD) function 1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) The use or disuse of the LVD function and the low voltage threshold level (7 levels: 1.91V, 2.01V, 2.31V, 2.51V, 2.81V, 3.79V, 4.28V) can be selected by optional configuration. Standby Function HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) There are four ways of resetting the HALT mode. (1) Setting the reset pin to the low level (2) System resetting by low-voltage detection (3) System resetting by watchdog timer (4) Occurrence of an interrupt HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, low-/medium-/ Frequency variable RC, and crystal oscillators automatically stop operation. Note: The oscillation of the low-speed RC oscillator is also controlled directly by the watchdog timer and its standby-mode-time oscillation is also controlled. 2) There are five ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) System resetting by low-voltage detection (3) System resetting by watchdog timer (4) Having an interrupt source established at either INT0, INT1, INT2, INT4, INT5 * INT0 and INT1 HOLD mode reset is available only when level detection is set. (5) Having an interrupt source established at port 0. Continued on next page. www.onsemi.com 4 LC87FBH08A Continued from preceding page. X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The CF, low-/medium-/ Frequency variable RC oscillators automatically stop operation. Note: The oscillation of the low-speed RC oscillator is also controlled directly by the watchdog timer and its standby-mode-time oscillation is also controlled. 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are six ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level. (2) System resetting by watchdog timer or low-voltage detection. (3) System resetting by watchdog timer or low-voltage detection. (4) Having an interrupt source established at either INT0, INT1, INT2, INT4, INT5 * INT0 and INT1 HOLD mode reset is available only when level detection is set. (5) Having an interrupt source established at port 0. (6) Having an interrupt source established in the base timer circuit. Note: Available only when X’tal oscillation is selected. Onchip Debugger (flash versions only) Supports software debugging with the microcontroller mounted on the target board. Software break setting Stepwise execution of instructions Real time RAM data monitoring function All the RAM data map contents can be monitored and rewritten on the screen when the program is running. (Part of the SFR data cannot be rewritten.) Two channels of on-chip debugger pins are available to be compatible with small pin count devices. DBGP0 (P0), DBGP1 (P1) Data Security Function (flash versions only) Protects the program data stored in flash memory from unauthorized read or copy. Note: This data security function does not necessarily provide absolute data security. Package Form QFP36(7mm7mm) : Pb-Free and Halogen Free type VQLP32(4mm4mm) : Pb-Free and Halogen Free type (Build-to-order) Development Tools On-chip-debugger : (1) TCB87 TypeB + LC87FBH08A (2) TCB87 TypeC (3 wire version) + LC87FBH08A Flash ROM Programming Boards Package Programming boards QFP36 (7mm7mm) W87F24Q VQLP32 (4mm4mm) (build-to-order ) www.onsemi.com 5 LC87FBH08A Flash ROM Programmer Maker Model Single AF9709/AF9709B/AF9709C Programmer (Including Ando Electric Co., Ltd. models) Gang (Including Ando Electric Co., Ltd. models) AF9723/AF9723B(Main body) Flash Support Group, Inc. (FSG) Programmer AF9833(Unit) (Including Ando Electric Co., Ltd. models) Flash Support Group, Inc. (FSG) + ON Semiconductor Device Rev 03.28 or later 87F008SU - - - - (Note 2) - AF9101/AF9103(Main body) In-circuit Programmer (FSG models) SIB87(Inter Face Driver) (ON Semiconductor model) (Note 1) ON Semiconductor Supported version Single/Gang SKK / SKK Type B / SKK Type C Programmer (SanyoFWS) 1.07 or later In-circuit/Gang SKK-DBG Type B / SKK-DBG Type C Chip Data Version Programmer (SanyoFWS) 2.38 or later Application Version LC87FBH08 For information about AF-Series: Flash Support Group, Inc. TEL: +81-53-459-1050 E-mail: [email protected] Note1: On-board-programmer from FSG (AF9101/AF9103) and serial interface driver from our company (SIB87) together can give a PC-less, standalone on-board-programming capabilities. Note2: It needs a special programming devices and applications depending on the use of programming environment. Please ask FSG or our company for the information. www.onsemi.com 6 LC87FBH08A Package Dimensions unit : mm LQFP36 7x7 / QFP36 CASE 561AV ISSUE A 0.50.2 9.00.2 36 7.00.1 9.00.2 7.00.1 1 2 0.65 0.30.1 (1.5) 0 to 10 0.10.1 1.7 MAX (0.9) 0.150.05 0.13 0.10 SOLDERING FOOTPRINT* GENERIC MARKING DIAGRAM* 8.40 XXXXXXXX YDD 8.40 (Unit: mm) XXXXX = Specific Device Code Y = Year DD = Additional Traceability Data XXXXXXXX YMDDD XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data 0.65 0.43 1.00 *This information is generic. Please refer to device data sheet for actual part marking. NOTE: The measurements are not to guarantee but for reference only. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 7 LC87FBH08A Package Dimensions unit : mm [Build to order] VQLP32 4x4 CASE 602AE ISSUE A GENERIC MARKING DIAGRAM* XXXXXX YMDDD XXXXX = Specific Device Code Y = Year M = Month DDD = Additional Traceability Data XXXXXX YDD XXXXX = Specific Device Code Y = Year DD = Additional Traceability Data www.onsemi.com 8 *This information is generic. Please refer to device data sheet for actual part marking. LC87FBH08A Pin Assignment 27 26 25 24 23 22 21 20 19 P03/AN3 P02/AN2 P01/AN1 P00/AN0 VSS2 N.C. P31/PWM5/INT5/T1IN P30/PWM4/INT5/T1IN P21/URX/INT4/T1IN/PWM5 LQFP36 7x7 / QFP36 28 29 30 31 32 33 34 35 36 LC87FBH08A 18 17 16 15 14 13 12 11 10 P20/UTX/INT4/T1IN/PWM4 P17/T1PWMH/BUZ P16/T1PWML N.C. N.C. P15/SCK1/DGBP10 P14/SI1/SB1/DBGP11 P13/SO1/DBGP12 P12/SCK0 P73/INT3/T0IN RES N.C. VSS1 CF1/XT1 CF2/XT2 VDD1 P10/SO0 P11/SI0/SB0 1 2 3 4 5 6 7 8 9 P04/AN4 P05/AN5/CKO/DBGP00 P06/AN6/T6O/DBGP01 P07/T7O/DBGP02 N.C. N.C. P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN/AN10 Top view QFP36 NAME QFP36 NAME 1 P73/INT3/T0IN 19 P21/URX/INT4/T1IN/PWM5 2 RES 20 P30/PWM4/INT5/T1IN 3 N.C. 21 P31/PWM5/INT5/T1IN 4 VSS1 22 N.C. 5 CF1/XT1 23 VSS2 6 CF2/XT2 24 P00/AN0 7 VDD1 25 P01/AN1 8 P10/SO0 26 P02/AN2 9 P11/SI0/SB0 27 P03/AN3 10 P12/SCK0 28 P04/AN4 11 P13/SO1/DBGP12 29 P05/AN5/CKO/DBGP00 12 P14/SI1/SB1/DBGP11 30 P06/AN6/T6O/DBGP01 13 P15/SCK1/DBGP10 31 P07/T7O/DBGP02 14 N.C. 32 N.C. 15 N.C. 33 N.C. 16 P16/T1PWML 34 P70/INT0/T0LCP/AN8 17 P17/T1PWMH/BUZ 35 P71/INT1/T0HCP/AN9 18 P20/UTX/INT4/T1IN/PWM4 36 P72/INT2/T0IN/AN10 Note: N.C. pins must be held open (disconnected). www.onsemi.com 9 LC87FBH08A Pin Assignment 19 P31/PWM5/INT5/T1IN 18 P30/PWM4/INT5/T1IN 17 P21/URX/INT4/T1IN/PWM5 22 P01/AN1 21 P00/AN0 20 VSS2 24 P03/AN3 23 P02/AN2 VQLP32 4x4 [Buitd to order] 16 P20/UTX/INT4/T1IN/PWM4 P04/AN4 25 P05/AN5/CKO/DBGP00 26 P06/AN6/T6O/DBGP01 27 15 N.C. 14 P17/T1PWMH/BUZ P07/T7O/DBGP02 28 P70/INT0/T0LCP/AN8 29 P71/INT1/T0HCP/AN9 30 LC87FBH08A 13 P16/T1PWML 12 P15/SCK1/DBGP10 11 P14/SI1/SB1/DBGP11 10 P13/SO1/DBGP12 P72/INT2/T0IN/AN10 31 P73/INT3/T0IN 32 P10/SO0 7 P11/SI0/SB0 8 CF1/XT1 4 CF2/XT2 5 VDD1 6 N.C. 2 VSS1 3 RES 1 9 P12/SCK0 Top view VQLP32 NAME VQLP32 NAME 1 RES 17 P21/URX/INT4/T1IN/PWM5 2 N.C. 18 P30/PWM4/INT5/T1IN 3 VSS1 19 P31/PWM5/INT5/T1IN 4 CF1/XT1 20 VSS2 5 CF2/XT2 21 P00/AN0 6 VDD1 22 P01/AN1 7 P10/SO0 23 P02/AN2 8 P11/SI0/SB0 24 P03/AN3 9 P12/SCK0 25 P04/AN4 10 P13/SO1/DBGP12 26 P05/AN5/CKO/DBGP00 11 P14/SI1/SB1/DBGP11 27 P06/AN6/T6O/DBGP01 12 P15/SCK1/DBGP10 28 P07/T7O/DBGP02 13 P16/T1PWML 29 P70/INT0/T0LCP/AN8 14 P17/T1PWMH/BUZ 30 P71/INT1/T0HCP/AN9 15 N.C. 31 P72/INT2/T0IN/AN10 16 P20/UTX/INT4/T1IN/PWM4 32 P73/INT3/T0IN Note: N.C. pins must be held open (disconnected). www.onsemi.com 10 LC87FBH08A System Block Diagram Interrupt control IR Flash ROM SRC Clock generator Standby control CF/ X’tal PLA PC RC MRC Reference voltage generator circuit ACC WDT Reset circuit (LVD/POR) Reset control RES B register C register SIO0 Bus interface SIO1 Port 0 Timer 0 Port 1 Timer 1 Port 2 Timer 6 Port 3 Timer 7 Port 7 Base timer ADC UART1 INT0 to 2 INT3 (Noise filter) PWM4 Port 2 INT4 PWM5 Port 3 INT5 ALU PSW RAR RAM Stack pointer On-chip debugger www.onsemi.com 11 LC87FBH08A Pin Function Chart Pin Name I/O Description Option VSS1, VSS2 - - Power supply pin No VDD1 - + Power supply pin No Port 0 I/O 8-bit I/O port I/O specifiable in 4-bit units P00 to P07 Pull-up resistors can be turned on and off in 4-bit units. HOLD reset input Port 0 interrupt input Pin functions Yes P05: System clock output P06: Timer 6 toggle output P07: Timer 7 toggle output P00(AN0) to P06(AN6): AD converter input P05(DBGP00) to P07(DBGP02): On-chip debugger 0 port Port 1 I/O 8-bit I/O port I/O specifiable in 1-bit units P10 to P17 Pull-up resistors can be turned on and off in 1-bit units. Pin functions P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O Yes P13: SIO1 data output P14: SIO1 data input / bus I/O P15: SIO1 clock I/O P16: Timer 1PWML output P17: Timer 1PWMH output / beeper output P15(DBGP10) to P13(DBGP12): On-chip-debugger 1 port Port 2 I/O 2-bit I/O port I/O specifiable in 1-bit units P20 to P21 Pull-up resistors can be turned on and off in 1-bit units. Pin functions P20: UART transmit / PWM4 output P21: UART receive / PWM5 output P20 to P21: INT4 input / HOLD reset input / timer 1 event input / timer 0L capture input / Yes timer 0H capture input Interrupt acknowledge types INT4 Port 3 P30 to P31 I/O Rising Falling enable enable Rising & Falling enable H level L level disable disable 2-bit I/O port I/O specifiable in 1 bit units Pull-up resistors can be turned on and off in 1 bit units. Pin functions P30: PWM4 output P31: PWM5 output P30 to P31: INT5 input/HOLD reset input / timer 1 event input / timer 0L capture input / Yes timer 0H capture input Interrupt acknowledge types INT5 Rising Falling enable enable Rising & Falling enable H level L level disable disable Continued on next page. www.onsemi.com 12 LC87FBH08A Continued from preceding page. Pin Name Port 7 I/O Description Option 4-bit I/O port I/O I/O specifiable in 1 bit units P70 to P73 Pull-up resistors can be turned on and off in 1 bit units. Pin functions P70: INT0 input / HOLD reset input / timer 0L capture input P71: INT1 input / HOLD reset input / timer 0H capture input P72: INT2 input / HOLD reset input / timer 0 event input / timer 0L capture input P73: INT3 input (with noise filter) / timer 0 event input / timer 0H capture input P70(AN8) to P72(AN10): AD converter input No Interrupt acknowledge types RES CF1/XT1 I/O Rising Falling Rising & Falling H level L level enable INT0 enable enable disable enable INT1 enable enable disable enable enable INT2 enable enable enable disable disable INT3 enable enable enable disable disable External reset input / internal reset output No Ceramic resonator or 32.768kHz crystal oscillator input pin I Pin function No General-purpose input port CF2/XT2 Ceramic resonator or 32.768kHz crystal oscillator output pin I/O Pin function No General-purpose I/O port Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name Option selected in units of Option type P00 to P07 1 bit 1 P10 to P17 1 bit Output type Pull-up resistor CMOS Programmable (Note 1) 2 Nch-open drain No 1 CMOS Programmable 2 Nch-open drain Programmable CMOS Programmable Programmable P20 to P21 1 bit 1 2 Nch-open drain P30 to P31 1 bit 1 CMOS Programmable 2 Nch-open drain Programmable Programmable P70 - No Nch-open drain P71 to P73 - No CMOS Programmable CF2/XT2 - No Ceramic resonator/32.768kHz crystal resonator No output Nch-open drain (N-channel open drain when set to general-purpose output port) Note 1: The control of the presence or absence of the programmable pull-up resistors for port 0 and the switching between low-and high-impedance pull-up connection is exercised in nibble (4-bit) units (P00 to 03 or P04 to 07). www.onsemi.com 13 LC87FBH08A User Option Table Option Name Port output type Mask version Flash-ROM Option Selected in *1 Version Units of P00 to P07 1 bit CMOS P10 to P17 1 bit CMOS P20 to P21 1 bit CMOS Option to be Applied on Option Selection Nch-open drain Nch-open drain Nch-open drain P30 to P31 1 bit CMOS - - 00000h - Nch-open drain Program start address *2 Low-voltage 01E00h Detect function Enable:Use detection reset function Power-on reset Disable:Not Used Detect level - 7-level Power-On reset level - 8-level function *1: Mask option selection - No change possible after mask is completed. *2: Program start address of the mask version is 00000h. Recommended Unused Pin Connections Recommended Unused Pin Connections Port Name Board Software P00 to P07 Open Output low P10 to P17 Open Output low P20 to P21 Open Output low P30 to P31 Open Output low P70 to P73 Open Output low CF1/XT1 Pulled low with a 100k resistor or less General-purpose input port CF2/XT2 Pulled low with a 100k resistor or less General-purpose input port On-chip Debugger Pin Connection Requirements For the treatment of the on-chip debugger pins, refer to the separately available documents entitled "RD87 on-chip debugger installation manual". Power Pin Treatment Recommendations (VDD1, VSS1) Connect bypass capacitors that meet the following conditions between the VDD1 and VSS1 pins: Connect among the VDD1 and VSS1 pins and bypass capacitors C1 and C2 with the shortest possible heavy lead wires, making sure that the impedances between the both pins and the bypass capacitors are as possible (L1=L1’ , L2=L2’). Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel. The capacitance of C2 should approximately 0.1F. L2 L1 VSS1 C1 C2 VDD1 L1’ L2’ Note: Be sure to electrically short-circuit between the VSS1 and VSS2 pins. www.onsemi.com 14 LC87FBH08A Absolute Maximum Ratings at Ta = 25C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Maximum supply min typ max VDD max VDD1 0.3 +6.5 Input voltage VI CF1 0.3 VDD+0.3 Input/output VIO Ports 0, 1, 2, 3, 0.3 VDD+0.3 voltage voltage High level output current Peak output Port 7, CF2, RES IOPH(1) Mean output CMOS output select Per 1 applicable pin P71 to P73 Per 1 applicable pin -5 IOMH(1) Ports 0, 1, 2, 3 CMOS output select 7.5 Per 1 applicable pin (Note 1-1) IOMH(2) P71 to P73 Per 1 applicable pin Total output IOAH(1) Ports 0, 1, 2, 3, Total of all applicable pins current IOPL(1) Mean output Total output 20 IOPL(2) P00, P01 Per 1 applicable pin 30 IOPL(3) Port 7, CF2 Per 1 applicable pin 10 IOML(1) P02 to P07 Per 1 applicable pin IOML(2) P00, P01 Per 1 applicable pin 20 IOML(3) Port 7, CF2 Per 1 applicable pin 7.5 IOAL(1) Ports 0, 1, Total of all applicable pins 70 Ports 2, 3, CF2 IOAL(2) Port 7 Total of all applicable pins Pd max(1) QFP36(77) Ta=40 to +85C dissipation 15 120 Package only Pd max(2) mA 15 Ports 1, 2, 3 current Power Per 1 applicable pin Ports 1, 2, 3 current (Note 1-1) P02 to P07, 3 25 P71 to P73 current V 10 IOPH(2) current Peak output Low level output current Ports 0, 1, 2, 3 current unit Ta=40 to +85C mW Package with thermal 275 resistance board (Note 1-2) Operating ambient Topr 40 +85 Tstg 55 +125 temperature Storage ambient C temperature Note 1-1: The mean output current is a mean value measured over 100ms. Note 1-2: SEMI standards thermal resistance board (size: 76.1114.31.6tmm, glass epoxy) is used. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 15 LC87FBH08A Allowable Operating Conditions at Ta = 40C to +85C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] max unit 5.5 VDD(2) 0.294s tCYC 200s 2.2 5.5 VDD(3) 0.735s tCYC 200s 1.8 5.5 supply voltage Memory typ 2.7 VDD(1) (Note 2-1) min 0.245s tCYC 200s Operating VHD VDD1 VDD1 sustaining RAM and register contents sustained in HOLD mode. 1.6 supply voltage High level VIH(1) Ports 1, 2, 3, 7 1.8 to 5.5 0.3VDD+0.7 VDD input voltage VIH(2) Ports 0 1.8 to 5.5 0.3VDD+0.7 VDD VIH(3) CF1, CF2, RES 1.8 to 5.5 0.75VDD VDD Low level VIL(1) Ports 1, 2, 3, 7 4.0 to 5.5 VSS 0.1VDD+0.4 1.8 to 4.0 VSS 0.2VDD VIL(2) Ports 0 4.0 to 5.5 VSS 0.15VDD+0.4 1.8 to 4.0 VSS 0.2VDD VIL(3) CF1, CF2, RES 1.8 to 5.5 VSS 0.25VDD input voltage High level IOH(1) Ports 0, 1, 2, output current IOH(2) P71 to P73 Per 1 applicable pin IOH(3) IOH(4) Ports 3, Per 1 applicable pin 4.5 to 5.5 1.0 2.7 to 4.5 0.35 1.8 to 2.7 0.15 4.5 to 5.5 6.0 2.7 to 4.5 1.4 1.8 to 2.7 0.8 V P05 (System clock IOH(5) IOH(6) IOH(1) output function used) 4.5 to 5.5 25 IOH(2) 2.7 to 4.5 11.2 IOH(3) 1.8 to 2.7 5.4 Low level IOL(1) output current IOL(2) Ports 0, 1, 2, 3, 7 Ports 0, 1, 2, 3 Total of all applicable pins Per 1 applicable pin IOL(3) IOL(4) Port 7, CF2 Per 1 applicable pin IOL(5) IOL(6) P00, P01 Per 1 applicable pin 0.8 2.7 to 5.5 1.4 1.8 to 2.7 0.8 25 4 IOL(8) 1.8 to 2.7 2 IOL(1) Ports 0, 1, 2, 3, IOL(2) CF2 Total of all applicable pins 4.5 to 5.5 70 2.7 to 4.5 34.6 1.8 to 2.7 19.2 2.7 to 5.5 5.6 IOL(5) 1.8 to 2.7 3.2 tCYC 2.7 to 5.5 0.245 200 2.2 to 5.5 0.294 200 1.8 to 5.5 0.735 200 2.7 to 5.5 0.1 12 1.8 to 5.5 0.1 4 3.0 to 5.5 0.2 24.4 2.0 to 5.5 0.2 8 Ports 7 Total of all applicable pins (Note 2-2) frequency 1.8 to 2.7 2.7 to 4.5 cycle time system clock 1.4 4.5 to 5.5 IOL(4) External 10 2.7 to 4.5 IOL(7) IOL(3) Instruction 4.5 to 5.5 FEXCF CF1 CF2 pin open System clock frequency division ratio=1/1 External system clock duty=505% CF2 pin open System clock frequency division ratio=1/2 External system clock duty=505% mA s MHz Note 2-1: VDD must be held greater than or equal to 2.2V in the flash ROM onboard programming mode. Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Continued on next page. www.onsemi.com 16 LC87FBH08A Continued from preceding page. Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Oscillation FmCF(1) CF1, CF2 See Fig. 1. frequency range 12MHz ceramic oscillation. FmCF(2) CF1, CF2 (Note 2-3) 10MHz ceramic oscillation. See Fig. 1. FmCF(3) CF1, CF2 min typ max 2.7 to 5.5 12 2.2 to 5.5 10 1.8 to 5.5 4 2.2 to 5.5 4 unit 4MHz ceramic oscillation. CF oscillation normal amplifier size selected. (CFLAMP=0) See Fig. 1. 4MHz ceramic oscillation. CF oscillation low amplifier size selected. (CFLAMP=1) MHz See Fig. 1. FmMRC(1) Frequency variable RC oscillation. (Note 2-4) FmMRC(2) 1.8 to 5.5 7.84 8.0 8.16 1.8 to 5.5 7.88 8.0 8.12 Frequency variable RC oscillation. Ta=-10 to +85C (Note 2-4) FmRC Internal medium-speed RC oscillation 1.8 to 5.5 0.5 1.0 2.0 FmSRC Internal low-speed RC oscillation 1.8 to 5.5 50 100 200 FsX’tal XT1, XT2 32.768kHz crystal oscillation See Fig. 1. Oscillation tmsMRC kHz 1.8 to 5.5 32.768 When Frequency variable RC stabilization oscillation state is switched from time stopped to enabled. 1.8 to 5.5 100 s See Fig. 3. Note 2-3: See Tables 1 and 2 for the oscillation constants. Note 2-4: When switching the system clock, allow an oscillation stabilization time of 100s or longer after the frequency variable RC oscillator circuit transmits from the "oscillation stopped" to "oscillation enabled" state. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 17 LC87FBH08A Electrical Characteristics at Ta = 40C to +85C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] High level input IIH(1) current Ports 0, 1, 2, 3, Output disabled Ports 7, RES Pull-up resistor off VIN=VDD (Including output Tr's off leakage min typ max unit 1.8 to 5.5 1 1.8 to 5.5 1 1.8 to 5.5 15 A V current) IIH(2) CF1, CF2 Input port selected VIN=VDD IIH(3) CF1 Reset state VIN=VDD Low level input IIL(1) current Ports 0, 1, 2, 3, Output disabled Ports 7, RES Pull-up resistor off VIN=VSS (Including output Tr's off leakage 1.8 to 5.5 1 1.8 to 5.5 1 current) IIL(2) CF1, CF2 Input port selected VIN=VSS High level output VOH(1) Ports 0, 1, 2 IOH=-1mA 4.5 to 5.5 VDD1 voltage VOH(2) P71 to P73 IOH=-0.35mA 2.7 to 5.5 VDD0.4 IOH=-0.15mA 1.8 to 5.5 VDD0.4 IOH=-6mA 4.5 to 5.5 VDD1 clock output IOH=-1.4mA 2.7 to 5.5 VDD0.4 VOH(6) function used) IOH=-0.8mA 1.8 to 5.5 VDD0.4 Low level output VOL(1) Ports 0, 1, 2, 3 IOL=10mA 4.5 to 5.5 1.5 voltage VOL(2) IOL=1.4mA 2.7 to 5.5 0.4 IOL=0.8mA 1.8 to 5.5 0.4 IOL=1.4mA 2.7 to 5.5 0.4 IOL=0.8mA 1.8 to 5.5 0.4 IOL=25mA 4.5 to 5.5 1.5 VOL(7) IOL=4mA 2.7 to 5.5 0.4 VOL(8) IOL=2mA 1.8 to 5.5 0.4 VOH=0.9VDD When Port 0 selected 4.5 to 5.5 15 35 80 low-impedance pull-up. 1.8 to 4.5 18 50 230 VOH=0.9VDD When Port 0 selected 1.8 to 5.5 VOH(3) VOH(4) VOH(5) Ports 3 P05 (System VOL(3) VOL(4) Port 7, CF2 VOL(5) VOL(6) Pull-up resistance Rpu(1) Rpu(2) Rpu(3) P00, P01 Ports 0, 1, 2, 3, Ports 7 Port 0 k 100 200 400 high-impedance pull-up. Hysteresis voltage Pin capacitance VHYS(1) Ports 1, 2, 3, 2.7 to 5.5 0.1VDD VHYS(2) Ports 7, RES 1.8 to 2.7 0.07VDD CP All pins 1.8 to 5.5 10 V For pins other than that under test: VIN=VSS f=1MHz pF Ta=25C Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 18 LC87FBH08A SIO0 Serial I/O Characteristics at Ta = 40C to +85C, VSS1 = VSS2 = 0V (Note 4-1-1) Parameter Symbol Frequency tSCK(1) Low level tSCKL(1) Specification Pin/ Conditions Remarks SCK0(P12) VDD[V] See Fig. 5. Input clock tSCKH(1) 1.8 to 5.5 pulse width tCYC 4 See Fig. 5. Output clock (Note 4-1-2) Frequency tSCK(2) Low level tSCKL(2) SCK0(P12) CMOS output selected 4/3 See Fig. 5. 1/2 pulse width tSCK High level tSCKH(2) pulse width tSCKHA(2) Continuous data 1/2 1.8 to 5.5 transmission/reception mode tSCKH(2) +2tCYC See Fig. 5. Serial input unit 1 Continuous data tSCKHA(1) CMOS output selected Data setup time tsDI(1) SB0(P11), SI0(P11) Data hold time Must be specified with respect to rising edge of SIOCLK. thDI(1) Input clock tdD0(1) time SO0(P10), SB0(P11) Continuous data (1/3)tCYC transmission/reception mode +0.08 s Synchronous 8-bit mode 1tCYC 1.8 to 5.5 Output clock tCYC tCYC 0.05 (Note 4-1-3) tdD0(3) +(10/3) 0.05 (Note 4-1-3) tdD0(2) tSCKH(2) 1.8 to 5.5 See Fig. 5. Output delay Serial output max 1 transmission/reception mode Serial clock typ 2 pulse width High level min +0.08 (Note 4-1-3) (1/3)tCYC +0.08 Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 5. www.onsemi.com 19 LC87FBH08A SIO1 Serial I/O Characteristics at Ta = 40C to +85C, VSS1 = VSS2 = 0V (Note 4-2-1) Input clock Symbol Frequency tSCK(3) Low level tSCKL(3) Specification Pin/ Conditions Remarks SCK1(P15) VDD[V] tSCK(4) Low level tCYC SCK1(P15) CMOS output selected 2 See Fig. 5. tSCKL(4) 1/2 1.8 to 5.5 tSCK tSCKH(4) 1/2 Serial input pulse width Data setup time tsDI(2) SI1(P14), SB1(P14) Data hold time Must be specified with respect to rising edge of SIOCLK. thDI(2) (1/3)tCYC 1.8 to 5.5 tdD0(4) SO1(P13), Serial output SB1(P14) +0.01 0.01 See Fig. 5. Output delay time unit 1 pulse width High level max 1 1.8 to 5.5 tSCKH(3) Frequency typ 2 pulse width High level min See Fig. 5. pulse width Output clock Serial clock Parameter Must be specified with respect to s falling edge of SIOCLK. Must be specified as the time to the beginning of output state (1/2)tCYC 1.8 to 5.5 +0.05 change in open drain output mode. See Fig. 5. Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. Pulse Input Conditions at Ta = 40C to +85C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] High/low level tPIH(1) INT0(P70), Interrupt source flag can be set. pulse width tPIL(1) INT1(P71), Event inputs for timer 0 or 1 are INT2(P72), enabled. min typ 1.8 to 5.5 1 1.8 to 5.5 2 1.8 to 5.5 64 1.8 to 5.5 256 1.8 to 5.5 200 max unit INT4(P20 to P21) INT5(P30 to P31) tPIH(2) INT3(P73) when noise Interrupt source flag can be set. tPIL(2) filter time constant is Event inputs for timer 0 are 1/1 enabled. tPIH(3) INT3(P73) when noise Interrupt source flag can be set. tPIL(3) filter time constant is Event inputs for timer 0 are 1/32 nabled. tPIH(4) INT3(P73) when noise Interrupt source flag can be set. tPIL(4) filter time constant is Event inputs for timer 0 are 1/128 tPIL(5) RES tCYC enabled. Resetting is enabled. www.onsemi.com 20 s LC87FBH08A AD Converter Characteristics at VSS1 = VSS2 = 0V <12bits AD Converter Mode at Ta = 40C to +85C > Specification Parameter Symbol Pin/Remarks Resolution N AN0(P00) to Absolute ET AN6(P06), VDD[V] 1.8 to 5.5 (Note 6-1) AN8(P70) to accuracy AN10(P72) Conversion time Conditions TCAD See Conversion time calculation formulas. (Note 6-2) Analog input VAIN min typ max unit 12 bit 2.7 to 5.5 16 1.8 to 5.5 20 2.7 to 5.5 32 115 2.2 to 5.5 134 215 1.8 to 5.5 400 430 VSS VDD 1.8 to 5.5 voltage range Analog port IAINH VAIN=VDD 1.8 to 5.5 input current IAINL VAIN=VSS 1.8 to 5.5 LSB s V 1 A 1 <8bits AD Converter Mode at Ta = 40C to +85C > Specification Parameter Symbol Pin/Remarks Resolution N AN0(P00) to Absolute ET AN6(P06), VDD[V] 1.8 to 5.5 typ max TCAD AN10(P72) unit 8 bit (Note 6-1) 1.8 to 5.5 See Conversion time calculation 2.7 to 5.5 20 90 2.2 to 5.5 80 135 1.8 to 5.5 245 265 VSS VDD formulas. (Note 6-2) Analog input min 1.5 AN8(P70) to accuracy Conversion time Conditions VAIN 1.8 to 5.5 voltage range Analog port IAINH VAIN=VDD 1.8 to 5.5 input current IAINL VAIN=VSS 1.8 to 5.5 LSB 1 1 s V A Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when: The first AD conversion is performed in the 12-bit AD conversion mode after a system reset. The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode. Conversion time calculation formulas: 12bits AD Converter Mode: TCAD(Conversion time) = ((52/(AD division ratio))+2)(1/3)tCYC 8bits AD Converter Mode: TCAD(Conversion time) = ((32/(AD division ratio))+2)(1/3)tCYC External Operating supply oscillation voltage range (FmCF) (VDD) CF-12MHz CF-8MHz CF-4MHz System division ratio Cycle time (SYSDIV) (tCYC) 2.7V to 5.5V 1/1 2.7V to 5.5V AD division AD conversion time (TCAD) ratio (ADDIV) 12bit AD 250ns 1/8 34.8s 21.5s 1/1 375ns 1/8 52.25s 32.25s 2.2V to 5.5V 1/1 375ns 1/32 208.25s 128.25s 2.7V to 5.5V 1/1 750ns 1/8 104.5s 64.5s 2.2V to 5.5V 1/1 750ns 1/16 208.5s 128.5s 1.8V to 5.5V 1/1 750ns 1/32 416.5s 256.5s www.onsemi.com 21 8bit AD LC87FBH08A Reference voltage (VREF17) Characteristics at Ta = 40C to +85C, VSS1 = VSS2 = 0V Parameter Symbol Output voltage VOVREF Reference voltage operation IDDVREF Pin/Remarks Conditions min typ 1.67 2.0 to 5.5 current (Note 7-1) Operation stabilization time Specification VDD[V] 2.0 to 5.5 tVRW max 1.75 V A 110 2.0 to 5.5 (Note 7-2) unit 1.83 s 100 Note 7-1: IDDVREF denotes the currents that only flow to multivariable RC oscillator circuit’s reference voltage circuit. Note 7-2: tVRW denotes the stabilization time from starting multivariable RC oscillator. Power-on Reset (POR) Characteristics at Ta = 40C to +85C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions Option selected voltage POR release PORRL voltage Detection voltage typ max Select from option. 1.67V 1.55 1.66 1.77 (Note 8-1) 1.97V 1.85 1.96 2.07 2.07V 1.93 2.05 2.17 2.37V 2.23 2.35 2.47 2.57V 2.43 2.55 2.67 2.87V 2.71 2.85 2.99 3.86V 3.65 3.83 4.00 4.35V 4.12 4.32 4.50 0.7 0.95 See Fig. 7. POUKS unknown state Power supply rise min (Note 8-2) Power supply rise PORIS time 100 time from 0V to 1.6V. unit V ms Note8-1: The POR release level can be selected out of 8 levels only when the LVD reset function is disabled. Note8-2: POR is in an unknown state before transistors start operation. Low Voltage Detection Reset (LVD) Characteristics at Ta = 40C to +85C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions Option selected voltage LVD reset voltage LVDET (Note 9-2) LVD hysteresis width Detection voltage LVUKS minimum width max 1.91V 1.81 1.91 2.01 2.01V 1.90 2.00 2.10 (Note 9-3) 2.31V 2.20 2.30 2.40 See Fig. 8. 2.51V 2.40 2.50 2.60 2.81V 2.68 2.80 2.92 3.79V 3.62 3.78 3.94 4.28V 4.09 4.27 4.45 1.91V 50 2.01V 50 2.31V 50 2.51V 50 2.81V 50 3.79V 50 4.28V 50 See Fig. 8. 0.7 (Note 9-4) TLVDW typ (Note 9-1) LVHYS unknown state Low voltage detection Select from option. min unit V mV 0.95 V LVDET-0.5V See Fig. 9. 0.2 ms (Reply sensitivity) Note9-1: The LVD reset level can be selected out of 7 levels only when the LVD reset function is enabled. Note9-2: LVD reset voltage specification values do not include hysteresis voltage. Note9-3: LVD reset voltage may exceed its specification values when port output state changes and/or when a large current flows through port. Note9-4: LVD is in an unknown state before transistors start operation. www.onsemi.com 22 LC87FBH08A Consumption Current Characteristics at Ta = 40C to +85C, VSS1 = VSS2 = 0V Parameter Normal mode Symbol IDDOP(1) Specification Pin/ Conditions Remarks VDD1 VDD[V] min typ max unit FmCF=12MHz ceramic oscillation mode consumption System clock set to 12MHz side current Internal low speed and medium speed RC 2.7 to 5.5 5.1 9.3 2.7 to 3.6 3.1 5.6 3.0 to 5.5 5.2 10 3.0 to 3.6 3.3 6.2 2.2 to 5.5 4.4 8.4 2.2 to 3.6 2.8 5.5 1.8 to 5.5 2.3 5.3 1.8 to 3.6 1.6 3.0 2.2 to 5.5 0.97 2.4 2.2 to 3.6 0.55 1.2 1.8 to 5.5 0.44 1.5 1.8 to 3.6 0.28 0.80 1.8 to 5.5 3.4 5.5 1.8 to 3.6 2.4 4.6 1.8 to 5.5 51 163 1.8 to 3.6 38 103 5.0 51 136 3.3 38 99 2.5 36 94 oscillation stopped. (Note 10-1) Frequency variable RC oscillation stopped. (Note 10-2) 1/1 frequency division ratio IDDOP(2) CF1=24MHz external clock System clock set to CF1 side Internal low speed and medium speed RC oscillation stopped. Frequency variable RC oscillation stopped. 1/2 frequency division ratio IDDOP(3) FmCF=10MHz ceramic oscillation mode System clock set to 10MHz side Internal low speed and medium speed RC oscillation stopped. Frequency variable RC oscillation stopped. 1/1 frequency division ratio IDDOP(4) FmCF=4MHz ceramic oscillation mode System clock set to 4MHz side Internal low speed and medium speed RC oscillation stopped. Frequency variable RC oscillation stopped. mA 1/1 frequency division ratio IDDOP(5) CF oscillation low amplifier size selected. (CFLAMP=1) FmCF=4MHz ceramic oscillation mode System clock set to 4MHz side Internal low speed and medium speed RC oscillation stopped. Frequency variable RC oscillation stopped. 1/4 frequency division ratio IDDOP(6) FsX’tal=32.768kHz crystal oscillation mode Internal low speed RC oscillation stopped. System clock set to internal medium speed RC oscillation. Frequency variable RC oscillation stopped. 1/2 frequency division ratio IDDOP(7) FsX’tal=32.768kHz crystal oscillation mode Internal low speed and medium speed RC oscillation stopped. System clock set to 8MHz with frequency variable RC oscillation 1/1 frequency division ratio IDDOP(8) External FsX’tal and FmCF oscillation stopped. System clock set to internal low speed RC oscillation. Internal medium speed RC oscillation stopped. Frequency variable RC oscillation stopped. 1/1 frequency division ratio IDDOP(9) A External FsX’tal and FmCF oscillation stopped. System clock set to internal low speed RC oscillation. Internal medium speed RC oscillation stopped. Frequency variable RC oscillation stopped. 1/1 frequency division ratio Ta=-10 to +50C Note10-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. Note10-2: The consumption current values do not include operational current of LVD function if not specified. Continued on next page. www.onsemi.com 23 LC87FBH08A Continued from preceding page. Parameter Normal mode Symbol IDDOP(10) Specification Pin/ Conditions Remarks VDD1 VDD[V] min typ max unit FsX’tal=32.768kHz crystal oscillation mode consumption System clock set to 32.768kHz side current Internal low speed and medium speed RC 1.8 to 5.5 34 97 1.8 to 3.6 14 44 5.0 34 88 3.3 14 36 2.5 9.1 22 2.7 to 5.5 2.6 4.8 2.7 to 3.6 1.4 2.4 3.0 to 5.5 2.7 5.3 3.0 to 3.6 1.6 2.9 2.2 to 5.5 2.2 4.3 2.2 to 3.6 1.2 2.2 1.8 to 5.5 1.3 3.3 1.8 to 3.6 0.56 1.2 2.2 to 5.5 0.74 1.8 2.2 to 3.6 0.34 0.68 1.8 to 5.5 0.32 0.90 1.8 to 3.6 0.21 0.44 oscillation stopped. (Note 10-1) Frequency variable RC oscillation stopped. (Note 10-2) 1/2 frequency division ratio IDDOP(11) A FsX’tal=32.768kHz crystal oscillation mode System clock set to 32.768kHz side Internal low speed and medium speed RC oscillation stopped. Frequency variable RC oscillation stopped. 1/2 frequency division ratio Ta=-10 to +50C HALT mode IDDHALT(1) HALT mode consumption FmCF=12MHz ceramic oscillation mode current System clock set to 12MHz side (Note 10-1) Internal low speed and medium speed RC (Note 10-2) oscillation stopped. Frequency variable RC oscillation stopped. 1/1 frequency division ratio IDDHALT(2) HALT mode CF1=24MHz external clock System clock set to CF1 side Internal low speed and medium speed RC oscillation stopped. Frequency variable RC oscillation stopped. 1/2 frequency division ratio IDDHALT(3) HALT mode FmCF=10MHz ceramic oscillation mode System clock set to 10MHz side Internal low speed and medium speed RC oscillation stopped. Frequency variable RC oscillation stopped. 1/1 frequency division ratio IDDHALT(4) HALT mode FmCF=4MHz ceramic oscillation mode System clock set to 4MHz side mA Internal low speed and medium speed RC oscillation stopped. Frequency variable RC oscillation stopped. 1/1 frequency division ratio IDDHALT(5) HALT mode CF oscillation low amplifier size selected. (CFLAMP=1) FmCF=4MHz ceramic oscillation mode System clock set to 4MHz side Internal low speed and medium speed RC oscillation stopped. Frequency variable RC oscillation stopped. 1/4 frequency division ratio IDDHALT(6) HALT mode FsX’tal=32.768kHz crystal oscillation mode Internal low speed RC oscillation stopped. System clock set to internal medium speed RC oscillation Frequency variable RC oscillation stopped. 1/2 frequency division ratio Note10-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. Note10-2: The consumption current values do not include operational current of LVD function if not specified. Continued on next page. www.onsemi.com 24 LC87FBH08A Continued from preceding page. Parameter HALT mode Symbol IDDHALT(7) Specification Pin/ Conditions remarks VDD1 VDD[V] min typ max consumption FsX’tal=32.768kHz crystal oscillation mode current Internal low speed and medium speed RC 1.8 to 5.5 1.3 2.3 mA oscillation stopped. (Note 10-1) unit HALT mode System clock set to 8MHz with (Note 10-2) frequency variable RC oscillation 1.8 to 3.6 0.91 1.5 1.8 to 5.5 18 68 1.8 to 3.6 11 35 5.0 18 46 3.3 11 27 2.5 7.4 19 1.8 to 5.5 24 98 1.8 to 3.6 8.0 35 5.0 24 63 1/1 frequency division ratio IDDHALT(8) HALT mode External FsX’tal and FmCF oscillation stopped. System clock set to internal low speed RC oscillation. Internal medium speed RC oscillation stopped. Frequency variable RC oscillation stopped. 1/1 frequency division ratio IDDHALT(9) HALT mode External FsX’tal and FmCF oscillation stopped. System clock set to internal low speed RC oscillation. Internal medium speed RC oscillation stopped. Frequency variable RC oscillation stopped. 1/1 frequency division ratio Ta=-10 to +50C IDDHALT(10) HALT mode FsX’tal=32.768kHz crystal oscillation mode System clock set to 32.768kHz side Internal low speed and medium speed RC oscillation stopped. Frequency variable RC oscillation stopped. 1/2 frequency division ratio IDDHALT(11) HALT mode FsX’tal=32.768kHz crystal oscillation mode System clock set to 32.768kHz side A Internal low speed and medium speed RC oscillation stopped. 3.3 8.0 23 2.5 3.5 11 23 Frequency variable RC oscillation stopped. 1/2 frequency division ratio Ta=-10 to +50C HOLD mode IDDHOLD(1) consumption current (Note 10-1) IDDHOLD(2) (Note 10-2) HOLD mode 1.8 to 5.5 0.019 CF1=VDD or open (External clock mode) 1.8 to 3.6 0.011 11 HOLD mode 5.0 0.019 1.2 CF1=VDD or open (External clock mode) 3.3 0.011 0.59 2.5 0.010 0.30 1.8 to 5.5 2.6 26 1.8 to 3.6 2.0 13 5.0 2.6 3.8 Ta=-10 to +50C 3.3 2.0 2.8 LVD option selected 2.5 1.7 2.5 Ta=-10 to +50C IDDHOLD(3) HOLD mode CF1=VDD or open (External clock mode) LVD option selected IDDHOLD(4) HOLD mode CF1=VDD or open (External clock mode) Timer HOLD IDDHOLD(5) mode consumption current (Note 10-1) (Note 10-2) IDDHOLD(6) Timer HOLD mode 1.8 to 5.5 22 84 FsX’tal=32.768kHz crystal oscillation mode 1.8 to 3.6 6.5 30 5.0 22 53 3.3 6.5 16 2.5 2.7 7.2 Timer HOLD mode FsX’tal=32.768kHz crystal oscillation mode Ta=-10 to +50C Note10-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. Note10-2: The consumption current values do not include operational current of LVD function if not specified. www.onsemi.com 25 LC87FBH08A F-ROM Programming Characteristics at Ta = +10C to +55C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Onboard IDDFW(1) VDD1 min typ max unit Only current of the Flash block. programming 2.2 to 5.5 5 10 mA 20 30 ms 40 60 s current Programming tFW(1) Erasing time time tFW(2) Programming time 2.2 to 5.5 UART (Full Duplex) Operating Conditions at Ta = 40C to +85C, VSS1 = VSS2 = 0V Specification Parameter Symbol Pin/Remarks Conditions VDD[V] Transfer rate UBR P20, P21 1.8 to 5.5 min typ max 16/3 8192/3 Data length: 7/8/9 bits (LSB first) Stop bits: 1 bit (2-bit in continuous data transmission) Parity bits: None Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data=55H) Start bit Start of transmission Stop bit Transmit data (LSB first) End of transmission UBR Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data=55H) Stop bit Start bit Start of reception Receive data (LSB first) UBR www.onsemi.com 26 End of reception unit tCYC LC87FBH08A Characteristics of a Sample Main System Clock Oscillation Circuit Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator CF oscillation normal amplifier size selected (CFLAMP=0) MURATA Nominal Frequency 12MHz Circuit Constant Operating Oscillation Voltage Stabilization Time Type Oscillator Name SMD CSTCE12M0G52-R0 SMD CSTCE10M0G52-R0 (10) (10) Open 680 2.1 to 5.5 0.02 0.3 CSTLS10M0G53-B0 (15) (15) Open 680 2.4 to 5.5 0.02 0.3 CSTLS10M0G53095-B0 (15) (15) Open 680 2.0 to 5.5 0.01 0.15 10MHz C1 C2 Rf Rd Range typ max [pF] [pF] [] [] [V] [ms] [ms] (10) (10) Open 680 2.6 to 5.5 0.02 0.3 Remarks LEAD SMD CSTCE8M00G52-R0 (10) (10) Open 1k 2.1 to 5.5 0.02 0.3 CSTLS8M00G53-B0 (15) (15) Open 1k 2.2 to 5.5 0.02 0.3 CSTLS8M00G53095-B0 (15) (15) Open 1k 1.9 to 5.5 0.01 0.15 CSTCR6M00G53-R0 (15) (15) Open 1.5k 2.0 to 5.5 0.02 0.3 CSTCR6M00G53093-R0 (15) (15) Open 1.5k 1.8 to 5.5 0.01 0.15 CSTLS6M00G53-B0 (15) (15) Open 1.5k 2.0 to 5.5 0.02 0.3 CSTLS6M00G53095-B0 (15) (15) Open 1.5k 1.8 to 5.5 0.01 0.15 SMD CSTCR4M00G53-R0 (15) (15) Open 1.5k 1.8 to 5.5 0.03 0.45 LEAD CSTLS4M00G53-B0 (15) (15) Open 1.5k 1.8 to 5.5 0.02 0.3 8MHz LEAD Internal C1, C2 SMD 6MHz LEAD 4MHz CF oscillation low amplifier size selected (CFLAMP=1) MURATA Nominal Frequency 12MHz Circuit Constant Operating Oscillation Voltage Stabilization Time Type Oscillator Name [pF] [pF] [] [] [V] [ms] [ms] SMD CSTCE12M0G52-R0 (10) (10) Open 470 3.9 to 5.5 0.03 0.45 SMD CSTCE10M0G52-R0 (10) (10) Open 470 2.9 to 5.5 0.03 0.45 0.45 10MHz C1 C2 Rf Rd Range typ max CSTLS10M0G53-B0 (15) (15) Open 470 3.6 to 5.5 0.03 CSTLS10M0G53095-B0 (15) (15) Open 470 2.7 to 5.5 0.02 0.3 CSTCE8M00G52-R0 (10) (10) Open 680 2.7 to 5.5 0.03 0.45 Remarks LEAD SMD 8MHz CSTLS8M00G53-B0 (15) (15) Open 680 3.0 to 5.5 0.03 0.45 CSTLS8M00G53095-B0 (15) (15) Open 680 2.5 to 5.5 0.01 0.15 CSTCR6M00G53-R0 (15) (15) Open 1k 2.6 to 5.5 0.03 0.45 CSTCR6M00G53095-R0 (15) (15) Open 1k 2.2 to 5.5 0.02 0.3 CSTLS6M00G53-B0 (15) (15) Open 1k 2.7 to 5.5 0.03 0.45 CSTLS6M00G53095-B0 (15) (15) Open 1k 2.2 to 5.5 0.01 0.15 LEAD SMD Internal C1, C2 6MHz LEAD CSTCR4M00G53-R0 (15) (15) Open 1k 2.1 to 5.5 0.04 0.6 CSTCR4M00G53095-R0 (15) (15) Open 1k 1.8 to 5.5 0.02 0.3 CSTLS4M00G53-B0 (15) (15) Open 1k 2.1 to 5.5 0.02 0.3 CSTLS4M00G53095-B0 (15) (15) Open 1k 1.8 to 5.5 0.01 0.15 SMD 4MHz LEAD The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in follwing cases (see Figure 3). The time interval that is required for the oscillation to get stabilized after the instruction for starting the mainclock oscillation circuit is executed. The time interval that is required for the oscillation to get stabilized after the HOLD mode is reset and oscillation is started. The time interval that is required for the oscillation to get stabilized after the X’tal Hold mode, under the state which the main clock oscillation is enabled, is reset and oscillation is started. www.onsemi.com 27 LC87FBH08A Characteristics of a Sample Subsystem Clock Oscillator Circuit Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a our designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator EPSON TOYOCOM Nominal Type Frequency 32.768kHz SMD Circuit Constant Oscillator Name MC-306 Operating Oscillation Voltage Stabilization Time C1 C2 Rf Rd Range typ max [pF] [pF] [] [] [V] [s] [s] 9 9 Open 330k 1.8 to 5.5 1.4 4.0 Remarks Applicable CL value = 7.0pF SEIKO INSTRUMENTS Nominal Type Frequency 32.768kHz SMD Circuit Constant Oscillator Name SSP-T7-F Operating Oscillation Voltage Stabilization Time C1 C2 Rf Rd Range typ max [pF] [pF] [] [] [V] [s] [s] 18 22 Open 330k 1.8 to 5.5 0.75 2.0 Remarks Applicable CL value = 12.5pF The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Figure 3). The time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed. The time interval that is required for the oscillation to get stabilized after the Hold mode, under the state which the subclock oscillation is enabled, is reset and oscillation is started. (Notes on the implementation of the oscillator circuit) Oscillation is influenced by the circuit pattern layout of printed circuit board. Place the oscillation-related components as close to the CPU chip and to each other as possible with the shortest possible pattern length. Keep the signal lines whose state changes suddenly or in which large current flows as far away from the oscillator circuit as possible and make sure that they do not cross one another. Be sure to insert a current limiting resistor (Rd) so that the oscillation amplitude never exceeds the input voltage level that is specified as the absolute maximum rating. The oscillator circuit constants shown above are sample characteristic values that are measured using the Our designated oscillation evaluation board. Since the accuracy of the oscillation frequency and other characteristics vary according to the board on which the IC is installed, it is recommended that the user consult the resonator vendor for oscillation evaluation of the IC on a user's production board when using the IC for applications that require high oscillation accuracy. For further information, contact your resonator vendor or Our company sales representative serving your locality. It must be noted, when replacing the flash ROM version of a microcontroller with a mask ROM version, that their operating voltage ranges may differ even when the oscillation constant of the external oscillator is the same. CF2/XT2 CF1/XT1 Rf Rd C1 CF/X’tal 0.5VDD C2 Figure 1 CF and XT Oscillator Circuit Figure 2 AC Timing Measurement Point www.onsemi.com 28 LC87FBH08A VDD Operating VDD lower limit 0V Power supply Reset time RES Internal medium speed RC oscillation tmsCF/tmsXtal CF1/XT1 CF2/XT2 tmsMRC Frequency variable RC oscillation Instruction for enabling oscillation executed Operating mode Unpredictable Reset Instruction execution Reset Time and Oscillation Stabilization Time HOLD reset signal HOLD reset signal absent HOLD reset signal valid HALT reset signal valid Internal medium speed RC oscillation or low speed RC oscillation tmsCF/tmsXtal CF1/XT1, CF2/XT2 (Note) tmsMRC Frequency variable RC oscillation Instruction for enabling oscillation executed State HOLD HALT Instruction execution HOLD Reset Signal and Oscillation Stabilization Time Note: External oscillation circuit is selected. Figure 3 Oscillation Stabilization Times www.onsemi.com 29 LC87FBH08A VDD Note: External circuits for reset may vary depending on the usage of POR and LVD. Please refer to the user’s manual for more information. RRES RES CRES Figure 4 Reset Circuit SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DI7 DI8 DO7 DO8 Data RAM transfer period (SIO0 only) tSCK tSCKL tSCKH SIOCLK: thDI tsDI DATAIN: tdDO DATAOUT: Data RAM transfer period (SIO0 only) tSCKHA tSCKL SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Figure 5 Serial I/O Output Waveforms tPIL tPIH Figure 6 Pulse Input Timing Signal Waveform www.onsemi.com 30 LC87FBH08A (a) POR release voltage (PORRL) (b) VDD Reset period 100s or longer Reset period Unknown-state (POUKS) RES Figure 7 Waveform observed when only POR is used (LVD not used) (RESET pin: Pull-up resistor RRES only) The POR function generates a reset only when power is turned on starting at the VSS level. No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level as shown in (a). If such a case is anticipated, use the LVD function together with the POR function or implement an external reset circuit. A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on again after this condition continues for 100s or longer. LVD hysteresis width (LVHYS) LVD release voltage (LVDET+LVHYS) VDD LVD reset voltage (LVDET) Reset period Reset period Reset period Unknown-state (LVUKS) RES Figure 8 Waveform observed when both POR and LVD functions are used (RESET pin: Pull-up resistor RRES only) Resets are generated both when power is turned on and when the power level lowers. A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection level. www.onsemi.com 31 LC87FBH08A VDD LVD release voltage LVD reset voltage LVDET-0.5V TLVDW VSS Figure 9 Low voltage detection minimum width (Example of momentary power loss/Voltage variation waveform) ORDERING INFORMATION Package Shipping (Qty / Packing) LC87FBH08AU-EB-3H Device LQFP36 7x7 / QFP36 (Pb-Free / Halogen Free) 500 / Tray Foam LC87FBH08AU-EB-NH LQFP36 7x7 / QFP36 (Pb-Free / Halogen Free) 1000 / Tape & Reel † For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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