Anpec APW7062B Synchronous buck pwm controller Datasheet

APW7062B
Synchronous Buck PWM Controller
Features
General Description
•
The APW7062B is a voltage mode, synchronous PWM
controller which drives dual N-Channel MOSFETs. It
integrates the control, monitoring and protection functions into a single package, provides one controlled
power outputs with under-voltage and over-current
protection.
APW7062B provide excellent regulation for output load
variation. An internal 0.8V temperature-compensated
reference voltage is designed to meet the requirement
of low output voltage applications. It includes a 200kHz
free-running triangle-wave oscillator that is adjustable
from 70kHz to 800kHz.
The power-on-reset (POR) circuit monitors the VCC,
EN, OCSET input voltage to start-up or shutdown the
IC. The over-current protection (OCP) monitors the
output current by using the voltage drop across the
upper MOSFET’s RDS(ON), eliminating the need for a
current sensing resistor. The under-voltage protection
(UVP) monitors the voltage of FB pin for short-circuit
protection.
The over-current protection trip cycle the soft-start function until the fault events be removed. Under-voltage
protection will shutdown the IC directly.
Simple Single-Loop Control Design
- Voltage-Mode PWM Control
•
Fast Transient Response
- Full 0–100% Duty Ratio
•
Excellent Output Voltage Regulation
- 0.8V Internal Reference
- ± 1% Over Line Voltage and Temperature
•
Over Current Fault Monitor
- Uses Upper MOSFETs RDS (ON)
•
•
Converter Can Source and Sink Current
Small Converter Size
- 200kHz Free-Running Oscillator
- Programmable from 70kHz to 800kHz
• 14-Lead SOIC Package
• Lead Free Available (RoHS Compliant)
Applications
•
•
•
•
Graphic Cards
DDR Memory Power Supply
Pinouts
DDR Memory Termination Voltage
Low-Voltage Distributed Power Supplies
RT
1
14
VCC
OCSET
2
13
PVCC
SS
3
12
LGATE
COMP
4
11
PGND
FB
5
10
EN
6
9
UGATE
GND
7
8
PHASE
BOOT
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
1
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APW7062B
Ordering and Marking Information
P ackage C ode
K : S O P -1 4
O p e ra tin g J u n c tio n T e m p . R a n g e
C : 0 to 7 0 ° C
H a n d lin g C o d e
TU : Tube
TR : Tape & R eel
L e a d F re e C o d e
L : L e a d F re e D e v ic e
B la n k : O rig in a l D e v ic e
APW 7062B
L e a d F re e C o d e
H a n d lin g C o d e
Tem p. R ange
P a ck ag e C o d e
A P W 7062B
XXXXX
A P W 7062B K :
X X X X X - D a te C o d e
Notes： ANPEC lead-free products contain molding compounds/die attach materials and 100% matte in plate
termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering
operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for
MSL classification at lead-free peak reflow temperature.
Block Diagram
VCC
OCSET
G ND
P ower-O n
Res et
EN
IO C SET
200uA
vc c
BOOT
UG A T E
ISS
10uA
S oft S tart
SS
O .C.P
Com parator
P HA S E
5.8V
U.V .P
Com parator
:2
50% V R EF
PVCC
PW M
Com parator
G ate C ontrol
E rror A m p
P G ND
V R EF
O s c illator
FB
LGATE
C O MP
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
Triangle
W ave
RT
2
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APW7062B
Application Cicuit
12V
R1
10R
D1
C1
1uF
R2
10K
1K
U1
APW7062B
R4
1
2
3
4
5
6
7
NC
14
RT
VCC 13
OCSET PVCC 12
SS
LGATE 11
COMP
PGND 10
FB
BOOT 9
EN
UGATE 8
GND
PHASE
C7
0.1uF
L1
R3
1N4148
C2
R5
8
7
6
5
1nF
4
1
2
3
2R2
C8
0.1uF
C13
47pF
R6
C12
8200pF
4
1
2
3
0R


VOUT = VREF ×  1 +
+ C6
470uF
16V
30mR
1uH
+ C4
100uF
16V
Q1
APM4220
1.2V
L2
8
7
6
5
R10
15K
SHDN
+ C3
470uF
16V
30mR
C5
4.7uF
12V
2.2uH
Q2
APM4220
R8 

R9 
D2
SR24
2A/40V
R7
NC
C12
NC
R8
1KF
1%
+ C9
1000uF
6.3V
30mR
+ C10
1000uF
6.3V
30mR
C11
4.7uF
R9
2KF
1%
Absolute Maximum Ratings
Symbol
Rating
Unit
VCC to GND
30
V
VBOOT
BOOT to GND
30
V
VPHASE
PHASE to GND
30
VCC
Parameter
Operating Junction Temperature
TSTG
Storage Temperature
0~150
-65 ~ 150
o
o
TSDR
Soldering Temperature (10 Seconds)
300
VESD
Minimum ESD Rating
±2
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
3
V
o
C
C
C
KV
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APW7062B
Electrical Characteristics
APW7062B
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
VCC SUPPLY CURRENT
ICC
Nominal Supply
Shutdown Supply
EN=VCC; UGATE and LGATE
Open
EN=0V
2
250
mA
350
µA
10.4
V
POWER-ON-RESET
Rising VCC Threshold
VOCSET=4.5V DC
Falling VCC Threshold
VOCSET=4.5V DC
8.8
Enable-Input Threshold
Voltage
VOCSET=4.5V DC
0.8
Rising VOCSET Threshold
V
2.0
1.27
V
V
OSCILLATOR
∆VOSC
Free Running Frequency
RT=OPEN, VCC=12
170
Total Variation
6KΩ < RT to GND < 200KΩ
-15
Ramp Amplitude
RT=OPEN
200
230
kHz
+15
%
1.9
VP-P
REFERENCE VOLTAGE ACCURANCY
∆VREF
VREF
Reference Voltage Tolerance
-1
PWM Error Amplifier
+1
%
0.80
V
800
mA
GATE DRIVERS
IUGATE
Upper Gate Source
VBOOT=12V, VUGATE=6V
RUGATE
Upper Gate Sink
ILGATE=0.3A
ILGATE
Lower Gate Source
PVCC=12V, VLGATE=6V
RLGATE
Lower Gate Sink
ILGATE=0.3A
4
Dead Time
VOUT=2.5V, IOUT=1A, RT=OPEN
50
ns
50
%
TD
650
4
550
7
700
Ω
mA
7
Ω
PROTECTION
FB Under Voltage
IOCSET
ISS
OCSET Current Source
VOCSET=4.5V DC
Soft-Start Current
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
4
170
200
230
µA
8
10
12
µA
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APW7062B
Functional Pin Description
RT (Pin1)
This pin can adjust the switching frequency. Connect
a resistor from RT to GND for increasing the switching
frequency:
FS = 200kHz +
SS (Pin3)
Connect a capacitor from the pin to GND to set the
soft-start interval of the converter. An internal 10uA
current source charges this capacitor to 5.8V. The
SS voltage clamps the error amplifier output, and Figure1 shows the soft-start interval. At t1, the SS voltage reaches the valley of the oscillator’s triangle wave.
The PWM comparator starts to generate a PWM signal to control logic, and the output is rising rapidly.
Until the output is in regulation at t2, the clamp on the
COMP is released. This method provides a rapid and
controlled output voltage rise.
When over current protection occurs, the VOUT is
shutdown, and re-soft-start again, if the over current
condition still exists in soft-start , the VOUT is
shutdowned again, after the SS reaches 4.5V, the SS
is discharged to zero. The soft-start is recurring until
the over current condition is eliminated.
4.15 × 10 6
RT
(RT to GND,FS = 200kHz to 400kHz)
Conversely, connect a resistor from RT to VCC for decreasing the switching frequency:
F S = 200kHz -
3.51 × 10 7
RT
(RT to V CC , F S = 200kHz to 75kHz)
OCSET (Pin2)
This pin serves two functions: a shutdown control and
the setting of over current limit threshold. Pulling this
pin below 1.27V will shutdown the controller, forcing
the UGATE and LGATE signals to be at 0V.
A resistor (Rocset) connected between this pin and the
drain of the high side MOSFET will determine the over
current limit. An internal 200uA current source will
flow through this resistor, creating a voltage drop,
which will be compared with the voltage across the
high side MOSFET. The threshold of the over current
limit is therefore given by:
IPEAK =
VO L TAGE
VSOF T STAR T
VOU T
Erro r Am p
Ou tp u t
VOSC (M IN )
VSS= 1 .2 V
IOCSET (200uA ) × ROCSET
RDS(ON)
t0
To avoid noise interference from switching transient, a
delay time is designed in the OCP comparator.
The over current protection is active only when the
high side MOSFET is turned on longer than 300ns.
t1
TIME
t3
FIGURE1. SOFT-START INTERVAL
t2 =
CSS
ISS
× (VOSC(MIN)+ t1)
tSoftStart = t3 − t2 =
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
t2
5
CSS
×
ISS
V OUT SteadyState
VIN
× ∆VOSC
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APW7062B
Functional Pin Description (Cont.)
Where :
LGATE pins are held low. The EN pin is the opencollector, it will not be floating.
t1=1.2V
CSS = Soft Start Capacitor
GND (Pin7)
ISS = Soft Start Current = 10µA
Signal ground for the IC.
VOSC(MIN) = Bottom of Oscillator = 1.35V
VIN = Input Voltage
PHASE (Pin8)
This pin is connected to the source of the high-side
MOSFET and is used to monitor the voltage drop across
the high-side MOSFET for over-current protection.
∆Vosc = Peak to Peak Oscillator Voltage = 1.9V
∆VOUTSteadyState = Steady State Output Voltage
COMP (Pin4)
This pin is the output of the error amplifier. Add an
external resistor and capacitor network to provide the
loop compensation for the PWM converter (see Application Information).
UGATE (Pin9)
Connect the pin to external MOSFET, and provides
the gate drive for the upper MOSFET.
FB (Pin5)
FB pin is the inverter input of the error amplifier. and it
receives the feedback voltage from an external resis-
BOOT (Pin 10)
This pin provides the supply voltage to the high side
MOSFET driver. For driving logic level N-channel
MOSEFT, a bootstrap circuit can be used to create a
suitable driver’s supply.
tive divider across the output (VOUT). The output voltage is determined by:


VOUT = 0.8V × 1 +
ROUT 

RGND 
PGND (Pin11)
Power ground for the gate diver. Connect the lower
MOSFET source to this pin.
where ROUT is the resistor connected from VOUT to FB
and RGND is the resistor connected from FB to GND.
LGATE (Pin 12)
Connect the pin to external MOSFET, and provides
the gate drive signal for the lower MOSFET.
If the FB voltage is under 50% VREF, because of the
short circuit or other influence , it will cause the under
voltage protection, and the device is shutdowned. Remove the error condition and restart the VCC voltage
or pull the EN from low to high once, the device can
be enabled again.
PVCC (Pin13)
This pin provides a supply voltage for the lower gate
drive, connect it to VCC pin in common use.
VCC (Pin14)
EN (Pin6)
Pull the pin higher than 2V to enable the device, and
pull the pin lower than 0.8V to shutdown the device. In
shutdown, the SS is discharged and the UGATE and
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
This pin provides a supply voltage for the device, when
VCC is above the rising threshold 10.4V, the device is
turned on, conversely, VCC is below the falling
threshold, the device is turned off.
6
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APW7062B
Typical Characteristics
Power Up
V CC (5V/div)
Power Down
VCC=12V, VIN=12V
VOUT=2.5V, L=2.2uH
V CC(5V/div)
SS(2V/div)
SS(2V/div)
VOUT(1V/div)
VOUT(1V/div)
Time(10ms/div)
Time(10ms/div)
Enable (EN = VCC)
EN(10V/div)
VCC=12V, VIN=12V
VOUT=2.5V, L=2.2uH
Shutdown (EN=GND)
EN(10V/div)
VCC=12V, V IN=12V
VOUT=2.5V, L=2.2uH
SS(2V/div)
SS(2V/div)
V OUT(1V/div)
VOUT(1V/div)
Time(10ms/div)
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
VCC=12V, VIN=12V
VOUT=2.5V, L=2.2uH
Time(2ms/div)
7
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APW7062B
Typical Characteristics (Cont.)
Load Transient Response
Under Voltage Protection
VCC=12V, VIN=12V
VOUT=2.5V, L=2.2uH
VOUT(100mV/div)
VCC=12V, VIN=12V
VOUT=2.5V, RT=Open
L=2.2uH
VOUT(2V/div)
SS(5V/div)
IOUT(2A/div)
IL(10A/div)
UGATE(20V/div)
Time(20us/div)
Time(20us/div)
UGATE Rising
UGATE Falling
VCC=12V, VIN=12V
VOUT=2.5V, RT=Open
VCC=12V, VIN=12V
VOUT=2.5V, RT=Open
UGATE(10V/div)
UGATE(10V/div)
LGATE(10V/div)
LGATE(10V/div)
Phase(10V/div)
Phase(10V/div)
Time(50ns/div)
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
Time(50ns/div)
8
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APW7062B
Typical Characteristics (Cont.)
UGATE Source Current vs. UGATE Voltage
1.2
VBOOT=12V
1.2
UGATE Sink Current (A)
UGATE Source Current (A)
1.4
UGATE Sink Current vs. UGATE Voltage
1
0.8
0.6
0.4
0.2
0
VBOOT=12V
1
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10
12
0
2
LGATE Source Current vs. LGATE Voltage
8
10
12
LGATE Sink Current vs. LGATE Voltage
1.2
PVCC=12V
1.2
PVCC=12V
1
LGATE Sink Current (A)
LGATE Source Current (A)
6
UGATE Voltage (V)
UGATE Voltage (V)
1.4
4
1
0.8
0.6
0.4
0.2
0.8
0.6
0.4
0.2
0
0
0
2
4
6
8
10
0
12
LGATE Voltage (V)
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
2
4
6
8
10
12
LGATE Voltage (V)
9
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APW7062B
Typical Characteristics (Cont.)
RT Resistance vs. Switching Frequency
Over Current Protection
VCC=12V, VIN=12V, VOUT=2.5V,
ROCEST=1KΩ, RT=Open, RDS(ON)=14mΩ,
IOUT=16.3A, L=2.2uH, LOUT=16.3A
10000
VOUT(1V/div)
RT Resistance (kΩ)
RT pull up to 12V
SS(5V/div)
IL(10A/div)
UGATE(20V/div)
1000
100
RT pull down to GND
10
1
10
100
1000
Switching Frequency (kHz)
Time(20ms/div)
Switching Frequency vs. Junction Temperature
Reference Voltage vs. Junction Temperature
220
VCC =12V
RT=Open
210
0.798
Switching Frequency
Reference Voltage (V)
0.8
0.796
0.794
0.792
200
190
180
170
160
0.79
-40
-20
0
20
40
60
80
-40
100 120
Junction Temperature (°C)
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
-20
0
20
40
60
80
100 120
Junction Temperature (°C)
10
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APW7062B
Application Information
Component Selection Guidelines
∆VOUT = IRIPPLE x ESR
Output Capacitor Selection
The selection of COUT is determined by the required
effective series resistance (ESR) and voltage rating
rather than the actual capacitance requirement. Therefore select high performance low ESR capacitors that
are intended for switching regulator applications. In
some applications, multiple capacitors have to be
paralled to achieve the desired ESR value. If tantalum
capacitors are used, make sure they are surge tested
by the manufactures. If in doubt, consult the capacitors manufacturer.
where Fs is the switching frequency of the regulator.
Input Capacitor Selection
The input capacitor is chosen based on the voltage
rating and the RMS current rating. For reliable
operation, select the capacitor voltage rating to be at
least 1.3 times higher than the maximum input voltage.
The maximum RMS current rating requirement is approximately IOUT/2 , where IOUT is the load current.
During power up, the input capacitors have to handle
large amount of surge current. If tantalum capacitors
are used, make sure they are surge tested by the
manufactures. If in doubt, consult the capacitors
manufacturer.
For high frequency decoupling, a ceramic capacitor
between 0.1uF to 1uF can be connected between VCC
and ground pin.
Inductor Selection
The inductance of the inductor is determined by the
output voltage requirement. The larger the inductance,
the lower the inductor’s current ripple. This will translate into lower output ripple voltage. The ripple current
and ripple voltage can be approximated by:
IRIPPLE =
VIN - VOUT
Fs x L
x
There is a tradeoff exists between the inductor’s ripple
current and the regulator load transient response time
A smaller inductor will give the regulator a faster load
transient response at the expense of higher ripple current and vice versa. The maximum ripple current occurs at the maximum input voltage. A good starting
point is to choose the ripple current to be approximately 30% of the maximum output current.
Once the inductance value has been chosen, select
an inductor that is capable of carrying the required
peak current without going into saturation. In some
type of inductors, especially core that is make of
ferrite, the ripple current will increase abruptly when it
saturates. This will result in a larger output ripple
voltage.
Compensation
The output LC filter introduces a double pole, which
contributes with –40dB/decade gain slope and 180
degrees phase shift in the control loop. A compensation network between COMP pin and ground should
be added. The simplest loop compensation network
is shown in Fig. 4.
The output LC filter consists of the output inductor
and output capacitors. The transfer function of the LC
filter is given by:
GAINLC =
1 + s × ESR × COUT
2
s × L × COUT + s × ESR + 1
VOUT
VIN
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
11
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APW7062B
Application Information (Cont.)
Compensation (Cont.)
The poles and zero of this transfer function are:
FLC =
FESR =
GAINPWM =
∆VOSC
VIN
1
2 × π × L × COUT
Driver
PWM
Comparator
1
2 × π × ESR × COUT
VOSC
The FLC is the double poles of the LC filter, and FESR is
the zero introduced by the ESR of the output capacitor.
PHASE
VIN
L
Output of
Error
Amplifier
PHASE
Output
Driver
COUT
Figure 3. The PWM Modulator
ESR
The compensation circuit is shown in Figure 4. R3
and C1 introduce a zero and C2 introduces a pole to
reduce the switching noise. The transfer function of
error amplifier is given by:
Figure 1. The Output LC Filter
FLC
-40dB/dec
Gain


GAINAMP = gm × Zo = gm ×   R3 +
FESR
=
gm ×
(R3sC1 + 1)


s×s +
-20dB/dec
 1 
 //

sC1  sC2 
1


R3 × C1× C2 
C1 + C2
The poles and zero of the compensation network are:
Frequency
1
FP =
Figure 2. The Output LC Filter Gain & Frequency
The PWM modulator is shown in Figure. 3. The input
is the output of the error amplifier and the output is the
PHASE node. The transfer function of the PWM modulator is given by:
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
FZ
12
=
2 × π × R3 ×
C1× C2
C1 + C2
1
2 × π × R3 × C1
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APW7062B
Application Information (Cont.)
Calculate the C2 by the equation:
Compensation (Cont.)
V OU T
C2 =
C1
π × R3 × C1 × F S − 1
E rror
A m plifier
R1
FB
FZ=0.75FLC
-
COM P
20⋅ log(gm⋅ R3)
R2
+
R3
V R EF
Compensation
Gain
C2
C1
FLC
20 ⋅ log
Figure 4. Compensation Network
The closed loop gain of the converter can be written
as:
GAINLC x GAINPWM x
R2
R1 + R2
∆ V OSC
V IN
×
F ESR
F LC
2
×
ΔVOSC
FESR
PWM &
Filter Gain
Converter
Gain
Frequency
Figure 5. Converter Gain & Frequency
R1 + R2
R2
×
FO
gm
Where:
MOSFET Selection
The selection of the N-channel power MOSFETs are
determined by the RDS(ON), reverse transfer capacitance
(CRSS) and maximum output current requirement.The
losses in the MOSFETs have two components: conduction loss and transition loss. For the upper and
lower MOSFET, the losses are approximately given
by the following :
PUPPER = Iout2 (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FS
gm=900uA/V
2.Place the zero FZ before the LC filter double poles
FLC:
FZ = 0.75 x FLC
Calculate the C1 by the equation:
C1 =
FO
VIN
x GAINAMP
Figure 5 shows the converter gain and the following
guidelines will help to design the compensation
network.
1.Select the desired zero crossover frequency FO:
(1/5 ~ 1/10) x FS >FO>FZ
Use the following equation to calculate R3:
R3 =
FP=0.5FS
10
2 × π × R1× FLC
3. Set the pole at the half the switching frequency:
FP = 0.5xFS
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
13
PLOWER = Iout2 (1+ TC)(RDS(ON))(1-D)
where IOUT is the load current
TC is the temperature dependency of RDS(ON)
FS is the switching frequency
tsw is the switching interval
D is the duty cycle
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APW7062B
Application Information (Cont.)
Note that both MOSFETs have conduction losses while
the upper MOSFET include an additional transition
loss.The switching internal, tsw, is a function of the
reverse transfer capacitance CRSS. Figure 3 illustrates
the switching waveform internal of the MOSFET.
The (1+TC) term is to factor in the temperature dependency of the RDS(ON) and can be extracted from the
“RDS(ON) vs Temperature” curve of the power MOSFET.
single point grounding. Figure 4 illustrates the layout,
with bold lines indicating high current paths. Components along the bold lines should be placed close
together. Below is a checklist for your layout:
• Keep the switching nodes (UGATE, LGATE and
PHASE) away from sensitive small signal nodes
since these nodes are fast moving signals. There
fore keep traces to these nodes as short as
possible.
Layout Considerations
• The ground return of CIN must return to the combine
In high power switching regulator, a correct layout is
important to ensure proper operation of the regulator.
In general, interconnecting impedances should be minimized by using short, wide printed circuit traces. Signal and power grounds are to be kept separate and
finally combined using ground plane construction or
COUT (-) terminal.
• Capacitor CBOOT should be connected as close to
the BOOT and PHASE pins as possible.
V DS
Voltage across
drain and source of MO SFET
V IN
C IN
A P W 7062B
P GND
LG AT E
11
12
U
UGATE 9
1
P HAS E 8
t sw
Tim e
Figure 3. Switching waveform across MOSFET
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
+
C OU T
Q1
Q2
+
L1
L
O
A
D
VO U T
F igure 4. R ec om m ended Lay out D iagram
14
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APW7062B
Package Information
E
H
0 . 01 5 x 4 5
SOP – 14 (150mil)
A
0 . 0 10
A1
A
D
Ee
B
L
Dim
A
A1
B
C
D
E
e
H
L
θ°
Millimeters
Min.
1.477
0.102
0.331
0.191
8.558
3.82
Inches
Max.
1.732
0.255
0.509
0.2496
8.762
3.999
Min.
0.058
0.004
0.013
0.0075
0.336
0.150
6.215
1.274
8°
0.228
0.015
0°
1.274
5.808
0.382
0°
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
Max.
0.068
0.010
0.020
0.0098
0.344
0.157
0.050
15
0.244
0.050
8°
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APW7062B
Physical Specifications
Terminal Material
Lead Solderability
Packaging
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
2500 devices per reel
Reflow Condition
(IR/Convection or VPR Reflow)
tp
TP
Critical Zone
T L to T P
Temperature
Ram p-up
TL
tL
Tsm ax
Tsm in
Ram p-down
ts
Preheat
25
t 25 °C to Peak
Tim e
Classificatin Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
- Time (tL)
Peak/Classificatioon Temperature (Tp)
Time within 5°C of actual
Peak Temperature (tp)
Ramp-down Rate
Sn-Pb Eutectic Assembly
Pb-Free Assembly
3°C/second max.
3°C/second max.
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
183°C
60-150 seconds
217°C
60-150 seconds
See table 1
See table 2
10-30 seconds
20-40 seconds
6°C/second max.
6°C/second max.
6
minutes
max.
8 minutes max.
Time 25°C to Peak Temperature
Notes: All temperatures refer to topside of the package .Measured on the body surface.
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
16
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APW7062B
Classificatin Reflow Profiles(Cont.)
Table 1. SnPb Entectic Process – Package Peak Reflow Tem peratures
3
3
Package Thickness
Volum e m m
Volum e m m
<350
≥ 350
<2.5 m m
240 +0/-5°C
225 +0/-5°C
≥2.5 m m
225 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Tem peratures
3
3
3
Package Thickness
Volum e mm
Volum e mm
Volum e mm
<350
350-2000
>2000
<1.6 m m
260 +0°C*
260 +0°C*
260 +0°C*
1.6 m m – 2.5 m m
260 +0°C*
250 +0°C*
245 +0°C*
≥2.5 m m
250 +0°C*
245 +0°C*
245 +0°C*
*Tolerance: The device m anufacturer/supplier shall assure process com patibility up to and
including the stated classification tem perature (this m eans Peak reflow tem perature +0°C.
For exam ple 260°C+0°C) at the rated MSL level.
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B,A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C, 5 SEC
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1tr > 100mA
Carrier Tape & Reel Dimension
t
E
D
P
Po
P1
W
F
Ao
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
D1
17
Ko
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APW7062B
Carrier Tape & Reel Dimension
T2
J
C
A
B
T1
Application
A
330REF
SOP-14
(150mil)
F
7.5
B
C
13.0 + 0.5
100REF
- 0.2
D
D1
φ0.50 +
0.1
φ1.50
(MIN)
J
T1
2 ± 0.5
T2
16.5REF 2.5 ± 025
W
16.0 ± 0.3
P
E
8
1.75
Po
P1
Ao
Ko
t
4.0
2.0
6.5
2.10
0.3±0.05
(mm)
Cover Tape Dimensions
Application
SOP- 14
Carrier Width
24
Cover Tape Width
21.3
Devices Per Reel
2500
Customer Service
Anpec Electronics Corp.
Head Office :
5F, No. 2 Li-Hsin Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright  ANPEC Electronics Corp.
Rev. A.3 - Mar., 2005
18
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