Samsung K7A403600B 128kx36/x32 & 256kx18 synchronous sram Datasheet

K7A403600B
K7A403200B
K7A401800B
128Kx36/x32 & 256Kx18 Synchronous SRAM
4Mb Sync. Pipelined Burst SRAM
Specification
100 TQFP with Pb & Pb-Free
(RoHS compliant)
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
ALL INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military
or defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 2.0 July 2006
K7A403600B
K7A403200B
K7A401800B
128Kx36/x32 & 256Kx18 Synchronous SRAM
Document Title
128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM
Revision History
History
Draft Date
Remark
0.0
1. Initial draft
May. 15. 2001
Preliminary
0.1
1. Changed DC parameters
Icc ; from 350mA to 290mA at -16,
from 330mA to 270mA at -15,
from 300mA to 250mA at -14,
ISB1; from 100mA to 80mA
June. 12. 2001
Preliminary
0.2
1. Delete Pass-Through
June.25. 2001
Preliminary
0.3
1. Add x32 org. and industrial temperature
Aug. 11. 2001
Preliminary
1.0
1. Final spec release
2. Changed Pin Capacitance
- Cin ; from 5pF to 4pF
- Cout; from 7pF to 6pF
Nov. 15. 2001
Final
2.0
1. Add Pb-free package
Jul. 03. 2006
Final
Rev. No
-2-
Rev. 2.0 July 2006
K7A403600B
K7A403200B
K7A401800B
128Kx36/x32 & 256Kx18 Synchronous SRAM
4Mb SPB SRAM Ordering Information
Org.
256Kx18
128Kx32
128Kx36
VDD (V)
Speed (ns)
Access Time (ns)
Part Number
RoHS Avail.
3.3
6.0
3.5
K7A401800B-P(Q)1C(I)216
√
3.3
7.2
4.0
K7A401800B-Q C(I)14
•
3.3
6.0
3.5
K7A403200B-P(Q)1C(I)216
√
3.3
7.2
4.0
K7A403200B-Q C(I)14
•
3.3
6.0
3.5
K7A403600B-P(Q)1C(I)216
√
3.3
7.2
4.0
K7A403600B-Q3C(I)14
•
3
3
Note 1. P(Q) [Package type]: P-Pb Free, Q-Pb
2. C(I) [Operating Temperature]: C-Commercial, I-Industrial
3. Support only Pb package parts at this frequency. To use Pb-Free package, use faster frequency parts.
-3-
Rev. 2.0 July 2006
K7A403600B
K7A403200B
K7A401800B
128Kx36/x32 & 256Kx18 Synchronous SRAM
128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM
FEATURES
GENERAL DESCRIPTION
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• VDD= 3.3V+0.3V/-0.165V Power Supply.
• VDDQ Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
• Three Chip Enables for simple depth expansion with No Data Contnention; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A.
• Operating in commercial and industrial temperature range.
The K7A403600B, K7A403200B and K7A401800B are
4,718,592-bit Synchronous Static Random Access Memory
designed for high performance second level cache of Pentium and Power PC based System.
It is organized as 128K(256K) words of 36(18) bits and integrates address and control registers, a 2-bit burst address
counter and added some new functions for high performance cache RAM applications; GW, BW, LBO, ZZ. Write
cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status
processor (ADSP) or address status cache controller
(ADSC) inputs. Subsequent burst addresses are generated
internally in the system′s burst sequence and are controlled
by the burst address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(linear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A403600B, K7A403200B and K7A401800B are fabricated using SAMSUNG′s high performance CMOS technology and is available in a 100pin TQFP package. Multiple
power and ground pins are utilized to minimize ground
bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Symbol
-16
-14
Unit
tCYC
6.0
7.2
ns
Clock Access Time
tCD
3.5
4.0
ns
Output Enable Access Time
tOE
3.5
4.0
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
BURST CONTROL
LOGIC
CONTROL
REGISTER
ADV
ADSC
BURST
ADDRESS A′0~A′1
COUNTER
A0~A1
A0~A16
or A0~A17
ADSP
ADDRESS
REGISTER
A2~A16
or A2~A17
DATA-IN
REGISTER
CONTROL
REGISTER
CS1
CS2
CS2
GW
BW
OUTPUT
REGISTER
CONTROL
LOGIC
BUFFER
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DQa0 ~ DQd7
DQPa ~ DQPd
128Kx36/32, 256Kx18
MEMORY
ARRAY
36/32 or 18
or DQa0 ~ DQb7
DQPa ~ DQPb
-4-
Rev. 2.0 July 2006
K7A403600B
K7A403200B
K7A401800B
128Kx36/x32 & 256Kx18 Synchronous SRAM
WEd
WEc
WEb
WEa
CS2
VDD
VSS
CLK
GW
BW
OE
ADSC
ADSP
ADV
A8
A9
94
93
92
91
90
89
88
87
86
85
84
83
82
81
CS2
97
95
CS1
98
96
A6
A7
99
100 Pin TQFP
(20mm x 14mm)
47
48
49
50
A13
A14
A15
A16
41
VDD
46
40
VSS
A12
39
N.C.
45
38
A11
37
A0
N.C.
44
36
A1
A10
35
A2
43
34
A3
N.C.
33
A4
42
32
N.C.
31
K7A403600B(128Kx36)
K7A403200B(128Kx32)
A5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LBO
DQPc/NC
DQc0
DQc1
VDDQ
VSSQ
DQc2
DQc3
DQc4
DQc5
VSSQ
VDDQ
DQc6
DQc7
N.C.
VDD
N.C.
VSS
DQd0
DQd1
VDDQ
VSSQ
DQd2
DQd3
DQd4
DQd5
VSSQ
VDDQ
DQd6
DQd7
DQPd/NC
100
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb/NC
DQb7
DQb6
VDDQ
VSSQ
DQb5
DQb4
DQb3
DQb2
VSSQ
VDDQ
DQb1
DQb0
VSS
N.C.
VDD
ZZ
DQa7
DQa6
VDDQ
VSSQ
DQa5
DQa4
DQa3
DQa2
VSSQ
VDDQ
DQa1
DQa0
DQPa/NC
PIN NAME
SYMBOL
A0 - A16
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
WEx
(x=a,b,c,d)
OE
GW
BW
ZZ
LBO
PIN NAME
TQFP PIN NO.
32,33,34,35,36,37
44,45,46,47,48,49
50,81,82,99,100
83
Burst Address Advance
Address Status Processor 84
Address Status Controller 85
89
Clock
98
Chip Select
97
Chip Select
92
Chip Select
93,94,95,96
Byte Write Inputs
Address Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
86
88
87
64
31
SYMBOL
PIN NAME
TQFP PIN NO.
VDD
VSS
Power Supply(+3.3V)
Ground
15,41,65,91
17,40,67,90
N.C.
No Connect
14,16,38,39,42,43,66
DQa0~a7
DQb0~b7
DQc0~c7
DQd0~d7
DQPa~Pd
/NC
Data Inputs/Outputs
52,53,56,57,58,59,62,63
68,69,72,73,74,75,78,79
2,3,6,7,8,9,12,13
18,19,22,23,24,25,28,29
51,80,1,30
Output Power Supply
(2.5V or 3.3V)
Output Ground
4,11,20,27,54,61,70,77
VDDQ
5,10,21,26,55,60,71,76
VSSQ
-5-
Rev. 2.0 July 2006
K7A403600B
K7A403200B
K7A401800B
128Kx36/x32 & 256Kx18 Synchronous SRAM
CLK
GW
BW
OE
ADSC
ADSP
ADV
A8
A9
88
87
86
85
84
83
82
81
WEa
VSS
WEb
93
89
N.C.
94
90
N.C.
95
CS2
CS2
96
VDD
CS1
97
91
A7
98
92
A6
99
100 Pin TQFP
(20mm x 14mm)
47
48
49
50
A14
A15
A16
A17
41
VDD
46
40
VSS
A13
39
N.C.
45
38
N.C.
A12
37
A0
44
36
A1
A11
35
A2
43
34
A3
N.C.
33
A4
42
32
N.C.
31
K7A401800B(256Kx18)
A5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LBO
N.C.
N.C.
N.C.
VDDQ
VSSQ
N.C.
N.C.
DQb0
DQb1
VSSQ
VDDQ
DQb2
DQb3
N.C.
VDD
N.C.
VSS
DQb4
DQb5
VDDQ
VSSQ
DQb6
DQb7
DQPb
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
100
PIN CONFIGURATION(TOP VIEW)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A10
N.C.
N.C.
VDDQ
VSSQ
N.C.
DQPa
DQa7
DQa6
VSSQ
VDDQ
DQa5
DQa4
VSS
N.C.
VDD
ZZ
DQa3
DQa2
VDDQ
VSSQ
DQa1
DQa0
N.C.
N.C.
VSSQ
VDDQ
N.C.
N.C.
N.C.
PIN NAME
SYMBOL
PIN NAME
TQFP PIN NO.
A0 - A17
Address Inputs
ADV
ADSP
ADSC
CLK
CS1
CS2
CS2
WEx
(x=a,b)
OE
GW
BW
ZZ
LBO
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Chip Select
Chip Select
Byte Write Inputs
32,33,34,35,36,37,
44,45,46,47,48,49,
50,80,81,82,99,100
83
84
85
89
98
97
92
93,94
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
86
88
87
64
31
SYMBOL
PIN NAME
TQFP PIN NO.
VDD
VSS
N.C.
Power Supply(+3.3V)
Ground
No Connect
15,41,65,91
17,40,67,90
1,2,3,6,7,14,16,25,28,29,
30,38,39,42,43,51,52,53,
56,57,66,75,78,79,95,96
DQa0~a7
DQb0~b7
DQPa, Pb
VDDQ
Data Inputs/Outputs
58,59,62,63,68,69,72,73
8,9,12,13,18,19,22,23
74,24
4,11,20,27,54,61,70,77
VSSQ
-6-
Output Power Supply
(2.5V or 3.3V)
Output Ground
5,10,21,26,55,60,71,76
Rev. 2.0 July 2006
K7A403600B
K7A403200B
K7A401800B
128Kx36/x32 & 256Kx18 Synchronous SRAM
FUNCTION DESCRIPTION
The K7A4036/3200B and K7A401800B are synchronous SRAM designed to support the burst address accessing sequence of the
P6 and Power PC based microprocessor. All inputs (with the exception of OE, LBO and ZZ) are sampled on rising clock edges. The
start and duration of the burst access is controlled by ADSC, ADSP and ADV and chip select pins.
The accesses are enabled with the chip select signals and output enabled signals. Wait states are inserted into the access with ADV.
When ZZ is pulled high, the SRAM will enter a Power Down State. At this time, internal state of the SRAM is preserved. When ZZ
returns to low, the SRAM normally operates after 2cycles of wake up time. ZZ pin is pulled down internally.
Read cycles are initiated with ADSP(regardless of WEx and ADSC)using the new external address clocked into the on-chip address
register whenever ADSP is sampled low, the chip selects are sampled active, and the output buffer is enabled with OE. In read operation the data of cell array accessed by the current address, registered in the Data-out registers by the positive edge of CLK, are carried to the Data-out buffer by the next positive edge of CLK. The data, registered in the Data-out buffer, are projected to the output
pins. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on the subsequent clock edges. The address
increases internally for the next access of the burst when WEx are sampled High and ADV is sampled low. And ADSP is blocked to
control signals by disabling CS1.
All byte write is done by GW(regaedless of BW and WEx.), and each byte write is performed by the combination of BW and WEx
when GW is high.
Write cycles are performed by disabling the output buffers with OE and asserting WEx. WEx are ignored on the clock edge that samples ADSP low, but are sampled on the subsequent clock edges. The output buffers are disabled when WEx are sampled
Low(regardless of OE). Data is clocked into the data input register when WEx sampled Low. The address increases internally to the
next address of burst, if both WEx and ADV are sampled Low. Individual byte write cycles are performed by any one or more byte
write enable signals(WEa, WEb, WEc or WEd) sampled low. The WEa control DQa0 ~ DQa7 and DQPa, WEb controls DQb0 ~ DQb7
and DQPb, WEc controls DQc0 ~ DQc7 and DQPc, and WEd control DQd0 ~ DQd7 and DQPd. Read or write cycle may also be initiated with ADSC, instead of ADSP. The differences between cycles initiated with ADSC and ADSP as are follows;
ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
WEx are sampled on the same clock edge that sampled ADSC low(and ADSP high).
Addresses are generated for the burst access as shown below, The starting point of the burst sequence is provided by the external
address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state
of the LBO pin. When this pin is Low, linear burst sequence is selected. When this pin is High, Interleaved burst sequence is
selected.
BURST SEQUENCE TABLE
LBO PIN
(Interleaved Burst)
Case 1
HIGH
A1
0
0
1
1
First Address
Fourth Address
Case 2
A0
0
1
0
1
A1
0
0
1
1
Case 3
A0
1
0
1
0
A1
1
1
0
0
Case 4
A0
0
1
0
1
A1
1
1
0
0
A0
1
0
1
0
Note: 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
BQ TABLE
LBO PIN
(Linear Burst)
Case 1
LOW
A1
0
0
1
1
First Address
Fourth Address
Case 2
A0
0
1
0
1
A1
0
1
1
0
Case 3
A0
1
0
1
0
A1
1
1
0
0
Case 4
A0
0
1
0
1
A1
1
0
0
1
A0
1
0
1
0
Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
ASYNCHRONOUS TRUTH TABLE
(See Notes 1 and 2):
OPERATION
ZZ
OE
I/O STATUS
Sleep Mode
H
X
High-Z
L
L
DQ
L
H
High-Z
Write
L
X
Din, High-Z
Deselected
L
X
High-Z
Read
Notes
1. X means "Don′t Care".
2. ZZ pin is pulled down internally
3. For write cycles that following read cycles, the output buffers must be
disabled with OE, otherwise data bus contention will occur.
4. Sleep Mode means power down state of which stand-by current does
not depend on cycle time.
5. Deselected means power down state of which stand-by current
depends on cycle time.
-7-
Rev. 2.0 July 2006
K7A403600B
K7A403200B
K7A401800B
128Kx36/x32 & 256Kx18 Synchronous SRAM
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CS1
CS2
CS2
H
X
X
ADSP ADSC
X
L
ADV
WRITE
CLK
ADDRESS ACCESSED
OPERATION
X
X
↑
N/A
Not Selected
L
L
X
L
X
X
X
↑
N/A
Not Selected
L
X
H
L
X
X
X
↑
N/A
Not Selected
L
L
X
X
L
X
X
↑
N/A
Not Selected
L
X
H
X
L
X
X
↑
N/A
Not Selected
L
H
L
L
X
X
X
↑
External Address
Begin Burst Read Cycle
L
H
L
H
L
X
L
↑
External Address
Begin Burst Write Cycle
L
H
L
H
L
X
H
↑
External Address
Begin Burst Read Cycle
X
X
X
H
H
L
H
↑
Next Address
Continue Burst Read Cycle
H
X
X
X
H
L
H
↑
Next Address
Continue Burst Read Cycle
X
X
X
H
H
L
L
↑
Next Address
Continue Burst Write Cycle
H
X
X
X
H
L
L
↑
Next Address
Continue Burst Write Cycle
X
X
X
H
H
H
H
↑
Current Address
Suspend Burst Read Cycle
H
X
X
X
H
H
H
↑
Current Address
Suspend Burst Read Cycle
X
X
X
H
H
H
L
↑
Current Address
Suspend Burst Write Cycle
H
X
X
X
H
H
L
↑
Current Address
Suspend Burst Write Cycle
Notes: 1. X means "Don′t Care".
2. The rising edge of clock is symbolized by ↑.
3. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
4. Operation finally depends on status of asynchronous input pins(ZZ and OE).
WRITE TRUTH TABLE(x36/32)
GW
BW
WEa
WEb
WEc
WEd
OPERATION
H
H
X
X
X
X
READ
H
L
H
H
H
H
READ
H
L
L
H
H
H
WRITE BYTE a
H
L
H
L
H
H
WRITE BYTE b
H
L
H
H
L
L
WRITE BYTE c and d
H
L
L
L
L
L
WRITE ALL BYTEs
L
X
X
X
X
X
WRITE ALL BYTEs
Notes: 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
WRITE TRUTH TABLE(x18)
GW
BW
WEa
WEb
OPERATION
H
H
X
X
READ
H
L
H
H
READ
H
L
L
H
WRITE BYTE a
H
L
H
L
WRITE BYTE b
H
L
L
L
WRITE ALL BYTEs
L
X
X
X
WRITE ALL BYTEs
Notes: 1. X means "Don′t Care".
2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑).
-8-
Rev. 2.0 July 2006
K7A403600B
K7A403200B
K7A401800B
128Kx36/x32 & 256Kx18 Synchronous SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
SYMBOL
RATING
UNIT
VDD
-0.3 to 4.6
V
VDDQ
VDD
V
Voltage on VDD Supply Relative to VSS
Voltage on VDDQ Supply Relative to VSS
Voltage on Input Pin Relative to VSS
VIN
-0.3 to VDD+0.3
V
Voltage on I/O Pin Relative to VSS
VIO
-0.3 to VDDQ+0.3
V
Power Dissipation
Storage Temperature
Operating Temperature
PD
2.2
W
TSTG
-65 to 150
°C
Commercial
TOPR
0 to 70
°C
Industrial
TOPR
-40 to 85
°C
TBIAS
-10 to 85
°C
Storage Temperature Range Under Bias
*Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING CONDITIONS at 3.3V I/O (0°C≤ TA≤70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
MIN
Typ.
MAX
UNIT
VDD
3.135
3.3
3.6
V
VDDQ
3.135
3.3
3.6
V
VSS
0
0
0
V
* The above parameters are also guaranteed at industrial temperature range.
OPERATING CONDITIONS at 2.5V I/O(0°C ≤ TA ≤ 70°C)
PARAMETER
Supply Voltage
Ground
SYMBOL
MIN
Typ.
MAX
UNIT
VDD
3.135
3.3
3.6
V
VDDQ
2.375
2.5
2.9
V
VSS
0
0
0
V
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*(TA=25°C, f=1MHz)
PARAMETER
Input Capacitance
Output Capacitance
SYMBOL
TEST CONDITION
TYP
MAX
UNIT
CIN
VIN=0V
-
4
pF
COUT
VOUT=0V
-
6
pF
*Note : Sampled not 100% tested.
-9-
Rev. 2.0 July 2006
K7A403600B
K7A403200B
K7A401800B
128Kx36/x32 & 256Kx18 Synchronous SRAM
DC ELECTRICAL CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT
Input Leakage Current(except ZZ)
IIL
VDD = Max; VIN=VSS to VDD
-2
+2
µA
Output Leakage Current
IOL
Output Disabled, VOUT=VSS to VDDQ
-2
+2
µA
Operating Current
ICC
Device Selected, IOUT=0mA, ZZ≤VIL,
All Inputs=VIL or VIH, Cycle Time ≥cyc Min.
-16
-
290
-14
-
250
ISB
Device deselected, IOUT=0mA,ZZ≤VIL,
f=Max, All Inputs≤0.2V or ≥ VDD-0.2V
-16
-
140
-14
-
130
ISB1
Device deselected, IOUT=0mA, ZZ≤0.2V,
f = 0, All Inputs=fixed (VDD-0.2V or 0.2V)
-
80
mA
ISB2
Device deselected, IOUT=0mA, ZZ≥VDD-0.2V,
f=Max, All Inputs≤VIL or ≥VIH
-
50
mA
Standby Current
mA
mA
Output Low Voltage(3.3V I/O)
VOL
IOL = 8.0mA
-
0.4
V
Output High Voltage(3.3V I/O)
VOH
IOH = -4.0mA
2.4
-
V
Output Low Voltage(2.5V I/O)
VOL
IOL = 1.0mA
-
0.4
V
Output High Voltage(2.5V I/O)
VOH
IOH = -1.0mA
2.0
-
V
Input Low Voltage(3.3V I/O)
VIL
-0.5*
0.8
V
Input High Voltage(3.3V I/O)
VIH
2.0
VDD+0.3**
V
Input Low Voltage(2.5V I/O)
VIL
-0.3*
0.7
V
Input High Voltage(2.5V I/O)
VIH
1.7
VDD+0.3**
V
The above parameters are also guaranteed at industrial temperature range.
* VIL(Min)=-2.0(Pulse Width ≤ tCYC/2)
** VIH(Max)=4.6(Pulse Width ≤ tCYC/2)
** In Case of I/O Pins, the Max. VIH=VDDQ+0.3V
TEST CONDITIONS
(VDD=3.3V+0.3V/-0.165V,VDDQ=3.3V+0.3/-0.165V or VDD=3.3V+0.3V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0 to 70°C)
PARAMETER
VALUE
Input Pulse Level(for 3.3V I/O)
0 to 3V
Input Pulse Level(for 2.5V I/O)
0 to 2.5V
Input Rise and Fall Time(Measured at 0.3V and 2.7V for 3.3V I/O)
1ns
Input Rise and Fall Time(Measured at 0.3V and 2.1V for 2.5V I/O)
1ns
Input and Output Timing Reference Levels for 3.3V I/O
1.5V
Input and Output Timing Reference Levels for 2.5V I/O
VDDQ/2
Output Load
See Fig. 1
* The above parameters are also guaranteed at industrial temperature range.
- 10 -
Rev. 2.0 July 2006
K7A403600B
K7A403200B
K7A401800B
128Kx36/x32 & 256Kx18 Synchronous SRAM
Output Load (B)
(for tLZC, tLZOE, tHZOE & tHZC)
Output Load(A)
Dout
RL=50Ω
Z0=50Ω
30pF*
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
VL=1.5V for 3.3V I/O
VDDQ/2 for 2.5V I/O
319Ω / 1667Ω
Dout
353Ω / 1538Ω
* Capacitive Load consists of all components of
the test environment.
5pF*
* Including Scope and Jig Capacitance
Fig. 1
AC TIMING CHARACTERISTICS(TA=0 to 70°C, VDD=3.3V+0.3V/-0.165V)
PARAMETER
Symbol
Cycle Time
Clock Access Time
-16
Min.
-14
Max
Min.
Max
Unit
tCYC
6.0
-
7.2
-
ns
tCD
-
3.5
-
4.0
ns
Output Enable to Data Valid
tOE
-
3.5
-
4.0
ns
Clock High to Output Low-Z
tLZC
0
-
0
-
ns
Output Hold from Clock High
tOH
1.5
-
1.5
-
ns
Output Enable Low to Output Low-Z
tLZOE
0
-
0
-
ns
Output Enable High to Output High-Z
tHZOE
-
3.5
-
4.0
ns
tHZC
1.5
3.5
1.5
4.0
ns
tCH
2.4
-
2.8
-
ns
Clock High to Output High-Z
Clock High Pulse Width
Clock Low Pulse Width
tCL
2.4
-
2.8
-
ns
Address Setup to Clock High
tAS
1.5
-
1.5
-
ns
Address Status Setup to Clock High
tSS
1.5
-
1.5
-
ns
Data Setup to Clock High
tDS
1.5
-
1.5
-
ns
Write Setup to Clock High (GW, BW, WEX)
Address Advance Setup to Clock High
Chip Select Setup to Clock High
Address Hold from Clock High
tWS
1.5
-
1.5
-
ns
tADVS
1.5
-
1.5
-
ns
tCSS
1.5
-
1.5
-
ns
tAH
0.5
-
0.5
-
ns
Address Status Hold from Clock High
tSH
0.5
-
0.5
-
ns
Data Hold from Clock High
tDH
0.5
-
0.5
-
ns
Write Hold from Clock High (GW, BW, WEX)
tWH
0.5
-
0.5
-
ns
tADVH
0.5
-
0.5
-
ns
Chip Select Hold from Clock High
tCSH
0.5
-
0.5
-
ns
ZZ High to Power Down
tPDS
2
-
2
-
cycle
ZZ Low to Power Up
tPUS
2
-
2
-
cycle
Address Advance Hold from Clock High
Notes: 1. The above parameters are also guaranteed at industrial temperature range.
2. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP
is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times
whenever this device is chip selected.
3. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
4. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
- 11 -
Rev. 2.0 July 2006
- 12 -
Data Out
OE
ADV
CS
WRITE
ADDRESS
ADSC
ADSP
CLOCK
tCSS
tAS
tSS
A1
tADVS
tCSH
tWS
tAH
tSH
Q1-1
A2
tHZOE
tSH
Q2-1
tCD
tOH
Q2-2
A3
Q2-3
(ADV INSERTS WAIT STATE)
BURST CONTINUED WITH
NEW BASE ADDRESS
NOTES: WRITE = L means GW = L, or GW = H, BW = L, WEx = L
CS = L means CS1 = L, CS2 = H and CS2 = L
CS = H means CS1 = H, or CS1 = L and CS2 = H, or CS1 = L, and CS2 = L
tLZOE
tOE
tADVH
tWH
tSS
tCL
tCYC
tCH
TIMING WAVEFORM OF READ CYCLE
Q2-4
Q3-1
Q3-2
Q3-3
Undefined
Don′t Care
Q3-4
tHZC
K7A403600B
K7A403200B
K7A401800B
128Kx36/x32 & 256Kx18 Synchronous SRAM
Rev. 2.0 July 2006
- 13 -
Data Out
Data In
OE
ADV
CS
WRITE
ADDRESS
ADSC
ADSP
CLOCK
Q0-3
tCSS
tAS
tSS
Q0-4
A1
tHZOE
tCSH
tAH
tSH
D1-1
tCL
tCYC
tCH
A2
D2-1
D2-2
(ADV SUSPENDS BURST)
D2-2
D2-3
(ADSC EXTENDED BURST)
TIMING WAVEFORM OF WRTE CYCLE
D2-4
D3-1
A3
tDS
tADVS
tWS
tSS
D3-2
tDH
tADVH
tWH
tSH
D3-3
Undefined
Don′t Care
D3-4
K7A403600B
K7A403200B
K7A401800B
128Kx36/x32 & 256Kx18 Synchronous SRAM
Rev. 2.0 July 2006
- 14 -
Data Out
Data In
OE
ADV
CS
WRITE
ADDRESS
ADSP
CLOCK
tHZC
tSS
A1
tSH
tCD
tLZC
tAS
Q1-1
A2
tCL
tHZOE
tDS
tADVS
tWS
tAH
tCYC
tCH
D2-1
tDH
tADVH
tWH
A3
tLZOE
Q3-1
Q3-2
tOH
Q3-3
TIMING WAVEFORM OF COMBINATION READ/WRTE CYCLE(ADSP CONTROLLED, ADSC=HIGH)
Undefined
Don′t Care
Q3-4
K7A403600B
K7A403200B
K7A401800B
128Kx36/x32 & 256Kx18 Synchronous SRAM
Rev. 2.0 July 2006
- 15 -
Data In
Data Out
OE
ADV
CS
WRITE
ADDRESS
ADSC
CLOCK
tCSS
tSS
A1
tCSH
tSH
tOE
tLZOE
A2
Q1-1
A3
Q2-1
A4
Q3-1
Q4-1
tHZOE
D5-1
A5
tDS
tWS
D6-1
A6
tDH
tWH
D7-1
A7
tCL
tWS
tCYC
tCH
A8
tLZOE
tWH
A9
TIMING WAVEFORM OF SINGLE READ/WRITE CYCLE(ADSC CONTROLLED, ADSP=HIGH)
Q8-1
Undefined
Don′t Care
Q9-1
tOH
K7A403600B
K7A403200B
K7A401800B
128Kx36/x32 & 256Kx18 Synchronous SRAM
Rev. 2.0 July 2006
- 16 -
ZZ
Data Out
Data In
OE
ADV
CS
WRITE
ADDRESS
ADSC
ADSP
CLOCK
tCSS
tAS
tSS
A1
tCSH
tAH
tSH
tLZOE
tOE
Q1-1
ZZ Setup Cycle
tPDS
tHZC
Sleep State
ZZ Recovery Cycle
tPUS
tCL
tCYC
tCH
TIMING WAVEFORM OF POWER DOWN CYCLE
tWS
Normal Operation Mode
tHZOE
A2
D2-1
tWH
Undefined
Don′t Care
D2-2
K7A403600B
K7A403200B
K7A401800B
128Kx36/x32 & 256Kx18 Synchronous SRAM
Rev. 2.0 July 2006
K7A403600B
K7A403200B
K7A401800B
128Kx36/x32 & 256Kx18 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 128Kx36 Synchronous Pipelined Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 128K depth to 256K depth without extra logic.
I/O[0:71]
Data
Address
A[0:17]
A[17]
A[0:16]
A[17]
Address
CLK
Address
Data
CS2
CS2
ADSC
CLK
WEx
ADSC
WEx
(Bank 0)
OE
Cache
Controller
CLK
128Kx36
SPB
SRAM
CLK
Address
Data
CS2
CS2
64-Bits
Microprocessor
A[0:16]
128Kx36
SPB
SRAM
(Bank 1)
OE
CS1
CS1
ADV
ADV
ADSP
ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED, ADSC=HIGH)
Clock
tSS
tSH
ADSP
tAS
ADDRESS
[0:n]
tAH
A2
A1
tWS
tWH
WRITE
tCSS
tCSH
CS1
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
tADVS
tADVH
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
ADV
OE
Data Out
(Bank 0)
tLZOE
tOE
tHZC
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Data Out
(Bank 1)
Q2-1
*Notes: n = 14 32K depth
15 64K depth
16 128K depth
17 256K depth
Q2-2
Q2-3
Don′t Care
- 17 -
Q2-4
Undefined
Rev. 2.0 July 2006
K7A403600B
K7A403200B
K7A401800B
128Kx36/x32 & 256Kx18 Synchronous SRAM
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 256Kx18 Synchronous Pipelinde Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 256K depth to 512K depth without extra logic.
I/O[0:71]
Data
Address
A[18]
A[0:18]
A[0:17]
A[18]
Address
CLK
Microprocessor
CS2
CS2
CS2
WEx
ADSC
WEx
(Bank 0)
OE
Cache
Controller
CLK
256Kx18
SPB
SRAM
ADSC
CLK
Address
Data
CS2
CLK
Address
A[0:17]
OE
Data
256Kx18
SPB
SRAM
(Bank 1)
CS1
CS1
ADV
ADV
ADSP
ADSP
ADS
INTERLEAVE READ TIMING (Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED, ADSC=HIGH)
Clock
tSS
tSH
ADSP
tAS
ADDRESS
[0:n]
tAH
A2
A1
tWS
tWH
WRITE
tCSS
tCSH
CS1
Bank 0 is selected by CS2, and Bank 1 deselected by CS2
An+1
tADVS
tADVH
Bank 0 is deselected by CS2, and Bank 1 selected by CS2
ADV
OE
Data Out
(Bank 0)
tLZOE
tOE
tHZC
Q1-1
Q1-2
Q1-3
Q1-4
tCD
tLZC
Data Out
(Bank 1)
Q2-1
*Notes: n = 14 32K depth, 15 64K depth, 16 128K depth, 17 256K depth
- 18 -
Q2-2
Q2-3
Don′t Care
Q2-4
Undefined
Rev. 2.0 July 2006
K7A403600B
K7A403200B
K7A401800B
128Kx36/x32 & 256Kx18 Synchronous SRAM
PACKAGE DIMENSIONS
100-TQFP-1420A
Units ; millimeters/Inches
0~8°
22.00 ±0.30
0.10
0.127 +- 0.05
20.00 ±0.20
16.00 ±0.30
14.00 ±0.20
0.10 MAX
(0.83)
0.50 ±0.10
#1
0.65
(0.58)
0.30 ±0.10
0.10 MAX
1.40 ±0.10 1.60 MAX
0.50 ±0.10
- 19 -
0.05 MIN
Rev. 2.0 July 2006