CAT5140 Single Channel 256 Tap DPPt with Integrated EEPROM and I2C Control The CAT5140 is a single channel non-volatile 256−tap digitally programmable potentiometer (DPPt). This DPP is comprised of a series of equal value resistor elements connected between two externally accessible end points. The tap points between each resistive element can be selectively connected to the wiper output via internal CMOS switches forming a linear taper electronic potentiometer. The CAT5140 contains a volatile wiper register (WR) and an 8−bit non−volatile EEPROM for wiper position and 5 additional non−volatile registers for general purpose data storage. Programming of the registers is controlled via I2C interface. On power up, the wiper position is reset to the most recent value stored in the non−volatile memory register (IVR). The CAT5140 is available in an Pb free, RoHS compliant 8−lead MSOP package, and operates over the industrial temperature range of −40°C to +85°C. http://onsemi.com MSOP−8 3x3 Z SUFFIX CASE 846AD MARKING DIAGRAM Features • • • • • • • • • • • • ABTV YMX 400 kHz I2C Compatible Interface 256 Position Linear Taper Potentiometer End−to−End Resistance = 50 kW / 100 kW TCR = 100 ppm/°C (typical) Standby Current = 2 mA (max) Typical Wiper Resistance = 70 W @ 3.3 V Operating Voltage = 2.5 V to 5.5 V 6 Registers 8−bit Non−volatile EEPROM 2,000,000 Data Write Stores 100 Year Data Retention 8−Lead MSOP Package Pb−free RoHS Compliant: NiPdAu Plating Volatile SCL SDA I2C and CONTROL WP GND ACR WIPER 1 Non−Volatile 1 ABTV = 100 kW Resistance ABTJ = 50 kW Resistance Y = Production Year Y = (Last Digit) M = Production Month M = (1 − 9, A, B, C) X = Production Revision PIN CONNECTIONS WP 1 VCC SCL RH VCC SDA RL RH GND RW (Top View) IVR GP GP GP ABTJ YMX RL ORDERING INFORMATION RW See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Figure 1. Functional Block Diagram © Semiconductor Components Industries, LLC, 2009 May, 2009 − Rev. 0 1 Publication Order Number: CAT5140/D CAT5140 Table 1. ORDERING INFORMATION Part Number Resistance CAT5140ZI−50−GT3 50 kW CAT5140ZI−00−GT3 100 kW Temperature Range Package Shipping† −40°C to 85°C MSOP−8 3x3 (Pb−Free) 3000/Tape & Reel 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Table 2. PIN FUNCTION DESCRIPTION Pin No. Pin Name Description 1 WP Memory Write Protect: Active Low 2 SCL Serial Clock 3 SDA Serial Data 4 GND Ground 5 RW Wiper Terminal 6 RL Potentiometer Low Terminal 7 RH Potentiometer High Terminal 8 VCC Supply Voltage WP: Write Protect Input open drain output and can be wire-Ored with the other open drain or open collector I/Os. The WP pin when tied low prevents any write operations within the device. RH, RL: Resistor End Points SCL: Serial Clock The set of RH and RL pins is equivalent to the terminal connections on a mechanical potentiometer. The CAT5140 serial clock input pin is used to clock all data transfers into or out of the device. RW: Wiper SDA: Serial Data The RW pin is equivalent to the wiper terminal of a mechanical potentiometer and its position is controlled by the WR register. The CAT5140 bidirectional serial data pin is used to transfer data into and out of the device. The SDA pin is an Table 3. ABSOLUTE MAXIMUM RATINGS Parameter Rating Unit −0.5 to +7 V −0.5 to VCC + 0.5 V ±6.0 mA Storage Temperature Range −65 to +150 °C Junction Temperature Range −40 to +150 °C Lead Soldering Temperature (10 seconds) 300 °C ESD Rating HBM (Human Body Model) 2000 V ESD Rating MM (Machine Model) 200 V VIN Supply Voltage VCC to Ground (Note 1) Terminal voltages: RH, RL, RW , SDA, SCL, WP Wiper Current Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5 V, which may overshoot to VCC +2.0 V for periods of less than 20 ns. Table 4. RECOMMENDED OPERATING CONDITIONS Parameter VCC Wiper Current Temperature Range http://onsemi.com 2 Rating Unit 2.5 to 5.5 V ±3 mA −40 to +85 _C CAT5140 Table 5. POTENTIOMETER CHARACTERISTICS (Note 2) (VCC = +2.5 V to +5.5 V, −40_C to +85_C unless otherwise specified.) Limits Parameter Test Conditions Symbol Min Typ Max Units Potentiometer Resistance ‘−50’ RPOT 50 kW Potentiometer Resistance ‘−00’ RPOT 100 kW Potentiometer Resistance Tolerance Power Rating 25°C Wiper Current IW Wiper Resistance Integral Non−Linearity Integral Non−Linearity mW ±3 mA 200 W RW Voltage Divider Mode INL ±1 LSB (Note 3) DNL ±0.5 LSB (Note 3) RINL ±1 LSB (Note 3) RDNL ±0.5 LSB (Note 3) VCC V Resistor Mode Differential Non−Linearity Voltage on RH or RL % 50 IW = ±3 mA VCC = 3.3 V Differential Non−Linearity VSS = 0 V VTERM 70 ±20 VSS Resolution 0.4 % Zero Scale Error 0 0.5 2 LSB (Note 4) Full Scale Error −2 −0.5 0 LSB (Note 4) Temperature Coefficient of RPOT (Notes 5, 6) TCRPOT Ratiometric Temp. Coefficient (Notes 5, 6) TCRATIO Potentiometer Capacitances (Notes 5, 6) CH/CL/CW 10/10/25 pF RPOT = 50 kW (Note 7) fc 0.4 MHz Frequency Response ppm/°C ±100 20 ppm/°C 2. 3. 4. 5. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VCC +1 V. LSB = RTOT / 255 or (RH − RL) / 255, single pot. V(RW)255−V(RW)0]/255 (RW)255 = 0xFF, (RW)0 = 0x00. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 6. Relative linearity is a measure of the error in step size. It is determined by the actual change in voltage between two successive tap positions when used as a potentiometer. 7. This parameter is tested initially and after a design or process change that affects the parameter. Table 6. D.C. OPERATING CHARACTERISTICS (VCC = +2.5 V to +5.5 V, −40°C to +85°C unless otherwise specified.) Test Conditions Symbol Power Supply Current Volatile Write & Read fSCL = 400 kHz VCC = 5.5 V, Inputs = GND Power Supply Current Non−volatile Write Parameter Standby Current Input Leakage Current Output Leakage Current Max Units ICC1 1 mA fSCL = 400 kHz VCC = 5.5 V, Inputs = GND ICC2 3 mA VCC = 5.0 V ISB VIN = GND to VCC ILI VOUT = GND to VCC ILO Min −10 2 mA +10 mA 10 mA Input Low Voltage VIL −1 VCC x 0.3 V Input High Voltage VIH VCC x 0.7 VCC + 1.0 V 0.4 V 2.0 V SDA Output Buffer Low Voltage Power−On Recall VCC = 2.5 V, IOL = 4 mA VOL1 Minimum VCC for memory recall VPOR http://onsemi.com 3 1.4 CAT5140 Table 7. CAPACITANCE (TA = 25°C, f = 1.0 MHz, VCC = 5 V) Test Conditions Symbol Max Units Input/Output Capacitance (SDA) VI/O = 0 V CI/O (Note 8) 8 pF Input Capacitance (SCL, WP) VIN = 0 V CIN (Note 8) 6 pF Test Table 8. POWER UP TIMING (Notes 8 and 9) Symbol Max Units Power−up to Read Operation tPUR 1 ms Power−up to Write Operation tPUW 1 ms Parameter 8. This parameter is tested initially and after a design or process change that affects the parameter. 9. tPUR and tPUW are delays required from the time VCC is stable until the specified operation can be initiated. Table 9. DPP TIMING Parameter Symbol Wiper Response Time After Power Supply Stable Wiper Response Time: SCL falling edge after last bit of wiper position data byte to wiper change Max Units tWRPO Min 50 ms tWR 20 ms Max Units Table 10. ENDURANCE Parameter Reference Test Method Symbol Min Endurance MIL−STD−883, Test Method 1033 NEND 2,000,000 Cycles Data Retention MIL−STD−883, Test Method 1008 TDR 100 Years Table 11. A.C. CHARACTERISTICS (VCC = +2.5 V to +5.5 V, −40_C to +85_C unless otherwise specified.) Symbol Parameter Min Typ Max Units 400 kHz Clock Frequency fSCL Clock High Period tHIGH 600 ns Clock Low Period tLOW 1300 ns Start Condition Setup Time (for a Repeated Start Condition) tSU:STA 600 ns Start Condition Hold Time tHD:STA 600 ns Data in Setup Time tSU:DAT 100 ns Data in Hold Time tHD:DAT 0 ns Stop Condition Setup Time tSU:STO 600 ns tBUF 1300 ns WP Setup Time tSU:WP 0 ms WP Hold Time tHD:WP 2.5 ms Time the bus must be free before a new transmission can start SDA and SCL Rise Time tR 300 ns SDA and SCL Fall Time tF 300 ns Data Out Hold Time tDH 100 ns Noise Suppression Time Constant at SCL, SDA Inputs TI 50 ns SLC Low to SDA Data Out and ACK Out tAA 1 ms Non−Volatile Write Cycle Time tWR 10 ms http://onsemi.com 4 4 CAT5140 SCL SDA Start Condition Stop Condition Figure 2. Start and STOP Timing tHIGH tF tR tLOW SCL tSU:STA tHD:DAT tHD:STA tSU:DAT tSU:STO SDA IN tBUF tAA tDH SDA OUT Figure 3. Bus Timing Bus Release Delay (Receiver) Bus Release Delay (Transmitter) SCL from Master 1 8 9 Data Output from Transmitter Data Output from Receiver ACK Setup (≥ tSU:DAT) Start ACK Delay (≤ tAA) Figure 4. Acknowledge Timing Start Stop SCL tHD:STO, tHD:STO:NV CLK1 SDA IN tHD:WP tSU:WP WP Figure 5. WP Timing http://onsemi.com 5 CAT5140 Device Operation START Condition The CAT5140 is a resistor array integrated with a I2C serial interface logic, an 8−bit volatile wiper register, and six 8−bit, non−volatile memory data registers. The resistor array contains 255 separate resistive elements connected in series. The physical ends of the array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL). The tap positions between and at the ends of the series resistors are connected to the output wiper terminal (RW) by CMOS transistor switches. Only one tap point for the potentiometer is connected to the wiper terminal at a time and is determined by the value of an 8−bit Wiper Register (WR). The START condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT5140 monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. Device Addressing The bus Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. CAT5140 has a fixed 7 bit slave address: 0101000. The 8th bit (LSB) is the Read/Write instruction bit. For a Read the value is “1” and for Write the value is “0”. After the Master sends a START condition and the slave address byte, the CAT5140 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. RH FFh FEh 80h RW Table 12. SALVE ADDRESS BIT FORMAT MSB 01h 0 00h LSB 1 0 1 0 0 0 R/W Acknowledge (ACK) RL After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. CAT5140 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8−bit byte. When the CAT5140 is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT5140 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. When power is first applied to CAT5140 the wiper is set to midscale; Wiper Register = 80h. When the power supply becomes sufficient to read the non−volatile memory the value stored in the Initial Value Register (IVR) is transferred into the Wiper Register and the wiper moves to this new position. Five additional 8−bit non−volatile memory data registers are provided for general purpose data storage. Data can be read or written to the volatile or the non−volatile memory data registers via the I2C bus. Serial Bus Protocol The following defines the features of the 2−wire bus protocol: 1. Data transfer may be initiated only when the bus is not busy. 2. During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock is high will be interpreted as a START or STOP condition. The device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the CAT5140 will be considered a slave device in all applications. WRITE Operation In the Write mode, the Master device sends the START condition and the slave address information to the Slave device. In CAT5140’s case the slave address also contains a Read/Write command (R/W) on the last bit of the 1st byte. After receiving an acknowledge from the Slave, the Master device transmits a second byte containing a Memory Address to select an available register. After a second acknowledge is received from the Slave, the Master device sends the data to be written into the selected register. The CAT5140 acknowledges once more and the Master http://onsemi.com 6 CAT5140 READ Operation generates the STOP condition, at which time if a nonvolatile data register is being selected, the device begins an internal programming cycle to non−volatile memory. If the STOP condition is not sent immediately after the last ACK the internal non−volatile programming cycle doesn’t start. While this internal cycle is in progress, the device will not respond to any request from the Master device. Write operations to volatile memory are completed during the last bit of the data byte before the slave’s acknowledge. The device will be ready for another command only after a STOP condition sent by Master. A Read operation with a designated address consists of a three byte instruction followed by one or more Data Bytes (See Figure 3). The master initiates the operation issuing a START, an Identification byte with the R/W bit set to “0”, an Address Byte. Then the master sends a second START, and a second Identification byte with the R/W bit set to “1”. After each of the three bytes, the CAT5140 responds with an ACK. Then CAT5140 transmits the Data Byte. The master then can continue the read operation with the content of the next register by sending acknowledge or can terminate the read operation by issuing a NoACK followed by a STOP condition after the last bit of a Data Byte. Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation, the CAT5140 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address. If the CAT5140 is still busy with the write operation, no ACK will be returned. If the CAT5140 has completed the write operation, an acknowledge will be returned and the host can then proceed with the next instruction operation. Table 13. MEMORY MAP Non−volatile Default Value Register Address 8 ACR 7 WRITE Protection The Write Protection feature allows the user to protect against inadvertent programming of the non−volatile data registers. If the WP pin is tied to LOW, the data registers are protected and become read only. Similarly, the WP pin going low after start will interrupt a nonvolatile write to data registers, while the WP pin going low after an internal write cycle has started will have no effect on any write operation. CAT5140 will accept slave addresses but the data registers are protected from programming, which the device indicates by failing to send an acknowledge after data is received. Volatile Register Reserved 6 General Purpose 00h N/A 5 General Purpose 00h N/A 4 General Purpose 00h N/A 3 General Purpose 00h N/A 2 General Purpose 00h N/A 1 Device ID (read only) D0h N/A 0 IVR 80h WR If the master sends address 07h or addresses greater than 08h the slave responds with NoACK after the Memory Address byte. Address 8: Volatile Access Control Register − ACR (I/O) The ACR bit 7 (VOL) toggles between Non−volatile and volatile registers accessed at address 00h. When VOL is Low (0), the non−volatile IVR is accessed at address 00h. When VOL is high (1), the volatile Wiper Register is accessed at address 00h. The initial default value for VOL = 0. Bit 7 6 5 4 3 2 1 0 Name 0/1 VOL 0 0 0 0 0 0 0 00h and 80h are the only values that should be written to address 08h. For any other value written to address 08h the slave will load only bit 7 but it will answer with a NoACK. Address 7: RESERVED The user should not read or write to this address. CAT5140 will respond with NoACK and it will take no action. Address 07h can be accessed only in a sequential read and its content is FFh. Address 6−2: Non−Volatile General Purpose Memory (I/O) 8−bit Non−volatile Memory Bit 7 6 5 4 3 2 1 0 Name − − − − − − − − General Purpose Memories are preprogrammed at the factory to a default value of “00h”. http://onsemi.com 7 CAT5140 Address 1: Device ID (Read Only) Bit 7 defines the DPP device manufacturer; Catalyst/On Semiconductor = high (1) Bit 7 6 5 4 3 2 1 0 Name 1 1 0 1 0 0 0 0 A writing to address 1 has no effect. Attempts to do so will return an ACK but no data will be written. Address 0: IVR/WR Register (I/O) Address 00h accesses one of two memory registers: the initial value register (IVR) or the wiper register (WR) depending upon the value of bit 7 in Access Control Register (ACR) which is at address 08h, above. WR controls the wiper’s position and is a volatile memory while IVR is non−volatile and retains its data after the chip has been powered down. Writes to IVR automatically update the WR while writes to WR leave IVR unaffected. WR: Wiper Register = Volatile. IVR: Initial Value Register = Non−volatile. Writing and Reading operations: 1. If Bit 7 from ACR is 0 (non−volatile): ♦ A write operation to address 00h will write the same value in WR and IVR. ♦ A read operation to address 00h will output the content of IVR. 2. If bit 7 from ACR is 1 (volatile): ♦ A write operation to address 00h will write in WR only. ♦ A read operation to address 00h will output the content of WR. All changes to the wiper’s position are immediate. There is no delay the wiper’s movement when writing to non−volatile memory. Bit 7 6 5 4 3 2 1 0 Name − − − − − − − − IVR is preprogrammed at the factory to a default value of “80h”. I2C SERIAL BUS INSTRUCTION FORMAT Table 14. I2C SLAVE ADDRESS BITS Slave Address R/W bit Transfer Data bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read 51h 0 1 0 1 0 0 0 1 (R) Write 50h 0 (W) If the Slave Address Byte sent by the host is different the device will send a NoACK. I2C Protocol: (A) Write data procedure with designated address. (See Table 15) 1. Host transfers the start condition 2. Host transfers the device slave address with the write mode R/W bit (0). 3. Device sends ACK 4. Host transfers the corresponding memory address to the device 5. Device sends ACK 6. Host transfers the write data to the designated address 7. Device sends ACK 8. Routines (6) and (7) are repeated based on the transfer data, and the designated address is automatically incremented* 9. Host transfers the stop condition. *Automatically incremented writes are not possible after a non−volatile write. http://onsemi.com 8 CAT5140 Single write to either a volatile or non−volatile register. Note that Bit 7 of ACR determines which memory type is being written. Table 15. SINGLE WRITE (1) (2) Start Slave Address 0 R/W (3) (4) (5) (6) (7) (9) 0 ACK Memory Address 0 ACK Write Data 0 ACK Stop A single write to either a volatile or non−volatile register. At address 00h bit 7 of ACR determines which memory type is being written. Table 16. MULTIPLE WRITES (1) (2) Start Slave Address 0 R/W (3) (4) (5) (6) (7) 0 ACK Memory Address 0 ACK Write Data 0 ACK (8) (9) Write Data 0 ACK Stop Multiple writes are possible only if the starting address is 08h and it should be stopped with the first nonvolatile data byte. If a nonvolatile write does not end with a STOP procedure the register is not written. (B) Read data procedure with designated address. 1. Host transfers the start condition 2. Host transfers the device slave address with the write mode R/W bit (0) 3. ACK signal recognition from the device 4. Host transfers the read address 5. ACK signal recognition from the device 6. Host transfers the re−start condition 7. Host transfers the slave address with the read mode R/W bit (1). 8. ACK signal recognition from the device 9. The device transfers the read data from the designated address 10. Host transfers ACK signal 11. The (9) & (10) routines above are repeated if needed, and the read address is auto−incremented 12. Host transfers ACK ‘H’ to the device 13. Host transfers the stop condition Table 17. READ DATA (1) (2) Start Slave Address 0 R/W (3) (4) (5) (6) (7) 0 ACK Memory Address 0 ACK Restart Slave Address 1 R/W (8) (9) (10) (11) (12) (13) 0 ACK Read Data 0 ACK Read Data 1 ACK Stop (C) Read data procedure without a designated address. 1. Host transfers the start condition 2. Host transfers the device slave address with the read mode R/W bit =1 3. ACK signal recognition from the device. (Host then changes to receiver) 4. The device transfers data from the previous access address +1 5. Host transfers ACK signal 6. The (4) & (5) routines above are repeated if needed 7. Host transfers ACK ‘H’ 8. Host transfers the stop condition Table 18. Read Data w/o Designated Address (1) Start (2) Slave Address 1 R/W (3) (4) (5) (6) (7) (8) 0 ACK Read Data 0 ACK Read Data 1 ACK Stop http://onsemi.com 9 CAT5140 PACKAGE DIMENSIONS MSOP 8, 3x3 CASE 846AD−01 ISSUE O SYMBOL MIN NOM MAX 1.10 A E A1 0.05 0.10 0.15 A2 0.75 0.85 0.95 b 0.22 0.38 0.23 c 0.13 D 2.90 3.00 3.10 E 4.80 4.90 5.00 E1 2.90 3.00 3.10 E1 0.65 BSC e L 0.60 0.40 L1 0.25 BSC L2 θ 0.80 0.95 REF 0º 6º TOP VIEW D A A2 A1 DETAIL A e b c SIDE VIEW END VIEW q L2 Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-187. L L1 DETAIL A http://onsemi.com 10 CAT5140 DPP is a trademark of Semiconductor Components Industries, LLC (SCILLC) ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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