TI1 LM9820 10/12-bit image sensor processor analog front end Datasheet

LM9810,LM9820
LM9810/LM9820 10/12-Bit Image Sensor Processor Analog Front End
Literature Number: SNOS420A
LM9810/LM9820
10/12-Bit Image Sensor Processor Analog Front End
General Description
Features
The LM9810 and LM9820 are high performance Analog
Front Ends (AFEs) for image sensor processing systems.
The LM9810/20 performs all the analog and mixed signal
functions (correlated double sampling, color specific gain
and offset correction, and analog to digital conversion) necessary to digitize the output of a wide variety of CIS and CCD
sensors. The LM9810 has a 10-bit 6 MHz ADC, and the
LM9820 has a 12-bit 6 MHz ADC. The LM9810 and LM9820
are pin-for-pin and functionally compatible.
n 6 million pixels/s conversion rate
n Digitally programmed gain and offset for red, green and
blue pixels
n Correlated Double Sampling for lowest noise
n TTL/CMOS input/output compatible
Key Specifications
n
n
n
n
Output Data Resolution
Pixel Conversion Rate
Supply Voltage
Power Dissipation
10/12 Bits
6 MHz
5V ± 5%
300 mW
Applications
n
n
n
n
n
Color Flatbed Document Scanners
Color Sheetfed Scanners
Multifunction Imaging Products
Digital Copiers
General Purpose Linear CCD Imaging
Connection Diagram
DS100943-69
Ordering Information
Commercial (0˚C ≤ TA ≤ +70˚C)
Package
LM9810CCWM
20-Pin Wide SOIC
LM9810CCWMX
20-Pin Wide SOIC, Tape and Reel
LM9820CCWM
20-Pin Wide SOIC
LM9820CCWMX
20-Pin Wide SOIC, Tape and Reel
© 2000 National Semiconductor Corporation
DS100943
www.national.com
LM9810/20 10/12-Bit Image Sensor Processor Analog Front End
October 2000
DS100943-70
LM9810/20
Block Diagram
www.national.com
2
Operating Ratings (Notes 1, 2)
Positive Supply Voltage (V+ = VA = VD)
with Respect to
GND = AGND = DGND
Voltage on any Input or Output Pin
Input Current at any Pin (Note 3)
Package Input Current (Note 3)
Package Dissipation at TA = 25˚C
ESD Susceptibility (Note 5)
Human Body Model
Soldering Information (Note 6)
Infrared, 10 seconds
Storage Temperature
Operating Temperature
Range
TMIN = 0˚C ≤ TA ≤ TMAX +70˚C
+4.75V to +5.25V
VA Supply Voltage
+4.75V to +5.25V
VD Supply Voltage
≤ 100 mV
|VA–VD|
OSR, OSG, OSB
Input Voltage Range
−0.05V to VA + 0.05V
NewLine, SampCLK, D0-D2, MCLK
Input Voltage Range
−0.05V to VD + 0.05V
6.5V
0.3V to V+ +0.3V
± 25 mA
± 50 mA
(Note 4)
2000V
300˚C
−65˚C to +150˚C
Electrical Characteristics
The following specifications apply for AGND = DGND = 0V, VA = VD = +5.0VDC, fMCLK = 24 MHz, RS = 25Ω. Boldface limits
apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. (Notes 7, 8, 12)
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 9)
(Note 10)
(Limits)
CCD/CIS SOURCE REQUIREMENTS FOR FULL SPECIFIED ACCURACY AND DYNAMIC RANGE (Note 12)
VOS PEAK
Sensor’s Maximum Peak Differential
Gain = 0.933
2.1
V
Signal Range
Gain = 3.0
0.65
V
Gain = 9.0
0.21
V
ANALOG INPUT CHARACTERISTICS
OSR, OSG, OSB Input Capacitance
5
OSR, OSG, OSB Input Leakage
Measured with OS = 3.5 VDC
Current
CDS disabled, selected OS Input
CDS disabled, unselected OS Input
20
pF
25
10
µA (max)
nA
COARSE COLOR BALANCE PGA CHARACTERISTICS
Monotonicity
5
bits (min)
G0 (Minimum PGA Gain)
PGA Setting = 0
0.93
.90
V/V (min)
.96
V/V (max)
G31 (Maximum PGA Gain)
PGA Setting = 31
3.0
2.96
V/V (min)
3.15
V/V (max)
x3 Boost Gain
x3 Boost Setting On
3.0
(bit B5 of Gain Register is set)
± 0.4
Gain Error at any Gain (Note 13)
2.93
V/V (min)
3.05
V/V (max)
1.67
% (max)
INTERNAL REFERENCE CHARACTERISTICS
VREFMID
Mid Supply Output Voltage
VREF+
Positive Reference Output Voltage
3.5
V
VREF
Negative Reference Output Voltage
1.5
V
∆VREF
Differential Reference Voltage
2.0
V
2.5
V
VREF+ - VREF-
LM9810 Electrical Characteristics
The following specifications apply for AGND = DGND = 0V, VA = VD = +5.0VDC, fMCLK = 24 MHz, RS = 25Ω. Boldface limits
apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. All LSB limits are in units of the LM9810’s 10-bit ADC.
(Notes 7, 8, 12)
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 9)
(Note 10)
(Limits)
10
bits (min)
± 0.35
± 1.5
LSB (max)
ADC CHARACTERISTICS
Resolution with No Missing Codes
INL
Integral Non-Linearity Error (Note 11)
3
www.national.com
LM9810/20
Absolute Maximum Ratings (Notes 1, 2)
LM9810/20
LM9810 Electrical Characteristics
(Continued)
The following specifications apply for AGND = DGND = 0V, VA = VD = +5.0VDC, fMCLK = 24 MHz, RS = 25Ω. Boldface limits
apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. All LSB limits are in units of the LM9810’s 10-bit ADC.
(Notes 7, 8, 12)
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 9)
(Note 10)
(Limits)
± 0.25
± 1.0
LSB (max)
ADC CHARACTERISTICS
DNL
Differential Non-Linearity
FULL CHANNEL LINEARITY (Note 14)
INL
Integral Non-Linearity Error (Note 11)
DNL
Differential Non-Linearity
± 0.9
± 0.40
LSB
LSB
STATIC OFFSET DAC CHARACTERISTICS
Monotonicity
Offset DAC LSB Size
PGA Gain = 1
Offset DAC Adjustment Range
PGA Gain = 1
5
6
bits (min)
3.4
LSB (min)
6.4
LSB(max)
± 150
± 140
LSB (min)
502
468
LSB (min)
532
LSB (max)
-7.2
LSB (min)
+15.7
LSB (max)
SYSTEM CHARACTERISTICS (SEE SECTION 1.7.1, INTERNAL OFFSETS)
C
VOS1
Analog Channel Gain Constant
Includes Voltage Reference
(ADC Codes/V)
Variation, Gain Setting = 1
Pre-Boost Analog Channel Offset Error,
4.4
CCD Mode
VOS1
Pre-Boost Analog Channel Offset Error,
4.5
CIS Mode
VOS2
VOS3
Pre-PGA Analog Channel Offset Error
-10
Post-PGA Analog Channel Offset Error
-11
-6.5
LSB (min)
+15.2
LSB (max)
-28
LSB (min)
+5.3
LSB (max)
-30.6
LSB (min)
+7.3
LSB (max)
LM9820 Electrical Characteristics
The following specifications apply for AGND = DGND = 0V, VA = VD = +5.0VDC, fMCLK = 24 MHz, RS = 25Ω. Boldface limits
apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. All LSB limits are in units of the LM9810’s 12-bit ADC.
(Notes 7, 8, 12)
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 9)
(Note 10)
(Limits)
12
bits (min)
± 1.1
± 0.6
± 4.0
LSB (max)
+1.75
LSB (max)
ADC CHARACTERISTICS
Resolution with No Missing Codes
INL
Integral Non-Linearity Error (Note 11)
DNL
Differential Non-Linearity
-1.0
FULL CHANNEL LINEARITY (Note 14)
INL
Integral Non-Linearity Error (Note 11)
DNL
Differential Non-Linearity
± 3.4
± 0.65
LSB
LSB
STATIC OFFSET DAC CHARACTERISTICS
Monotonicity
Offset DAC LSB Size
Offset DAC Adjustment Range
PGA Gain = 1
PGA Gain = 1
20
6
bits (min)
14
LSB (min)
26
LSB(max)
± 590
± 575
LSB (min)
2008
1873
LSB (min)
2129
LSB (max)
-32.1
LSB (min)
+68.9
LSB (max)
SYSTEM CHARACTERISTICS (SEE SECTION 1.7.1, INTERNAL OFFSETS)
C
VOS1
Analog Channel Gain Constant
Includes Voltage Reference
(ADC Codes/V)
Variation, Gain Setting = 1
Pre-Boost Analog Channel Offset Error,
17.6
CCD Mode
www.national.com
4
(Continued)
The following specifications apply for AGND = DGND = 0V, VA = VD = +5.0VDC, fMCLK = 24 MHz, RS = 25Ω. Boldface limits
apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. All LSB limits are in units of the LM9810’s 12-bit ADC.
(Notes 7, 8, 12)
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 9)
(Note 10)
(Limits)
18
-22.2
LSB (min)
+57
LSB (max)
-94.3
LSB (min)
+16.4
LSB (max)
SYSTEM CHARACTERISTICS (SEE SECTION 1.7.1, INTERNAL OFFSETS)
VOS1
Pre-Boost Analog Channel Offset Error,
CIS Mode
VOS2
Pre-PGA Analog Channel Offset Error
-40
VOS3
Post-PGA Analog Channel Offset Error
-44
-121
LSB (min)
+28
LSB (max)
DC and Logic Electrical Characteristics
The following specifications apply for AGND = DGND = 0V, VA = VD = +5.0VDC, fMCLK = 24 MHz, Rs = 25Ω. Boldface limits
apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. (Notes 7, 8)
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 9)
(Note 10)
(Limits)
V (max)
D0–D2, MCLK, NewLine, SampCLK DIGITAL INPUT CHARACTERISTICS
VIN(1)
Logical “1” Input Voltage
VD = 5.25V
2.0
VIN(0)
Logical “0” Input Voltage
VD = 4.75V
0.8
IIN
Input Leakage Current
VIN = VD
0.1
µA (max)
VIN = DGND
−0.1
µA (max)
CIN
Input Capacitance
5
pF
V (min)
D0–D5, DIGITAL OUTPUT CHARACTERISTICS
VOUT(1)
Logical “1” Output Voltage
VD = 4.75V, IOUT = −360 µA
2.4
VD = 4.75V, IOUT = −10 µA
4.4
V (min)
V (min)
0.4
V (max)
VOUT(0)
Logical “0” Output Voltage
VD = 5.25V, IOUT = 1.6 mA
IOUT
TRI-STATE ® Output Current
VOUT = DGND
0.1
µA
(D0–D5 only)
VOUT = VD
−0.1
µA
Operating
45
57
mA (max)
Standby with Input Clocks Stopped
0.8
0.9
mA (max)
Standby with Input Clocks Running
3.0
Operating
220
320
µA (max)
Standby with Input Clocks Stopped
110
200
µA (max)
Standby with Input Clocks Running
220
POWER SUPPLY CHARACTERISTICS
IA
Analog Supply Current
ID
Digital Supply Current (Note 15)
mA
µA
AC Electrical Characteristics
The following specifications apply for AGND = DGND = 0V, VA = VD = +5.0VDC, fMCLK = 24 MHz, tMCLK = 1/fMCLK,
tr = tf = 5 ns, Rs = 25Ω. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. (Notes 7, 8)
Symbol
fMCLK
Parameter
Conditions
Typical
Limits
Units
(Note 9)
(Note 10)
(Limits)
Maximum MCLK Frequency
24
MHz (min)
MCLK Duty Cycle
40
60
41
(min)
(max)
tMCLK
MCLK Period
tSCNL
SampCLK Falling Edge before NewLine
Falling Edge
3
tMCLK (min)
tSampCLK
SampCLK Period
4
tMCLK (min)
tSampLo
Low Time for SampCLK
50
5
ns (min)
ns (min)
www.national.com
LM9810/20
LM9820 Electrical Characteristics
LM9810/20
AC Electrical Characteristics
(Continued)
The following specifications apply for AGND = DGND = 0V, VA = VD = +5.0VDC, fMCLK = 24 MHz, tMCLK = 1/fMCLK,
tr = tf = 5 ns, Rs = 25Ω. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. (Notes 7, 8)
Symbol
Parameter
tSampHi
High Time for SampCLK
tSampSU
SampCLK Falling Edge before Rising
Edge of MCLK
tDDO
Conditions
Typical
Limits
Units
(Note 9)
(Note 10)
(Limits)
50
ns (min)
4
ns (min)
Falling Edge of MCLK before New Valid
Data
40
ns (max)
tHDO
Hold Time of Current Data from Falling
edge of MCLK
15
ns (min)
fSCLK
D2(SCLK) Serial Clock Period
tDSU
Input Data Setup Time before
D2(SCLK) Rising Edge
0
ns (min)
tDH
Input Data Hold Time after
D2(SCLK) Rising Edge
3
ns (min)
tSCLKLA
D2(SCLK) Rising Edge after Bit B0
before D1(Latch) Rising Edge
3
ns (min)
tLASCLK
D1(Latch) Rising Edge before next
D2(SCLK) Rising Edge
3
ns (min)
tLA
High Time for D1(Latch)
3
tMCLK (min)
tLANL
D1(Latch) Rising Edge before
3
tSampCLK
1
NewLine Falling Edge
tMCLK (min)
(min)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN VA or VD), the current at that pin should be limited to 25 mA. The
50 mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25 mA to
two.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD = (TJmax–TA)/θJA. TJmax = 150˚C for this device. The typical thermal resistance (θJA) of this part when board
mounted is 84˚C/W for the M20 SOIC package.
Note 5: Human body model, 100 pF capacitor discharged through a 1.5 kΩ resistor.
Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any National Semiconductor
Linear Data Book for other methods of soldering surface mount devices.
Note 7: Two diodes clamp the OS analog inputs to AGND and VA as shown below. This input protection, in combination with the external clamp capacitor and the
output impedance of the sensor, prevents damage to the LM9810/20 from transients during power-up.
DS100943-71
Note 8: To guarantee accuracy, it is required that VA and VD be connected together to the same power supply with separate bypass capacitors at each supply pin.
Note 9: Typicals are at TJ = TA = 25˚C, fMCLK = 24 MHz, and represent most likely parametric norm.
Note 10: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 11: Integral non-linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual transfer function
of the ADC.
Note 12: VREF is defined as the CCD OS voltage for the reference period following the reset feedthrough pulse. VWHITE is defined as the peak CCD pixel output
voltage for a white (full scale) image with respect to the reference level, VREF. VRFT is defined as the peak positive deviation above VREF of the reset feedthrough
pulse. The maximum correctable range of pixel-to-pixel VWHITE variation is defined as the maximum variation in VWHITE (due to PRNU, light source intensity
variation, optics, etc.) that the LM9810/20 can correct for using its internal PGA.
www.national.com
6
LM9810/20
AC Electrical Characteristics
(Continued)
DS100943-72
Note 13: PGA Gain Error is the maximum difference between the measured gain for any PGA code and the ideal gain calculated by using the formula
.
Note 14: Full Channel INL and DNL are tested with CDS disabled, negative signal polarity, and a single OS input with a gain register setting of 1 (000001b) and
an offset register setting of 0 (000000b).
Note 15: The digital supply current (ID) does not include the load, data and switching frequency dependent current required to drive the digital output bus on pins
(D5-D0). The current required to switch the digital data bus can be calculated from: ISW = 2 x Nd x Psw x CL x VD/tSampCLK where Nd is total number of data pins,
Psw is the probability of each data bit switching, CL is the capacitive loading on each data pin, VD is the digital supply voltage and tSampCLK is the period of the
SampCLK signal. Since Nd is 6, Psw should be .5 and VD is nominally 5V, the switching current can usually be calculated from: ISW = 30 x CL/tSampCLK. For example,
if the capacitive load on each digital output pin (D5-D0) is 20 pF and the period of tSampCLK is 1/6 MHz or 167 ns, then the digital switching current would be 7.2
mA. The calculated digital switching current will be drawn through the VD pin and should be considered as part of the total power budget for the LM9810/20.
7
www.national.com
LM9810/20
Pin Descriptions
Analog Power
VA
This is the positive supply pin for the
analog supply. It should be connected
to a voltage source of +5V and
bypassed to the AGND with a 0.1 µF
monolithic capacitor in parallel with a
10 µF tantalum capacitor.
AGND
This is the ground return for the analog
supply.
Analog I/O
OSR, OSG,
OSB
Analog Inputs. These inputs (for Red,
Green, and Blue) should be tied to the
sensor’s OS (Output Signal) through DC
blocking capacitors.
RefBypass
Internally generated reference voltage
bypass pin. It should be bypassed to
AGND through a .05 µF monolithic
capacitor.
VREF,
VREFMID,
VREF−
Voltage reference bypass pins. They
should each be bypassed to AGND
through a .05 µF monolithic capacitor.
Input & Timing Control
MCLK
Master Clock. The ADC conversion rate
will be a maximum of 1⁄4 of MCLK.
Nominally 24 MHz.
SampCLK
Sample Clock. SampCLK controls the
conversion rate of the ADC (up to 1⁄4 of
the MCLK rate) and sample timing. The
signal level is sampled while SampCLK
is low and held on the rising edge of
SampCLK. When CDS is enabled, the
falling edge of SampCLK causes the
CCD reference level to be held. If CDS
is not enabled, VREF, or VREF− is held
on the falling edge of SampCLK,
depending on the programmed signal
polarity. SampCLK is also used with
NewLine to clamp the external coupling
capacitors.
www.national.com
8
LM9810/20
Pin Descriptions
(Continued)
NewLine
New Line signal. Used to indicate the
start of active pixels on a new line, to
allow clamping of the AC coupling caps
and to allow programming of the
configuration register. When NewLine is
high and SampCLK is low, the OS
inputs will be connected to either VREF,
or VREF−. On the first rising edge of
MCLK after NewLine goes low, the
internal mux and the offset and gain
settings will be set to the appropriate
values for the first color of the next line
set in the color mode setting in the
Sampler and Color Mode Register.
When NewLine is low, D transmit the
pixel conversion data from ADC. When
NewLine is high, D enter TRI-STATE
and D2, D1 and D0 act as a serial
interface for programming the
configuration registers.
VD
This is the positive supply pin for the
digital supply. It should be connected to
a voltage source of +5V and bypassed
to DGND with a 0.1 µF monolithic
capacitor.
DGND
This is ground return for the digital
supply.
Digital Power
Digital I/O
D5-D0
Data Input/Output pins. When NewLine
is low, the 10-bit or 12-bit conversion
results of the ADC are multiplexed to
D5-D0. When NewLine is high, the
output drivers enter TRI-STATE and D2,
D1 and D0 act as a serial interface for
writing to the configuration registers.
LM9810
Output
Mode
(NewLine
Low)
MCLK0, MCLK1, MCLK2, MCLK3
D5
b9,
b9,
b3,
b3
D4
b8,
b8,
b2,
b2
D3
b7,
b7,
b1,
b1
D2
b6,
b6,
b0,
b0
D1
b5,
b5,
0,
0
D0
b4,
b4,
0,
0
LM9820
Output
Mode
(NewLine
Low)
MCLK0, MCLK1, MCLK2, MCLK3
D5
b11,
b11,
b5,
b5
D4
b10,
b10,
b4,
b4
D3
b9,
b9,
b3,
b3
D2
b8,
b8,
b2,
b2
9
www.national.com
LM9810/20
Pin Descriptions
(Continued)
D1
b7,
b7,
b1,
b1
D0
b6,
b6,
b0,
b0
Input Mode
(NewLine
High)
D5-D3
Don’t Care
D2 (SCLK)
Serial Data Clock.
D1 (Latch)
Latch and Shift Enable Signal. When
D1(Latch) is low, data is shifted into
D0(SDI). When D1(Latch) goes high,
the last nine bits shifted into D0(SDI)
will be used to program the addressed
configuration register. To avoid
erroneous writes to the configuration
registers, D1(Latch) should be pulled
low when NewLine is high.
D0 (SDI)
Serial Input Data. Data is valid on
D2(SCLK) rising edge. Three address
bits followed by six data bits (MSB first)
should be shifted into D0 before
D1(Latch) goes high.
Timing Diagrams
DS100943-73
FIGURE 1. Pixel Conversion Timing and Latency
DS100943-74
FIGURE 2. SampCLK and Output Data Timing (NewLine Low)
www.national.com
10
LM9810/20
Timing Diagrams
(Continued)
DS100943-75
FIGURE 3. Timing for Programming the Configuration Registers
DS100943-76
FIGURE 4. CCD Clamping Timing
DS100943-77
FIGURE 5. CDS Timing
11
www.national.com
LM9810/20
Timing Diagrams
(Continued)
TABLE 1. Configuration Register Address Table
Address
(Decimal)
0
1
Address (Binary)
A2
A1
A0
0
0
0
0
2
0
3
Data Bits
0
0
1
1
1
0
1
4
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
B5
B4
B3
CDS
Polarity
B3
B2
B1
Mode1
Mode0
Sampler and Color Mode
N/A
Mode2
Red DAC Offset Setting
Polarity
MSB
LSB
Green DAC Offset Setting
Polarity
MSB
LSB
Blue DAC Offset Setting
Polarity
MSB
LSB
Red Gain Setting
x3
MSB
x3
MSB
LSB
Green Gain Setting
LSB
Blue Gain Setting
x3
MSB
Test
Test
LSB
Production Test and Power Down
Test
Test
Test
TABLE 2. Configuration Register Parameters
Parameter
Control Bits
(Address)
Result
Sampler and Color Mode (0)
B5
CDS Enable
0
CDS Enabled
(0)
1
Single Ended (CDS disabled)
B4
Signal Polarity
0
Negative Polarity
(0)
1
Positive Polarity
www.national.com
12
PD
LM9810/20
Timing Diagrams
(Continued)
TABLE 2. Configuration Register Parameters (Continued)
Parameter
Control Bits
(Address)
Result
Sampler and Color Mode (0)
B2
B1
B0
Line Rate Color - Mux, Gain & Offset change at the line rate:
*1st line: Mux = OSR, Gain & Offset = R
0
0
0
2nd line: Mux = OSG, Gain & Offset = G
3rd line: Mux = OSB, Gain & Offset = B
repeat...
*state of the first line after a write to this register
0
0
1
Single Input Color - Mux selects OSB input. Gain & Offset change at
the pixel rate:
Gain & Offset = R, G, B, R, G, B,...
Color Mode
(0)
0
1
0
RESERVED
0
1
1
Monochrome Mux selects OSR input. Gain & Offset = R
1
0
0
Monochrome Mux selects OSG input. Gain & Offset = G
1
0
1
Monochrome Mux selects OSB input. Gain & Offset = B
Bayer - Mux selects OSB input. Gain & Offset change at the pixel rate:
*1st line: Gain & Offset = G,R,G,R,...
1
1
0
2nd line: Gain & Offset = B,G,B,G,...
repeat...
*state of the first line after a write to this register
Green Stripe - Mux selects OSB input. Gain & Offset change at the
pixel rate:
1
1
1
*1st line: Gain & Offset = R,G,B,G,R,G,B,...
2nd line: Gain & Offset = B,G,R,G,B,G,R,...
repeat...
*state of the first line after a write to this register
Red, Green and Blue Offset DAC Setting (1, 2 and 3)
B5
Offset Polarity
0
Positive Offset
(1, 2 & 3)
1
Negative Offset
Offset Value
(1, 2 & 3)
B4(MSB)
B3
B2
B1
B0(LSB)
13
LM9810: Offset = 5LSBs x Offset Value x PGA
Gain
LM9820: Offset = 20LSBs x Offset Value x PGA
Gain
www.national.com
LM9810/20
Timing Diagrams
(Continued)
TABLE 2. Configuration Register Parameters (Continued)
Parameter
Control Bits
(Address)
Result
Red, Green and Blue Offset DAC Setting (1, 2 and 3)
Typical Offset
Values
(1, 2 & 3)
B5
B4
(SIGN)
(MSB)
B3
B2
0
0
0
0
0
0
0
0
0
0
...
...
0
0
B1
B0
Typical Offset (with PGA Gain =1)
(LSB)
LM9810
LSBs
0
0
0.00
0.00
0
0
1
+5
+20
0
1
0
+10
+40
...
...
...
...
...
...
1
1
1
1
0
+150
+600
1
1
1
1
1
+155
+620
1
0
0
0
0
0
0
0
1
0
0
0
0
1
-5
1
0
0
0
1
0
-10
...
...
...
...
...
...
...
...
1
1
1
1
LM9820
LSBs
-20
-40
1
1
1
0
-150
-600
1
1
1
1
-155
-620
Red, Green and Blue Gains Settings (4, 5 and 6)
Boost Gain
B5
Enable
0
(4, 5 and 6)
1
PGA Gain Value
(4, 5, and 6)
B4
Boost Gain = 1V/V
Boost Gain = 3V/V
B3
B2
Gain
B0
PGA Gain (V/V =.933 + 0.0667 x (PGA Gain
Value)
Gain = Boost Gain x PGA Gain
(4, 5 and 6)
Typical Gain Values
(4, 5 and 6)
B1
B5
B4
(x3)
(MSB)
B3
B2
0
0
0
0
0
0
0
0
0
0
...
...
0
0
B1
B0
Typical Gain
(LSB)
(V/V)
0
0
0.93
0
0
1
1.00
0
1
0
1.13
...
...
...
...
...
1
1
1
0
1
2.87
1
1
1
1
0
2.93
0
1
1
1
1
1
3.00
...
...
...
...
...
...
...
1
0
0
0
0
0
2.79
1
0
0
0
0
1
3.00
1
0
0
0
1
0
3.20
...
...
...
...
...
...
...
1
1
1
1
0
1
8.60
1
1
1
1
1
0
8.80
1
1
1
1
1
1
9.00
Production Test and Power Down (7)
Production Test
(7)
B5
Power Down
B0
Enable
0
(7)
1
www.national.com
B4
B3
B2
B1
Should all be set to zero for normal operation
Normal Operation
Power Down
14
1.0 PROGRAMMING THE LM9810/20
If the LM9810/20 is programmed for correlated double
sampling (bit B5 of register 0 is cleared), then the falling
edge of SampCLK should occur toward the end of period
3 and the rising edge of SampCLK should occur towards
the end of period 4. While SampCLK is high, the reference
level (VRESIDUAL) is sampled, and it is held at the falling
edge of SampCLK. While SampCLK is low, the signal
level (VSIGNAL + VRESIDUAL) is sampled and it is held at
the rising edge of SampCLK. The output from the sampler
is the potential difference between the two samples, or
VSIGNAL.
1.1 Writing to the Configuration Register
When NewLine is high, D2, D1 & D0 act as a serial
interface for writing to the configuration registers. D2 is the
input serial clock (SCLK), D0 is the input data pin (SDI),
and D1 is the latch and shift enable signal (Latch). When
D1(Latch) is low, serial data is shifted into D0(SDI), and
must be valid on each rising edge of D2(SDLK). Three
register address bits followed by six data bits should be
shifted into D0(SDI), MSB first. When D1(Latch) transitions from low to high, the last 6 data bits will be stored
into the configuration register addressed by the previous 3
address bits (as shown in Figure 3). D1(Latch) must remain high for at least 3 cycles of the serial clock on
D2(SCLK) to write to the configuration register.
1.3 CIS Mode
The LM9810/20 supports CIS (Contact Image Sensor)
devices by offering a sampling mode for capturing positive
going signals, as opposed to the CCD’s negative going
signal. The output signal of a CIS sensor (Figure 7) differs
from a CCD signal in two primary ways: its output increases with increasing signal strength, and it does not
usually have a reference level as an integral part of the
output waveform of every pixel.
1.2 CDS Mode
The LM9810/20 uses a high-performance CDS (Correlated Double Sampling) circuit to remove many sources of
noise and error from the CCD signal. It also supports CIS
image sensors with a single sampling mode.
Figure 6 shows the output stage of a typical CCD and the
resulting output waveform:
DS100943-79
FIGURE 7. CIS
When the LM9810/20 is in CIS mode (Register 0, B5 = 1),
it uses either VREF+ or VREF− depending on the signal
polarity setting (B4 of the Sampling and Color Mode register) as the reference (or black) voltage for each pixel. If
the signal polarity is set to one, then VREF− will be held on
the falling edge of SampCLK and the OS signal will be
held on the rising edge of SampCLK. If it is set to zero,
then VREF+ will be held on the falling edge of SampCLK
and the OS signal will be held on the rising edge of
SampCLK. The rising edge of SampCLK should occur
near the end of period 4, and at least 50 ns after the falling
edge of SampCLK.
DS100943-78
FIGURE 6. CDS
Capacitor C1 converts the electrons coming from the
CCD’s shift register to an analog voltage. The source
follower output stage (Q2) buffers this voltage before it
leaves the CCD. Q1 resets the voltage across capacitor
C1 between pixels at intervals 2 and 5. When Q1 is on,
the output signal (OS) is at its most positive voltage. After
Q1 turns off (period 3), the OS level represents the residual voltage across C1 (VRESIDUAL). VRESIDUAL includes
charge injection from Q1, thermal noise from the ON
resistance of Q1, and other sources of error. When the
shift register clock (Ø1) makes a low to high transition
(period 4), the electrons from the next pixel flow into C1.
The charge across C1 now contains the voltage proportional to the number of electrons plus VRESIDUAL, an error
term. If OS is sampled at the end of period 3 and that
voltage is subtracted from the OS at the end of period 4,
1.4 Multiplexer/Channel Switching
The offset and gain settings automatically switch after
each ADC conversion according to the color mode setting
in the Sampler and Color Mode register (register 0). For
example, if the color mode (bits B2, B1 and B0) is set to
001, the offset and gain will alternately switch between the
R, G and B settings after each conversion. The input
multiplexer never changes during a line, but if the color
mode is set to Line Rate Color (000), the mux will automatically switch after each new line.
The offset and gain settings will always start with the first
channel of the programmed mode after a falling edge of
15
www.national.com
LM9810/20
the VRESIDUAL term is canceled and the noise on the
signal is reduced ( − VRESIDUAL = VSIGNAL). This is the
principal of Correlated Double Sampling.
Applications Information
LM9810/20
Applications Information
If the x3 Boost gain is enable then the overall signal gain
will be three times the PGA gain.
(Continued)
NewLine. For example, the R offset and gain settings will
be used for the first conversion following a falling edge on
NewLine if the color mode is set to Single Input Color
(001).
1.7 Offset DAC
The Offset DAC removes the DC offsets generated by the
sensor and the LM9810/20’s analog signal chain (see
section 1.7.1, Internal Offsets). The DAC value for each
color (registers 1, 2 and 3) should be set during calibration
to the lowest value that still results in an ADC output code
greater than zero for all the pixels when scanning a black
line. With a PGA gain of 1 V/V, each LSB of the offset DAC
typically adds the equivalent of 5 LM9810 LSBs or 20
LM9820 LSBs, providing a total offset adjustment range of
± 150 LM9810 LSBs or ± 590 LM9820 LSBs. The Offset
DAC’s output voltage is given by:
VDAC = 9.75 mV x (value in B4 - B0)
(2)
For the Single Input Color, Bayer and Green Stripe
modes, the mux will always connect the OSB input to the
sampler. The offset and gain settings will alternate values
every pixel according to the order indicated by the Sampler and Color Mode register (see Table 2). The first falling
edge of NewLine following a write to the Sampler and
Color Mode register will ready the offset and gain to cycle
through the colors of the first line of the programmed color
mode. Each subsequent falling edge of NewLine will
switch the offset and gain settings to the first color of the
next line. The LM9810/20’s unused OS inputs should not
be left unconnected. All three OS inputs should be tied
together on the LM9810/20 side of the clamp capacitor
(see Figure 8).
In terms of output codes, the offset is given by:
Offset = 5 LSBs x (value in B4 - B0) x PGA Gain (3)
Offset = 20 LSBs x (value in B4 - B0) x PGA Gain (4)
The offset is positive if bit B5 is cleared and negative if B5
is set. Since the analog offset is added before the PGA
gain, the value of the PGA gain must be considered when
selecting the offset DAC values.
1.7.1 Internal Offsets
Figure 9 is a model of the LM9810/20’s internal offsets.
Equation (5) shows how to calculate the expected output
code given the input voltage (VIN), the LM9810/20 internal
offsets (VOS1, VOS2, VOS3), the programmed offset DAC
voltage (VDAC), the programmed gains (GB, GPGA) and
the analog channel gain constant C.
C is a constant that combines the gain error through the
AFE, reference voltage variance, and analog voltage to
digital code conversion into one constant. Ideally, C =
2048 codes/V (4096 codes/2V) for the LM9820 and 512
codes/V (1024 codes/2V) for the LM9810. Manufacturing
tolerances widen the range of C (see Electrical
Specifications).
DS100943-80
FIGURE 8. OS Connections for Signal Output Sensors
For the Line Rate Color mode, the mux will cycle through
the OSR, OSG and OSB inputs after each falling edge of
NewLine. The R, G and B offset and gain settings will be
used when the mux is set to OSR, OSG and OSB input,
respectively. OSR and the R offset and gain settings will
always be used on the first line following a write register 0.
1.5 Data Latency
The latency through the LM9810/20 is a 8 SampCLK
periods plus one MCLK period. The data output on D5 D0 (MSBs b11 - b6 or b9 - b4) represents data whose
reference signal was sampled 8 tSampCLK + tMCLK +
tSampSU earlier (See Figure 1).
1.6 Programmable Gain
The output of the Sampler drives the input of the x3 Boost
gain stage. The gain of the x3 Boost gain is 3 V/V if bit B5
of the current color’s gain register (registers 4, 5 and 6) is
set, or 1 V/V if bit B5 is cleared. The output of the x3 gain
stage is the input to the offset DAC and the output of the
offset DAC is the input to the PGA (Programmable Gain
Amplifier). The PGA provides 5 bits of gain correction over
a 0.93 V/V to 3 V/V (−0.6 to 9.5 dB) range. The x3 Boost
gain stage and the PGA can be combined for an overall
gain range of 0.93 V/V to 9.0 V/V (−0.6 to 19 dB). The gain
setting for each color (registers 4, 5 and 6) should be set
during calibration to bring the maximum amplitude of the
strongest pixel to a level just below the desired maximum
output from the ADC. The PGA gain is determined by the
following equation:
DS100943-81
FIGURE 9. Internal Offset Mode
DOUT = (((VIN + (VOS1)GB + VDAC + VOS2) GPGA +
VOS1)C
(5)
Equation (6) is a simplification of the output code calculation, neglecting the LM9810/20’s internal offsets.
DOUT = (VINGB + (VDAC)GPGAC
(6)
1.8 Power Down Mode
Setting the Power Down (bit B0 of register 7) puts the
device in a low power standby mode. The analog sections
are turned off to conserve power. The digital logic will
continue to operate if MCLK continues, so for minimum
power dissipation MCLK should be stopped when the
(1)
www.national.com
16
2.1.1 CDS Mode Minimum Clamp Capacitor
Calculation
(Continued)
LM9810/20 enters the Power Down mode. Recovery from
Power Down typically takes 50 µs (the time required for
the reference voltages to settle to 0.5 LSB accuracy).
The following figure takes the maximum leakage current
into the OS input, the maximum allowable droop, the
number of pixels on the sensor, and the pixel conversion
rate, fSampCLK, and provides the minimum clamp capacitor
value:
2.0 CLAMPING
To perform a DC restore across the AC coupling capacitors at the beginning of every line, the LM9810/20 implements a clamping function. When NewLine is high and
SampCLK is low, all three OS inputs will be connected to
either VREF+ or VREF−, depending on B4 of the Sampling
and Color Mode register. If B4 is set to one (positive signal
polarity), then the OS inputs will be connected to VREF−. If
B4 is set to zero (negative signal polarity), then they will
be connected to VREF+.
(7)
For example, if the OS input leakage current is 20 nA
worst-case, the sensor has 2700 active pixels, the conversion rate is 2 MHz (tSampCLK = 500 ns), and the max
droop desired is 0.1V, the minimum clamp capacitor value
is:
2.1 Clamp Capacitor Selection
This section explains how to select appropriate clamp
capacitor values.
(8)
2.1.2 CIS Mode Minimum Clamp Capacitor
Calculation
If CDS is disabled, then the maximum LM9810/20 OS
input leakage current can be calculated from:
ILEAKAGE = VSATfSampCLKCSAMP
(9)
where VSAT is the peak pixel signal swing of the CIS OS
output and CSAMP is the capacitance of the LM9810/20’s
internal sampling capacitor (2 pF). Inserting this into
Equation (7) results in:
DS100943-82
FIGURE 10. OS Clamp Capacitor and Internal Clamp
The output signal of many sensors rides on a DC offset
(greater than 5V for many CCDs) which is incompatible
with the LM9810/20’s 5V operation. To eliminate this offset without resorting to additional higher voltage components, the output of the sensor is AC coupled to the
LM9810/20 through a DC blocking capacitor, CCLAMP. The
sensor’s DOS output, if available, is not used. The value
of this capacitor is determined by the leakage current of
the LM9810/20’s OS input and the output impedance of
the sensor. The leakage through the OS input determines
how quickly the capacitor value will drift from the clamp
value of ,VREF+ or VREF−, which then determines how
many pixels can be processed before the droop causes
errors in the conversion ( ± 0.1V is the recommended limit
for CDS operation). The output impedance of the sensor
determines how quickly the capacitor can be charged to
the clamp value during the black reference period at the
beginning of every line.
The minimum clamp capacitor value is determined by the
maximum droop the LM9810/20 can tolerate while converting one sensor line. The minimum clamp capacitor
value is much smaller for CDS mode applications than it is
for CIS mode applications. The LM9810/20 input leakage
current is considerably less when the LM9810/20 is operating in CDS mode. In CDS mode, the LM9810/20 leakage current should be no more than 20 nA. With CDS
disabled, which will likely be the case when CIS sensors
are used, the LM9810/20 leakage current can be as high
as 25 µA at the maximum conversion rate.
(10)
with CSAMP equal to 2 pF and VSAT equal to 2V (the
LM19810/20’s maximum input signal), then Equation (10)
reduces to:
(11)
In CIS mode (CDS disabled), the max droop limit must be
much more carefully chosen, since any change in the
clamp capacitor’s DC value will affect the LM9810/20’s
conversion results. If a droop of one 10-bit LSB across a
line is considered acceptable, then the allowed droop
voltage is calculated as 2V/1024, or approximately 2 mV.
If there are 2700 active pixels on a line then:
(12)
2.1.3 Maximum Clamp Capacitor Calculation
The maximum size of the clamp capacitor is determined
by the amount of time available to charge it to the desired
value during the optical black portion of the sensor output.
The internal clamp is on when NewLine is high and SampCLK is low. If the applied SampCLK is low for half its
cycle, then the available charge time per line can be
calculated using:
17
www.national.com
LM9810/20
Applications Information
LM9810/20
Applications Information
after power-up, then a clamp capacitor value of 0.01
µF should be significantly greater than the calculated
CCLAMP MIN value and can virtually always be used.
(Continued)
If the LM9810/20 is operating in CIS mode, then significantly larger clamp capacitors must be used. Fortunately,
the output impedance of most CIS sensors is significantly
smaller than the output impedance of CCD sensors, and
RCLAMP will be dominated by the 50Ω from the LM9810/
20’s internal clamp switch. With a smaller RCLAMP value,
the clamp capacitors will charge faster.
(13)
For example, if a sensor has 18 black reference pixels
and fSampCLK is 2 MHz with a 50% duty cycle, then tCLAMP
is 4.5 µs.
The following figure takes the number of optical black
pixels, the amount of time (per pixel) that the clamp is
closed, the sensor’s output impedance, and the desired
accuracy of the final clamp voltage and provides the
maximum clamp capacitor value that allows the clamp
capacitor to settle to the desired accuracy within a single
line:
3.0 PERFORMANCE CONSIDERATIONS
3.1 Power Supply
The LM9810/20 should be powered by a single +5V
source. The analog supplies (VA) and the digital supply
(VD) are brought out individually to allow separate bypassing for each supply input. They should not be powered by
two or more different supplies.
In systems with separate analog and digital +5V supplies,
all the supply pins of the LM9810/20 should be powered
by the analog +5V supply. Each supply input should be
bypassed to its respective ground with a 0.1 µF capacitor
located as close as possible to the supply input pin. A
single 10 µF tantalum capacitor should be placed near the
VA supply pin to provide low frequency bypassing.
To minimize noise, keep the LM9810/20 and all analog
components as far as possible from noise generators,
such as switching power supplies and high frequency
digital busses. If possible, isolate all the analog components and signals (OS, reference inputs and outputs, VA,
AGND) on an analog ground plane, separate from the
digital ground plane. The two ground planes should be
tied together at a single point, preferably the point where
the power supply enters the PCB.
(14)
Where tCLAMP is the amount of time (per line) that the
clamp is on, RCLAMP is the output impedance of the CCD
plus 50Ω for the LM9810/20’s internal clamp switch, and
accuracy is the ratio of the worst-case initial capacitor
voltage to the desired final capacitor voltage. If tCLAMP is
4.5 µs, the output impedance of the sensor is 1500Ω, the
worst case voltage change required across the capacitor
(before the first line) is 5V, and the desired accuracy after
clamping is to within 0.1V (accuracy = 5/0.1 = 50), then:
(15)
The final value for CCLAMP should be less than or equal to
CCLAMP MAX, but no less than CCLAMP MIN.
3.2 SampCLK Timing
SampCLK is used to time the stages of the LM9810/20’s
sampler, offset DAC and programmable gain amplifier. To
allow for optimum input signal sampling times, SampCLK
may be applied asynchronously to MCLK. The LM9810/
20’s ADC is synchronized with the AFE (including the
sampler, the offset DAC and the PGA) by MCLK.
The LM9810/20’s internal ADC clock is created through a
combination of the applied SampCLK and MCLK signals.
MCLK is used to synchronize the applied SampCLK signal. The internal ADC clock will go low after the falling
edge of SampCLK is clocked by a rising of MCLK. The
ADC clock will stay low for two MCLK cycles and then go
high. It will stay high until the next falling edge of SampCLK is clocked by MCLK. Figure 11 illustrates this SampCLK, MCLK, and ADC clock timing relationship.
In some cases, depending primarily on the choice of
sensor, CCLAMP MAX may actually be less than CCLAMP
MIN, meaning that the capacitor can not be charged to its
final voltage during the black pixels at the beginning of a
line and hold its voltage without drooping for the duration
of that line. This is usually not a problem because in most
applications the sensor is clocked continuously as soon
as power is applied. In this case, a larger capacitor can be
used (guaranteeing that the CCLAMP MIN requirement is
met), and the final clamp voltage is forced across the
capacitor over multiple lines. This equation calculates how
many lines are required before the capacitor settles to the
desired accuracy:
(16)
Using the values shown before and a clamp capacitor
value of 0.01 µF, this works out to be:
(17)
In this example, a 0.01 µF capacitor takes 14 lines after
power-up to charge to its final value. On subsequent lines,
the only error will be the droop across a single line which
should be significantly less than the initial error. If the
LM9810/20 is operating in CDS mode and multiple
lines are used to charge up the clamping capacitors
www.national.com
DS100943-83
FIGURE 11. LM9810/20 Relative Event Timing
The LM9810/20 is a densely designed, mixed-signal,
monolithic semiconductor. In creating the timing for the
LM9810/20, it must be considered that internal events,
18
or to output data transitions. SampCLK edges should be
at least 20 ns away from ADC clock edges to avoid
interference between the ADC and the sampler. SampCLK edges should also be placed at least 40 ns after
output data transition times to avoid transition noise coupling.
(Continued)
such as ADC sampling, and output data bus switching can
potentially affect coincident events such as input signal
sampling or offset DAC settling. One event can interfere
with another by coupling noise on shared resources such
as the supply lines, internal voltage references, or the
silicon substrate.
To optimize the performance of the LM9810/20, SampCLK should be timed so that the input signal hold times do
not coincide with output data switching and ADC clock
transitions. In other words, the rising and falling edges of
SampCLK should not be placed close to ADC clock edges
Figure 11 is an example of SampCLK timing that will meet
these requirements at the maximum MCLK frequency of
24 MHz. In Figure 11, SampCLK transitions occur on
MCLK falling edges which will keep them more than 20 ns
away from ADC transitions, and 40 ns after output data
transitions.
19
www.national.com
LM9810/20
Applications Information
LM9810/20 10/12-Bit Image Sensor Processor Analog Front End
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Pin (.300” Wide) Molded Small Outline Package
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: [email protected]
www.national.com
National Semiconductor
Europe
Fax: +49 (0) 180-530 85 86
Email: [email protected]
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: [email protected]
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
www.ti.com/audio
Communications and Telecom www.ti.com/communications
Amplifiers
amplifier.ti.com
Computers and Peripherals
www.ti.com/computers
Data Converters
dataconverter.ti.com
Consumer Electronics
www.ti.com/consumer-apps
DLP® Products
www.dlp.com
Energy and Lighting
www.ti.com/energy
DSP
dsp.ti.com
Industrial
www.ti.com/industrial
Clocks and Timers
www.ti.com/clocks
Medical
www.ti.com/medical
Interface
interface.ti.com
Security
www.ti.com/security
Logic
logic.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Power Mgmt
power.ti.com
Transportation and Automotive www.ti.com/automotive
Microcontrollers
microcontroller.ti.com
Video and Imaging
RFID
www.ti-rfid.com
OMAP Mobile Processors
www.ti.com/omap
Wireless Connectivity
www.ti.com/wirelessconnectivity
TI E2E Community Home Page
www.ti.com/video
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2011, Texas Instruments Incorporated