DS100MB201
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SNLS333A – APRIL 2011 – REVISED APRIL 2013
DS100MB201 Dual Lane 2:1/1:2 Mux/Buffer with Equalization
Check for Samples: DS100MB201
FEATURES
DESCRIPTION
•
•
•
The DS100MB201 is a dual lane 2:1 multiplexer and
1:2 switch or fan-out buffer with signal conditioning
suitable for 10GE, Fibre Channel, Infiniband,
SATA/SAS and other high-speed bus applications up
to 10.31215 Gbps. The device performs receive
equalization allowing maximum flexibility of physical
placement within a system. The receiver's continuous
time linear equalizer (CTLE) provides a boost to
compensate for 10” of 4 mil FR4 stripline at 10.3125
Gbps. The DS100MB201 is capable of opening an
input eye that is completely closed due to intersymbol interference (ISI) induced by the interconnect
medium. The transmitter features a programmable
amplitude voltage levels to be selected from 600
mVp-p to 800 mVp-p. The signal conditioning settings
are programmable with register control.
1
2
•
•
•
•
•
•
•
•
Up to 10.3125 Gbps
Dual Lane 2:1 Mux, 1.2 Switch or Fanout
Adjustable Transmit Differential Output
Voltage (VOD)
<0.3 UI of Residual DJ at 10.3125 Gbps with
10” FR4 trace
Adjustable Electrical IDLE Detect Threshold
Signal Conditioning Programmable through
SMBus I/F
Single 2.5V Supply Operation
>6 kV HBM ESD Rating
3.3V Tolerant SMBus Interface
High Speed Signal flow–thru Pinout
Package: 54-pin WQFN (10 mm x 5.5 mm)
With a typical power consumption of 100 mW/channel
at 10.3125 Gbps, and SMBus register control to turnoff unused lanes, the DS100MB201 is part of TI's
PowerWise family of energy efficient devices.
APPLICATIONS
•
•
•
•
•
XAUI (3.125 Gbps), RXAUI (6.25 Gbps)
sRIO – Serial Rapid I/O
Fibre Channel (8.5 Gbps)
10GBase-CX4, InfiniBand (QDR, SDR & DDR)
FR4 Backplane Traces
Typical Application
SEL0
DS100MB201
HDD0
SIA0+Cs > 10 nF
RX
2
2
TX
Cs > 10 nF
2
TXA
DOUT0+SIB0+-
2
SIA1+-
2
SIB1+-
2
TXB
TXA
DOUT1+-
TXB
HDD1
RX
SATA/SAS
Controller
2
2
SOA0+-
2
SOB0+-
2
DIN0+-
TX
SOA1+-
2
SOB1+-
2
DIN1+-
RXA
RXB
RXA
RXB
SEL1
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
DS100MB201
SNLS333A – APRIL 2011 – REVISED APRIL 2013
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SDA
ENSMB
AD2
AD3
49
48
47
46
VDD
SCL
50
GND
51
53
52
AD0
AD1
54
Pin Diagram
SMBUS AND CONTROL
NC
1
45
SIA0+
NC
2
44
SIA0-
DOUT0+
3
43
SIB0+
DOUT0-
4
42
SIB0-
NC
5
41
VDD
NC
6
40
SIA1+
DOUT1+
7
39
SIA1-
DOUT1-
8
38
SIB1+
VDD
9
37
SIB1-
DIN0+
10
36
VDD
DIN0-
11
35
SOA0+
TOP VIEW
DAP = GND
NC
12
34
SOA0-
NC
13
33
SOB0+
24
25
26
27
TXIDLESO
FANOUT
SD_TH
SOB1-
TXIDLEDO
28
23
18
RESERVED
29
NC
21
NC
SOB1+
22
SOA1-
17
RATE
DIN1-
30
RESERVED
SOA1+
16
20
SOB0-
31
19
32
15
SEL1
14
SEL0
VDD
DIN1+
Figure 1. DS100MB201 Pin Diagram 54L WQFN Package
See Package Number NJY0054A
PIN DESCRIPTIONS (1)
Pin Name
I/O, Type (2) (3) (4)
Pin Number
Pin Description
Differential High Speed I/O's
SIA0+, SIA0-,
SIA1+, SIA1-
45, 44,
40, 39
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A gated onchip 50Ω termination resistor connects SIA_n+ to VDD and SIA_n- to VDD
when enabled.
SOA0+, SOA0-,
SOA1+, SOA1-
35, 34,
31, 30
O
Inverting and non-inverting low power differential signaling 50Ω outputs. Fully
compatible with AC coupled CML inputs.
SIB0+, SIB0-,
SIB1+, SIB1-
43, 42,
38, 37
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A gated onchip 50Ω termination resistor connects SIB_n+ to VDD and SIB_n- to VDD
when enabled.
SOB0+, SOB0-,
SOB1+, SOB1-
33, 32,
29, 28
O
Inverting and non-inverting low power differential signaling 50Ω outputs. Fully
compatible with AC coupled CML inputs.
DIN0+, DIN0-,
DIN1+, DIN1-
10, 11,
15, 16
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A gated onchip 50Ω termination resistor connects SIB_n+ to VDD and SIB_n- to VDD
when enabled.
(1)
(2)
(3)
(4)
2
1 = HIGH, 0 = LOW, FLOAT = 3rd input state.
FLOAT condition; Do not drive pin; pin is internally biased to mid level with 50 kΩ pull-up/pull-down.
Internal pulled-down = Internal 30 kΩ pull-down resistor to GND is present on the input.
Input edge rate for LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
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PIN DESCRIPTIONS(1) (continued)
Pin Name
Pin Number
DOUT0+, DOUT0-, 3, 4,
DOUT1+, DOUT1- 7, 8
I/O, Type (2) (3) (4)
Pin Description
O
Inverting and non-inverting low power differential signaling 50Ω outputs. Fully
compatible with AC coupled CML inputs.
Control Pins — (LVCMOS)
ENSMB
48
I, LVCMOS w/
internal pull-down
System Management Bus (SMBus) enable pin.
LOW = Reserved
HIGH = Register Access: Provides access to internal digital registers to control
such functions as equalization, VOD, channel powerdown, and idle detection
threshold.
Please refer to System Management Bus (SMBus) and Configuration
Registers for detailed information.
SDA
49
I, LVCMOS
The SMBus bi-directional SDA pin. Data input or open drain output. External
pull-up resistor is required. Refer to Rterm in the SMBus specification.
SCL
50
I, LVCMOS
SMBUS clock input pin. External pull-up resistor maybe needed. Refer to Rterm
in the SMBus specification.
AD[3:0]
46, 47, 53, 54
I, LVCMOS w/
internal pull-down
SMBus Slave Address Inputs. These pins set the SMBus address.
Control Pins — (LVCMOS)
RATE
21
I, Float, LVCMOS
LOW = Reserved
HIGH = 10.3125 Gbps operation
TXIDLEDO
24
I, Float, LVCMOS
TXIDLEDO, 3–level input controls the driver output.
LOW = disable the signal detect/squelch function for DOUT.
FLOAT = enable the signal auto detect/squelch function for DOUT and the
signal detect voltage threshold level can be adjusted using the SD_TH pin.
HIGH = force the DOUT to be muted (electrical idle). See Table 1
TXIDLESO
25
I, Float, LVCMOS
TXIDLESO, 3–level input controls the driver output.
LOW = disable the signal detect/squelch function for SOUT.
FLOAT = enable the signal auto detect/squelch function for SOUT and the
signal detect voltage threshold level can be adjusted using the SD_TH pin.
HIGH = force the SOUT to be muted (electrical idle). See Table 1
FANOUT
26
I, LVCMOS w/
internal pull-down
LOW = disable one of the outputs depending on the SEL0, SEL1 pin.
HIGH = enable both A/B outputs for broadcast mode.
FANOUT = 0 See Table 3
SEL0, SEL1
19, 20
I, LVCMOS w/
internal pull-down
SEL0 is for lane 0, SEL1 is for lane 1
SEL0, SEL1 = 0 selects B input and B output.
SEL0, SEL1 = 1 selects A input and A output. See Table 3
Reserved
52
I, LVCMOS
Tie to GND
27
I, ANALOG
Threshold select pin for electrical idle detect threshold. Float pin for default
130 mVp-p (differential).
See Table 2
Analog
SD_TH
Power
VDD
9, 14, 36, 41, 51 Power
2.5V Power supply pins.
GND
DAP
DAP is the large metal contact at the bottom side, located at the center of the
54 pin LLP package. It should be connected to the GND plane with at least 4
via to lower the ground impedance and improve the thermal performance of
the package.
Reserved
1, 2, 5, 6, 12,
13, 17, 18, 22,
23
Power
No Connect — Leave pin open
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings (1) (2)
Supply Voltage (VDD)
-0.5V to +3.0V
LVCMOS Input/Output Voltage
-0.5V to +4.0V
Differential Input Voltage
-0.5V to (VDD+0.5V)
Differential Output Voltage
-0.5V to (VDD+0.5V)
Analog (SD_TH)
-0.5V to (VDD+0.5V)
Junction Temperature
+105°C
Storage Temperature
-40°C to +125°C
Maximum Package Power Dissipation at 25°C
NJY0054A Package
4.21 W
Derate NJY0054A Package
ESD Rating
52.6mW/°C above +25°C
≥±6 kV
HBM, STD - JESD22-A114C
≥±250 V
MM, STD - JESD22-A115-A
Thermal Resistance
(1)
(2)
CDM, STD - JESD22-C101-C
≥±1250 V
θJC
11.5°C/W
θJA, No Airflow, 4 layer JEDEC
19.1°C/W
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Absolute
Maximum Numbers are guaranteed for a junction temperature range of -40°C to +125°C. Models are validated to Maximum Operating
Voltages only.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Recommended Operating Conditions (1)
Supply Voltage, VDD to GND
Ambient Temperature (2)
Min
Typ
Max
Units
2.375
2.5
2.625
V
-40
25
+85
°C
V
LVCMOS
0
2.625
SMBus (SDA, SCL)
0
3.6
V
CML Differential Input Voltage
0
2.0
Vp-p
Supply Noise Tolerance up to 50 MHz (3)
(1)
(2)
(3)
4
100
mVP-P
For soldering specifications: see product folder at: http://www.ti.com, http://www.ti.com/lit/SNOA549
OOB signal pass-through limited to a minimum ambient temperature of -10°C.
Allowed supply noise (mVP-P sine wave) under typical conditions.
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Electrical Characteristics (1)
Over recommended operating supply and temperature ranges with default register settings unless other specified.
Parameter
Test Conditions
Min
Typ
Max
Units
900
1000
mW
11
mW
2.75
V
POWER
PD
Power Dissipation
2.5V Operation
EQx = 0,
K28.5 pattern,
VOD = 700 mV p-p
Channel powerdown (2)
LVCMOS / LVTTL DC SPECIFICATIONS
VIH
High Level Input Voltage
2.0
VIL
Low Level Input Voltage
0
0.8
V
IIH
Input High Current
VIN = 2.5 V
-15
+15
μA
IIL
Input Low Current
VIN = 0V
-15
+15
μA
CML RECEIVER INPUTS (IN_n+, IN_n-)
RLRX-DIFF
Rx Differential Return Loss
(SDD11),
See (3)
150 MHz – 1.5 GHz
-20
150 MHz – 3.0 GHz
-13.5
150 MHz – 6.0 GHz
-8
Rx Common Mode Input Return
Loss (SCC11)
150 MHz – 3.0 GHz, See (3)
RRX-IB
Rx Impedance Balance (SCL11)
(3)
IIN
Maximum current allowed at IN+ or
IN- input pin.
RLRX-CM
150 MHz – 3.0 GHz, See
RIN
Input Resistance
Single ended to VDD, See
RITD
Input Differential Impedance
between
IN+ and IN-
See (3)
RITIB
Input Differential Impedance
Imbalance
See (3)
RICM
Input Common Mode Impedance
See (3)
20
VRX-DIFF
Differential Rx peak to peak voltage
DC voltage,
SD_TH = 20 kΩ to GND
VRX-SD_TH
Electrical Idle detect threshold
(differential)
SD_TH = Float,
See (4) and Figure 6
(1)
(2)
(3)
(4)
-10
dB
-27
dB
−30
(3)
dB
+30
mA
Ω
50
115
Ω
5
Ω
40
Ω
0.1
1.2
V
40
175
mVp-p
85
100
25
The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not guaranteed.
Measured with ENSMB = 1, all channels disabled using SMBus registers 0x01 and 0x02, and EQ in bypass (Default).
Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the
time of product characterization and are not guaranteed.
Measured at package pins of receiver. Less than 65 mVp-p is IDLE, greater than 175 mVp-p is ACTIVE. SD_TH pin connected with
resistor to GND overrides this default setting.
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Electrical Characteristics(1) (continued)
Over recommended operating supply and temperature ranges with default register settings unless other specified.
Parameter
Test Conditions
Min
Typ
Max
Units
RL = 50 Ω ±1% to GND (AC coupled with
10 nF), 6.4 Gbps, See (5)
VOD1–0 = 00
500
600
700
mVP-P
DIFFERENTIAL OUTPUTS (OUT_n+, OUT_n-)
VOD
Output Differential Voltage Swing
VOCM
Output Common-Mode Voltage
TTX-RF
Transmitter Rise/ Fall Time
Single-ended measurement DC-Coupled
with 50Ω termination,
See (6)
VDD –
1.4
20% to 80% of differential output voltage,
measured within 1” from output pins,
See (6) (5) and Figure 2
65
TRF-DELTA
Tx rise/fall mismatch
20% to 80% of differential output voltage,
See (6) (5)
RLTX-DIFF
Tx Differential Return Loss
(SDD22),
See (6)
Repeating 1100b (D24.3) pattern,
VOD = 0.8 Vp-p,
150 MHz – 1.5 GHz
-11
1.5 GHz – 3.0 GHz
-10
RLTX-CM
RTX-IB
85
ps
0.1
UI
dB
3 GHz – 6.0 GHz
-5
Tx Common Mode Return Loss
(SCC22)
Repeating 1100b (D24.3) pattern,
VOD = 0.8 Vp-p, See (6)
50 MHz – 3.0 GHz
-10
dB
Tx Impedance Balance
(SCL22)
Repeating 1100b (D24.3) pattern,
VOD = 0.8 Vp-p, See (6)
50 MHz – 3.0 GHz
-30
dB
ITX-SHORT
Tx Output Short Circuit Current
Limit
ROTD
Output Differential Impedance
between OUT+ and OUT-
See (6)
ROTIB
Output Differential Impedance
Imbalance
See (6)
ROCM
Output Common Mode Impedance
See (6)
VTX-CM-DELTA
Common Mode Voltage Delta
between active burst and electrical
Idle of an OOB signal
Minimum Temperature for OOB signal
pass-through is -10C.
VIN = 800 mVp-p, at 3 Gbps,
See (7)
Differential Propagation Delay (Low
to High and High to Low Edge
Propagation delay measure at midpoint
crossing between input to outputEQx[1:0]
= 11 Figure 3
150
EQz[1:0] = OFF
120
TPD
V
85
20
90
mA
125
Ω
5
Ω
35
Ω
±40
mV
200
250
ps
170
100
25
220
ps
TLSK
Lane to Lane Skew in a Single Part
VDD = 2.5V, TA = 25°C
27
ps
TPPSK
Part to Part Propagation Delay
Skew
VDD = 2.5V, TA = 25°C
35
ps
TSM
Switch/Mux Time
Time to switch/mux between A and B
input/output signals
150
ns
(5)
(6)
(7)
6
Measured with clock-like {11111 00000} pattern.
Typical values represent most likely parametric norms at VDD = 2.5V, TA = 25°C., and at the Recommended Operation Conditions at the
time of product characterization and are not guaranteed.
Common-mode voltage (VCM) is expressed mathematically as the average of the two signal voltages with respect to local ground.VCM
= (A + B) / 2, A = OUT+, B = OUT-.
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Electrical Characteristics(1) (continued)
Over recommended operating supply and temperature ranges with default register settings unless other specified.
Parameter
Test Conditions
Min
Typ
Max
Units
EQUALIZATION
DJ1
DJ2
RJ
Residual Deterministic Jitter at 8.5
Gbps
Tx Launch Amplitude = 0.8 to
1.2 Vp–p, 10” 4–mil FR4 trace,
VOD = 0.8 Vp-p, K28.5, SD_TH = float
0.1
0.25
UIP-P
Residual Deterministic Jitter at
10.3125 Gbps
Tx Launch Amplitude = 0.8 to
1.2 Vp–p, 10” 4–mil FR4 trace,
VOD = 0.8 Vp-p, K28.5, SD_TH = float
0.1
0.3
UIP-P
Random Jitter
Tx Launch Amplitude = 1.2 Vp–p,
Repeating 1100b (D24.3) pattern
0.5
psrms
Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
Parameter
Test Conditions
Min
Typ
Max
Units
0.8
V
3.6
V
SERIAL BUS INTERFACE DC SPECIFICATIONS
VIL
Data, Clock Input Low Voltage
VIH
Data, Clock Input High Voltage
IPULLUP
Current Through Pull-Up Resistor
or Current Source
VDD
Nominal Bus Voltage
ILEAK-Bus
Input Leakage Per Bus Segment
ILEAK-Pin
Input Leakage Per Device Pin
CI
Capacitance for SDA and SCL
See (1) (2)
RTERM
External Termination Resistance
pull to VDD = 2.5V ± 5% OR 3.3V ±
10%
VDD3.3, See (1) (2) (3)
2.1
High Power Specification
See (1)
4
mA
2.375
3.6
V
-200
+200
µA
-15
VDD2.5, See
µA
10
(1) (2) (3)
pF
2000
Ω
1000
Ω
SERIAL BUS INTERFACE TIMING SPECIFICATIONS. See Figure 5
FSMB
Bus Operating Frequency
TBUF
Bus Free Time Between Stop and
Start Condition
THD:STA
Hold time after (Repeated) Start
Condition. After this period, the first
clock is generated.
See (4)
10
100
kHz
4.7
µs
4.0
µs
4.7
µs
At IPULLUP, Max
TSU:STA
Repeated Start Condition Setup
Time
TSU:STO
Stop Condition Setup Time
4.0
µs
THD:DAT
Data Hold Time
300
ns
TSU:DAT
Data Setup Time
250
TTIMEOUT
Detect Clock Low Timeout
TLOW
Clock Low Period
THIGH
Clock High Period
TLOW:SEXT
Cumulative Clock Low Extend Time See (4)
(Slave Device)
tF
Clock/Data Fall Time
tR
tPOR
(1)
(2)
(3)
(4)
See (4)
25
ns
35
4.7
See (4)
4.0
ms
µs
50
µs
2
ms
See (4)
300
ns
Clock/Data Rise Time
See (4)
1000
ns
Time in which a device must be
operational after power-on reset
See (4)
500
ms
Recommended value. Parameter not tested in production.
Recommended maximum capacitance load per bus segment is 400pF.
Maximum termination voltage should be identical to the device supply voltage.
Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
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Timing Diagrams
Figure 2. Output Transition Times
Figure 3. Propagation Delay Timing Diagram
Figure 4. Idle Timing Diagram
tLOW
tR
tHIGH
SCL
tHD:STA
tBUF
tHD:DAT
tF
tSU:STA
tSU:DAT
tSU:STO
SDA
SP
ST
SP
ST
Figure 5. SMBus Timing Parameters
8
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Functional Description
The DS100MB201 is a 2–lane signal conditioning 2:1 multiplexer and 1:2 switch or fan-out buffer optimized for
PCB FR4 trace up to 10.3125 Gbps data rate. The DS100MB201 has direct register access through the SMBus.
The ENSMB pin must be tied high to enable proper operation of the DS100MB201.
Pin Control Mode
The RATE pin must be forced HIGH to enable 10.3125 Gbps operation. The receiver electrical idle detect
threshold is also programmable via an optional external resistor on the SD_TH pin.
SMBUS Register Programming
In SMBus mode the VOD amplitude level and equalization are all programmable on a individual lane basis. On
power-up and when ENSMB is driven low all registers are reset to their default state.
Table 1. Idle Control (3–Level Input)
TXIDLEDO/SO
Function
0
This state is for lossy media, dedicated Idle threshold detect circuit disabled,
output follows input based on EQ settings. Idle state not guaranteed.
Float
Float enables automatic idle detection. Idle on the input is passed to the
output. Internal 50KΩ resistors hold TXIDLEDO/SO pin at a mid level - don't
connect this pin if the automatic idle detect function is desired. This is the
default state. Output in Idle if differential input signal less than value set by
SD_TH pin.
1
Manual override, output in electrical Idle. Differential inputs are ignored.
Table 2. Receiver Electrical Idle Detect Threshold Adjust
SD_TH resistor value (Ω)
Receiver Electrical Idle Detect Threshold (DIFF p-p)
Float (no resistor required)
130 mV (default condition)
0
225 mV
80k
20 mV
ELECTRICAL IDLE DETECT THRESHOLD
(DIFF mVp-p)
SD_TH resistor value can be set from 0 through 80k ohms to achieve desired idle detect threshold, see Figure 6
250
VDD = 2.5V
TA = 25°C
200
150
100
50
0
0
10k 20k 30k 40k 50k 60k 70k 80k
SD_TH RESISTOR VALUE (:)
Figure 6. Typical Idle Threshold vs. SD_TH resistor value
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Device Connection Paths
The lanes of the DS100MB201 can be configured either as a 2:1 multiplexer, 1:2 switch or fan-out buffer. The
controller side is muxed to the disk drive side. The below table shows the logic for the multiplexer and switch
functions.
Table 3. Logic Table of Switch and Mux Control
FANOUT
SEL0
SEL1
0
0
0
DOUT0 connects to SIB0.
DOUT1 connects to SIB1.
DIN0 connects to SOB0. SOA0 is in idle (output muted).
DIN1 connects to SOB1. SOA1 is in idle (output muted).
Function — connection path
0
0
1
DOUT0 connects to SIB0.
DOUT1 connects to SIA1.
DIN0 connects to SOB0. SOA0 is in idle (output muted).
DIN1 connects to SOA1. SOB1 is in idle (output muted).
0
1
0
DOUT0 connects to SIA0.
DOUT1 connects to SIB1.
DIN0 connects to SOA0. SOB0 is in idle (output muted).
DIN1 connects to SOB1. SOA1 is in idle (output muted).
0
1
1
DOUT0 connects to SIA0.
DOUT1 connects to SIA1.
DIN0 connects to SOA0. SOB0 is in idle (output muted).
DIN1 connects to SOA1. SOB1 is in idle (output muted).
1
0
0
DOUT0 connects to SIB0.
DOUT1 connects to SIB1.
DIN0 connects to SOB0 and SOA0.
DIN1 connects to SOB1 and SOA1.
1
0
1
DOUT0 connects to SIB0.
DOUT1 connects to SIA1.
DIN0 connects to SOB0 and SOA0.
DIN1 connects to SOA1 and SOB1.
1
1
0
DOUT0 connects to SIA0.
DOUT1 connects to SIB1.
DIN0 connects to SOA0 and SOB0.
DIN1 connects to SOB1 and SOA1.
1
1
1
DOUT0 connects to SIA0.
DOUT1 connects to SIA1.
DIN0 connects to SOA0 and SOB0.
DIN1 connects to SOA1 and SOB1.
System Management Bus (SMBus) and Configuration Registers
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB must be
pulled high to enable SMBus mode and allow access to the configuration registers.
The DS100MB201 has the AD[3:0] inputs in SMBus mode. These pins set the SMBus slave address inputs. The
AD[3:0] pins have internal pull-down. When left floating or pulled low the AD[3:0] = 0000'b, the device default
address byte is A0'h. Based on the SMBus 2.0 specification, the DS100MB201 has a 7-bit slave address of
1010000'b. The LSB is set to 0'b (for a WRITE), thus the 8-bit value is 1010 0000'b or A0'h. The bold bits
indicate the AD[3:0] pin map to the slave address bits [4:1]. The device address byte can be set with the use of
the AD[3:0] inputs. Below are some examples.
AD[3:0] = 0001'b, the device address byte is A2'h
AD[3:0] = 0010'b, the device address byte is A4'h
AD[3:0] = 0100'b, the device address byte is A8'h
AD[3:0] = 1000'b, the device address byte is B0'h
The SDA, SCL pins are 3.3V tolerant, but are not 5V tolerant. External pull-up resistor is required on the SDA.
The resistor value can be from 1 kΩ to 5 kΩ depending on the voltage, loading and speed. The SCL may also
require an external pull-up resistor and it depends on the Host that drives the bus.
10
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TRANSFER OF DATA VIA THE SMBUS
During normal operation the data on SDA must be stable during the time when SCL is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SCL is High indicates a message START condition.
STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they
are High for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state.
SMBUS TRANSACTIONS
The device supports WRITE and READ transactions. See Register Description table for register address, type
(Read/Write, Read Only), default value and function information.
When SMBus is enabled, all outputs of the DS100MB201 must write VOD2 register to 0x01 (hex). See Table 4
for more information. Each channel must be set to the value of 0x01 (hex) through each register (0x18, 0x26,
0x2E, 0x35, 0x3C, 0x43) to ensure a proper output waveform. The driver Vout voltage is set on a per lane basis
using 6 different registers. Each register (0x17, 0x25, 0x2D, 0x34, 0x3B, 0x43) controls the VOD to 600 mV and
800 mV.
WRITING A REGISTER
To
1.
2.
3.
4.
5.
6.
7.
write a register, the following protocol is used (see SMBus 2.0 specification).
The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
The Device (Slave) drives the ACK bit (“0”).
The Host drives the 8-bit Register Address.
The Device drives an ACK bit (“0”).
The Host drive the 8-bit data byte.
The Device drives an ACK bit (“0”).
The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may
now occur.
READING A REGISTER
To read a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1” indicating end of the READ transfer.
10. The Host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now
occur.
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RECOMMENDED SMBUS REGISTER SETTINGS
Upon power-up, the default register settings are not configured to an appropriate level. Below is the
recommended settings to configure the EQ and VOD to a medium level that supports interconnect length of 10
inches FR4 trace. Please refer to Table 4, Table 5 for additional information and recommended settings.
1. Reset the SMBus registers to default values:
– Write 01'h to 0x00.
2. Set output voltage for all lanes:
– Write 01'h to 0x18, 0x26, 0x2E, 0x35, 0x3C, 0x43.
3. Set equalization ~6 dB at 5GHz for all lanes:
– Write 30'h to 0x0F, 0x16, 0x1D, 0x24, 0x2C, 0x3A.
4. Set VOD = 0.8 Vp-p for all lanes:
– Write 07'h to 0x17, 0x25, 0x2D, 0x34, 0x3B, 0x42.
Table 4. Output Driver Register Settings (must write when in SMBus mode)
Output Value
VOD Control 1
Register Setting
(800 mV)
VOD Control 2
Register Setting (must set)
10.3125 Gbps Operation
1V dB
0x07
0x01
10” trace
Table 5. SMBus Register Map
Address
0x00
Register Name
Reset
Bit(s)
Field
7:1
Reserved
0
Reset
Type
R/W
Default
0x00
Description
Set bits to 0.
SMBus Reset
1: Reset registers to default value
0x01
PWDN lanes
7:0
PWDN CHx
R/W
0x00
Power Down per lane
[7]: NC — SOB1
[6]: DIN1 — SOA1
[5]: NC — SOB0
[4]: DIN0 — SOA0
[3]: SIB1 — DOUT1
[2]: SIA1 — NC
[1]: SIB0 — DOUT0
[0]: SIA0 — NC
00'h = all lanes enabled
FF'h = all lanes disabled
0x02
PWDN Control
7:1
Reserved
R/W
0x00
Set bits to 0.
0
PWDN Control
7:3
Reserved
2
SEL1
0: Selects B input and output
1: Selects A input and output
1
SEL0
0: Selects B input and output
1: Selects A input and output
0
FANOUT
0: Enable only A or B output depends on SEL1 and
SEL0
1: Enable both A and B output
7:5
Reserved
4
Override IDLE
0: Allow IDLE pin control
1: Block IDLE pin control
3
Reserved
Set bit to 0.
2
Reserved
Set bit to 0.
1
Override SEL
0: Allow SEL pin control
1: Block SEL pin control
0
Override
FANOUT
0: Allow FANOUT pin control
1: Block FANOUT pin control
0x03
0x08
12
SEL / FANOUT
Control
Pin Control Override
0: Normal operation
1: Enable PWDN control in Register 0x01
R/W
R/W
0x00
0x00
Set bits to 0.
Set bits to 0.
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Table 5. SMBus Register Map (continued)
Address
0x0F
0x12
0x15
Register Name
Bit(s)
Field
Type
R/W
Default
0x20
Description
SIA0
EQ Control
7:6
Reserved
Set bits to 0.
5:0
SIA0 EQ
SIA0
IDLE Threshold
7:4
Reserved
3:0
IDLE threshold
DOUT0
IDLE Select
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
SIA0 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x00
Set bits to 0.
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
0x00
Set bits to 0.
3:0
Reserved
SIB0
EQ Control
7:6
Reserved
5:0
SIB0 EQ
DOUT0
VOD Control 1
7
Reserved
6:0
DOUT0 VOD 1
0x18
DOUT0
VOD Control 2
7:0
DOUT0 VOD 2
R/W
0x03
DOUT0 VOD Control
VOD Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h
0x19
SIB0
IDLE Threshold
7:4
Reserved
R/W
0x00
Set bits to 0.
3:0
IDLE threshold
0x16
0x17
Set bits to 0.
R/W
0x20
Set bits to 0.
SIB0 Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x03
Set bit to 0.
DOUT0 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
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Table 5. SMBus Register Map (continued)
Address
0x1D
0x20
0x23
Register Name
Bit(s)
Field
Type
R/W
Default
0x20
Description
SIA1
EQ Control
7:6
Reserved
Set bits to 0.
5:0
SIA1 EQ
SIA1
IDLE Threshold
7:4
Reserved
3:0
IDLE threshold
DOUT1
IDLE Select
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
SIA1 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x00
Set bits to 0.
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
0x00
Set bits to 0.
3:0
Reserved
SIB1
EQ Control
7:6
Reserved
5:0
SIB1 EQ
DOUT1
VOD Control 1
7
Reserved
6:0
DOUT1 VOD 1
0x26
DOUT1
VOD Control 2
7:0
DOUT1 VOD 2
R/W
0x03
DOUT1 VOD Control
VOD Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h
0x27
SIB1
IDLE Threshold
7:4
Reserved
R/W
0x00
Set bits to 0.
3:0
IDLE threshold
0x24
0x25
14
Set bits to 0.
R/W
0x20
Set bits to 0.
SIB1 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x03
Set bit to 0.
DOUT1 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
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Table 5. SMBus Register Map (continued)
Address
0x2B
Register Name
SOA0
IDLE Select
Bit(s)
Field
Type
R/W
Default
0x00
Description
7:6
Reserved
Set bits to 0.
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:0
Reserved
DIN0
EQ Control
7:6
Reserved
5:0
DIN0 EQ
SOA0
VOD Control 1
7
Reserved
6:0
SOA0 VOD 1
0x2E
SOA0
VOD Control 2
7:0
SOA0 VOD 2
R/W
0x03
SOA0 VOD Control
VOD Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h
0x2F
DIN0
IDLE Threshold
7:4
Reserved
R/W
0x00
Set bits to 0.
3:0
IDLE threshold
SOB0
IDLE Select
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
0x2C
0x2D
0x32
Set bits to 0.
R/W
0x20
Set bits to 0.
DIN0 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x03
Set bit to 0.
SOA0 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
0F'h = 1000 mV
1F'h = TBD mV
3F'h = TBD mV
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
0x00
Set bits to 0.
3:0
Reserved
SOB0
VOD Control 1
7
Reserved
6:0
SOB0 VOD 1
0x35
SOB0
VOD Control 2
7:0
SOB0 VOD 2
R/W
0x03
SOB0 VOD Control
VOD Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h
0x39
SOA1
IDLE Select
7:6
Reserve
R/W
0x00
Set bits to 0.
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
3:0
Reserved
Set bits to 0.
0x34
Set bits to 0.
R/W
0x03
Set bit to 0.
SOB0 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
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Table 5. SMBus Register Map (continued)
Address
0x3A
Register Name
Bit(s)
Field
Type
Reserved
5:0
DIN1 EQ
SOA1
VOD Control 1
7
Reserved
6:0
SOA1 VOD 1
0x3C
SOA1
VOD Control 2
7:0
SOA1 VOD 2
R/W
0x03
SOA1 VOD Control
VOD Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h
0x3D
DIN1
IDLE Threshold
7:4
Reserved
R/W
0x00
Set bits to 0.
3:0
IDLE threshold
SOB1
IDLE Select
7:6
Reserved
5
IDLE auto
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
4
IDLE select
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
0x40
0x20
Description
7:6
0x3B
R/W
Default
DIN1
EQ Control
Set bits to 0.
DIN1 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
R/W
0x03
Set bit to 0.
SOA1 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
R/W
0x00
Set bits to 0.
3:0
Reserved
SOB1
VOD Control
7
Reserved
6:0
SOB1 VOD
0x43
SOB1
VOD Control 2
7:0
SOB1 VOD 2
R/W
0x03
DOUT0 VOD Control
VOD Level Control
Register [TYPE] [Level Control] = Hex Value
00000001 = 01'h
0x47
Global VOD Adjust
7:2
Reserved
R/W
0x02
Set bits to 0.
1:0
VOD Adjust
0x42
16
Set bits to 0.
R/W
0x03
Set bit to 0.
SOB1 VOD Control
03'h = 600 mV (Default)
07'h = 800 mV
00
01
10
11
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= -25.0%
= -12.5%
= +0.0% (Default)
= +12.5%
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APPLICATIONS INFORMATION
GENERAL RECOMMENDATIONS
The DS100MB201 is a high performance circuit capable of delivering excellent performance. Careful attention
must be paid to the details associated with high-speed design as well as providing a clean power supply. Refer
to the LVDS Owner's Manual for more detailed information on high speed design tips to address signal integrity
design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL PAIRS
The CML inputs and CML compatible outputs must have a controlled differential impedance of 100Ω. It is
preferable to route differential lines exclusively on one layer of the board, particularly for the input traces. The
use of vias should be avoided if possible. If vias must be used, they should be used sparingly and must be
placed symmetrically for each side of a given differential pair. Route the differential signals away from other
signals and noise sources on the printed circuit board. See AN-1187 (SNOA401) for additional information on
WQFN packages.
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the DS100MB201 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be connected to power planes routed on adjacent layers
of the printed circuit board. The layer thickness of the dielectric should be minimized so that the VDD and GND
planes create a low inductance supply with distributed capacitance. Second, careful attention to supply
bypassing through the proper use of bypass capacitors is required. A 0.01 μF bypass capacitor should be
connected to each VDD pin such that the capacitor is placed as close as possible to the DS100MB201. Smaller
body size capacitors can help facilitate proper component placement. Additionally, three capacitors with
capacitance in the range of 2.2 μF to 10 μF should be incorporated in the power supply bypassing design as
well. These capacitors can be either tantalum or an ultra-low ESR ceramic.
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REVISION HISTORY
Changes from Original (April 2013) to Revision A
•
18
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 17
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PACKAGE OPTION ADDENDUM
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13-Jul-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DS100MB201SQ/NOPB
ACTIVE
WQFN
NJY
54
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
DS100MB201
SQ
DS100MB201SQE/NOPB
ACTIVE
WQFN
NJY
54
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
DS100MB201
SQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jul-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DS100MB201SQ/NOPB
WQFN
NJY
54
2000
330.0
16.4
5.8
10.3
1.0
12.0
16.0
Q1
DS100MB201SQE/NOPB
WQFN
NJY
54
250
178.0
16.4
5.8
10.3
1.0
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS100MB201SQ/NOPB
WQFN
NJY
54
2000
367.0
367.0
38.0
DS100MB201SQE/NOPB
WQFN
NJY
54
250
213.0
191.0
55.0
Pack Materials-Page 2
PACKAGE OUTLINE
NJY0054A
WQFN
SCALE 2.000
WQFN
5.6
5.4
B
A
PIN 1 INDEX AREA
0.5
0.3
0.3
0.2
10.1
9.9
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8 MAX
C
SEATING PLANE
2X 4
SEE TERMINAL
DETAIL
3.51±0.1
19
(0.1)
27
28
18
50X 0.5
7.5±0.1
2X
8.5
1
45
54
PIN 1 ID
(OPTIONAL)
46
54X
54X
0.5
0.3
0.3
0.2
0.1
0.05
C A
C
B
4214993/A 07/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
NJY0054A
WQFN
WQFN
(3.51)
SYMM
54X (0.6)
54
54X (0.25)
SEE DETAILS
46
1
45
50X (0.5)
(7.5)
SYMM
(9.8)
(1.17)
TYP
2X
(1.16)
28
18
( 0.2) TYP
VIA
19
27
(1) TYP
(5.3)
LAND PATTERN EXAMPLE
SCALE:8X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214993/A 07/2013
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
NJY0054A
WQFN
WQFN
SYMM
METAL
TYP
(0.855) TYP
46
54
54X (0.6)
54X (0.25)
1
45
50X (0.5)
(1.17)
TYP
SYMM
(9.8)
12X (0.97)
18
28
19
27
12X (1.51)
(5.3)
SOLDERPASTE EXAMPLE
BASED ON 0.125mm THICK STENCIL
EXPOSED PAD
67% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
4214993/A 07/2013
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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