AD ADSP-2187LBST-210 Dsp microcomputer Datasheet

a
FEATURES
PERFORMANCE
19 ns Instruction Cycle Time @ 3.3 Volts, 52 MIPS
Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 400 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
160K Bytes of On-Chip RAM, Configured as 32K Words
Program Memory RAM and 32K Words
Data Memory RAM
Dual Purpose Program Memory for Instruction␣ and Data
Storage
Independent ALU, Multiplier/Accumulator and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead TQFP
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to
On-Chip Memory (Mode Selectable)
4 MByte Memory Interface for Storage of Data Tables
and Program Overlays (Mode Selectable)
8-Bit DMA to Byte Memory for Transparent Program
and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O Memory
Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging in
Final Systems
DSP Microcomputer
ADSP-2187L
FUNCTIONAL BLOCK DIAGRAM
POWER-DOWN
CONTROL
DATA ADDRESS
GENERATORS
FULL MEMORY
MODE
MEMORY
PROGRAM
SEQUENCER
DAG 1 DAG 2
32K324 PM
(
32K316 DM
) (
8K324 OVERLAY 1
8K324 OVERLAY 2
8K316 OVERLAY 1
8K316 OVERLAY 2
)
PROGRAMMABLE
I/O
AND
FLAGS
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
BYTE DMA
CONTROLLER
PROGRAM MEMORY DATA
OR
DATA MEMORY DATA
EXTERNAL
DATA
BUS
ARITHMETIC UNITS
ALU
MAC
SHIFTER
SERIAL PORTS
SPORT 0 SPORT 1
ADSP-2100 BASE
ARCHITECTURE
TIMER
INTERNAL
DMA
PORT
HOST MODE
GENERAL NOTE
This data sheet represents specifications for the ADSP-2187L
3.3 V processor.
GENERAL DESCRIPTION
The ADSP-2187L is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.
The ADSP-2187L combines the ADSP-2100 family base architecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities and on-chip program and data
memory.
The ADSP-2187L integrates 160K bytes of on-chip memory
configured as 32K words (24-bit) of program RAM, and 32K
words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery operated portable
equipment. The ADSP-2187L is available in 100-lead TQFP
package.
In addition, the ADSP-2187L supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
biased rounding, result free ALU operations, I/O memory transfers and global interrupt masking, for increased flexibility.
Fabricated in a high speed, low power, CMOS process, the
ADSP-2187L operates with a 19 ns instruction cycle time. Every instruction can execute in a single processor cycle.
ICE-Port is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
␣␣
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
ADSP-2187L
The ADSP-2187L’s flexible architecture and comprehensive instruction set allow the processor to perform multiple operations
in parallel. In one processor cycle the ADSP-2187L can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
•
•
•
•
•
Registers and memory values can be examined and altered
PC upload and download functions
Instruction-level emulation of program booting and execution
Complete assembly and disassembly of instructions
C source-level debugging
See “Designing An EZ-ICE-Compatible Target System” in the
ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as
well as the Designing an EZ-ICE Compatible System section of
this data sheet for the exact specifications of the EZ-ICE target
board connector.
This takes place while the processor continues to:
• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the internal DMA port
• Receive and/or transmit data through the byte DMA port
• Decrement timer
Additional Information
This data sheet provides a general overview of ADSP-2187L
functionality. For additional information on the architecture and
instruction set of the processor, see the ADSP-2100 Family
User’s Manual, Third Edition. For more information about the
development tools, refer to the ADSP-2100 Family Development Tools Data Sheet.
DEVELOPMENT SYSTEM
The ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, supports the ADSP-2187L. The System Builder provides a high
level method for defining the architecture of systems under development. The Assembler has an algebraic syntax that is easy
to program and debug. The Linker combines object files into an
executable file. The Simulator provides an interactive instruction-level simulation with a reconfigurable user interface to display different portions of the hardware environment.
ARCHITECTURE OVERVIEW
The ADSP-2187L instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single processor cycle. The ADSP-2187L assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.
A PROM Splitter generates PROM programmer compatible
files. The C Compiler, based on the Free Software Foundation’s
GNU C Compiler, generates ADSP-2187L assembly source
code. The source code debugger allows programs to be corrected in the C environment. The Runtime Library includes over
100 ANSI-standard mathematical and DSP-specific functions.
POWER-DOWN
CONTROL
DATA ADDRESS
GENERATORS
PROGRAM
SEQUENCER
DAG 1 DAG 2
The EZ-KIT Lite is a hardware/software kit offering a complete
development environment for the entire ADSP-21xx family: an
ADSP-218x based evaluation board with PC monitor software
plus Assembler, Linker, Simulator, and PROM Splitter software. The ADSP-218x EZ-KIT Lite is a low cost, easy to use
hardware platform on which you can quickly get started with
your DSP software design. The EZ-KIT Lite includes the following features:
• 33 MHz ADSP-218x
• Full 16-bit Stereo Audio I/O with AD1847 SoundPort® Codec
• RS-232 Interface to PC with Windows 3.1 Control Software
• EZ-ICE® Connector for Emulator Control
• DSP Demo Programs
The ADSP-218x EZ-ICE Emulator aids in the hardware debugging of ADSP-2187L system. The emulator consists of hardware, host computer resident software and the target board
connector. The ADSP-2187L integrates on-chip emulation support with a 14-pin ICE-Port interface. This interface provides a
simpler target board connection requiring fewer mechanical
clearance considerations than other ADSP-2100 Family
EZ-ICEs. The ADSP-2187L device need not be removed from
the target system when using the EZ-ICE, nor are any adapters
needed. Due to the small footprint of the EZ-ICE connector, emulation can be supported in final board designs.
The EZ-ICE performs a full range of functions, including:
• In-target operation
• Up to 20 breakpoints
• Single-step or full-speed operation
FULL MEMORY
MODE
MEMORY
32K324 PM
(
32K316 DM
) (
8K324 OVERLAY 1
8K324 OVERLAY 2
8K316 OVERLAY 1
8K316 OVERLAY 2
)
PROGRAMMABLE
I/O
AND
FLAGS
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
BYTE DMA
CONTROLLER
PROGRAM MEMORY DATA
OR
DATA MEMORY DATA
EXTERNAL
DATA
BUS
ARITHMETIC UNITS
ALU
MAC
SHIFTER
ADSP-2100 BASE
ARCHITECTURE
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
INTERNAL
DMA
PORT
HOST MODE
Figure 1. Functional Block Diagram
Figure 1 is an overall block diagram of the ADSP-2187L. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization and derive exponent operations.
The shifter can be used to efficiently implement numeric format control including multiword and block floating-point
representations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc.
–2–
REV. 0
ADSP-2187L
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine
calls and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-2187L executes looped code with zero overhead; no explicit jump instructions are required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four possible modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers.
Efficient data transfer is achieved with the use of five internal
buses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permitting the ADSP-2187L to fetch two operands in a single cycle,
one from program memory and one from data memory. The
ADSP-2187L can fetch an operand from program memory and
the next instruction in the same cycle.
The ADSP-2187L provides up to 13 general-purpose flag pins.
The data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, there
are eight flags that are programmable as inputs or outputs and
three flags that are always outputs.
In lieu of the address and data bus for external memory connection, the ADSP-2187L may be configured for 16-bit Internal
DMA port (IDMA port) connection to external systems. The
IDMA port is made up of 16 data/address pins and five control
pins. The IDMA port provides transparent, direct access to the
DSPs on-chip program and data RAM.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports slow
memories and I/O memory-mapped peripherals with programmable wait state generation. External devices can gain control of
external buses with bus request/grant signals (BR, BGH, and BG).
One execution mode (Go Mode) allows the ADSP-2187L to continue running from on-chip memory. Normal execution mode requires the processor to halt while buses are granted.
The ADSP-2187L can respond to eleven interrupts. There can
be up to six external interrupts (one edge-sensitive, two levelsensitive and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORTs), the Byte
DMA port and the power-down circuitry. There is also a master
RESET signal. The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a
wide variety of framed or frameless data transmit and receive
modes of operation.
• SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every n processor cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial Ports
The ADSP-2187L incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications
and multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-2187L
SPORTs. For additional information on Serial Ports, refer to
the ADSP-2100 Family User’s Manual, Third Edition.
• SPORTs are bidirectional and have a separate, doublebuffered transmit and receive section.
• SPORTs can use an external serial clock or generate their
own serial clock internally.
• SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
• SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and µ-law companding according
to CCITT recommendation G.711.
• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24- or 32-word, time-division multiplexed,
serial bitstream.
• SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.
PIN DESCRIPTIONS
The ADSP-2187L will be available in a 100-lead TQFP package. In order to maintain maximum functionality and reduce
package size and pin count, some serial port, programmable
flag, interrupt and external bus pins have dual, multiplexed
functionality. The external bus pins are configured during
RESET only, while serial port pins are software configurable
during program execution. Flag and interrupt functionality is retained concurrently on multiplexed pins. In cases where pin
functionality is reconfigurable, the default state is shown in plain
text; alternate functionality is shown in italics. See CommonMode Pin Descriptions.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
REV. 0
–3–
ADSP-2187L
Common-Mode Pin Descriptions
Pin
Name(s)
# of Input/
Pins Output
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
IRQ2/
PF7
IRQL0/
PF6
IRQL1/
PF5
IRQE/
PF4
Mode D/
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PF3
Mode C/
I/O
1
PF2
Mode B/
1
I
I/O
1
PF0
CLKIN,
XTAL
CLKOUT
SPORT0
SPORT1
IRQ1:0
FI, FO
PWD
PWDACK
FL0, FL1,
FL2
VDD and
GND
EZ-Port
I
I/O
PF1
Mode A/
I
I
O
O
O
O
O
O
O
O
O
I
I/O
I
I/O
I
I/O
I
I/O
I
I
I/O
2
1
5
5
I
O
I/O
I/O
Function
Processor Reset Input
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Data Memory Select Output
Program Memory Select Output
Memory Select Output
Byte Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Edge- or Level-Sensitive Interrupt
Request.1 Programmable I/O Pin
Level-Sensitive Interrupt Requests1
Programmable I/O Pin
Level-Sensitive Interrupt Requests1
Programmable I/O Pin
Edge-Sensitive Interrupt Requests1
Programmable I/O Pin
Mode Select Input—Checked
Only During RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked
Only During RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked
Only During RESET
Programmable I/O Pin During
Normal Operation
Mode Select Input—Checked
Only During RESET
Programmable I/O Pin During
Normal Operation
1
1
I
O
Clock or Quartz Crystal Input
Processor Clock Output
Serial Port I/O Pins
Serial Port I/O Pins
Edge- or Level-Sensitive Interrupts,
Flag In, Flag Out2
Power-Down Control Input
Power-Down Control Output
3
O
Output Flags
16
9
I
I/O
Power and Ground
For Emulation Use
NOTES
1
Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate
interrupt vector address when the pin is asserted, either by external devices, or
set as a programmable flag.
2
SPORT configuration determined by the DSP System Control Register. Software configurable.
Memory Interface Pins
The ADSP-2187L processor can be used in one of two modes,
Full Memory Mode, which allows BDMA operation with full
external overlay memory and I/O capability, or Host Mode,
which allows IDMA operation with limited external addressing
capabilities. The operating mode is determined by the state of
the Mode C pin during RESET and cannot be changed while
the processor is running. See tables for Full Memory Mode Pins
and Host Mode Pins for descriptions.
Full Memory Mode Pins (Mode C = 0)
Pin
# of Input/
Name(s) Pins Output Function
A13:0
14
O
Address Output Pins for Program,
Data, Byte and I/O Spaces
D23:0
24
I/O
Data I/O Pins for Program, Data,
Byte and I/O Spaces (8 MSBs are
also used as Byte Memory addresses)
Host Mode Pins (Mode C = 1)
Pin
Name(s)
IAD15:0
A0
# of
Pins
16
1
D23:8
16
IWR
IRD
IAL
IS
IACK
1
1
1
1
1
Input/
Output Function
I/O
IDMA Port Address/Data Bus
O
Address Pin for External I/O, Program, Data or Byte access
I/O
Data I/O Pins for Program, Data
Byte and I/O spaces
I
IDMA Write Enable
I
IDMA Read Enable
I
IDMA Address Latch Pin
I
IDMA Select
O
IDMA Port Acknowledge Configurable in Mode D; Open Source
In Host Mode, external peripheral addresses can be decoded using the A0,
CMS, PMS, DMS and IOMS signals
Terminating Unused Pin
The following table shows the recommendations for terminating
unused pins.
Pin Terminations
Pin
Name
I/O
3-State
(Z)
Reset
State
XTAL
CLKOUT
A13:1 or
IAD12:0
A0
D23:8
D7 or
IWR
I
O
O (Z)
I/O (Z)
O (Z)
I/O (Z)
I/O (Z)
I
I
O
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
I
–4–
Hi-Z*
Caused
By
BR,
IS
BR,
BR,
BR,
EBR
EBR
EBR
EBR
Unused
Configuration
Float
Float
Float
Float
Float
Float
Float
High (Inactive)
REV. 0
ADSP-2187L
D6 or
IRD
D5 or
IAL
D4 or
IS
D3 or
IACK
D2:0 or
IAD15:13
PMS
DMS
BMS
IOMS
CMS
RD
WR
BR
BG
BGH
IRQ2/PF7
I/O (Z)
I
I/O (Z)
I
I/O (Z)
I
I/O (Z)
**
I/O (Z)
I/O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
I
O (Z)
O
I/O (Z)
IRQL0/PF6 I/O (Z)
IRQL1/PF5 I/O (Z)
Hi-Z
I
Hi-Z
I
Hi-Z
I
Hi-Z
**
Hi-Z
Hi-Z
O
O
O
O
O
O
O
I
O
O
I
I
I
IRQE/PF5
I/O (Z)
I
SCLK0
I/O
I
RFS0
DR0
TFS0
DT0
SCLK1
I/O
I
I/O
O
I/O
I
I
O
O
I
RFS1/RQ0
DR1/FI
TFS1/RQ1
DT1/FO
EE
EBR
EBG
ERESET
EMS
EINT
ECLK
ELIN
ELOUT
I/O
I
I/O
O
I
I
O
I
O
I
I
I
O
I
I
O
O
I
I
O
I
O
I
I
I
O
2. If the Interrupt/Programmable Flag pins are not used, there are two options:
Option 1: When these pins are configured as INPUTS at reset and function as
interrupts and input flag pins, pull the pins High (inactive).
Option 2: Program the unused pins as OUTPUTS, set them to 1, and let them
float.
3. All bidirectional pins have three-stated outputs. When the pins is configured as
an output, the output is Hi-Z (high impedance) when inactive.
4. CLKIN, RESET, and PF3:0 are not included in the table because these pins
must be used.
BR, EBR Float
BR, EBR High (Inactive)
Float
Low (Inactive)
BR, EBR Float
High (Inactive)
BR, EBR Float
**
BR, EBR Float
IS
Float
BR, EBR Float
BR, EBR Float
BR, EBR Float
BR, EBR Float
BR, EBR Float
BR, EBR Float
BR, EBR Float
High (Inactive)
EE
Float
Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High or Low,
Output = Float
High or Low
High or Low
High or Low
Float
Input = High or Low,
Output = Float
High or Low
High or Low
High or Low
Float
Interrupts
The interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-2187L provides four dedicated external interrupt
input pins, IRQ2, IRQL0, IRQL1 and IRQE. In addition,
SPORT1 may be reconfigured for IRQ0, IRQ1, FLAG_IN and
FLAG_OUT, for a total of six external interrupts. The ADSP2187L also supports internal interrupts from the timer, the byte
DMA port, the two serial ports, software and the power-down
control circuit. The interrupt levels are internally prioritized and
individually maskable (except power down and reset). The
IRQ2, IRQ0 and IRQ1 input pins can be programmed to be
either level- or edge-sensitive. IRQL0 and IRQL1 are levelsensitive and IRQE is edge sensitive. The priorities and vector
addresses of all interrupts are shown in Table I.
Table I. Interrupt Priority and Interrupt Vector Addresses
Interrupt Vector
Address (Hex)
RESET (or Power-Up with PUCR = 1)
Power-Down (Nonmaskable)
IRQ2
IRQL1
IRQL0
SPORT0 Transmit
SPORT0 Receive
IRQE
BDMA Interrupt
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
0000 (Highest Priority)
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028 (Lowest Priority)
Interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. Interrupts
can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed with the bits in
IMASK; the highest priority unmasked interrupt is then selected. The power-down interrupt is nonmaskable.
The ADSP-2187L masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect serial port autobuffering or DMA transfers.
NOTES
**Hi-Z = High Impedance.
**Determined by MODE D pin:
Mode D = 0 and in host mode: IACK is an active, driven signal and cannot be
“wire ORed.” If unused, let float.
Mode D = 1 and in host mode: IACK is an open source and requires an external pull-down, but multiple IACK pins can be “wire ORed” together. If unused, let float.
1. If the CLKOUT pin is not used, turn it OFF.
REV. 0
Source of Interrupt
The interrupt control register, ICNTL, controls interrupt nesting and defines the IRQ0, IRQ1 and IRQ2 external interrupts to
be either edge- or level-sensitive. The IRQE pin is an external
edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level-sensitive interrupts.
–5–
ADSP-2187L
The IFC register is a write-only register used to force and clear
interrupts. On-chip stacks preserve the processor status and are
automatically maintained during interrupt handling. The stacks
are twelve levels deep to allow interrupt, loop and subroutine
nesting. The following instructions allow global enable or disable servicing of the interrupts (including power down), regardless of the state of IMASK. Disabling the interrupts does not
affect serial port autobuffering or DMA.
Slow Idle
The IDLE instruction on the ADSP-2187L slows the processor’s
internal clock signal, further reducing power consumption. The
reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the
IDLE instruction. The format of the instruction is
IDLE (n);
where n = 16, 32, 64 or 128. This instruction keeps the processor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, CLKOUT and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
ENA INTS;
DIS INTS;
When the processor is reset, interrupt servicing is enabled.
LOW POWER OPERATION
The ADSP-2187L has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:
• Power-Down
• Idle
• Slow Idle
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to incoming interrupts. The one-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-2187L will remain in the idle
state for up to a maximum of n processor cycles (n = 16, 32, 64
or 128) before resuming normal operation.
The CLKOUT pin may also be disabled to reduce external
power dissipation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
Power-Down
The ADSP-2187L processor has a low power feature that lets
the processor enter a very low power dormant state through
hardware or software control. Here is a brief list of power-down
features. Refer to the ADSP-2100 Family User’s Manual, Third
Edition, “System Interface” chapter, for detailed information
about the power-down feature.
SYSTEM INTERFACE
• Quick recovery from power-down. The processor begins executing instructions in as few as 400 CLKIN cycles.
Figure 2 shows a typical basic system configuration with the
ADSP-2187L, two serial devices, a byte-wide EPROM, and
optional external program and data overlay memories (mode selectable). Programmable wait state generation allows the processor to connect easily to slow peripheral devices. The ADSP-2187L
also provides four external interrupts and two serial ports or six
external interrupts and one serial port. Host Memory Mode allows access to the full external data bus, but limits addressing to
a single address bit (A0) Additional system peripherals can be
added in this mode through the use of external hardware to generate and latch address signals.
• Support for an externally generated TTL or CMOS processor
clock. The external clock can continue running during powerdown without affecting the 400 CLKIN cycle recovery.
• Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits 4096 CLKIN
cycles for the crystal oscillator to start and stabilize), and letting the oscillator run to allow 400 CLKIN cycle start up.
• Power-down is initiated by either the power-down pin (PWD)
or the software power-down force bit Interrupt support allows
an unlimited number of instructions to be executed before optionally powering down. The power-down interrupt also can
be used as a non-maskable, edge-sensitive interrupt.
Clock Signals
The ADSP-2187L can be clocked by either a crystal or a TTLcompatible clock signal.
The CLKIN input cannot be halted, changed during operation
or operated below the specified frequency during normal operation. The only exception is while the processor is in the powerdown state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual, Third Edition, for detailed information on this power-down feature.
• Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
power-down state.
• The RESET pin also can be used to terminate power- down.
• Power-down acknowledge pin indicates when the processor
has entered power-down.
If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is connected
to the processor’s CLKIN input. When an external clock is
used, the XTAL input must be left unconnected.
Idle
When the ADSP-2187L is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs. When
an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the IDLE instruction. In
Idle Mode IDMA, BDMA and autobuffer cycle steals still occur.
–6–
REV. 0
ADSP-2187L
Because the ADSP-2187L includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors connected
as shown in Figure 3. Capacitor values are dependent on crystal
type and should be specified by the crystal manufacturer. A
parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used.
FULL MEMORY MODE
ADSP-2187L
1/2x CLOCK
OR
CRYSTAL
14
CLKIN
XTAL
A13-0
ADDR13-0
D23-16
FL0-2
24
DATA23-0
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
MODE D/PF3
MODE C/PF2
MODE A/PF0
MODE B/PF1
A0–A21
D15-8
DATA
BYTE
MEMORY
CS
BMS
A10-0
WR
RD
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled
by the CLK0DIS bit in the SPORT0 Autobuffer Control Register.
ADDR
D23-8
DATA
CS
IOMS
I/O SPACE
(PERIPHERALS)
2048 LOCATIONS
A13-0
ADDR
SPORT1
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SERIAL
DEVICE
SPORT0
SCLK0
RFS0
TFS0
DT0
DR0
SERIAL
DEVICE
D23-0
DATA
OVERLAY
MEMORY
TWO 8K
PM SEGMENTS
PMS
DMS
CMS
CLKIN
TWO 8K
DM SEGMENTS
XTAL
CLKOUT
DSP
BR
BG
BGH
PWD
PWDACK
Figure 3. External Crystal Connections
HOST MEMORY MODE
Reset
ADSP-2187L
1/2x CLOCK
OR
CRYSTAL
CLKIN
A0
The RESET signal initiates a master reset of the ADSP-2187L.
The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
1
XTAL
FL0-2
16
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
WR
RD
SPORT1
IOMS
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SERIAL
DEVICE
SCLK0
RFS0
TFS0
DT0
DR0
SPORT0
IDMA PORT
16
BMS
MODE D/PF3
MODE C/PF2
MODE A/PF0
MODE B/PF1
SERIAL
DEVICE
SYSTEM
INTERFACE
OR
mCONTROLLER
DATA23-8
IRD/D6
IWR/D7
IS/D4
IAL/D5
IACK/D3
IAD15-0
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum
of 2000 CLKIN cycles ensures that the PLL has locked, but
does not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the minimum pulsewidth specification, tRSP .
PMS
DMS
CMS
BR
BG
BGH
The RESET input contains some hysteresis; however, if an
RC circuit is used to generate the RESET signal, an external
Schmidt trigger is recommended.
PWD
PWDACK
Figure 2. ADSP-2187L Basic System Configuration
The ADSP-2187L uses an input clock with a frequency equal to
half the instruction rate; a 26.00 MHz input clock yields a 19 ns
processor cycle (which is equivalent to 52 MHz). Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
REV. 0
–7–
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting, the boot-loading
sequence is performed. The first instruction is fetched from
on-chip program memory location 0x0000 once boot loading
completes.
ADSP-2187L
Table II. Modes of Operations 1
MODE D2
MODE C3
MODE B4
MODE A5
Booting Method
X
0
0
0
X
0
1
0
0
1
0
0
0
1
0
1
1
1
0
0
1
1
0
1
BDMA feature is used to load the first 32 program memory words from the
byte memory space. Program execution is held off until all 32 words have
been loaded. Chip is configured in Full Memory Mode.6
No Automatic boot operations occur. Program execution starts at external
memory location 0. Chip is configured in Full Memory Mode. BDMA can still
be used, but the processor does not automatically use or wait for these operations.
BDMA feature is used to load the first 32 program memory words from the
byte memory space. Program execution is held off until all 32 words have
been loaded. Chip is configured in Host Mode. IACK has active pulldown. (REQUIRES ADDITIONAL HARDWARE.)
IDMA feature is used to load any internal memory as desired. Program execution is held off until internal program memory location 0 is written to. Chip is
configured in Host Mode.6 IACK has active pull-down.
BDMA feature is used to load the first 32 program memory words from the
byte memory space. Program execution is held off until all 32 words have
been loaded. Chip is configured in Host Mode. IACK has active pulldown. (REQUIRES ADDITIONAL HARDWARE.)
IDMA feature is used to load any internal memory as desired. Program execution is held off until internal program memory location 0 is written to. Chip is
configured in Host Mode. IACK requires external pull-down.6
NOTES
1
All mode pins are recognized while RESET is active (low).
2
When Mode D = 0 and in host mode, IACK is an active, driven signal and cannot be “wire ORed”.
When Mode D = 1 and in host mode, IACK is an open source and requires an external pull-down, multiple IACK pins can be “wire ORed” together.
3
When Mode C = 0, Full Memory enabled. When Mode C = 1, Host Memory Mode enabled.
4
When Mode B = 0, Auto Booting enabled. When Mode B = 1, no Auto Booting.
5
When Mode A = 0, BDMA enabled. When Mode A = 1, IDMA enabled.
6
Considered as standard operating settings. Using these configurations allows for easier design and better memory management.
MODES OF OPERATION
allowing full use of the PF2 pin as either an input or output. To
minimize power consumption during power-down, configure
the programmable flag as an output when connected to a threestated buffer. This ensures that the pin will be held at a constant
level and not oscillate should the three-state driver’s level hover
around the logic switching point.
Table II summarizes the ADSP-2187L memory modes.
Setting Memory Mode
Memory Mode selection for the ADSP-2187L is made during
chip reset through the use of the Mode C pin. This pin is multiplexed with the DSP’s PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are active and passive.
MEMORY ARCHITECTURE
The ADSP-2187L provides a variety of memory and peripheral
interface options. The key functional groups are Program
Memory, Data Memory, Byte Memory, and I/O. Refer to the
following figures and tables for PM and DM memory allocations in the ADSP-2187L.
Passive configuration involves the use a pull-up or pull-down
resistor connected to the Mode C pin. To minimize power consumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down, on the order of
100 kΩ, can be used. This value should be sufficient to pull the
pin to the desired level and still allow the pin to operate as
a programmable flag output without undue strain on the
processor’s output driver. For minimum power consumption
during power-down, reconfigure PF2 to be an input, as the
pull-up or pull-down will hold the pin in a known state, and
will not switch.
PROGRAM MEMORY
Program Memory (Full Memory Mode) is a 24-bit-wide
space for storing both instruction opcodes and data. The ADSP2187L has 32K words of Program Memory RAM on chip, and
the capability of accessing up to two 8K external memory overlay spaces using the external data bus.
Active configuration involves the use of a three-statable external driver connected to the Mode C pin. A driver’s output
enable should be connected to the DSP’s RESET signal such
that it only drives the PF2 pin when RESET is active (low).
When RESET is deasserted, the driver should three-state, thus
IACK Configuration
Mode D = 0 and in host Mode: IACK is an active, driven signal
and cannot be “wire ORed.”
Mode D = 1 and in host mode: IACK is an open source and requires an external pull-down, but multiple IACK pins can be
“wire ORed” together.
–8–
REV. 0
ADSP-2187L
PM (MODE B = 0)
PM (MODE B = 1)1
ALWAYS
ACCESSIBLE
AT ADDRESS
030000 – 031FFF
ACCESSIBLE WHEN
PMOVLAY = 0
RESERVED
032000–
033FFF
ACCESSIBLE WHEN
PMOVLAY = 0
032000–
033FFF
032000–
033FFF
INTERNAL
RESERVED
MEMORY
032000–
030000–
INTERNAL ACCESSIBLE WHEN
RESERVED
033FFF
031FFF2
PMOVLAY = 4
MEMORY
032000–
ACCESSIBLE WHEN
ACCESSIBLE
WHEN
2
033FFF
PMOVLAY = 5
PMOVLAY = 1
032000–
EXTERNAL
ACCESSIBLE WHEN
RESERVED
033FFF2
MEMORY
PMOVLAY = 1
EXTERNAL
ACCESSIBLE WHEN
1WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0
MEMORY
PMOVLAY = 2
2SEE TABLE III FOR PMOVLAY BITS
PROGRAM MEMORY
MODE B = 0
ADDRESS
033FFF
PROGRAM MEMORY
MODE B = 1
ADDRESS
033FFF
8K INTERNAL
PMOVLAY = 0, 4, 5
OR
8K EXTERNAL
PMOVLAY = 1, 2
8K INTERNAL
PMOVLAY = 0
032000
031FFF
032000
031FFF
8K EXTERNAL
8K INTERNAL
030000
030000
Figure 4. Program Memory
Program Memory (Host Mode) allows access to all internal
memory. External overlay access is limited by a single external
address line (A0). External program execution is not available
in host mode due to a restricted data bus that is 16-bits wide
only.
DATA MEMORY
DATA MEMORY
32 MEMORY
MAPPED
REGISTERS
ALWAYS
ACCESSIBLE
AT ADDRESS
032000 – 033FFF
ACCESSIBLE WHEN
DMOVLAY = 0
030000–
031FFF
Table III. PMOVLAY Bits
INTERNAL
MEMORY
PMOVLAY Memory
A13
A12:0
0, 4, 5
1
Internal
External
Overlay 1
Not Applicable
0
2
External
Overlay 2
1
Not Applicable
13 LSBs of Address
Between 0x2000
and 0x3FFF
13 LSBs of Address
Between 0x2000
and 0x3FFF
ACCESSIBLE WHEN
DMOVLAY = 4
REV. 0
030000–
031FFF
ACCESSIBLE WHEN
DMOVLAY = 1
EXTERNAL
MEMORY
033FFF
033FE0
033FDF
032000
031FFF
8K INTERNAL
DMOVLAY = 0, 4, 5
OR
EXTERNAL 8K
DMOVLAY = 1, 2
030000–
031FFF
ACCESSIBLE WHEN
DMOVLAY = 5
030000
030000–
031FFF
ACCESSIBLE WHEN
DMOVLAY = 2
Figure 5. Data Memory Map
Data Memory (Host Mode) allows access to all internal memory.
External overlay access is limited by a single external address line
(A0). The DMOVLAY bits are defined in Table IV.
Table IV. DMOVLAY Bits
DATA MEMORY
Data Memory (Full Memory Mode) is a 16-bit-wide space
used for the storage of data variables and for memory-mapped
control registers. The ADSP-2187L has 32K words on Data
Memory RAM on chip, consisting of 16,352 user-accessible locations and 32 memory-mapped registers. Support also exists
for up to two 8K external memory overlay spaces through the
external data bus. All internal accesses complete in one cycle.
Accesses to external memory are timed using the wait states
specified by the DWAIT register.
INTERNAL
8160
WORDS
032000–
031FFF
ADDRESS
DMOVLAY
Memory
0, 4, 5
1
Internal
Not Applicable
External 0
Overlay 1
2
External 1
Overlay 2
–9–
A13
A12:0
Not Applicable
13 LSBs of Address
Between 0x2000
and 0x3FFF
13 LSBs of Address
Between 0x2000
and 0x3FFF
ADSP-2187L
I/O Space (Full Memory Mode)
Byte Memory
The ADSP-2187L supports an additional external memory
space called I/O space. This space is designed to support simple
connections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space supports 2048 locations of 16-bit wide data. The lower eleven bits
of the external address bus are used; the upper three bits are undefined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated 3-bit wait state
registers, IOWAIT0-3, that specify up to seven wait states to be
automatically generated for each of four regions. The wait states
act on address ranges as shown in Table V.
The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The BDMA Control Register is
shown in Figure 7. The byte memory space consists of 256 pages,
each of which is 16K × 8.
Table V. Wait States
The byte memory space on the ADSP-2187L supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.
This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be
used without glue logic. All byte memory accesses are timed by
the BMWAIT register.
Byte Memory DMA (BDMA, Full Memory Mode)
Address Range
Wait State Register
0x000–0x1FF
0x200–0x3FF
0x400–0x5FF
0x600–0x7FF
IOWAIT0
IOWAIT1
IOWAIT2
IOWAIT3
The Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space
while the processor is operating normally, and steals only one
DSP cycle per 8-, 16- or 24-bit word transferred.
15 14 13 12 11 10
Composite Memory Select (CMS)
0
The ADSP-2187L has a programmable memory select signal
that is useful for generating memory select signals for memories
mapped to more than one space. The CMS signal is generated
to have the same timing as each of the individual memory select
signals (PMS, DMS, BMS, IOMS) but can combine their
functionality.
2
1
0
1
1
1
SPORT0 ENABLE
1 = ENABLED, 0 = DISABLED
SPORT1 ENABLE
1 = ENABLED, 0 = DISABLED
SPORT1 CONFIGURE
1 = SERIAL PORT
0 = F1, FO, IRQ0, IRQ1, SCLK
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
4
3
2
1
0
0
1
0
0
0
DM (033FE3)
BTYPE
BDMA
OVERLAY
BITS
BDIR
0 = LOAD FROM BM
1 = STORE TO BM
The BDMA circuit supports four different data formats that are
selected by the BTYPE register field. The appropriate number
of 8-bit accesses are done from the byte memory space to build
the word size selected. Table VI shows the data formats supported by the BDMA circuit.
The ADSP-2187L also lets you boot the processor from one external memory space while using a different external memory
space for BDMA transfers during normal operation. You can
use the CMS to select the first external memory space for
BDMA transfers and BMS to select the second external
memory space for booting. The BMS signal can be disabled by
setting Bit 3 of the System Control Register to 1. The System
Control Register is illustrated in Figure 6.
0
0
Figure 7. BDMA Control Register
Boot Memory Select (BMS) Disable
0
0
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
The CMS pin functions like the other memory select signals,
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits default to 1 at reset, except the BMS bit.
0
0
BMPAGE
Each bit in the CMSSEL register, when set, causes the CMS
signal to be asserted when the selected memory select is asserted. For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in the
CMSSEL register and use the CMS pin to drive the chip select
of the memory; use either DMS or PMS as the additional
address bit.
SYSTEM CONTROL REGISTER
15 14 13 12 11 10 9 8 7 6 5 4 3
0
BDMA CONTROL
9 8 7 6 5
DM (033FFF)
PWAIT
PROGRAM MEMORY
WAIT STATES
Table VI. Data Formats
BTYPE
Internal
Memory Space
Word Size
Alignment
00
01
10
11
Program Memory
Data Memory
Data Memory
Data Memory
24
16
8
8
Full Word
Full Word
MSBs
LSBs
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external
byte memory space. The 8-bit BMPAGE register specifies the
starting page for the external byte memory space. The BDIR
register field selects the direction of the transfer. Finally the 14bit BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
BMS ENABLE
0 = ENABLED, 1 = DISABLED
Figure 6. System Control Register
–10–
REV. 0
ADSP-2187L
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT
register.
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is
completely asynchronous and can be written to while the
ADSP-2187L is operating at full speed.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is generated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.
The DSP memory address is latched and then automatically incremented after each IDMA transaction. An external device can
therefore access a block of sequentially addressed memory by
specifying only the starting address of the block. This increases
throughput as the address does not have to be sent for each
memory access.
The source or destination of a BDMA transfer will always be
on-chip program or data memory.
When the BWCOUNT register is written with a nonzero value,
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to
create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to external memory have priority over BDMA byte memory accesses.
The BDMA Context Reset bit (BCR) controls whether or not
the processor is held off while the BDMA accesses are occurring. Setting the BCR bit to 0 allows the processor to continue
operations. Setting the BCR bit to 1 causes the processor to
stop execution while the BDMA accesses are occurring, to clear
the context of the processor and start execution at address 0
when the BDMA accesses have completed.
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a
14-bit address and 1-bit destination type can be driven onto the
bus by an external device. The address specifies an on-chip
memory location; the destination type specifies whether it is a
DM or PM access. The falling edge of the address latch signal
latches this value into the IDMAA register.
Once the address is stored, data can either be read from or
written to the ADSP-2187L’s on-chip memory. Asserting the
select line (IS) and the appropriate read or write line (IRD and
IWR respectively) signals the ADSP-2187L that a particular
transaction is required. In either case, there is a one-processorcycle delay for synchronization. The memory access consumes
one additional processor cycle.
Once an access has occurred, the latched address is automatically incremented and another access can occur.
The BDMA overlay bits specify the OVLAY memory blocks to
be accessed for internal memory.
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation. Asserting
the IDMA port select (IS) and address latch enable (IAL) directs the ADSP-2187L to write the address onto the IAD0–14
bus into the IDMA Control Register. If IAD[15] is set to 0,
IDMA latches the address. If IAD[15] is set to 1, IDMA
latches OVLAY memory. The IDMA OVLAY and address are
stored in separate memory-mapped registers. The IDMAA register, shown below, is memory mapped at address DM (0x3FE0).
Note that the latched address (IDMAA) cannot be read back by
the host. The IDMA OVLAY register is memory mapped at
address DM (0x3FE7). See Figures 8 and 9 for more information on IDMA and DMA memory maps.
Internal Memory DMA Port (IDMA Port; Host Memory
Mode)
The IDMA Port provides an efficient means of communication
between a host system and the ADSP-2187L. The port is used
to access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot be used, however, to write to the DSP’s memorymapped control registers. A typical IDMA transfer process is
described as follows:
1. Host starts IDMA transfer.
2. Host checks IACK control line to see if the DSP is busy.
3. Host uses IS and IAL control lines to latch either the DMA
starting address (IDMAA) or the PM/DM OVLAY selection
into the DSP’s IDMA control registers.
IDMA OVERLAY
15 14 13 12 11 10
0
0
If IAD[15] = 1, the value of IAD[7:0] represent the IDMA
overlay: IAD[14:8] must be set to 0.
0
0
0
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0 DM(033FE7)
RESERVED
SET TO 0
If IAD[15] = 0, the value of IAD[13:0] represent the starting address of internal memory to be accessed and IAD[14]
reflects PM or DM for access.
ID DMOVLAY
ID PMOVLAY
IDMA CONTROL (U = UNDEFINED AT RESET)
4. Host uses IS and IRD (or IWR) to read (or write) DSP internal memory (PM or DM).
15 14 13 12 11 10
U
U
U
U
U
9
8
7
6
5
4
3
2
1
0
U
U
U
U
U
U
U
U
U
U DM(033FE0)
IDMAA
ADDRESS
IDMAD
DESTINATION MEMORY TYPE:
0 = PM
1 = DM
5. Host checks IACK line to see if the DSP has completed the
previous IDMA operation.
6. Host ends IDMA transfer.
Figure 8. IDMA Control/OVLAY Registers
REV. 0
–11–
ADSP-2187L
DMA
PROGRAM MEMORY
OVLAY
DMA
DATA MEMORY
OVLAY
ALWAYS
ACCESSIBLE
AT ADDRESS
030000 – 031FFF
ALWAYS
ACCESSIBLE
AT ADDRESS
032000 – 033FFF
ACCESSIBLE WHEN
PMOVLAY = 0
032000–
033FFF
032000–
033FFF
ACCESSIBLE WHEN
PMOVLAY = 4
032000–
033FFF
ACCESSIBLE WHEN
PMOVLAY = 5
ACCESSIBLE WHEN
DMOVLAY = 0
Bus Request and Bus Grant (Full Memory Mode)
The ADSP-2187L can relinquish control of the data and address buses to an external device. When the external device requires access to memory, it asserts the bus request (BR) signal.
If the ADSP-2187L is not performing an external memory access, it responds to the active BR input in the following processor cycle by:
030000–
031FFF
030000–
031FFF
ACCESSIBLE WHEN
DMOVLAY = 4
030000–
031FFF
• asserting the bus grant (BG) signal, and
ACCESSIBLE WHEN
DMOVLAY = 5
• halting program execution.
NOTE:
IDMA AND BDMA HAVE
SEPARATE DMA CONTROL REGISTERS
Figure 9. Direct Memory Access-PM and DM Memory Maps
Bootstrap Loading (Booting)
The ADSP-2187L has two mechanisms to allow automatic
loading of the internal program memory after reset. The method
for booting after reset is controlled by the Mode A, B and C
configuration bits.
When the mode pins specify BDMA booting, the ADSP-2187L
initiates a BDMA boot sequence when reset is released.
The BDMA interface is set up during reset to the following defaults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD and BEAD registers are set to 0, the BTYPE register is
set to 0 to specify program memory 24-bit words, and the
BWCOUNT register is set to 32. This causes 32 words of onchip program memory to be loaded from byte memory. These
32 words are used to set up the BDMA to load in the remaining
program code. The BCR bit is also set to 1, which causes program execution to be held off until all 32 words are loaded into
on-chip program memory. Execution then begins at address 0.
If the ADSP-2187L is performing an external memory access
when the external device asserts the BR signal, it will not threestate the memory interfaces or assert the BG signal until the
processor cycle after the access completes. The instruction does
not need to be completed when the bus is granted. If a single instruction requires two external memory accesses, the bus will be
granted between the two accesses.
The bus request feature operates at all times, including when
the processor is booting and when RESET is active.
The BGH pin is asserted when the ADSP-2187L is ready to execute an instruction, but is stopped because the external bus is
already granted to another device. The other device can release
the bus by deasserting bus request. Once the bus is released, the
ADSP-2187L deasserts BG and BGH and executes the external
memory access.
Flag I/O Pins
The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in Host Mode, the addresses to boot memory must be constructed externally to the
ADSP-2187L. The only memory address bit provided by the
processor is A0.
The ADSP-2187L can also boot programs through its Internal
DMA port. If Mode C = 1, Mode B = 0 and Mode A = 1, the
ADSP-2187L boots from the IDMA port. IDMA feature can
load as much on-chip memory as desired. Program execution is
held off until on-chip program memory location 0 is written to.
If Go Mode is enabled, the ADSP-2187L will not halt program
execution until it encounters an instruction that requires an external memory access.
When the BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program execution from the point at which it stopped.
The ADSP-2100 Family Development Software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space compatible boot code.
IDMA Port Booting
• three-stating the data and address buses and the PMS, DMS,
BMS, CMS, IOMS, RD, WR output drivers,
The ADSP-2187L has eight general purpose programmable
input/output flag pins. They are controlled by two memory
mapped registers. The PFTYPE register determines the direction, 1 = output and 0 = input. The PFDATA register is used to
read and write the values on the pins. Data being read from a
pin configured as an input is synchronized to the ADSP-2187L’s
clock. Bits that are programmed as outputs will read the value
being output. The PF pins default to input during reset.
In addition to the programmable flags, the ADSP-2187L has
five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and
FL2. FL0-FL2 are dedicated output flags. FLAG_IN and
FLAG_OUT are available as an alternate configuration of
SPORT1.
Note: Pins PF0, PF1, PF2 and PF3 are also used for device
configuration during reset.
–12–
REV. 0
ADSP-2187L
INSTRUCTION SET DESCRIPTION
The ADSP-2187L assembly language instruction set has an
algebraic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of
the processor’s unique architecture, offers the following benefits:
One method of ensuring that the values located on the mode
pins are those desired is to construct a circuit like the one shown
in Figure 10. This circuit forces the value located on the Mode
A pin to logic high; regardless if it latched via the RESET or
ERESET pin.
• The algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.
ERESET
RESET
ADSP-2187L
• Every instruction assembles into a single, 24-bit word that can
execute in a single instruction cycle.
• The syntax is a superset ADSP-2100 Family assembly language and is completely source and object code compatible
with other family members. Programs may need to be relocated to utilize on-chip memory and conform to the ADSP2187L’s interrupt vector and reset vector map.
MODE A/PFO
PROGRAMMABLE I/O
Figure 10. Mode A Pin/EZ-ICE Circuit
The ICE-Port interface consists of the following ADSP-2187L
pins:
• Sixteen condition codes are available. For conditional jump,
call, return or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
EBR
EMS
ELIN
• Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The ADSP-2187L has on-chip emulation support and an ICEPort, a special set of pins that interface to the EZ-ICE. These
features allow in-circuit emulation without replacing the target
system processor by using only a 14-pin connection from the
target system to the EZ-ICE. Target systems must have a 14-pin
connector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug.
See the ADSP-2100 Family EZ-Tools data sheet for complete information on ICE products.
Issuing the chip reset command during emulation causes the
DSP to perform a full chip reset, including a reset of its memory
mode. Therefore, it is vital that the mode pins are set correctly
PRIOR to issuing a chip reset command from the emulator user
interface. If you are using a passive method of maintaining
mode information (as discussed in Setting Memory Modes)
then it does not matter that the mode information is latched by
an emulator reset. However, if you are using the RESET pin as
a method of setting the value of the mode pins, then you have to
take into consideration the effects of an emulator reset.
REV. 0
1kV
EBG
EINT
ELOUT
ERESET
ECLK
EE
These ADSP-2187L pins must be connected only to the EZ-ICE
connector in the target system. These pins have no function except during emulation, and do not require pull-up or pull-down
resistors. The traces for these signals between the ADSP-2187L
and the connector must be kept as short as possible, no longer
than three inches.
The following pins are also used by the EZ-ICE:
BR
RESET
BG
GND
The EZ-ICE uses the EE (emulator enable) signal to take control of the ADSP-2187L in the target system. This causes the
processor to use its ERESET, EBR and EBG pins instead of the
RESET, BR and BG pins. The BG output is three-stated. These
signals do not need to be jumper-isolated in your system.
The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The ribbon cable is 10 inches in
length with one end fixed to the EZ-ICE. The female plug is
plugged onto the 14-pin connector (a pin strip header) on the
target board.
–13–
ADSP-2187L
Target Board Connector for EZ-ICE Probe
PM, DM, BM, IOM and CM
The EZ-ICE connector (a standard pin strip header) is shown in
Figure 11. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow enough
room in your system to fit the EZ-ICE probe onto the 14-pin
connector.
Design your Program Memory (PM), Data Memory (DM),
Byte Memory (BM), I/O Memory (IOM) and Composite
Memory (CM) external interfaces to comply with worst case
device timing requirements and switching characteristics as
specified in the DSP’s data sheet. The performance of the
EZ-ICE may approach published worst case specification for
some memory access timing requirements and switching
characteristics.
1
2
BG
GND
3
4
EBG
5
6
EBR
KEY (NO PIN)
Note: If your target does not meet the worst case chip specification for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. Depending on the severity of the specification violation, you may
have trouble manufacturing your system as DSP components
statistically vary in switching characteristic and timing requirements within published limits.
BR
EINT
7
8
9
10
3
ELIN
ELOUT
ECLK
11
Restriction: All memory strobe signals on the ADSP-2187L
(RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your
target system must have 10 kΩ pull-up resistors connected when
the EZ-ICE is being used. The pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. These resistors may be removed at
your option when the EZ-ICE is not being used.
12
EMS
EE
13
14
RESET
ERESET
TOP VIEW
Figure 11. Target Board Connector for EZ-ICE
The 14-pin, 2-row pin strip header is keyed at the Pin 7 location—you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spacing should be 0.1 × 0.1 inches. The pin strip header must have
at least 0.15 inch clearance on all sides to accept the EZ-ICE
probe plug.
Target System Interface Signals
When the EZ-ICE board is installed, the performance on some
system signals changes. Design your system to be compatible
with the following system interface signal changes introduced by
the EZ-ICE board:
• EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and the DSP on the RESET
signal.
Pin strip headers are available from vendors such as 3M,
McKenzie and Samtec.
Target Memory Interface
For your target system to be compatible with the EZ-ICE emulator, it must comply with the memory interface guidelines listed
below.
• EZ-ICE emulation introduces an 8 ns propagation delay between your target circuitry and the DSP on the BR signal.
• EZ-ICE emulation ignores RESET and BR when singlestepping.
• EZ-ICE emulation ignores RESET and BR when in Emulator
Space (DSP halted).
• EZ-ICE emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (BG) is asserted
by the EZ-ICE board’s DSP.
–14–
REV. 0
SPECIFICATIONS
ADSP-2187L
RECOMMENDED OPERATING CONDITIONS
K Grade
Parameter
VDD
TAMB
Supply Voltage
Ambient Operating Temperature
B Grade
Min
Max
Min
Max
Unit
3.0
0
3.6
+70
3.0
–40
3.6
+85
V
°C
ELECTRICAL CHARACTERISTICS
Parameter
VIH
VIH
VIL
VOH
Test Conditions
Hi-Level Input Voltage1, 2
Hi-Level CLKIN Voltage
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage 1, 4, 5
VOL
Lo-Level Output Voltage1, 4, 5
IIH
Hi-Level Input Current 3
IIL
Lo-Level Input Current3
IOZH
Three-State Leakage Current7
IOZL
Three-State Leakage Current7
IDD
Supply Current (Idle)9
IDD
Supply Current (Dynamic) 11
CI
Input Pin Capacitance3, 6, 12
CO
Output Pin Capacitance 6, 7, 12, 13
@ VDD = max
@ VDD = max
@ VDD = min
@ VDD = min
IOH = –0.5 mA
@ VDD = min
IOH = –100 µA 6
@ VDD = min
IOL = 2 mA
@ VDD = max
VIN = VDD max
@ VDD = max
VIN = 0 V
@ VDD = max
VIN = VDD max8
@ VDD = max
VIN = 0 V 8
@ VDD = 3.3
tCK = 19 ns10
tCK = 25 ns10
tCK = 30 ns10
@ VDD = 3.3
TAMB = +25°C
tCK = 19 ns10
tCK = 25 ns10
tCK = 30 ns10
@ VIN = 2.5 V
fIN = 1.0 MHz
TAMB = +25°C
@ VIN = 2.5 V
fIN = 1.0 MHz
TAMB = +25°C
␣␣␣␣␣
␣ K/B Grades
Min
Typ
Max
2.0
2.2
0.8
Unit
V
V
V
2.4
V
VDD – 0.3
V
0.4
V
10
µA
10
µA
10
µA
10
µA
10
8
7
mA
mA
mA
51
41
34
mA
mA
mA
8
pF
8
pF
NOTES
11 Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.
12 Input only pins: RESET, BR, DR0, DR1, PWD.
13 Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.
14 Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.
15 Although specified for TTL outputs, all ADSP-2187L outputs are CMOS-compatible and will drive to V
DD and GND, assuming no dc loads.
16 Guaranteed but not tested.
17 Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.
18 0 V on BR.
19 Idle refers to ADSP-2187L state of operation during execution of IDLE instruction. Deasserted pins are driven to either V
DD or GND.
10 V
IN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.
11 I
DD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2
and type 6, and 20% are idle instructions.
12 Applies to TQFP package type.
13 Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
REV. 0
–15–
ADSP-2187L
ABSOLUTE MAXIMUM RATINGS *
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Operating Temperature Range (Ambient) . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 sec) TQFP . . . . . . . . . . . . . . . . +280°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ESD SENSITIVITY
The ADSP-2187L is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readily
accumulate on the human body and equipment and can discharge without detection. Permanent
damage may occur to devices subjected to high energy electrostatic discharges.
The ADSP-2187L features proprietary ESD protection circuitry to dissipate high energy discharges
(Human Body Model). Per method 3015 of MIL-STD-883, the ADSP-2187L has been classified
as a Class 1 device.
WARNING!
ESD SENSITIVE DEVICE
Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Unused devices must be stored in conductive foam or shunts, and the foam should be
discharged to the destination before devices are removed.
MEMORY TIMING SPECIFICATIONS
TIMING PARAMETERS
GENERAL NOTES
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.
TIMING NOTES
Switching Characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a
device connected to the processor (such as memory) is satisfied.
Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
The table below shows common memory device specifications
and the corresponding ADSP-2187L timing parameters, for
your convenience.
Memory
Device
Specification
ADSP-2187L
Timing
Parameter
Timing
Parameter
Definition
Address Setup to
Write Start
Address Setup to
Write End
Address Hold Time
tASW
tAW
Data Setup Time
Data Hold Time
OE to Data Valid
Address Access Time
tDW
tDH
tRDD
tAA
A0–A13, xMS Setup before
WR Low
A0–A13, xMS Setup before
WR Deasserted
A0–A13, xMS Hold before
WR Low
Data Setup before WR High
Data Hold after WR High
RD Low to Data Valid
A0–A13, xMS to Data Valid
tWRA
xMS = PMS, DMS, BMS, CMS, IOMS.
FREQUENCY DEPENDENCY FOR TIMING
SPECIFICATIONS
tCK = Instruction Clock Period. tCKI = External Clock Period.
tCK is defined as 0.5tCKI. The ADSP-2187L uses an input clock
with a frequency equal to half the instruction rate: a 26 MHz
input clock (which is equivalent to 38 ns) yields a 19 ns processor
cycle (equivalent to 52 MHz). tCK values within the range of
0.5tCKI period should be substituted for all relevant timing
parameters to obtain the specification value.
Example: tCKH = 0.5tCK – 7 ns = 0.5 (19 ns) – 7 ns = 2.5 ns
–16–
REV. 0
ADSP-2187L
OUTPUT DRIVE CURRENTS
Figure 12 shows typical I-V characteristics for the output drivers
of the ADSP-2187L. The curves represent the current drive
capability of the output drivers as a function of output voltage.
Total Power Dissipation = PINT + (C × VDD2 × f )
PINT = internal power dissipation from Power vs. Frequency
graph, see Figure 14.
(C × VDD 2 × f ) is calculated for each output:
80
SOURCE CURRENT – mA
# of
Pins × C
3.6V, –408C
60
3.3V, +258C
Address, DMS
Data Output, WR
RD
CLKOUT
40
20
3.0V, +858C
0
× 10 pF
× 10 pF
× 10 pF
× 10 pF
8
9
1
1
×f
× 3.3
× 3.3 2
× 3.3 2
× 3.3 2
× 33.3 MHz
× 16.67 MHz
× 16.67 MHz
× 33.3 MHz
2
V
V
V
V
3.0V, +858C
–20
= 29.0 mW
= 16.3 mW
= 1.8 mW
= 3.6 mW
50.7 mW
Total power dissipation for this example is PINT + 50.7 mW.
3.3V, +258C
2187L POWER, INTERNAL1, 3, 4
–40
250
–60
3.6V, –408C
216mW
200
0
0.5
1
1.5
2
2.5
3
SOURCE VOLTAGE – Volts
3.5
4
POWER – mW
–80
× VDD 2
Figure 12. Typical Drive Currents
Figure 13 shows the typical power-down supply current.
VDD = 3.6V
168.3mW
VDD = 3.3V
150
144mW
100 112.2mW
132mW
VDD = 3.0V
87mW
50
VDD = 3.6V
VDD = 3.3V
VDD = 3.0V
0
52
33.3
FREQUENCY – MHz
100
POWER, IDLE1, 2, 3
45
40
35mW
VDD = 3.6V
35
10
POWER – mW
CURRENT (LOG SCALE) – mA
1000
0
0
25
55
85
30
VDD = 3.3V
25mW
30mW
25
20
21mW
23mW
32mW
VDD = 3.0V
15
TEMPERATURE – 8C
10
NOTES:
1. REFLECTS ADSP-2187L OPERATION IN LOWEST POWER MODE.
(SEE "SYSTEM INTERFACE" CHAPTER OF THE ADSP-2100 FAMILY
USER'S MANUAL FOR DETAILS.)
2. CURRENT REFLECTS DEVICE OPERATING WITH NO INPUT LOADS.
5
0
33.33
52
FREQUENCY – MHz
POWER, IDLE n MODES3
Figure 13. Power-Down Supply Current (Typical)
45
40
POWER DISSIPATION
35
POWER – mW
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C × VDD2 × f
C = load capacitance, f = output switching frequency.
In an application where external data memory is used and no other
outputs are active, power dissipation is calculated as follows:
Assumptions:
•
External data memory is accessed every cycle with 50% of the
address pins switching.
•
External data memory writes occur every other cycle with
50% of the data pins switching.
•
•
Each address and data pin has a 10 pF total load at the pin.
The application operates at VDD = 3.3 V and tCK = 34.7 ns.
IDLE
25
20
23mW
15
13mW
10mW
Example:
REV. 0
32mW
30
10
12mW
9mW
IDLE (16)
IDLE (128)
5
8
33.33
52
FREQUENCY – MHz
VALID FOR ALL TEMPERATURE GRADES.
1POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2IDLE REFERS TO ADSP-2187L STATE OF OPERATION DURING EXECUTION OF IDLE
INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND.
3TYPICAL POWER DISSIPATION AT 3.3V V
DD AND 258C EXCEPT WHERE SPECIFIED.
4I
DD MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL
MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14),
30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.
Figure 14. Power vs. Frequency
–17–
ADSP-2187L
CAPACITIVE LOADING
Figures 15 and 16 show the capacitive loading characteristics of
the ADSP-2187L.
INPUT
OR
OUTPUT
T = +858C
VDD = 3.0V
RISE TIME (0.4V – 2.4V) – ns
Output Enable Time
14
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when
the output has reached a specified high or low trip point, see
Figure 18. If multiple pins (such as the data bus) are enabled,
the measurement value is that of the first pin to start driving.
12
10
8
6
4
2
0
REFERENCE
SIGNAL
0
50
100
150
CL – pF
200
tMEASURED
250
tENA
VOH
(MEASURED)
Figure 15. Typical Output Rise Time vs. Load Capacitance,
CL (at Maximum Ambient Operating Temperature)
tDIS
VOH
(MEASURED)
OUTPUT
VOH (MEASURED) – 0.5V
2.0V
VOL (MEASURED) +0.5V
1.0V
VOL
(MEASURED)
10
9
8
VALID OUTPUT DELAY
OR HOLD – ns
1.5V
Figure 17. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
18
16
1.5V
VOL
(MEASURED)
tDECAY
OUTPUT STARTS
DRIVING
OUTPUT STOPS
DRIVING
7
6
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
5
4
Figure 18. Output Enable/Disable
3
2
IOL
1
NOMINAL
–1
–2
–3
–4
0
20
40
60
80
100 120
CL – pF
140
160
180
TO
OUTPUT
PIN
200
+1.5V
50pF
Figure 16. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
IOH
Figure 19. Equivalent Device Loading for AC Measurements (Including All Fixtures)
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured output high or low voltage to a high impedance state, see Figure
17. The output disable time (tDIS) is the difference between
tMEASURED and tDECAY, see Figure 18. The time is the interval
from when a reference signal reaches a high or low voltage level
to when the output voltages have changed by 0.5 V from the
measured output high or low voltage. The decay time, tDECAY, is
dependent on the capacitive load, CL, and the current load, iL,
on the output pin. It can be approximated by the following
equation:
t DECAY =
CL • 0.5V
iL
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating is shown below:
TAMB = TCASE – (PD × θ CA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θ CA = Thermal Resistance (Case-to-Ambient)
θ J A = Thermal Resistance (Junction-to-Ambient)
θ J C = Thermal Resistance (Junction-to-Case)
Package
θJA
θJC
θCA
TQFP
50°C/W
2°C/W
48°C/W
from which
t DIS = t MEASURED – t DECAY
is calculated. If multiple pins (such as the data bus) are disabled,
the measurement value is that of the last pin to stop driving.
–18–
REV. 0
ADSP-2187L
TIMING PARAMETERS (See page 16, Frequency Depending for Timing Specifications, for timing definitions.)
Parameter
Min
Max
Timing Requirements:
tCKI
CLKIN External Clock Period
CLKIN Width Low
tCKIL
CLKIN Width High
tCKIH
38
15
15
100
Switching Characteristics:
CLKOUT Width Low
tCKL
CLKOUT Width High
tCKH
CLKIN High to CLKOUT High
tCKOH
0.5tCK – 7
0.5tCK – 7
0
Unit
Clock Signals and Reset
20
ns
ns
ns
ns
ns
ns
Control Signals
Timing Requirement:
RESET Width Low
tRSP
Mode Setup before RESET High
tMS
tMH
Mode Hold after RESET High
5tCK1
2
5
ns
ns
ns
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
PF(3:0)*
tMS
tMH
RESET
*PF3 IS MODE D, PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A
Figure 20. Clock Signals
REV. 0
–19–
ADSP-2187L
Parameter
Min
Max
Unit
Interrupts and Flag
Timing Requirements:
tIFS
IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4
IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4
tIFH
0.25tCK + 15
0.25tCK
Switching Characteristics:
Flag Output Hold after CLKOUT Low5
tFOH
tFOD
Flag Output Delay from CLKOUT Low5
ns
ns
0.5tCK – 7
0.15tCK + 6
ns
ns
NOTES
1
If IRQx and FI inputs meet t IFS and t IFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)
2
Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.
4
PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
5
Flag outputs = PFx, FL0, FL1, FL2, Flag_out4.
tFOD
CLKOUT
tFOH
FLAG
OUTPUTS
tIFH
IRQx
FI
PFx
tIFS
Figure 21. Interrupts and Flags
–20–
REV. 0
ADSP-2187L
Parameter
Min
Max
Unit
Bus Request–Bus Grant
Timing Requirements:
tBH
BR Hold after CLKOUT High1
BR Setup before CLKOUT Low1
tBS
0.25tCK + 2
0.25tCK + 17
Switching Characteristics:
CLKOUT High to xMS, RD, WR Disable
tSD
xMS, RD, WR Disable to BG Low
tSDB
BG High to xMS, RD, WR Enable
tSE
xMS, RD, WR Enable to CLKOUT High
tSEC
xMS, RD, WR Disable to BGH Low2
tSDBH
tSEH
BGH High to xMS, RD, WR Enable 2
0
0
0.25tCK – 4
0
0
ns
ns
0.25tCK + 10
ns
ns
ns
ns
ns
ns
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.
1
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition for BR/BG cycle relationships.
2
BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
WR
BG
BGH
tSD
tSEC
tSDB
tSE
tSDBH
tSEH
Figure 22. Bus Request–Bus Grant
REV. 0
–21–
ADSP-2187L
Parameter
Min
Max
Unit
0.5tCK – 9 + w
0.75tCK – 12.5 + w
ns
ns
ns
Memory Read
Timing Requirements:
tRDD
RD Low to Data Valid
A0–A13, xMS to Data Valid
tAA
Data Hold from RD High
tRDH
0
Switching Characteristics:
RD Pulsewidth
tRP
CLKOUT High to RD Low
tCRD
A0–A13, xMS Setup before RD Low
tASR
A0–A13, xMS Hold after RD Deasserted
tRDA
tRWR
RD High to RD or WR Low
0.5tCK – 5 + w
0.25tCK – 5
0.25tCK – 6
0.25tCK – 3
0.5tCK – 5
0.25tCK + 7
ns
ns
ns
ns
ns
w = wait states x t CK
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
A0–A13
DMS, PMS,
BMS, IOMS,
CMS
tRDA
RD
tASR
tRP
tCRD
tRWR
D
tAA
tRDD
tRDH
WR
Figure 23. Memory Read
–22–
REV. 0
ADSP-2187L
Parameter
Min
Max
Unit
Memory Write
Switching Characteristics:
tDW
Data Setup before WR High
Data Hold after WR High
tDH
WR Pulsewidth
tWP
WR Low to Data Enabled
tWDE
A0–A13, xMS Setup before WR Low
tASW
Data Disable before WR or RD Low
tDDR
CLKOUT High to WR Low
tCWR
A0–A13, xMS, Setup before Deasserted
tAW
A0–A13, xMS Hold after WR Deasserted
tWRA
tWWR
WR High to RD or WR Low
0.5tCK – 7 + w
0.25tCK – 2
0.5tCK – 5 + w
0
0.25tCK – 6
0.25tCK – 7
0.25tCK – 5
0.75tCK – 9 + w
0.25tCK – 3
0.5tCK – 5
0.25 tCK + 7
w = wait states x t CK.
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
A0–A13
DMS, PMS,
BMS, CMS,
IOMS
tWRA
WR
tASW
tWWR
tWP
tAW
tDH
tCWR
D
tDW
tWDE
RD
Figure 24. Memory Write
REV. 0
–23–
tDDR
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADSP-2187L
Parameter
Min
Max
Unit
Serial Ports
Timing Requirements:
tSCK
SCLK Period
DR/TFS/RFS Setup before SCLK Low
tSCS
DR/TFS/RFS Hold after SCLK Low
tSCH
SCLKIN Width
tSCP
38
4
7
15
Switching Characteristics:
CLKOUT High to SCLKOUT
tCC
SCLK High to DT Enable
tSCDE
SCLK High to DT Valid
tSCDV
TFS/RFSOUT Hold after SCLK High
tRH
TFS/RFSOUT Delay from SCLK High
tRD
DT Hold after SCLK High
tSCDH
TFS (Alt) to DT Enable
tTDE
TFS (Alt) to DT Valid
tTDV
SCLK High to DT Disable
tSCDD
tRDV
RFS (Multichannel, Frame Delay Zero) to DT Valid
CLKOUT
tCC
ns
ns
ns
ns
0.25tCK
0
0.25tCK + 10
15
0
15
0
0
14
15
15
tCC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSCK
SCLK
tSCP
tSCS
tSCP
tSCH
DR
TFSIN
RFSIN
tRD
tRH
RFSOUT
TFSOUT
tSCDD
tSCDV
tSCDH
tSCDE
DT
tTDE
tTDV
TFSOUT
ALTERNATE
FRAME MODE
tRDV
RFSOUT
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)
tTDE
tTDV
TFSIN
ALTERNATE
FRAME MODE
tRDV
RFSIN
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)
Figure 25. Serial Ports
–24–
REV. 0
ADSP-2187L
Parameter
Min
Max
Unit
IDMA Address Latch
Timing Requirements:
tIALP
Duration of Address Latch1, 2
IAD15–0 Address Setup before Address Latch End2
tIASU
IAD15–0 Address Hold after Address Latch End2
tIAH
IACK Low before Start of Address Latch2, 3
tIKA
Start of Write or Read after Address Latch End2, 3
tIALS
tIALD
Address Latch Start after Address Latch End1, 2
10
5
2
0
3
2
ns
ns
ns
ns
ns
ns
NOTES
1
Start of Address Latch = IS Low and IAL High.
2
End of Address Latch = IS High or IAL Low.
3
Start of Write or Read = IS Low and IWR Low or IRD Low.
IACK
tIKA
tIALD
IAL
tIALP
tIALP
IS
IAD15–0
tIASU
tIAH
tIASU
RD OR WR
Figure 26. IDMA Address Latch
REV. 0
–25–
tIAH
tIALS
ADSP-2187L
Parameter
Min
Max
Unit
IDMA Write, Short Write Cycle
Timing Requirements:
tIKW
IACK Low before Start of Write1
Duration of Write1, 2
tIWP
IAD15–0 Data Setup before End of Write2, 3, 4
tIDSU
IAD15–0 Data Hold after End of Write2, 3, 4
tIDH
0
15
5
2
Switching Characteristic:
tIKHW
Start of Write to IACK High
4
ns
ns
ns
ns
15
ns
NOTES
1
Start of Write = IS Low and IWR Low.
2
End of Write = IS High or IWR High.
3
If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH .
4
If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH .
tIKW
IACK
tIKHW
IS
tIWP
IWR
tIDSU
IAD15–0
tIDH
DATA
Figure 27. IDMA Write, Short Write Cycle
–26–
REV. 0
ADSP-2187L
Parameter
Min
Max
Unit
IDMA Write, Long Write Cycle
Timing Requirements:
tIKW
IACK Low before Start of Write1
IAD15–0 Data Setup before IACK Low2, 3, 4
tIKSU
IAD15–0 Data Hold after IACK Low2, 3, 4
tIKH
0
0.5tCK + 10
2
Switching Characteristics:
Start of Write to IACK Low4
tIKLW
tIKHW
Start of Write to IACK High
1.5tCK
4
ns
ns
ns
15
ns
ns
NOTES
1
Start of Write = IS Low and IWR Low.
2
If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH .
3
If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH .
4
This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual, Third Edition.
tIKW
IACK
tIKHW
tIKLW
IS
IWR
tIKSU
tIKH
DATA
IAD15–0
Figure 28. IDMA Write, Long Write Cycle
REV. 0
–27–
ADSP-2187L
Parameter
Min
Max
Unit
IDMA Read, Long Read Cycle
Timing Requirements:
tIKR
IACK Low before Start of Read1
End of Read after IACK Low2
tIRK
0
2
Switching Characteristics:
IACK High after Start of Read1
tIKHR
IAD15–0 Data Setup before IACK Low
tIKDS
IAD15–0 Data Hold after End of Read2
tIKDH
IAD15–0 Data Disabled after End of Read2
tIKDD
IAD15–0 Previous Data Enabled after Start of Read
tIRDE
IAD15–0 Previous Data Valid after Start of Read
tIRDV
IAD15–0 Previous Data Hold after Start of Read (DM/PM1)3
tIRDH1
tIRDH2
IAD15–0 Previous Data Hold after Start of Read (PM2)4
ns
ns
4
0.5tCK – 7
0
15
10
0
10
2tCK – 5
tCK – 5
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1
Start of Read = IS Low and IRD Low.
2
End of Read = IS High or IRD High.
3
DM read or first half of PM read.
4
Second half of PM read.
IACK
tIKHR
tIKR
IS
tIRK
IRD
tIKDH
tIKDS
tIRDE
PREVIOUS
DATA
IAD15–0
READ
DATA
tIRDV
tIKDD
tIRDH
Figure 29. IDMA Read, Long Read Cycle
–28–
REV. 0
ADSP-2187L
Parameter
Min
Max
Unit
IDMA Read, Short Read Cycle
Timing Requirements:
tIKR
IACK Low before Start of Read1
Duration of Read
tIRP
0
15
Switching Characteristics:
IACK High after Start of Read1
tIKHR
IAD15–0 Data Hold after End of Read2
tIKDH
IAD15–0 Data Disabled after End of Read2
tIKDD
IAD15–0 Previous Data Enabled after Start of Read
tIRDE
tIRDV
IAD15–0 Previous Data Valid after Start of Read
ns
ns
4
0
15
10
0
10
NOTES
1
Start of Read = IS Low and IRD Low.
2
End of Read = IS High or IRD High.
IACK
tIKR
tIKHR
IS
tIRP
IRD
tIRDE
tIKDH
PREVIOUS
DATA
IAD15–0
tIRDV
tIKDD
Figure 30. IDMA Read, Short Read Cycle
REV. 0
–29–
ns
ns
ns
ns
ns
ADSP-2187L
76 D16
77 D17
79 D19
78 D18
81 D20
80 GND
82 D21
84 D23
83 D22
86 FL1
85 FL2
87 FL0
89 PF2 [MODE C]
88 PF3 [MODE D]
91 PWD
90 VDD
94 PF0 [MODE A]
93 PF1 [MODE B]
92 GND
96 PWDACK
95 BGH
97 A0
99 A2/IAD1
98 A1/IAD0
100 A3/IAD2
100-Lead TQFP Package Pinout
75 D15
74 D14
1
A4/IAD3
A5/IAD4
2
PIN 1
IDENTIFIER
GND
3
73 D13
A6/IAD5
A7/IAD6
4
5
72 D12
71 GND
A8/IAD7
A9/IAD8
6
7
70 D11
69 D10
A10/IAD9
8
68 D9
A11/IAD10 9
A12/IAD11 10
67 VDD
66 GND
A13/IAD12 11
GND 12
65 D8
64 D7/IWR
63 D6/IRD
ADSP-2187L
CLKIN 13
TOP VIEW
(Not to Scale)
XTAL 14
VDD 15
62 D5/IAL
61 D4/IS
60 GND
59 VDD
58 D3/IACK
CLKOUT 16
GND 17
VDD 18
WR 19
RD 20
57 D2/IAD15
56 D1/IAD14
BMS 21
DMS 22
55 D0/IAD13
54 BG
53 EBG
PMS 23
52 BR
51 EBR
–30–
EINT 50
ELIN 49
ECLK 47
ELOUT 48
EMS 45
EE 46
RESET 44
SCLK1 42
ERESET 43
GND 41
DR1 40
RFS1 39
DT1 37
TFS1 38
VDD 36
DR0 34
SCLK0 35
TFS0 32
RFS0 33
IRQ2+PF7 30
DT0 31
IRQL1+PF6 29
IRQE+PF4 26
IRQL0+PF5 27
GND 28
IOMS 24
CMS 25
REV. 0
ADSP-2187L
The ADSP-2187L package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when
Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in
brackets [␣ ] are state bits latched from the value of the pin at the deassertion of RESET.
TQFP Pin Configurations
TQFP
Number
Pin
Name
TQFP
Number
Pin
Name
TQFP
Number
Pin
Name
TQFP
Number
Pin
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
A4/IAD3
A5/IAD4
GND
A6/IAD5
A7/IAD6
A8/IAD7
A9/IAD8
A10/IAD9
A11/IAD10
A12/IAD11
A13/IAD12
GND
CLKIN
XTAL
VDD
CLKOUT
GND
VDD
WR
RD
BMS
DMS
PMS
IOMS
CMS
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
IRQE + PF4
IRQL0 + PF5
GND
IRQL1 + PF6
IRQ2 + PF7
DT0
TFS0
RFS0
DR0
SCLK0
VDD
DT1
TFS1
RFS1
DR1
GND
SCLK1
ERESET
RESET
EMS
EE
ECLK
ELOUT
ELIN
EINT
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
EBR
BR
EBG
BG
D0/IAD13
D1/IAD14
D2/IAD15
D3/IACK
VDD
GND
D4/IS
D5/IAL
D6/IRD
D7/IWR
D8
GND
VDD
D9
D10
D11
GND
D12
D13
D14
D15
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
D16
D17
D18
D19
GND
D20
D21
D22
D23
FL2
FL1
FL0
PF3 [Mode D]
PF2 [Mode C]
VDD
PWD
GND
PF1 [Mode B]
PF0 [Mode A]
BGH
PWDACK
A0
A1/IAD0
A2/IAD1
A3/IAD2
REV. 0
–31–
ADSP-2187L
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C3174–3–7/98
100-Lead Metric Thin Plastic Quad Flatpack (TQFP)
(ST-100)
0.640 (16.25)
0.630 (16.00) TYP SQ
0.620 (15.75)
0.555 (14.10)
0.551 (14.00) TYP SQ
0.547 (13.90)
0.063 (1.60) MAX
0.030 (0.75)
0.024 (0.60) TYP
0.020 (0.50)
12
TYP
100
1
76
75
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.004
(0.102)
MAX LEAD
COPLANARITY
25
68 ± 48
51
50
26
08 – 78
0.020 (0.50)
0.007 (0.177)
BSC
0.005 (0.127) TYP
0.003 (0.077)
LEAD PITCH*
0.011 (0.27)
0.009 (0.22) TYP
0.007 (0.17)
LEAD WIDTH
*THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.0032 (0.08) FROM ITS
IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION. CENTER
FIGURE ARE TYPICAL UNLESS OTHERWISE NOTED.
ORDERING GUIDE
Part Number
Ambient
Temperature
Range
Instruction
Rate
(MHz)
Package
Description
Package
Option*
ADSP-2187LKST-160
ADSP-2187LBST-160
ADSP-2187LKST-210
ADSP-2187LBST-210
0°C to +70°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
40
40
52
52
100-Lead TQFP
100-Lead TQFP
100-Lead TQFP
100-Lead TQFP
ST-100
ST-100
ST-100
ST-100
PRINTED IN U.S.A.
*ST = Plastic Thin Quad Flatpack (TQFP).
–32–
REV. 0