LINER LTC4312 Pin-selectable, 2-channel, 2-wire multiplexer with bus buffer Datasheet

LTC4312
Pin-Selectable, 2-Channel,
2-Wire Multiplexer
with Bus Buffers
DESCRIPTION
FEATURES
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The LTC®4312 is a hot-swappable 2-channel 2-wire bus
multiplexer that allows one upstream bus to connect to
any combination of downstream busses or channels.
An individual enable pin controls each connection. The
LTC4312 provides bidirectional buffering, keeping the upstream bus capacitance isolated from the downstream bus
capacitances. The high noise margin allows the LTC4312
to be interoperable with I2C devices that drive a high VOL
(> 0.4V). The LTC4312 supports level translation between
1.5V, 1.8V, 2.5V, 3.3V and 5V busses. The hot-swappable
nature of the LTC4312 allows I/O card insertion into, and
removal from, a live backplane without corruption of the
data and clock busses.
1:2 Multiplexer/Switch for 2-Wire Bus
Bidirectional Buffer for SDA and SCL Lines
High Noise Margin with VIL = 0.3•VCC
ENABLE Pins Connect SDA and SCL Lines
Selectable Rise Time Accelerator Current and
Activation Voltage
Level Shift 1.5V, 1.8V, 2.5V, 3.3V and 5V Busses
Prevents SDA and SCL Corruption During Live Board
Insertion and Removal from Backplane
Stuck Bus Disconnect and Recovery
Compatible with I2C, I2C Fast Mode and SMBus
±4kV Human Body Model (HBM) ESD Ruggedness
14-Lead 4mm × 3mm DFN and 16-Lead MSOP
Packages
If both data and clock are not simultaneously high at
least once in 45ms and DISCEN is high, a FAULT signal is
generated indicating a stuck bus low condition, the input
is disconnected from each enabled output channel and up
to 16 clocks are generated on the enabled downstream
busses. A three state ACC pin enables input and output
side rise time accelerators of varying strengths and sets
the VIL,RISING voltage.
APPLICATIONS
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Telecommunications Systems Including ATCA
Address Expansion
Level Translator
Capacitance Buffers/Bus Extender
Live Board Insertion
PMBus
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents, including
6356140, 6650174, 7032051, 7478286.
TYPICAL APPLICATION
0.01μF
10k
10k
3.3V
VCC2
VCC
SCLIN
SCLIN
SDAIN
SDAIN
Rising Edge from Asserted Low
with Level Translation
10k
10k
0.01μF
6V
ENABLE1
ENABLE1
SCLOUT1
SCLOUT1
ENABLE2
ENABLE2
SDAOUT1
SDAOUT1
5V
3.3V
LTC4312
10k
10k
FAULT
1V/DIV
3.3V
CSCLOUT1 + CSCLOUT2 = 100pF
CSCLIN = 50pF
SCLOUT2
SCLOUT1
5V
3.3V
SCLIN
10k
ACC
SCLOUT2
SCLOUT2
DISCEN
SDAOUT2
SDAOUT2
0V
FAULT
GND
200ns/DIV
4312 TA01b
4314 TA01a
4312f
1
LTC4312
ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage
VCC, VCC2 ................................................. –0.3V to 6V
Input Voltages
ACC, DISCEN, ENABLE1-2 ....................... –0.3V to 6V
Input/Output Voltages
SDAIN, SCLIN, SCLOUT1-2,
SDAOUT1-2, FAULT ................................. –0.3V to 6V
Output DC Sink Currents
FAULT.................................................................50mA
Operating Ambient Temperature Range
LTC4312C ................................................ 0°C to 70°C
LTC4312I..............................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
MSOP .............................................................. 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
VCC
1
14 DISCEN
SCLOUT1
2
13 ACC
SDAOUT1
3
SDAIN
4
SCLIN
5
10 FAULT
SCLOUT2
6
9
ENABLE1
SDAOUT2
7
8
ENABLE2
DISCEN
VCC
SCLOUT1
SDAOUT1
SDAIN
SCLIN
SCLOUT2
SDAOUT2
12 GND
15
11 VCC2
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
ACC
GND
NC
NC
VCC2
FAULT
ENABLE1
ENABLE2
MS PACKAGE
16-LEAD PLASTIC MSOP
DE14 PACKAGE
14-LEAD (4mm = 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 120°C/W, θJC = 21°C/W
TJMAX = 125°C, θJA = 43°C/W, θJC = 5°C/W
EXPOSED PAD (PIN #15) PCB CONNECTION TO GND IS OPTIONAL
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC4312IDE#PBF
LTC4312IDE#TRPBF
4312
14-Lead (4mm × 3mm) DFN
–40°C to 85°C
LTC4312IMS#PBF
LTC4312IMS#TRPBF
4312
16-Lead Plastic MSOP
–40°C to 85°C
LTC4312CDE#PBF
LTC4312CDE#TRPBF
4312
14-Lead (4mm × 3mm) DFN
0°C to 70°C
LTC4312CMS#PBF
LTC4312CMS#TRPBF
4312
16-Lead Plastic MSOP
0°C to 70°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
4312f
2
LTC4312
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = VCC2 = 3.3V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power Supply/Start-Up
VCC
Input Supply Range
l
2.9
5.5
V
VDD, BUS
2-Wire Bus Supply Voltage
l
2.25
5.5
V
VCC2
Output Side Accelerator Supply
Range
l
2.25
5.5
V
ICC
Input Supply Current
One or Both VENABLE1-2 = VCC = VCC2 = 5.5V (Note 3) l
6.0
7.3
9
mA
ICC(DISABLED)
Input Supply Current
VENABLE1-2 = 0V; VCC = VCC2 = 5.5V (Note 3)
l
1.6
2.2
3.5
mA
One or Both VENABLE1-2 = VCC = VCC2 = 5.5V (Note 3) l
0.35
0.5
0.6
mA
60
110
200
μs
2.3
2.6
V
ICC2
VCC2 Supply Current
tUVLO
UVLO Delay
l
VTH_UVLO
UVLO Threshold
l
VCC_UVLO(HYST) UVLO Threshold Hysteresis
Voltage
200
mV
Buffers
VOS1(SAT)
Buffer Offset Voltage
VOS2(SAT)
Buffer Offset Voltage
VOS
Buffer Offset Voltage
VOS2
Buffer Offset Voltage
IOL = 4mA, Driven VSDAIN,SCLIN = 50mV
l
130
IOL = 500μA, Driven VSDAIN,SCLIN = 50mV
l
IOL = 4mA, Driven VSDAOUT,SCLOUT = 50mV
l
IOL = 500μA, Driven VSDAOUT,SCLOUT = 50mV
l
IOL = 4mA, Driven VSDAIN,SCLIN = 200mV
l
IOL = 500μA, Driven VSDAIN,SCLIN = 200mV
220
280
mV
15
60
120
mV
90
190
260
mV
15
55
110
mV
50
130
195
mV
l
15
55
110
mV
IOL = 4mA, Driven VSDAOUT,SCLOUT = 200mV
l
35
95
170
mV
IOL = 500μA, Driven VSDAOUT,SCLOUT = 200mV
l
15
50
100
mV
VIL,FALLING
Buffer Input Logic Low Voltage
SDA, SCL Pins (Notes 4, 5)
l
VIL,RISING
Buffer Input Logic Low Voltage
SDA, SCL Pins; ACC Grounded
l
SDA, SCL Pins; ACC Open or High (Notes 4, 5)
l
l
ILEAK
Input Leakage Current
SDA, SCL Pins; VCC , VCC2 = 0V, 5.5V
CIN
Input Capacitance
SDA, SCL Pins (Note 6)
0.3•VMIN 0.33•VMIN 0.36•VMIN
0.5
0.6
0.7
0.3•VMIN 0.33•VMIN 0.36•VMIN
V
V
V
±10
μA
<20
pF
Rise Time Accelerators
l
0.1
0.2
0.4
V/μs
SDA, SCL Pins; VCC = VCC2 = 5V, ACC Grounded
l
0.7
0.8
0.9
V
ACC Open or High, VCC = VCC2 = 5V (Note 4)
l 0.36•VMIN 0.4•VMIN 0.44•VMIN
SDA, SCL Pins; VCC = VCC2 = 5V, ACC Grounded
l
ACC Open, VCC = VCC2 = 5V (Note 4)
l 0.05•VMIN 0.07•VMIN
SDA, SCL Pins; VCC = VCC2 = 5V, ACC Grounded
(Note 7)
l
20
35
45
mA
ACC Open, VCC = VCC2 = 5V (Note 7)
l
1.5
3
4
mA
l
0.8
1.4
2
V
l
0.8
1.4
dV/dt (RTA)
Minimum Slew Rate Requirement SDA, SCL Pins; VCC = VCC2 = 5V
VRTA(TH)
Rise Time Accelerator DC
Threshold Voltage
ΔVACC
Buffers Off to Accelerator On
Voltage
IRTA
Rise Time Accelerator Pull-Up
Current
100
200
V
mV
mV
Enable/Control
VDISCEN(TH)
DISCEN Threshold Voltage
ΔVDISCEN(HYST) DISCEN Hysteresis Voltage
VEN(TH)
ENABLE1-2 Threshold Voltage
ΔVEN(HYST)
ENABLE1-2 Hysteresis Voltage
tLH_EN
ENABLE1-2 High to Buffer Active
20
mV
2
20
0.56
V
mV
1
μs
4312f
3
LTC4312
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = VCC2 = 3.3V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
TYP
MAX
UNITS
ILEAK
Input Leakage Current
DISCEN = ENABLE1-2 = 5.5V
l
MIN
0.1
±10
μA
IACC(IN, HL)
ACC High, Low Input Current
VCC = 5V, VACC = 5V, 0V
l
±23
±40
μA
IACC(IN, Z)
Allowable Leakage Current in
Open State
VCC = 5V
l
±5
μA
IACC(EN, Z)
ACC High Z Input Current
VCC = 5V
l
±5
VACC(L, TH)
ACC Input Low Threshold
Voltages
VCC = 5V
l
0.2•VCC
0.3•VCC
0.4•VCC
V
VACC(H,TH)
ACC Input High Threshold
Voltages
VCC = 5V
l
0.7•VCC
0.8•VCC
0.9•VCC
V
35
45
55
ms
0.4
V
±5
μA
μA
Stuck Low Timeout Circuitry
tTIMEOUT
Bus Stuck Low Timer
SDAOUT or SCLOUT < 0.3•VCC
l
VFAULT(OL)
FAULT Output Low Voltage
IFAULT = 3mA
l
IFAULT(OH)
FAULT Leakage Current
l
0.1
I2C Interface Timing
fSCL(MAX)
I2C Frequency Max
(Note 6)
tPDHL
SDA, SCL Fall Delay
VCC = 3V to 5.5V, CBUS = 50pF, IBUS = 1mA (Note 6)
60
tf
SDA, SCL Fall Times
VCC = 3V to 5.5V, CBUS = 50pF, IBUS = 1mA (Note 6)
10
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive and all voltages are referenced to
GND unless otherwise indicated.
Note 3: SDAIN, SCLIN pulled low.
Note 4: VMIN = minimum of VCC and VCC2 if VCC2 > 2.25V else VMIN = VCC.
l
400
kHz
100
ns
ns
Note 5: VIL is tested for the following (VCC, VCC2) combinations:
(2.9V, 5.5V), (5.5V, 2.25V), (3.3V, 3.3V) and (5V, 0V).
Note 6: Guaranteed by design and not tested.
Note 7: Measured in a special DC mode with VSDA,SCL = VRTA(TH) + 1V.
The transient IRTA seen during rising edges when ACC is low will depend
on the bus loading condition and the slew rate of the bus. The LTC4312’s
internal slew rate control circuitry limits the maximum bus rise rate to
75V/μs by controlling the transient IRTA.
4312f
4
LTC4312
TYPICAL PERFORMANCE CHARACTERISTICS
ICC Enabled Current
vs Supply Voltage
TA = 25°C, VCC = 3.3V unless otherwise noted.
ICC Disabled (ENABLE1-2 Low)
Current vs Supply Voltage
8.0
Multiplexer Switch Resistance
RMUX vs Temperature
3.0
10
VSDAIN, SCLIN = 0V
VSDAIN, SCLIN = 0V
IDS = 4mA
9
2.5
VCC2 = 3.3V
7.5
RMUX (Ω)
ICC (mA)
ICC (mA)
8
2.0
7.0
7
VCC2 = 5V
6
1.5
5
6.5
3
2
4
5
1.0
6
3
2
4
VCC (V)
5
100
Input to Output Offset Voltage
vs Bus Current for Different Driven
Input Voltage Levels
350
250
VCC = VCC2 = 3.3V
VCC = VCC2 = VDD, BUS = 5V
VCC = VCC2 = VDD, BUS = 5V
RBUS = 2.7kΩ
300
200
DRIVEN VSDAIN, SCLIN = 50mV
250
8
VSDAIN,SCLIN = 0.4V
7
6
150
VOS (mV)
tPDF (ns)
IOL (mA)
75
4312 G03
Buffer High to Low Propagation
Delay vs Output Capacitance
9
100
–25
25
75
0
50
TEMPERATURE (°C)
100
0
125
0
500
0
1000
1500
16
14
250
tRISE(30%–70%) vs CBUS
12
10
8
IBUS (mA)
4312 G07
6
–50
125
100
5V
75
3.3V
25
50
6
VCC = VCC2 = VDD, BUS
ACC = 0V
50
3.3V
≥200mV
4
150
tRISE (ns)
IRTA (mA)
DRIVEN VSDAOUT, SCLOUT = 50mV
2
4312 G06
VCC = VCC2 = VDD, BUS
VSDA,SCLtVDD,BUS
ACC = 0V
CBUS = 400pF
5V
RBUS = 10k
VCC = VCC2 = VDD, BUS = 5V
300
0
6
4312 G05
350
100mV
4
IBUS (mA)
Rise Time Accelerator Current
vs Temperature
200
2
0
CBUS (pF)
Output to Input Offset Voltage
vs Bus Current for Different
Driven Output Voltage Levels
100
150
50
4312 G04
150
100mV
100
50
4
–50
200
≥200mV
VSDAOUT,SCLOUT = 0.4V
5
VOS (mV)
0
50
25
TEMPERATURE (°C)
4312 G02
Buffer DC IOL vs Temperature
0
–25
VCC (V)
4312 G01
10
4
–50
6
–25
25
50
0
TEMPERATURE (°C)
75
100
4312 G08
0
0
200
400
CBUS (pF)
600
800
4312 G09
4312f
5
LTC4312
PIN FUNCTIONS
ACC: Three-State Acceleration and Buffer Mode Selector.
This pin controls the turn on voltage of the rise time accelerators and their current strength on both the input and
output sides. It also controls the turn-off voltage of the
buffers. See Table 1 in the Applications Information section.
DISCEN: Disconnect Stuck Bus Enable Input. When this
pin is high, stuck busses are automatically disconnected
and FAULT is pulled low after a timeout period of 45ms.
Up to sixteen clock pulses are subsequently applied to the
stuck output channels. When DISCEN pin is low, stuck
busses are neither disconnected nor clocked but FAULT
is pulled low. Connect to GND if unused.
ENABLE1-ENABLE2: Connection Enable Inputs. These
input pins enable or disable the corresponding output
channel. Driving an ENABLE pin low isolates SDAIN and
SCLIN from the corresponding SDAOUT and SCLOUT.
Only enable and disable a channel when all busses are
idle. During a bus stuck low fault condition, a falling edge
on all ENABLE pins followed by a rising edge on one or
more ENABLE pins forces a connection from SDAIN to
the selected SDAOUT and SCLIN to the selected SCLOUT.
Connect to GND if unused.
Exposed Pad (DFN Package Only): Exposed pad may be
left open or connected to device ground.
FAULT: Stuck Bus Fault Output. This open drain N-channel
MOSFET output pulls low if a simultaneous high on the
enabled SCLOUT and SDAOUT channels does not occur in
45ms. In normal operation FAULT is high. Connect a pull
up resistor, typically 10k, from this pin to the bus pull-up
supply. Leave open or tie to GND if unused.
GND: Device Ground.
SCLIN: Upstream Serial Bus Clock Input/Output. Connect
this pin to the SCL line on the upstream bus. Connect an
external pull-up resistor or current source between this
pin and the bus supply. Do not leave open.
SCLOUT1-SCLOUT2: Downstream Serial Bus Clock Input/
Output Channels 1-2. Connect pins SCLOUT1-SCLOUT2
to the SCL lines on the downstream channels 1-2, respectively. When in use, an external pull-up resistor or current
source is required between the pin and the corresponding
bus supply. Leave open or tie to GND and connect the
corresponding ENABLE pin to GND, if unused.
SDAIN: Upstream Serial Bus Data Input/Output. Connect
this pin to the SDA line on the upstream bus. Connect an
external pull-up resistor or current source between this
pin and the bus supply. Do not leave open.
SDAOUT1-SDAOUT2: Downstream Serial Bus Data Input/
Output Channels 1-2. Connect pins SDAOUT1-SDAOUT2 to
the SDA lines on downstream channels 1-2, respectively.
When in use, an external pull-up resistor or current source
is required between the pin and the corresponding bus
supply. Leave open or tie to GND and connect the corresponding ENABLE pin to GND, if unused.
VCC: Power Supply Voltage. Power this pin from a supply between 2.9V and 5.5V. Bypass with at least 0.01μF
to GND.
VCC2: Output Side Rise Time Accelerator (RTA) Power
Supply Voltage. When powering VCC2, use a supply voltage ranging from 2.25V to 5.5V and bypass with at least
0.01μF to GND. If the downstream busses are powered
from multiple supply voltages, power VCC2 from the lowest supply voltage. Output side RTAs are active if VCC2 ≥
2.25V and ACC is low or open. Grounding VCC2 disables
output side RTAs.
4312f
6
LTC4312
BLOCK DIAGRAM
VCC
VCC2
IRTA
IRTA
CO1
SCLIN
SLEW RATE
DETECTOR
0.2V/μs
SCLOUT1
VCC2
IRTA
CIN
SLEW RATE
DETECTOR
0.2V/μs
VCC
CO2
SCLOUT2
VCC2
IRTA
IRTA
MUX
SDAIN
DO1
SLEW RATE
DETECTOR
0.2V/μs
SLEW RATE
DETECTOR
0.2V/μs
DIN
SDAOUT1
VCC2
IRTA
+
VIL
CONNECT
–
–
GND
VCC
LOGIC
45ms
TIMER
–
SDAOUT2
VCC2
VIL
+
–
UVLO
DO2
EN2
+
+
VIL
EN1
VIL
110μs
TIMER
FAULT
ACC
DISCEN
IBOOST_SCL /IBOOST_SDA
ENABLE1
ENABLE2
4314 BD
4312f
7
LTC4312
OPERATION
The Block Diagram shows the major functional blocks of the
LTC4312. The LTC4312 is a 1:2 multiplexer with capacitance
buffering for I2C signals. Capacitance buffering is achieved
by use of back to back buffers on the clock and data channels which isolate the SDAIN and SCLIN capacitances from
the SDAOUT and SCLOUT capacitances respectively. All
SDA and SCL pins are fully bidirectional. The high noise
margin allows the LTC4312 to operate with I2C devices
that drive a non-compliant high VOL. Multiplexing is done
using N-channel MOSFETs that are controlled by dedicated
ENABLE pins. When enabled, rise time accelerator pull-up
currents IRTA turn on during rising edges to reduce system rise time. In a typical application the input side bus
is pulled up to VCC and the output side busses are pulled
up to VCC2 although these are not requirements. VCC is
the primary power supply to the LTC4312. VCC and VCC2
serve as the input and output side rise time accelerator
supplies respectively. Grounding VCC2 disables the output
side accelerators. The multiplexer N-channel MOSFET
gates of the enabled channels are driven to VCC2 if VCC2
is > 1.8V, otherwise they are driven to VCC.
When the LTC4312 first receives power on its VCC pin, it
starts out in an undervoltage lockout mode (UVLO) until
110μs after VCC exceeds 2.3V. During this time, the buffers
and rise time accelerators are disabled, the multiplexer
gates are off and the LTC4312 ignores transitions on the
clock and data pins independent of the state of the ENABLE
pins. VCC2 transitions from a high to a low or vice-versa
across a 1.8V threshold also cause the LTC4312 to disable the buffers, rise time accelerators and transmission
gates and to ignore the clock and data pins until 110μs
after that transition. Assuming that the LTC4312 is not in
UVLO mode, when one or both ENABLEs are asserted,
the LTC4312 activates the connection circuitry between
the SDAIN/SCLIN inputs and selected output channels.
The input rise time accelerators and the output rise time
accelerators of the selected channels are also enabled at
this time. When a SDA/SCL input pin or output pin on an
enabled output channel is driven below the VIL,FALLING
level of 0.33 • VMIN, the buffers are turned on and the
logic low level is propagated though the LTC4312 to
the other side. For VCC2 > 1.8V, VMIN is the lower of the
VCC and VCC2 voltages. For VCC2 < 1.8V, VMIN is the VCC
voltage. The LTC4312 is designed to sink a minimum
total bus current IOL of 4mA while holding a VOL of 0.4V.
If multiple output channels are enabled, the bus current of
all enabled channels needs to be summed to get the total
bus current. See the Typical Performance Characteristics
curves for IOL as a function of temperature.
A high occurs when all devices on the input and output
sides release high. Once the bus voltages rise above the
VIL, RISING level, which is determined by the state of the ACC
pin, the buffers are turned off. The rise time accelerators
are turned on at a slightly higher voltage. The rise time
accelerators accelerate the rising edges of the SDA/SCL
inputs and selected outputs up to voltages of 0.9•VCC and
0.8•VCC2 respectively, provided that the busses on their
own are rising at a minimum rate of 0.2V/μs as determined
by the slew rate detectors. ACC is a 3-state input that controls VIL,RISING , the rise time accelerator turn-on voltage
and the rise time accelerator pull-up strength.
The LTC4312 detects a bus stuck low (fault) condition
when both clock and data busses are not simultaneously
high at least once in 45ms. The voltage monitoring for a
stuck low condition is done on the common internal node
of the clock and data outputs. Hence a stuck low condition
is detected only if it occurs on an enabled output channel.
When a stuck bus occurs, the LTC4312 asserts the FAULT
flag. If DISCEN is tied high, the LTC4312 also disconnects
the input and output sides. After waiting at least 40μs, it
generates up to sixteen 5.5kHz clock pulses on the enabled
SCLOUT pins and a stop bit to attempt to free the stuck
bus. If the bus recovers high before 16 clocks are issued,
the LTC4312 ceases issuing clocks and generates a stop
bit. If DISCEN is tied low, a stuck bus event only causes
FAULT flag assertion. Disconnection of the input and output
sides and clock generation do not occur. Once the stuck
bus recovers and the fault has been cleared, in order for a
connection to be established between the input and output
sides, both ENABLE pins need to be driven low followed
by the assertion high of the desired ENABLE pins. When
powering into a stuck low condition, the LTC4312 upon
exiting UVLO will connect the input and output sides for
45ms until a stuck bus timeout event is detected.
4312f
8
LTC4312
APPLICATIONS INFORMATION
The LTC4312 is a 1:2 pin selectable I2C multiplexer that
provides a high noise margin, capacitance buffering and
level translation capability on its clock and data pins. Rise
time accelerators accelerate rising edges to enable operation at high frequencies with heavy loads. These features
are illustrated in the following subsections.
Table 1. ACC Control of the Rise Time Accelerator Current IRTA
and Buffer Turn-Off Voltage VIL,RISING
Rise Time Accelerators and DC Hold-Off Voltage
The ACC pin has a resistive divider between VCC and GND
to set its voltage to 0.5•VCC if left open. In the current
source accelerator mode, the LTC4312 provides a 3mA
constant current source pull-up. In the strong mode, the
LTC4312 sources pull-up current to make the bus rise at
75V/μs (typical). The strong mode current is therefore
directly proportional to the bus capacitance. The LTC4312
is capable of sourcing up to 45mA of current in the strong
mode. The effect of the rise time accelerator strength is
shown in the SDA waveforms in Figures 1 and 2 for identical bus loads for a single enabled output channel. The
rise time accelerator supplies 3mA and 10mA of pull-up
current (IRTA) respectively in the current source and strong
modes for the bus conditions shown in Figures 1 and 2.
The rise time accelerator turn-on voltage in the strong
mode is also lower as compared to the current source
mode. For identical bus loading conditions, the bus returns
high faster in Figure 1 compared to Figure 2 because of
both the higher IRTA and the lower turn-on voltage of the
rise time accelerator. In each figure, note that the input
and output rising waveforms are nearly coincident due to
the input and output busses having nearly identical bus
current and capacitance.
Once the LTC4312 has exited UVLO and a connection has
been established between the SDA and SCL inputs and
outputs, the rise time accelerators on both the input and
output sides of the SDA and SCL busses are activated
based on the state of the ACC pin and the VCC2 supply
voltage. During positive bus transitions of at least 0.2V/
μs, the rise time accelerators provide pull-up currents to
reduce rise time. Enabling the rise time accelerators allows users to choose larger bus pull-up resistors, reducing power consumption and improving logic low noise
margins, to design with bus capacitances outside of the
I2C specification or to switch at a higher clock frequency.
The ACC pin sets the turn-off threshold voltage for the
buffers, the turn-on voltage for the rise time accelerators,
and the rise time accelerator pull-up current strength. The
ACC functionality is shown in Table 1. Set ACC open or
high when a high noise margin is required such as when
the LTC4312 is used in a system having I2C devices with
VOL > 0.4V.
ACC
IRTA
VIL,RISING
Low
Strong
0.8V
0.6V
Open
3mA
0.4•VMIN
0.33•VMIN
High
None
N/A
0.33•VMIN
CIN = COUT = 200pF
RBUS = 10kΩ
ACC = OPEN
VCC = VCC2 = 5V
SDAOUT1
0V
2V/DIV
CIN = COUT = 200pF
RBUS = 10kΩ
ACC = 0
VCC = VCC = 5V
2V/DIV
VRTA(TH)
SDAOUT1
0V
SDAIN
SDAIN
0V
0V
500ns/DIV
4312 F01
Figure 1. Bus Rising Edge for the
Strong Accelerator Mode
500ns/DIV
4312 F02
Figure 2. Bus Rising Edge for the
Current Source Accelerator Mode
4312f
9
LTC4312
APPLICATIONS INFORMATION
If VCC2 is tied low, the output side rise time accelerators
are disabled independent of the state of the ACC pin.
ACC tied high disables input and output RTAs. Using a
combination of the ACC pin and the VCC2 voltage allows
the user independent control of the input and output side
rise time accelerators. The rise time accelerators are also
internally disabled during power-up and VCC2 transitions,
as described in the Operation section, as well as during
automatic clocking and stop bit generation for a bus stuck
low recovery event.
Supply Voltage Considerations in Level Translation
Applications
Care must be taken to ensure that the bus supply voltages
on the input and output sides are greater than 0.9•VCC and
0.8•VCC2 , respectively, to ensure that the bus is not driven
above the bus supplies by the rise time accelerators. This
is usually accomplished in a level shifting application by
tying VCC to the input bus supply and VCC2 to the minimum
bus supply on the output side as shown in Figure 3.
If VCC2 is grounded, the multiplexer pass gates are powered
from VCC. In this case the minimum output bus supply
of the enabled channels should be greater than or equal
to VCC to prevent cross-conduction between the enabled
output channels. This is shown in Figure 4. Grounding VCC2
as shown in Figure 4 disables the output side rise time
accelerators independent of the state of the ACC pin. The
input rise time accelerators in this configuration continue
to be controlled by the ACC pin and can be enabled independently. In Figure 4, ACC is left open to obtain a high VIL
and a 3mA rise time accelerator current on the input side.
The rise time accelerators when activated pull the bus up
to 0.9•VCC on the input side of the SDA and SCL lines.
On the output side the SDAOUT and SCLOUT lines are
pulled up by the rise time accelerators to 0.8•VCC2. For
VCC2 voltages approaching 2.3V, acceleration of the output
bus may not be seen all the way to 0.8•VCC2 due to the
threshold voltage of the NFET pass device.
3.3V
C1
0.01μF
R1
10k
3.3V
R2
10k
VCC2
VCC
SCLIN
SCLIN
SDAIN
SDAIN
R4
10k
R5
10k
C2
0.01μF
ENABLE1
ENABLE1
SCLOUT1
SCLOUT1
ENABLE2
ENABLE2
SDAOUT1
SDAOUT1
5V
LTC4312
3.3V
R3
10k
R6
10k
ACC
DISCEN
FAULT
R7
10k
SCLOUT2
SCLOUT2
SDAOUT2
SDAOUT2
FAULT
GND
4312 F03
Figure 3. Connection of the LTC4312 in a Level Shift Application. VCC2 Is
Less Than or Equal to the Minimum Bus Supply Voltage on the Output Side
4312f
10
LTC4312
APPLICATIONS INFORMATION
3.3V
C1
0.01μF
R1
10k
3.3V
R2
10k
VCC2
VCC
SCLIN
SCLIN
SDAIN
SDAIN
R4
10k
R5
10k
C2
0.01μF
ENABLE1
ENABLE1
SCLOUT1
SCLOUT1
ENABLE2
ENABLE2
SDAOUT1
SDAOUT1
R3
10k
R6
10k
ACC
DISCEN
FAULT
5V
LTC4312
3.3V
R7
10k
SCLOUT2
SCLOUT2
SDAOUT2
SDAOUT2
FAULT
GND
4312 F04
Figure 4. Connection of the LTC4312 in a Level Shift Application. VCC Is Less Than or Equal to the Minimum
Bus Supply Voltages on the Output Side. VCC2 Is Grounded to Disable Output Rise Time Accelerators
Pull-Up Resistor Value Selection
Input to Output Offset Voltage and Propagation Delay
To guarantee that the rise time accelerators are activated
during a rising edge, the bus must rise on its own with
a positive slew rate of at least 0.4V/μs. To achieve this,
choose a maximum RBUS using equation 1:
The LTC4312 introduces both an offset as well as a
propagation delay for falling edges between the input and
output. When a logic low voltage of ≥200mV is driven
on any of the LTC4312’s data or clock pins, the LTC4312
regulates the voltage on the opposite side to a slightly
higher value. When SCLIN or SDAIN is driven to a logic
low voltage, SCLOUT or SDAOUT is driven to a slightly
higher voltage as directed by equation 3 which uses SDA
as an example:
RBUS (Ω)≤
( VDD,BUS(MIN) − VRTA(TH) )
0.4
V
• CBUS
µs
(1)
RBUS is the bus pull-up resistor, VDD, BUS(MIN) the minimum
bus pull-up supply voltage, VRTA(TH) the voltage at which
the rise time accelerator turns on, which is a function of
ACC, and CBUS the equivalent bus capacitance. RBUS values
on each output channel must also be chosen to ensure
that when all the required output channels are enabled, the
total bus current is ≤4mA. The bus current in each output
channel can be 4mA if only one output channel is enabled
at any given time. The RBUS value on the input side must
also be chosen to limit the bus current to be ≤4mA. The
bus current for a single bus is determined by equation 2:
IBUS (A)=
VDD,BUS − 0.4V
RBUS
(2)
VSDAOUT (V) = VSDAIN + 45mV
+ (10Ω + R MUX ) •
VDD,BUS
(3)
R BUS
VDD,BUS is the output bus voltage, RBUS the output bus
pull-up resistance and RMUX is the resistance of the channel
transmission gate in the multiplexer shown in the block
diagram. The offset is affected by the VCC2 voltage and bus
current. A higher VCC2 voltage (VCC if VCC2 is grounded)
reduces RMUX leading to a lower offset. See the Typical
Performance Characteristics plots for the variation of RMUX
as a function of VCC2 and temperature. When SDAOUT or
SCLOUT is driven to a logic low voltage ≥ 200mV, SCLIN
4312f
11
LTC4312
APPLICATIONS INFORMATION
or SDAIN is regulated to a logic low voltage as directed
by equation 4 which uses SDA as an example:
VSDAIN (V)= VSDAOUT + 45mV +10Ω •
VDD,BUS
RBUS
Cascading LTC4312 Devices and Other LTC Bus Buffers
Multiple LTC4312s can be cascaded or the LTC4312 may
be cascaded with other LTC bus buffers as required by the
application. This is shown for the data pathway in Figure 5
where an LTC4312 is cascaded with other LTC4312s and
some select LTC bus buffers. The clock path is identical.
When using such cascades, users should be aware of the
additive logic low offset voltages (VOS) when determining system noise margin. If the sum of the offsets (refer
to Equations 3 and 4 and to the data sheets of the corresponding bus buffers) plus the worst-case driven logic
low voltage across the cascade exceeds the buffer turn off
voltage, signals will not be propagated across the cascade.
Also the minimum rise time accelerator (RTA) turn-on voltage (wherever applicable) of each device in the cascade
should also be greater than the maximum buffer turn-off
voltage of all the devices in the cascade. This condition
is required to prevent contention between one device’s
buffer and another’s RTA. Based on this requirement,
(4)
The SCLOUT/SDAOUT to SCLIN/SDAIN offset is lower
than the reverse case as the multiplexer transmission gate
does not affect this offset. For driven logic low voltages
< 200mV, the above equations do not apply as the saturation
voltage of the open collector output transistor results in a
higher offset. However, the offset is guaranteed to be less
than 400mV for a total bus pull-up current of 4mA under
all conditions. See the Typical Performance Characteristics
curves for the buffer offset voltage as a function of the
driven logic low voltage and bus pull-up current.
The high-to-low propagation delay arises due to both the
finite response time of the buffers and their finite current
sink capability. See the Typical Performance Characteristics
curves for the propagation delay as a function of the bus
capacitance.
3.3V
C1
0.01μF
5V
R1
10k
VCC
VCC2
LTC4312
R2
10k
R3
10k
R4
10k
R5
10k
3.3V
C4
0.01μF
VCC
VCC2
R6
10k
LTC4312
C5
0.01μF
SDAIN
SDAOUT1
SDAIN
SDAOUT1
SDAOUT1
ACC
SDAOUT2
ACC
SDAOUT2
SDAOUT2
GND
GND
3.3V
3.3V
5V
C2
0.01μF
VCC
R7
10k
LTC4301
VCC
VCC2
C3
0.01μF
SDAIN
GND
SDAOUT
LTC4312
SDAIN
SDAOUT1
ACC
SDAOUT2
VCC
R8
10k
LTC4303
GND
SDAOUT3
5V
SDAIN
GND
SDAOUT
SDAOUT4
5V
VCC
R9
10k
LTC4307
SDAIN
GND
SDAOUT
SDAOUT5
4312 F05
Figure 5. Cascading LTC4312s with Other LTC4312s and LTC Bus Buffers. Only the SDA Path Is Shown for Simplicity
4312f
12
LTC4312
APPLICATIONS INFORMATION
the LTC4312 can be cascaded with the LTC4303 and
LTC4307 if the LTC4312’s RTA turn-on voltage is set to be
0.8V (ACC low). The LTC4312 can be cascaded with the
LTC4301 and LTC4301L under all ACC settings as these
devices do not have RTAs. The LTC4312 can be cascaded
with the LTC4302, LTC4304, LTC4305 and LTC4306 if the
LTC4312’s RTAs are set to turn on at 0.8V (ACC low) or
under all ACC settings if the RTAs on the other bus buffers are disabled. Finally, two LTC4312s can be cascaded
if their ACC pins are tied to the same state, HIGH, LOW
or open or if the ACC pin of one LTC4312 is tied high and
the other is left open.
Radial Telecommunications
Figure 6 shows the use of the LTC4312 in a radial telecommunications application. Two Shelf Managers are wired to
communicate with slave I2C devices for redundancy. Each
Shelf Manager can have as many LTC4312s as required
depending on the number of boards in the system and
the desired radial/star configuration. The ENABLE pins of
the LTC4312s inside only one Shelf Manager are asserted
high at any time. For simplicity, in Figure 6 only the SDA
pathway is shown. The SCL pathway is identical.
BACKPLANE
SHMC #1
FRU #1
3.3V
3.3V
R1
10k
VCC
3.3V
VCC2
R2
10k
LTC4312 #1
SDAIN
μP
ENABLE1A
ENABLE1
ENABLE2A
ENABLE2
IPMB-A
SDA1
SDAOUT1
t
IPMB-B
SDA1
SDAOUT2
t
ACC
GND
t
t
t
t
t t t
3.3V
VCC
VCC2
LTC4312 #12
ENABLE2
SDAOUT1
t
ENABLE1
ENABLE24A
t
SDAIN
ENABLE23A
3.3V
R3
10k
IPMB-A
SDA24
SDAOUT2
SDA1
IPMB-B (×24)
t t t
GND
t
ACC
FRU #24
SDA24
SHMC #2
(IDENTICAL TO SHMC#1)
IPMB-A (×24)
SDA1
t t t
IPMB-B (×24)
IPMB-B
SDA24
SDA24
4312 F06
Figure 6. LTC4312s Configured for a Radially Connected Redundant Telecommunications Shelf Manager Application
in a 12 × 2 Arrangement. The ENABLE Pins on Only One of the Shelf Managers Are High at Any Time. Only the SDA
Path Is Shown for Simplicity
4312f
13
LTC4312
APPLICATIONS INFORMATION
and output, asserting FAULT low and generating up to
16 clock pulses at 5.5kHz on the SCLOUT node common
to the two channels. Should the stuck bus release high
during this period, clock pulsing is stopped, a stop bit is
generated and FAULT is cleared. In order for a connection to be established between the input and output, all
ENABLEs have to be taken low followed by an assertion
of the ENABLEs of the required channels.This process is
illustrated in Figure 8 for the case where only channel 1 is
active and SDAOUT1 starts out stuck low and then recovers. If DISCEN is tied low and a stuck low event occurs,
the FAULT flag is driven low, but the connection between
the input and output is not broken and clock generation
is not done.
Nested Addressing
The LTC4312 can provide nested addressing when its
ENABLE pins are used as channel select bits. This is
shown in Figure 7 where the master communicates with
slave devices that have the same address by selectively
enabling only one output channel at a time. Since slaves
have the same address care must be taken that the master
never enables both channels at the same time.
Stop Bit Generation and FAULT Clocking
If the output bus sticks low (SCLOUT or SDAOUT stuck
low for at least 45ms) on one of the enabled channels
and DISCEN is high, the LTC4312 attempts to unstick the
bus by first breaking the connection between the input
3.3V
C1
0.01μF
R1
10k
3.3V
R2
10k
VCC
VCC2
R4
10k
R5
10k
C2
0.01μF
SCLIN
I2C
DEVICE
SDAIN
ENABLE1
ENABLE1
SCLOUT1
ENABLE2
ENABLE2
SDAOUT1
I2C
DEVICE
ADDRESS = 1001 000
5V
LTC4312
3.3V
R6
10k
ACC
R3
10k
R7
10k
SCLOUT2
DISCEN
I2C
DEVICE
SDAOUT2
FAULT
FAULT
ADDRESS = 1001 000
GND
4312 F07
Figure 7. Nested Addressing
ENABLE1
5V/DIV
DISCONNECT
AT TIMEOUT
CONNECT AT RISING EDGE OF ENABLE1
SDAIN
5V/DIV
SDAOUT1
5V/DIV
STUCK LOW>45ms
RECOVERS
DRIVEN LOW
AUTOMATIC CLOCKING
SCLOUT1
5V/DIV
1ms/DIV
4312 F08
Figure 8.Bus Waveforms During a SDAOUT Stuck Low and Recovery Event
4312f
14
LTC4312
APPLICATIONS INFORMATION
Demultiplexer Function
Due to its bi-directional nature, the LTC4312 can be used
as a demultiplexer. This is shown in Figure 9 where two
channels are used to drive I2C data from the master side
with redundancy to the slave side. In this application the
SDAOUT/SCLOUT channels serve as the inputs while the
SDAIN/SCLIN channel is the output. Redundancy on the
master side provides protection against power supply
failure. In Figure 9, if the 5V bus supply on channel 1 falls
below 1.4V, channel 1 gets disabled as ENABLE1 is driven
below its digital threshold. Simultaneously, the VBE of the
NPN pull-down device on ENABLE2 falls below 0.7V and
it turns off. This causes ENABLE2 to be pulled up by R7
which in turn enables channel 2, causing control to be
transferred to the backup I2C master device.
5V
3.3V
R1
10k
R2
10k
LTC4312
SDAOUT1
SCLOUT1
ENABLE1
PRIMARY
I2C
MASTER
CONTROLLER
CARD
VCC
VCC2
3.3V
R3
10k
R4
10k
R5
100k
R8
10k
R9
10k
R10
10k
SDAIN
SCLIN
C1
0.01μF
SDA
SCL
ACC
DISCEN
R7
20k
FAULT
BACKUP
I2C
MASTER
FAULT
SDAOUT2
SCLOUT2
ENABLE2
GND
CONTROLLER
CARD
BF840
4312 F09
R6
50k
Figure 9. The LTC4312 Configured as a 2:1 Demultiplexer in a System with Redundancy
4312f
15
LTC4312
APPLICATIONS INFORMATION
Hot-Swapping
Figure 10 shows the LTC4312 in a typical hot-swapping
application where the LTC4312 is on the backplane and I/O
cards plug into the downstream channels. The outputs must
idle high and the corresponding output channel must be
disabled before an I/0 card can be plugged or unplugged
from an output channel. Figure 10 also shows the use of
a non-compliant I2C device with the LTC4312. The high
noise margin of the LTC4312 supports logic low levels up
to 0.3 • VCC, allowing devices to drive greater than 0.4V
logic low levels on the clock and data lines.
3.3V
C1
0.01μF
I2C
DEVICE
VOL = 0.6V
R1
10k
R2
10k
3.3V
VCC2
VCC
R4
10k
R5
10k
C2
0.01μF
SCLIN
SDAIN
ENABLE1
ENABLE1
SCLOUT1
ENABLE2
ENABLE2
SDAOUT1
I2C
DEVICE
IO CARD
5V
LTC4312
CONNECTOR
3.3V
R3
10k
R6
10k
ACC
SCLOUT2
DISCEN
FAULT
R7
10k
I2C
DEVICE
SDAOUT2
FAULT
IO CARD
GND
CONNECTOR
4312 F10
Figure 10. SDA, SCL Hot Swap™ and Operation with a Non-Compliant I2C Device
4312f
16
LTC4312
APPLICATIONS INFORMATION
Level Translating to Bus Voltages < 2.25V
in order to meet the VIH = 0.7 • VDD,BUS requirement and
not impact the high side noise margin. Users willing to live
with a lower logic high noise margin can level translate
down to 1.5V. An example of voltage level translation from
3.3V to 1.8V is illustrated in Figure 11, where a 3.3V input
voltage level is translated to a 1.8V output voltage level on
channel 1. Tying VCC to 3.3V satisfies equation 5. Grounding VCC2 disables the RTA on the low voltage channel.
VMIN defaults to VCC under these conditions, making the
buffer turn off voltage 0.99V. Channel 2 must be disabled
when channel 1 is enabled. A similar voltage translation
can also be performed going from a 3.3V bus supply on
the output side to a 1.8V bus supply on the input side if
ACC is tied high to disable the input RTA and if VCC and
VCC2 are tied to the output side bus supply.
The LTC4312 can be used for level translation to bus voltages below 2.25V if certain conditions are met. In order
to perform this level translation, RTAs on the low voltage
side need to be disabled in order to prevent an over drive
of the low voltage bus. If one of the output channels is
pulled up to the low voltage bus supply, the other output
channel needs to be disabled when this channel is active,
in order to prevent cross conduction between the output
channels. Since the buffer turn-on and turn-off voltages
are 0.3• VMIN, the minimum bus supply voltage is determined by equation 5:
VDD,BUS(MIN) ≥
0.3 • VMIN
(5)
0.7
3.3V
C1
0.01μF
1.8V
R1
10k
R2
10k
VCC2
VCC
SCLIN
SCLIN
SDAIN
SDAIN
R4
10k
R5
10k
C2
0.01μF
ENABLE1
ENABLE1
SCLOUT1
SCLOUT1
ENABLE2
ENABLE2
SDAOUT1
SDAOUT1
3.3V
5V
LTC4312
R3
10k
R6
10k
ACC
R7
10k
C3
0.01μF
DISCEN
SCLOUT2
SCLOUT2
FAULT
SDAOUT2
SDAOUT2
GND
4312 F11
Figure 11. Level Shifting Down to 1.8V Using the LTC4312, VCC2 Is Grounded to Disable the Rise Time Accelerator
on the Low Voltage Bus. ENABLE2 Must Be Low Whenever ENABLE1 Is High
4312f
17
LTC4312
PACKAGE DESCRIPTION
DE Package
14-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1708 Rev B)
0.70 ±0.05
3.30 ±0.05
3.60 ±0.05
2.20 ±0.05
1.70 ± 0.05
PACKAGE
OUTLINE
0.25 ± 0.05
0.50 BSC
3.00 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
R = 0.115
TYP
4.00 ±0.10
(2 SIDES)
R = 0.05
TYP
3.00 ±0.10
(2 SIDES)
8
0.40 ± 0.10
14
3.30 ±0.10
1.70 ± 0.10
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
PIN 1
TOP MARK
(SEE NOTE 6)
(DE14) DFN 0806 REV B
7
0.200 REF
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
3.00 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
4312f
18
LTC4312
PACKAGE DESCRIPTION
MS Package
16-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1669 Rev Ø)
0.889 p 0.127
(.035 p .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.305 p 0.038
(.0120 p .0015)
TYP
4.039 p 0.102
(.159 p .004)
(NOTE 3)
0.50
(.0197)
BSC
0.280 p 0.076
(.011 p .003)
REF
16151413121110 9
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
DETAIL “A”
3.00 p 0.102
(.118 p .004)
(NOTE 4)
4.90 p 0.152
(.193 p .006)
0o – 6o TYP
GAUGE PLANE
0.53 p 0.152
(.021 p .006)
DETAIL “A”
0.18
(.007)
SEATING
PLANE
1234567 8
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
BSC
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.86
(.034)
REF
0.1016 p 0.0508
(.004 p .002)
MSOP (MS16) 1107 REV Ø
4312f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC4312
TYPICAL APPLICATION
Level Translating 2.5V, 3.3V and 5V Busses and Operation with a Non-Compliant I2C Device
3.3V
C1
0.01μF
5V
R2
10k
R1
10k
VCC2
VCC
R3
10k
R4
10k
C2
0.01μF
SCLIN
SDAIN
ENABLE1
SCLOUT1
SCLOUT1
ENABLE2
SDAOUT1
SDAOUT1
LTC4312
2.5V
3.3V
R5
10k
ACC
DISCEN
NON-COMPLIANT
I2C DEVICE
VOL = 0.6V
R6
10k
SCLOUT2
SCLOUT2
SDAOUT2
SDAOUT2
GND
4312 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC4300A-1/
LTC4300A-2/
LTC4300A-3
Hot-Swappable 2-Wire Bus Buffers
-1: Bus Buffer with READY and ENABLE
-2: Dual Supply Buffer with ACC
-3: Dual Supply Buffer with ENABLE
LTC4302-1/
LTC4302-2
Addressable 2-Wire Bus Buffer
Address Expansion, GPIO, Software Controlled
LTC4303
LTC4304
Hot-Swappable 2-Wire Bus Buffer with Stuck Bus
Recovery
Provides Automatic Clocking to Free Stuck I2C Busses
LTC4305
LTC4306
2- or 4-Channel, 2-Wire Bus Multiplexers with
Capacitance Buffering
2 or 4 Software Selectable Downstream Busses, Stuck Bus Disconnect, Rise
Time Accelerators, Fault Reporting, ±10kV HBM ESD Tolerance
LTC4307
Low Offset Hot-Swappable 2-Wire Bus Buffer with
Stuck Bus Recovery
60mV Bus Offset, 30ms Stuck Bus Disconnect and Recovery, Rise Time
Accelerators, ±5kV HBM ESD Tolerance
LTC4307-1
High Definition Multimedia Interface (HDMI) Level
Shifting 2-Wire Bus Buffer
60mV Buffer Offset, 3.3V to 5V Level Shifting, ±5kV HBM ESD Tolerance
LTC4308
Low Voltage, Level Shifting Hot-Swappable 2-Wire
Bus Buffer with Stuck Bus Recovery
Bus Buffer with ENABLE and READY, Level Translation to 1V Busses,
Output Side Rise Time Accelerators
LTC4309
Low Offset Hot-Swappable 2-Wire Bus Buffer with
Stuck Bus Recovery
60mV Buffer Offset, 30ms Stuck Bus Disconnect and Recovery, Rise Time
Accelerators, ±5kV HBM ESD Tolerance
LTC4310-1/
LTC4310-2
Hot-Swappable I2C Isolators
-1: 100kHz Bus
-2: 400kHz Bus
LTC4311
Low Voltage I2C/SMBus Accelerator
Rise Time Acceleration with ENABLE and ±8kV HBM ESD Tolerance
LTC4314
Pin-Selectable, 4-Channel, 2-Wire Multiplexer with
Bus Buffer
4 Pin-Selectable Downstream Busses, Stuck Bus Disconnect and Recovery,
Selectable Rise Time Accelerator Current and Activation Voltage, ±4kV HBM
ESD Tolerance
LTC4301
Supply Independent Hot Swappable 2-Wire Bus Buffer Bus Buffer with 1V Pre-Charge, CS and READY
LTC4301L
Hot-Swappable 2-Wire Bus Buffer with Low Voltage
Level Translation
Bus Buffer with CS and READY Allowing for Input Bus Voltages of Up to 1V
LTC1694-1
SMBus/I2C Accelerator
Rise Time Accelerator
4312f
20 Linear Technology Corporation
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