FINAL Am29F010 1 Megabit (128 K x 8-bit) CMOS 5.0 Volt-only, Uniform Sector Flash Memory DISTINCTIVE CHARACTERISTICS ■ Single power supply operation — 5.0 V ± 10% for read, erase, and program operations — Simplifies system-level power requirements ■ High performance — 45 ns maximum access time ■ Low power consumption — 30 mA max active read current — 50 mA max program/erase current — <25 µA typical standby current ■ Flexible sector architecture — Eight uniform sectors — Any combination of sectors can be erased — Supports full chip erase ■ Sector protection — Hardware-based feature that disables/reenables program and erase operations in any combination of sectors — Sector protection/unprotection can be implemented using standard PROM programming equipment ■ Embedded Algorithms — Embedded Erase algorithm automatically pre-programs and erases the chip or any combination of designated sector — Embedded Program algorithm automatically programs and verifies data at specified address ■ Minimum 100,000 program/erase cycles guaranteed ■ Package options — 32-pin PLCC — 32-pin TSOP — 32-pin PDIP ■ Compatible with JEDEC standards — Pinout and software compatible with single-power-supply flash — Superior inadvertent write protection ■ Data# Polling and Toggle Bits — Provides a software method of detecting program or erase cycle completion Publication# 16736 Rev: G Amendment/+2 Issue Date: March 1998 GENERAL DESCRIPTION The Am29F010 is a 1 Mbit, 5.0 Volt-only Flash memory organized as 131,072 bytes. The Am29F010 is offered in 32-pin PLCC, TSOP, and PDIP packages. The bytewide data appears on DQ0-DQ7. The device is designed to be programmed in-system with the standard system 5.0 Volt VCC supply. A 12.0 volt VPP is not required for program or erase operations. The device can also be programmed or erased in standard EPROM programmers. The standard device offers access times of 45, 55, 70, 90, and 120 ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE) controls. The device requires only a single 5.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This invokes the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. 2 Device erasure occurs by executing the erase command sequence. This invokes the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is erased when shipped from the factory. The hardware data protection measures include a low VCC detector automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory, and is implemented using standard EPROM programmers. The system can place the device into the standby mode. Power consumption is greatly reduced in this mode. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the h i g h e st l e ve l s o f q u a l i ty, re l i a b il i ty, a n d c o s t effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection. Am29F010 PRODUCT SELECTOR GUIDE Family Part Number Speed Option Am29F010 VCC = 5.0 V ± 5% -45 -55 (P) VCC = 5.0 V ± 10% -55 (J, E, F) -70 -90 -120 Max Access Time (ns) 45 55 70 90 120 CE# Access (ns) 45 55 70 90 120 OE# Access (ns) 25 30 30 35 50 Note: See the AC Characteristics section for full specifications. BLOCK DIAGRAM DQ0–DQ7 VCC VSS WE# Input/Output Buffers Erase Voltage Generator State Control Command Register PGM Voltage Generator Chip Enable Output Enable Logic CE# OE# VCC Detector Address Latch STB Timer A0–A16 STB Data Latch Y-Decoder Y-Gating X-Decoder Cell Matrix 16736G-1 Am29F010 3 CONNECTION DIAGRAMS 2 31 WE# A15 3 30 NC A12 4 29 A14 A7 5 29 A14 A7 5 28 A13 A6 6 28 A13 A6 6 27 A8 A5 A5 7 26 A9 A4 7 8 27 26 A9 A4 8 A3 9 25 A11 9 PDIP 25 24 A11 A3 OE# A2 10 24 OE# A2 10 23 A10 A1 11 23 A10 A1 11 22 CE# A0 12 22 A0 12 21 DQ7 DQ0 13 CE# DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 VSS 16 17 DQ3 A11 A9 A8 A13 A14 NC WE# VCC NC A16 A15 A12 A7 A6 A5 A4 4 3 2 WE# NC A16 VCC VCC A16 32 NC 1 A12 A15 NC 1 32 31 30 PLCC 21 DQ5 DQ6 DQ4 VSS DQ3 DQ1 DQ2 14 15 16 17 18 19 20 16736G-2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A8 Standard TSOP 16736G-3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 16736G-4 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Reverse TSOP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A11 A9 A8 A13 A14 NC WE# VCC NC A16 A15 A12 A7 A6 A5 A4 16736G-5 4 Am29F010 PIN CONFIGURATION A0–A16 LOGIC SYMBOL = 17 Addresses DQ0–DQ7 = 8 Data Inputs/Outputs 17 CE# = Chip Enable OE# = Output Enable WE# = Write Enable VCC = +5.0 Volt Single Power Supply (See Product Selector Guide for speed options and voltage supply tolerances) VSS = Device Ground NC = Pin Not Connected Internally A0–A16 8 DQ0–DQ7 CE# OE# WE# 16736G-6 Am29F010 5 ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am29F010 -70 E C B OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In (Contact an AMD representative for more information.) TEMPERATURE RANGE C = Commercial (0°C to +70°C) I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C) PACKAGE TYPE P = 32-Pin Plastic DIP (PD 032) J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032) E = 32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032) F = 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR032) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am29F010 1 Megabit (128 K x 8-Bit) CMOS Flash Memory 5.0 Volt-only Read, Program, and Erase Valid Combinations Valid Combinations AM29F010-45 Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. PC, PI, PE, JC, JI, JE, EC, EI, EE, FC, FI, FE AM29F010-55 VCC = 5.0 V ± 5% PC5, PI5, PE5 AM29F010-55 VCC = 5.0 V ± 10% JC, JI, JE, EC, EI, EE, FC, FI, FE AM29F010-70 AM29F010-90 AM29F010-120 6 PC, PI, PE, JC, JI, JE, EC, EI, EE, FC, FI, FE Am29F010 DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the Table 1. register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The appropriate device bus operations table lists the inputs and control levels required, and the resulting output. The following subsections describe each of these operations in further detail. Am29F010 Device Bus Operations CE# OE# WE# Addresses (Note 1) DQ0–DQ7 Read L L H AIN DOUT Write L H L AIN DIN VCC ± 0.5 V X X X High-Z Output Disable L H H X High-Z Hardware Reset X X X X High-Z Temporary Sector Unprotect X X X AIN DIN Operation Standby Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Addresses In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A16:A0. 2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Protection/Unprotection” section. Requirements for Reading Array Data Writing Commands/Command Sequences To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See “Reading Array Data” for more information. Refer to the AC Read Operations table for timing specifications and to the Read Operations Timings diagram for the timing waveforms. ICC1 in the DC Characteristics table represents the active current specification for reading array data. An erase operation can erase one sector, multiple sectors, or the entire device. The Sector Address Tables indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. See the “Command Definitions” section for details on erasing a sector or the entire chip. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations. Am29F010 7 Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to “Write Operation Status” for more information, and to each AC Characteristics section in the appropriate data sheet for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. Table 2. The device enters the CMOS standby mode when the CE# pin is held at VCC ± 0.5 V. (Note that this is a more restricted voltage range than VIH.) The device enters the TTL standby mode when CE# is held at VIH. The device requires the standard access time (tCE) before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics tables represents the standby current specification. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state. Am29F010 Sector Addresses Table Sector A16 A15 A14 Address Range SA0 0 0 0 00000h-03FFFh SA1 0 0 1 04000h-07FFFh SA2 0 1 0 08000h-0BFFFh SA3 0 1 1 0C000h-0FFFFh SA4 1 0 0 10000h-13FFFh SA5 1 0 1 14000h-17FFFh SA6 1 1 0 18000h-1BFFFh SA7 1 1 1 1C000h-1FFFFh Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes (High Voltage Method) table. In addition, when verifying sector protection, the sector ad- 8 dress must appear on the appropriate highest order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions table shows the remaining address bits that are don’t care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7–DQ0. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the Command Definitions table. This method does not require VID . See “Command Definitions” for details on using the autoselect mode. Am29F010 Table 3. Am29F010 Autoselect Codes (High Voltage Method) CE# OE# WE# A16 to A14 Manufacturer ID: AMD L L H X X VID X L X L L 01h Device ID: Am29F010 L L H X X VID X L X L H 20h Description A13 to A10 A9 A8 to A7 A6 A5 to A2 A1 A0 DQ7 to DQ0 01h (protected) Sector Protection Verification L L H SA X VID X L X H L 00h (unprotected) L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. Sector Protection/Unprotection The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Sector protection/unprotection must be implemented using programming equipment. The procedure requires a high voltage (VID) on address pin A9 and the control pins. Details on this method are provided in a supplement, publication number 20495. Contact an AMD representative to obtain a copy of the appropriate document. The device is shipped with all sectors unprotected. AMD offers the option of programming and protecting sectors at its factory prior to shipping the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. It is possible to determine whether a sector is protected or unprotected. See “Autoselect Mode” for details. gramming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until VCC is greater than VLKO . The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Hardware Data Protection Power-Up Write Inhibit The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to the Command Definitions table). In addition, the following hardware data protection measures prevent accidental erasure or pro- If WE# = CE# = V IL and OE# = V IH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is a u to m at i c a l l y r e s e t t o r e a d i n g a r r a y d a ta o n power-up. Am29F010 9 COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next. See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parameters, and Read Operation Timings diagram shows the timing diagram. Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data. 10 Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. The Command Definitions table shows the address and data requirements. This method is an alternative to that shown in the Autoselect Codes (High Voltage Method) table, which is intended for PROM programmers and requires VID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h or retrieves the manufacturer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. Refer to the Sector Address tables for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Byte Program Command Sequence Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verify the programmed cell margin. The Command Definitions take shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using DQ7or DQ6. See “Write Operation Status” for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still “0”. Only erase operations can convert a “0” to a “1”. Am29F010 Chip Erase Command Sequence Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The Command Definitions table shows the address and data requirements for the chip erase command sequence. START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No The system can determine the status of the erase operation by using DQ7 or DQ6. See “Write Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Yes Increment Address No Last Address? Figure 2 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in “AC Characteristics” for parameters, and to the Chip/Sector Erase Operation Timings for timing waveforms. Yes Programming Completed 16736G-7 Note: See the appropriate Command Definitions table for program command sequence. Figure 1. Program Operation Any commands written to the chip during the Embedded Erase algorithm are ignored. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is Am29F010 11 written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the system need not monitor DQ3. Any command during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. START Write Erase Command Sequence The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the “DQ3: Sector Erase Timer” section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Data Poll from System Once the sector erase operation has begun, all other commands are ignored. No When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7 or DQ6. Refer to “Write Operation Status” for information on these status bits. Figure 2 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the “AC Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms. Embedded Erase algorithm in progress Data = FFh? Yes Erasure Completed 16736G-8 Notes: 1. See the appropriate Command Definitions table for erase command sequence. 2. See “DQ3: Sector Erase Timer” for more information. Figure 2. 12 Am29F010 Erase Operation Table 4. Am2F010 Command Definitions Cycles Bus Cycles (Notes 2-3) Addr Read (Note 4) 1 RA RD Reset (Note 5) 1 XXXX F0 Manufacturer ID 4 5555 AA 2AAA 55 5555 90 XX00 01 Device ID 4 5555 AA 2AAA 55 5555 90 XX01 20 Sector Protect Verify (Note 7) 5555 AA 2AAA 55 5555 90 (SA) X02 00 4 Command Sequence (Note 1) Autoselect (Note 6) First Second Data Third Addr Data Addr Fourth Data Addr Data Fifth Sixth Addr Data Addr Data 01 Program 4 5555 AA 2AAA 55 5555 A0 PA PD Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA 30 Legend: X = Don’t care PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except when reading array or autoselect data, all command bus cycles are write operations. 4. No unlock or command cycles required when reading array data. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A16–A14 uniquely select any sector. 5. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data). 6. The fourth cycle of the autoselect command sequence is a read operation. 7. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information. Am29F010 13 WRITE OPERATION STATUS The device provides several bits to determine the status of a write operation: DQ3, DQ5, DQ6, and DQ7. Table 5 and the following subsections describe the functions of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. These three bits are discussed first. Table 5 shows the outputs for Data# Polling on DQ7. Figure 3 shows the Data# Polling algorithm. START DQ7: Data# Polling Read DQ7–DQ0 Addr = VA The Data# Polling bit, DQ7, indicates to the host sy stem whether an Embedded Algorithm is in progress or completed. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 2 µs, then the device returns to reading array data. DQ7 = Data? No No When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7– DQ0 on the following read cycles. This is because DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. The Data# Polling Timings (During Embedded Algorithms) figure in the “AC Characteristics” section illustrates this. DQ5 = 1? Yes During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, Data# Polling produces a “1” on DQ7. This is analogous to the complement/true datum output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to “1”; prior to this, the device outputs the “complement,” or “0.” The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. Read DQ7–DQ0 Addr = VA DQ7 = Data? Yes No FAIL PASS Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. 16736G-9 Figure 3. 14 Yes Am29F010 Data# Polling Algorithm DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. START Read DQ7–DQ0 During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. Read DQ7–DQ0 After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. Toggle Bit = Toggle? No Read DQ7–DQ0 Twice Reading Toggle Bit DQ6 The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not DQ5 = 1? Yes The Write Operation Status table shows the outputs for Toggle Bit I on DQ6. Refer to Figure 4 for the toggle bit algorithm, and to the Toggle Bit Timings figure in the “AC Characteristics” section for the timing diagram. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. No Yes If a program address falls within a protected sector, DQ6 toggles for approximately 2 µs after the program command sequence is written, then returns to reading array data. Refer to Figure 4 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. 1 Toggle Bit = Toggle? (Notes 1, 2) No Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. See text. 16736G-10 Figure 4. Toggle Bit Algorithm gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 4). Am29F010 15 DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or erase cycle was not successfully completed. The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a “1.” Under both these conditions, the system must issue the reset command to return the device to reading array data. DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If addi- Table 5. Operation Embedded Program Algorithm Embedded Erase Algorithm tional sectors are selected for erasure, the entire timeout also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from “0” to “1.” The system may ignore DQ3 if the system can guarantee that the time between additional sector erase commands will always be less than 50 µs. See also the “Sector Erase Command Sequence” section. After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device has accepted the command sequence, and then read DQ3. If DQ3 is “1”, the internally controlled erase cycle has begun; all further commands are ignored until the erase operation is complete. If DQ3 is “0”, the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 5 shows the outputs for DQ3. Write Operation Status DQ7 (Note 1) DQ6 DQ5 (Note 2) DQ3 DQ7# Toggle 0 N/A 0 Toggle 0 1 Notes: 1. DQ7 requires a valid address when reading status information. Refer to the appropriate subsection for further details. 2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See “DQ5: Exceeded Timing Limits” for more information. 16 Am29F010 ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C Ambient Temperature with Power Applied . . . . . . . . . . . . . –55°C to +125°C Voltage with Respect to Ground VCC (Note 1). . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V 20 ns 20 ns +0.8 V –0.5 V –2.0 V A9 (Note 2). . . . . . . . . . . . . . . . . . . .–2.0 V to +12.5 V 20 ns All other pins (Note 1) . . . . . . . . . . . .–2.0 V to +7.0 V Output Short Circuit Current (Note 3) . . . . . . 200 mA 16736G-11 Notes: 1. Minimum DC voltage on input or I/O pin is –0.5 V. During voltage transitions, inputs may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 5. Maximum DC voltage on input and I/O pins is VCC + 0.5 V. During voltage transitions, input and I/O pins may overshoot to V CC + 2.0 V for periods up to 20 ns. See Figure 6. 2. Minimum DC input voltage on A9 pin is –0.5V. During voltage transitions, A9 pins may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 5. Maximum DC input voltage on A9 is +12.5 V which may overshoot to 13.5 V for periods up to 20 ns. Figure 5. Maximum Negative Overshoot Waveform 20 ns VCC +2.0 V VCC +0.5 V 2.0 V 3. No more than one output shorted at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. 20 ns 20 ns 16736G-12 Figure 6. Maximum Positive Overshoot Waveform OPERATING RANGES Commercial (C) Devices Case Temperature (TA) . . . . . . . . . . . . . 0°C to +70°C Industrial (I) Devices Case Temperature (TA) . . . . . . . . . . . –40°C to +85°C Extended (E) Devices Case Temperature (TA) . . . . . . . . . . –55°C to +125°C VCC Supply Voltages VCC for ±5% devices . . . . . . . . . . .+4.75 V to +5.25 V VCC for ±10% devices . . . . . . . . . .+4.50 V to +5.50 V Operating ranges define those limits between which the functionality of the device is guaranteed. Am29F010 17 DC CHARACTERISTICS TTL/NMOS Compatible Parameter Symbol Parameter Description Test Description Max Unit ±1.0 µA 50 µA ±1.0 µA ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.5 V ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ICC1 VCC Active Current (Note 1) CE# = VIL, OE# = VIH, VCC = VCC Max 30 mA ICC2 VCC Active Current (Notes 2, 3) CE# = VIL, OE# = VIH, VCC = VCC Max 50 mA ICC3 VCC Standby Current VCC = VCC Max, CE# and OE# = VIH 1.0 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 2.0 VCC + 0.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 5.0 V 11.5 12.5 V VOL Output Low Voltage IOL = 12 mA, VCC = VCC Min 0.45 V VOH Output High Voltage IOH = –2.5 mA, VCC = VCC Min VLKO Low VCC Lock-out Voltage 2.4 3.2 Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. ICC active while Embedded Program or Embedded Erase Algorithm is in progress. 3. Not 100% tested. 18 Min Am29F010 V 4.2 V DC CHARACTERISTICS (continued) CMOS Compatible Parameter Symbol Parameter Description Test Description Min Max Unit ±1.0 µA 50 µA ±1.0 µA ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.5 V ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ICC1 VCC Active Current (Note 1) CE# = VIL, OE# = VIH, VCC = VCC Max 30 mA ICC2 VCC Active Current (Notes 2, 3) CE# = VIL, OE# = VIH, VCC = VCC Max 50 mA ICC3 VCC Standby Current 100 µA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 x VCC VCC + 0.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 5.0 V 11.5 12.5 V VOL Output Low Voltage IOL = 12 mA, VCC = VCC Min 0.45 V VOH1 Output High Voltage VOH2 VLKO VCC = VCC Max, CE# = VCC ± 0.5 V, OE# = VIH IOH = –2.5 mA, VCC = VCC Min 0.85 VCC V IOH = –100 µA, VCC = VCC Min VCC –0.4 V Low VCC Lock-out Voltage 3.2 4.2 V Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. ICC active while Embedded Program or Embedded Erase Algorithm is in progress. 3. Not 100% tested. Am29F010 19 TEST CONDITIONS Table 6. Test Specifications 5.0 V Test Condition Output Load 2.7 kΩ Device Under Test CL -45 6.2 kΩ 1 TTL gate Output Load Capacitance, CL (including jig capacitance) 30 100 pF Input Rise and Fall Times 5 20 ns 0.0–3.0 0.45–2.4 V Input timing measurement reference levels 1.5 0.8 V Output timing measurement reference levels 1.5 2.0 V Input Pulse Levels Note: Diodes are IN3064 or equivalent All others Unit 16736G-13 Figure 7. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Steady Changing from H to L Changing from L to H Don’t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High Z) KS000010-PAL 20 Am29F010 AC CHARACTERISTICS Read-only Operations Characteristics Parameter Symbol JEDEC Std. Parameter Description Test Setup -45 -55 -70 -90 -120 Unit Min 45 55 70 90 120 ns tAVAV tRC Read Cycle Time (Note 1) tAVQV tACC Address to Output Delay CE# = VIL OE# = VIL Max 45 55 70 90 120 ns tELQV tCE Chip Enable to Output Delay OE# = VIL Max 45 55 70 90 120 ns tGLQV tOE Output Enable to Output Delay Max 25 30 30 35 50 ns tEHQZ tDF Chip Enable to Output High Z (Notes 1, 2) Max 10 15 20 20 30 ns tGHQZ tDF Output Enable to Output High Z (Notes 1, 2) Max 10 15 20 20 30 ns tOEH Output Enable Hold Time (Note 1) tOH Output Hold Time From Addresses CE# or OE#, Whichever Occurs First tAXQX Read Min 0 ns Toggle and Data Polling Min 10 ns Min 0 ns Notes: 1. Not 100% tested. 2. Output Driver Disable Time. 3. See Figure 7 and Table 6 for test specifications. tRC Addresses Stable Addresses tACC CE# tDF tOE OE# tOEH WE# tCE tOH HIGH Z HIGH Z Output Valid Outputs 16736G-14 Figure 8. Read Operations Timings Am29F010 21 AC CHARACTERISTICS Erase and Program Operations Parameter Symbol JEDEC Standard Parameter Description -45 -55 -70 -90 -120 Unit 45 55 70 90 120 ns tAVAV tWC Write Cycle Time (Note 1) Min tAVWL tAS Address Setup Time Min tWLAX tAH Address Hold Time Min 35 45 45 45 50 ns tDVWH tDS Data Setup Time Min 20 20 30 45 50 ns tWHDX tDH Data Hold Time Min 0 ns tGHWL tGHWL Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min tWHWL tWPH Write Pulse Width High Min 20 ns tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 14 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1.0 sec tVCS VCC Set Up Time (Note 1) Min 50 µs Read Recover Time Before Write (OE# High to WE# Low) 0 25 Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more informaiton. 22 Am29F010 30 35 ns 45 50 ns AC CHARACTERISTICS Program Command Sequence (last two cycles) tAS tWC Addresses 555h Read Status Data (last two cycles) PA PA PA tAH CE# tCH tGHWL OE# tWHWH1 tWP WE# tWPH tCS tDS tDH PD A0h Data Status DOUT tVCS VCC 16736G-13 Note: PA = program address, PD = program data, DOUT is the true data at the program address. Figure 9. Program Operation Timings Erase Command Sequence (last two cycles) tAS tWC 2AAh Addresses Read Status Data VA SA VA 555h for chip erase tAH CE# tGHWL tCH OE# tWP WE# tWPH tCS tWHWH2 tDS tDH Data 55h 30h In Progress Complete 10 for Chip Erase tVCS VCC 16736G-13 Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”). Figure 10. Chip/Sector Erase Operation Timings Am29F010 23 AC CHARACTERISTICS tRC Addresses VA VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH High Z DQ7 Complement Complement DQ0–DQ6 Status Data Status Data Valid Data True High Z Valid Data True Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. 16736G-15 Figure 11. Data# Polling Timings (During Embedded Algorithms) tRC Addresses VA VA VA VA tACC tCE CE# tCH tOE OE# tOEH tDF WE# tOH DQ6 High Z Valid Status Valid Status (first read) (second read) Valid Status Valid Data (stops toggling) Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. 16736G-16 Figure 12. 24 Toggle Bit Timings (During Embedded Algorithms) Am29F010 AC CHARACTERISTICS Erase and Program Operations Alternate CE# Controlled Writes Parameter Symbol JEDEC Standard Parameter Description -45 -55 -70 -90 -120 Unit 45 55 70 90 120 ns tAVAV tWC Write Cycle Time (Note 1) Min tAVEL tAS Address Setup Time Min tELAX tAH Address Hold Time Min 35 45 45 45 50 ns tDVEH tDS Data Setup Time Min 20 20 30 45 50 ns tEHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time (Note 1) Min 0 ns tGHEL tGHEL Read Recover Time Before Write Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min tEHEL tCPH CE# Pulse Width High Min 20 ns tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 14 µs tWHWH2 tWHWH2 Chip/Sector Erase Operation (Note 2) Typ 1.0 sec 0 25 30 35 ns 45 50 ns Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Am29F010 25 AC CHARACTERISTICS 555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase Data# Polling Addresses PA tWC tAS tAH tWH WE# tGHEL OE# tWHWH1 or 2 tCP CE# tWS tCPH tDS tDH DQ7# Data A0 for program 55 for erase DOUT PD for program 30 for sector erase 10 for chip erase Notes: 1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data. 2. Figure indicates the last two bus cycles of the command sequence. 16736G-17 Figure 13. Alternate CE# Controlled Write Operation Timings ERASE AND PROGRAMMING PERFORMANCE Limits Parameter Typ (Note 1) Max (Note 2) Unit Comments Chip/Sector Erase Time 1.0 15 sec Excludes 00h programming prior to erasure (Note 4) Byte Programming Time 14 1000 µs Chip Programming Time (Note 3) 1.8 12.5 sec Excludes system-level overhead (Note 5) Notes: 1. Typical program and erase times assume the following conditions: 25°C, 5.0 V VCC, 100,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 4.5 V (4.75 V for -45, -55 PDIP), 100,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does the device set DQ5 = 1. See the section on DQ5 for further information. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 1 for further information on command definitions. 6. The device has a typical erase and program cycle endurance of 1,000,000 cycles. 100,000 cycles are guaranteed. 26 Am29F010 LATCHUP CHARACTERISTIC Parameter Description Input Voltage with respect to VSS on I/O pins VCC Current Min Max –1.0 V VCC + 1.0 V –100 mA +100 mA Note: Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time. TSOP PIN CAPACITANCE Parameter Symbol Parameter Description Test Conditions Input Capacitance VIN = 0 COUT Output Capacitance VOUT = 0 CIN2 Control Pin Capacitance VIN = 0 CIN Typ Max Unit 6 7.5 pF 8.5 12 pF 8 10 pF Typ Max Unit Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. PLCC AND PDIP PIN CAPACITANCE Parameter Symbol Parameter Description Test Conditions Input Capacitance VIN = 0 4 6 pF COUT Output Capacitance VOUT = 0 8 12 pF CIN2 Control Pin Capacitance VPP = 0 8 12 pF CIN Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Description Test Conditions Min Unit 150°C 10 Years 125°C 20 Years Minimum Pattern Data Retention Time Am29F010 27 PHYSICAL DIMENSIONS PD 032 32-Pin Plastic DIP (measured in inches) 1.640 1.680 .600 .625 17 32 .008 .015 .530 .580 Pin 1 I.D. .630 .700 16 .045 .065 0˚ 10˚ .005 MIN .140 .225 16-038-SB_AG PD 032 DG75 2-28-95 ae SEATING PLANE .090 .110 .120 .160 .014 .022 .015 .060 PL 032 32-Pin Plastic Leaded Chip Carrier (measured in inches) .447 .453 .485 .495 .009 .015 .585 .595 .042 .056 .125 .140 Pin 1 I.D. .080 .095 .547 .553 SEATING PLANE .400 REF. .490 .530 .013 .021 .050 REF. .026 .032 TOP VIEW 28 SIDE VIEW Am29F010 16-038FPO-5 PL 032 DA79 6-28-94 ae PHYSICAL DIMENSIONS (continued) TS 032 32-Pin Standard Thin Small Outline Package (measured in millimeters) 0.95 1.05 Pin 1 I.D. 1 7.90 8.10 0.50 BSC 0.05 0.15 18.30 18.50 19.80 20.20 0.08 0.20 0.10 0.21 1.20 MAX 0° 5° 0.25MM (0.0098") BSC 16-038-TSOP-2 TS 032 DA95 4-4-95 ae 0.50 0.70 Am29F010 29 PHYSICAL DIMENSIONS (continued) TSR 032 32-Pin Standard Thin Small Outline Package (measured in millimeters) 0.95 1.05 Pin 1 I.D. 1 7.90 8.10 0.50 BSC 0.05 0.15 18.30 18.50 19.80 20.20 0.08 0.20 0.10 0.21 1.20 MAX 0° 5° 0.25MM (0.0098") BSC 0.50 0.70 30 Am29F010 16-038-TSOP-2 TSR032 DA95 4-4-95 ae REVISION SUMMARY FOR AM29F010 Revision F+1 Erase and Programming Performance Product Selector Guide There are now two VCC supply operating ranges available for the 55 ns speed option. The PDIP package is only available in the ±5% VCC operating range. The other packages are available in the ±10% operating range. Ordering Information The 45 ns speed grade is now also available in PC configuration (PDIP package, commercial temperature.) Operating Ranges VCC Supply Voltages: Changed to reflect the available speed options. AC Characteristics Write/Erase/Program Operations: Corrected to indicate tVLHT, tOESP, tWHWH1, and tWHWH2 are typical values, not minimum values. Changed value for tWHWH2. AC Characteristics Write/Erase/Program Operations, Alternate CE# Controlled Writes: Corrected to indicate t WHWH1 and t WHWH2 are typical values, not minimum values. Changed value for tWHWH2. Combined chip and sector erase specifications; changed typical and maximum values. Added Note 6. Revision G Global Made formatting and layout consistent with other data sheets. Used updated common tables and diagrams. Revision G+1 Table 4, Command Definitions Address bits A0–A14 are required for unlock cycles. Therefore, addresses for second and fifth write cycles are 2AAAh. Addresses for first, third, fourth, and sixth cycles are 5555h. Read cycles are not affected. Deleted Note 4 to reflect the correction. Revision G+2 AC Characteristics Erase/Program Operations; Erase and Program Operations Alternate CE# Controlled Writes: Corrected the notes reference for tWHWH1 and tWHWH2. These parameters are 100% tested. Corrected the note reference for tVCS. This parameter is not 100% tested. Trademarks Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Am29F010 31