ICST M2006-02AI669.6429 Vcso based fec clock pll Datasheet

Product Data Sheet
Integrated
Circuit
Systems, Inc.
M2006-02A
VCSO BASED FEC CLOCK PLL
GENERAL DESCRIPTION
PIN ASSIGNMENT (9 x 9 mm SMT)
27
26
25
24
23
22
21
20
19
FIN_SEL1
GND
NC
DIF_REF0
nDIF_REF0
REF_SEL
DIF_REF1
nDIF_REF1
VCC
The M2006-02A is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator
PLL designed for clock frequency
translation and jitter attenuation.
The device supports both forward
and inverse FEC (Forward Error
Correction) clock multiplication
ratios. Multiplication ratios are
pin-selected from pre-programming look-up tables.
FIN_SEL0
FEC_SEL0
FEC_SEL1
FEC_SEL2
FEC_SEL3
VCC
DNC
DNC
DNC
FEATURES
• 255/238 (OTU1) Mapping and 238/255 De-mapping
• 255/237 (OTU2) Mapping and 237/255 De-mapping
• 255/236 (OTU3) Mapping and 236/255 De-mapping
M2006-02A
(Top View)
P0_SEL
P1_SEL
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
GND
18
17
16
15
14
13
12
11
10
GND
GND
GND
OP_IN
nOP_OUT
nVC
VC
OP_OUT
nOP_IN
1
2
3
4
5
6
7
8
9
◆ Reduced intrinsic output jitter and improved power
supply noise rejection compared to M2006-02
◆ Low phase jitter of 0.25 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
◆ Pin-selectable PLL divider ratios support forward and
inverse FEC ratio translation, including:
28
29
30
31
32
33
34
35
36
Figure 1: Pin Assignment
◆ Input reference and VCSO frequencies up to 700MHz,
supports loop timing modes
(Specify VCSO frequency at time of order)
◆ Supports active switching between inverse-FEC and
non-FEC clock ratios (same VCSO center frequency)
◆ Ideal for complex ratio FEC ratio translation and
for use with an unstable reference (i.e., similar to the
M2006-12A - and pin-compatible - but without the
Hitless Switching and Phase Build-out functions)
Example I/O Clock Combinations
Using M2006-02A-622.0800
PLL Ratio
Input Clock (MHz)
Output Clock (MHz)
1/1
622.08, 155.52,
77.76, or 19.44
669.3266, 167.3316,
83.6658, or 20.9165
622.08
or
155.52
237/255
(inverse FEC)
Table 1: Example I/O Clock Combinations Using M2006-02A-622.0800
Using M2006-02A-669.3266
◆ Single 3.3V power supply
PLL Ratio
Input Clock (MHz)
Output Clock (MHz)
◆ Small 9 x 9 mm SMT (surface mount) package
237/255
(FEC rate)
1/1
622.08, 155.52,
77.76, or 19.44
669.3266, 167.3316,
83.6658, or 20.9165
669.3266
or
167.3316
Table 2: Example I/O Clock Combinations Using M2006-02A-669.3266
SIMPLIFIED BLOCK DIAGRAM
Loop
Filter
M2006-02A
DIF_REF0
0
nDIF_REF0
Rfec Div
DIF_REF1
Mfec Div
REF_SEL
FIN_SEL1:0
(1 or 4)
nFOUT0
1
nDIF_REF1
FEC_SEL3:0
FOUT0
P0 Div
VCSO
4
Mfin Div
(1, 4, 8, or 32)
Mfec / Rfec
Divider LUT
2
FOUT1
P1 Div
(1 or 4)
nFOUT1
Mfin Divider
LUT
P0_SEL
P1_SEL
Figure 2: Simplified Block Diagram
M2006-02A Datasheet Rev 1.0
Revised 28Jul2004
M2006-02A VCSO Based FEC Clock PLL
Integrated Circuit Systems, Inc.
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M2006-02A
Integrated
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Systems, Inc.
VCSO BASED FEC CLOCK PLL
Product Data Sheet
DETAILED BLOCK DIAGRAM
RLOOP
CLOOP
RPOST
External
Loop Filter
Components
CPOST
CPOST
RLOOP
M2006-02 A
OP_IN
MUX
DIF_REF0
nDIF_REF0
0
DIF_REF1
nDIF_REF1
1
Phase
Detector
RPOST
CLOOP
nOP_IN
OP_OUT
nOP_OUT
RIN
Rfec
Divider
RIN
Loop Filter
Amplifier
nVC
VC
SAW Delay Line
Phase
Locked
Loop
(PLL)
Phase
Shifter
VCSO
Mfec Divider
REF_SEL
Mfin Divider
P0 Divider
FEC_SEL3:0
FIN_SEL1:0
4
FOUT0
nFOUT0
P = 1 ( P0_SEL = 0 )
or 4 ( P0_SEL = 1 )
Mfec / Rfec
Divider LUT
P1 Divider
Mfin Divider
LUT
2
FOUT1
nFOUT1
P = 1 ( P1_SEL = 0 )
or 4 ( P1_SEL = 1 )
P0_SEL
P1_SEL
Figure 3: Detailed Block Diagram
PIN DESCRIPTIONS
Number
1, 2, 3, 10, 14, 26
4
9
5
8
6
7
Name
GND
OP_IN
nOP_IN
nOP_OUT
OP_OUT
nVC
VC
11, 19, 33
VCC
12, 13
15, 16
17
18
FOUT1, nFOUT1
FOUT0, nFOUT0
P1_SEL
P0_SEL
20
21
nDIF_REF1
22
REF_SEL
23
24
nDIF_REF0
25
27
28
29
30
31
32
NC
FIN_SEL1
FIN_SEL0
FEC_SEL0
FEC_SEL1
FEC_SEL2
FEC_SEL3
34, 35, 36
DNC
I/O
Configuration
Description
Ground
Power supply ground connections.
Input
External loop filter connections. See Figure 4.
Output
Input
Power
Output
Input
Input
DIF_REF1
Input
Input
DIF_REF0
Power supply connection, connect to +3.3V.
No internal terminator
Clock output pairs. Differential LVPECL.
Internal pull-down resistor1
P Divider controls. LVCMOS/LVTTL.
(For P0_SEL, P1_SEL, see Table 6 on pg. 3.
Internal pull-UP resistor1
Reference clock input pair 1.
Differential LVPECL or LVDS.
Internal pull-down resistor1
Internal pull-down resistor1
Internal pull-UP resistor1
1
Internal pull-down resistor
Reference clock input selection. LVCMOS/LVTTL:
Logic 1 selects DIF_REF1, nDIF_REF1.
Logic 0 selects DIF_REF0, nDIF_REF0.
Reference clock input pair 0.
Differential LVPECL or LVDS.
No internal connection.
Input clock frequency selection. LVCMOS/LVTTL.
(For FIN_SEL1:0, see Table 4 on pg. 3.
Input
Internal pull-down resistor1
Input
Internal pull-UP resistor1
FEC PLL divider ratio selection. LVCMOS/ LVTTL.
(For FEC_SEL3:0, see Table 5 on pg. 3.)
Do Not Connect.
Internal nodes. Connection to these pins can
cause erratic device operation.
Table 3: Pin Descriptions
M2006-02A Datasheet Rev 1.0
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VCSO BASED FEC CLOCK PLL
Product Data Sheet
PLL DIVIDER LOOK-UP TABLES
Post-PLL Dividers
Mfin Divider Look-Up Table (LUT)
The M2006-02A also features two post-PLL dividers,
one for each output pair. The “P1” divider is for FOUT1
and nFOUT1; the “P0” divider is for FOUT0 and nFOUT0.
The FIN_SEL1:0 pins select the feedback divider value
“Mfin” (for Frequency Input).
Mfin Value
FIN_SEL1:0
1
1
0
0
1
0
1
0
1*
4
8
32
M2006-02A-622.0800
Sample Ref. Freq. (MHz) †
622.08
155.52
77.76
19.44
Each divides the VCSO frequency to produce one of
two output frequencies (1/4 or 1/1 of the VCSO
frequency). The P1_SEL and P0_SEL pins each select the
value for their corresponding divider.
M2006-02A-622.0800
Table 4: Mfin Divider Look-Up Table (LUT)
Note *: Do not use with FEC_SEL3:0=1100 or 1101 or an excessive
phase detector frequency will result.
Note †: Example with M2006-02A-622.0800 and “Non-FEC ratio”
selection made from Table 5 (FEC_SEL2=1).
P1_SEL, P0_SEL
P Value
1
0
4
1
Sample Output
Frequency (MHz)
155.52
622.08
Table 6: P Divider Selector, Values, and Frequencies
FEC PLL Ratio Dividers Look-up Table (LUT)
FUNCTIONAL DESCRIPTION
The FEC_SEL3:0 pins select the FEC feedback and
reference divider values Mfec and Rfec.
The M2006-02A is a PLL (Phase Locked Loop) based
clock generator that generates output clocks synchronized to one of two selectable input reference clocks.
FEC_SEL3:0 Mfec Rfec1
0
0
0
0
0
0
0
0
An internal high "Q" SAW filter provides low jitter signal
performance and controls the output frequency of the
VCSO (Voltage Controlled SAW Oscillator).
0
1
0
1
236
79
14
239
255
85
15
255
0 1 0 0
236
236 Non-FEC ratio, complements 0000 or 1000 2
0 1 0 1
79
79
Non-FEC ratio, complements 0001 or 1001 2
0 1 1 0
14
14
Non-FEC ratio, complements 0010 or 1010 2
0
1
1
1
1
1
1
1
1
239
255
85
15
255
1
2
4
8
239
236
79
14
239
1
2
4
8
Non-FEC ratio, complements 0011 or 1011 2
FEC ratio (OTU3)
FEC ratio, equivalent to 255/237 (OTU2)
FEC ratio, equivalent to 255/238 (OTU1)
FEC ratio
1
0
0
0
0
1
1
1
1
0
0
1
1
Description
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
Inverse FEC ratio
Inverse FEC ratio, equivalent to 237/255
Inverse FEC ratio, equivalent to 238/255
Inverse FEC ratio
Configurable FEC feedback and reference dividers (the
“Mfec Divider” and “Rfec Divider”) provide the
multiplication ratios necessary to accomodate clock
translation for both forward and inverse Forward Error
Correction.
In addition, a configurable feedback divider (labeled
“Mfin Divider”) provides the broader division options
needed to accomodate various reference clock
frequencies.
Non-FEC ratio 3 Do not use these two settings
with FIN_SEL1:0=11
For example, the M2006-02A-622.0800 (see “Ordering
Information” on pg. 8) has a 622.08MHz VCSO
frequency:
• The inverse FEC PLL ratios (at top of Table 5) enable
Non-FEC ratio 3
Table 5: FEC PLL Ratio Dividers Look-up Table (LUT)
Note 1: The phase detector frequency (Fpd, which is calculated as
Fref/Rfec) should be above 1.5 MHz to prevent spurs on the
output clock. To ensure the PLL remains locked when using a
recovered clock (such as in loop timing mode), the phase
detector frequency should ideally be about 20MHz, or at least
less than 50 MHz.
Note 2: These table selections use the same or similar Mfec divider
values as the complementary selections noted. This allows the
use of the same loop filter component values and yields the
same PLL loop bandwidth and damping factor values for
complementary selections. Complementary selections can be
actively switched in a given application.
Note 3: In non-FEC applications, these settings can be used to
optimize phase detector frequency or to actively change PLL
loop bandwidth.
M2006-02A Datasheet Rev 1.0
Integrated Circuit Systems, Inc.
•
the M2006-02A-622.0800 to accept “base” input reference
frequencies of: 663.7255, 666.5143, 669.3266,
672.1627, and 622.08MHz.
The Mfin feedback divider enables the actual input
reference clock to be the “base” input frequency
divided by 1, 4, 8, or 32. Therefore, for the base input
frequency of 622.08MHz, the actual input reference
clock frequencies can be: 622.08, 155.52, 77.76, and
19.44MHz. (See Table 4 on pg. 3.)
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Integrated
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Systems, Inc.
VCSO BASED FEC CLOCK PLL
Product Data Sheet
The PLL
Relationship Among Frequencies and Dividers
The PLL uses a phase detector and configurable
dividers to synchronize the output of the VCSO with
selected reference clock.
The VCSO center frequency must be specified at time
of order. The relationship between the VCSO (Fvcso)
frequency, the Mfin divider, the Mfec divider, the Rfec
divider, and the input reference frequency (Fin) is:
The “Mfin Divider” and “Mfec Divider” divide the VCSO
frequency, feeding the result into the phase detector.
Mfec
Fvcso = Fin × Mfin × -------------Rfec
The selected input reference clock is divided by the
“Rfec Divider”. The result is fed into the other input of
the phase detector.
The phase detector compares its two inputs. It then
outputs pulses to the loop filter as needed to increase or
decrease the VCSO frequency and thereby match and
lock the divider output’s frequency and phase to those
of the input reference clock.
As an example, for the M2006-02A-622.0800, the non-FEC
and inverse-FEC PLL ratios in Table 5 enable use with
these corresponding input reference frequencies:
M2006-02A-622.0800
VCSO Clock
Frequency (MHz)
Due to the narrow tuning range of the VCSO
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
622.08
÷
FEC Ratio
1
/ 1
238 / 255
237 / 255
236 / 255
Table 7: Example FEC PLL Rations and Input Reference Frequencies
Note 1: Input reference clock (“Fin”) can be the base frequency
shown divided by “Mfin” (as shown in Table 4 on pg. 3).
Maintaining PLL Lock:
The narrow tuning range of the VCSO requires that the
input reference frequency must remain suitable for the
current look-up table selection. For example, when
switching between “Inverse FEC ratio” and “Non-FEC
ratio” look-up table selections (see Table 5 on pg. 3), the
input reference frequency must change accordingly in
order for the PLL to lock.
Outputs
The M2006-02A provides a total of two differential
LVPECL output pairs: FOUT1 and FOUT0. Because each
output pair has its own P divider, the FOUT1 pair and the
FOUT0 can output the two different frequencies at the
same time. For example, FOUT1 can output 155.52MHz
while FOUT0 outputs 622.08MHz.
An out-of-lock condition due to an inappropriate
configuration will typically result in the VCSO
operating at its lower or upper frequency rail,
which is approximately 200ppm above or below
the nominal VCSO center frequency.
M2006-02A Datasheet Rev 1.0
Integrated Circuit Systems, Inc.
M2006-02A-622.0800
Base Input Ref.
= Frequency (MHz) 1
622.0800
666.5143
669.3266
672.1627
Any unused output should be left unconnected
(floating) in the system application. This will
minimize output switching current and therefore
minimize noise modulation of the VCSO.
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VCSO BASED FEC CLOCK PLL
Product Data Sheet
External Loop Filter
To provide stable PLL operation, and thereby a low jitter
output clock, the M2006-02A requires the use of an
external loop filter. This is provided via the provided
filter pins (see Figure 4).
Due to the differential signal path design, the
implementation requires two identical complementary
RC filters as shown here.
RLOOP
CLOOP
PLL bandwidth is affected by loop filter component
values, “Mfec” and “Mfin” values, and the “PLL Loop
Constants” listed in AC Characteristics on pg. 7.
The various “Non-FEC ratio” settings can be used to
actively change PLL loop bandwidth in a given
application. See “FEC PLL Ratio Dividers Look-up
Table (LUT)” on pg. 3.
See Example External Loop Filter Component Values table.
RPOST
PLL Simulator Tool Available
CPOST
CPOST
RLOOP
OP_IN
nOP_IN
4
CLOOP
RPOST
OP_OUT
9
nOP_OUT
8
nVC
5
VC
6
A free PC software utility is available on the ICS website
(www.icst.com). The M2000 Timing Modules PLL
Simulator is a downloadable application that simulates
PLL jitter and wander transfer characteristics. This
enables the user to set appropriate external loop
component values in a given application.
7
Go to the SAW PLL Simulator Software web page at
www.icst.com/products/calculators/m2000filterSWdesc.htm
Figure 4: External Loop Filter
Example External Loop Filter Component Values1
VCSO Parameters: KVCO = 800kHz/V, RIN = 50kΩ, VCSO Bandwidth = 700kHz.
Device Configuration
FRef
(MHz)
Example External Loop Filter Component Values
FVCSO (MHz) FIN_SEL1:0 FEC_ SEL3:0
pins
pins
R loop
C loop
R post
C post
11.5kΩ
2.2µF
34kΩ
470pF
0 0
1100
77.76
0 1
1110
155.52
1 0
1111
622.08
1 1
0110
5.11kΩ
167.3317
1 0
0001
669.3266
1 1
19.44
155.52
622.08
1 0
669.3266
1001
1 1
622.08
Nominal Performance Using These Values
PLL Loop
Bandwidth
Damping Passband
Factor Peaking (dB)
1kHz
6.0
0.05
4.7µF
6.0
0.06
113.0kΩ
0.22µF
6.0
0.06
28.0kΩ
1.0µF
6.3
0.05
121.0kΩ
0.22µF
6.0
0.05
30.1kΩ
1.0µF
6.5
0.05
Table 8: Example External Loop Filter Component Values
Note 1: KVCO , VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor, and
Passband Peaking. For PLL Simulator software, go to www.icst.com.
ABSOLUTE MAXIMUM RATINGS1
Symbol Parameter
Rating
Unit
VI
Inputs
-0.5 to VCC +0.5
V
VO
Outputs
-0.5 to VCC +0.5
V
VCC
Power Supply Voltage
TS
Storage Temperature
4.6
V
-45 to +100
oC
Table 9: Absolute Maximum Ratings
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions
or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
M2006-02A Datasheet Rev 1.0
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Integrated
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Systems, Inc.
VCSO BASED FEC CLOCK PLL
Product Data Sheet
RECOMMENDED CONDITIONS OF OPERATION
Symbol Parameter
VCC
Positive Supply Voltage
TA
Ambient Operating Temperature
Commercial
Industrial
Min
Typ
Max
Unit
3.135
3.3
3.465
V
o
+70
+85
0
-40
o
C
C
Table 10: Recommended Conditions of Operation
ELECTRICAL SPECIFICATIONS
DC Characteristics
Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT = 622-675MHz,
LVPECL outputs terminated with 50Ω to VCC - 2V
Symbol Parameter
Power Supply VCC
Positive Supply Voltage
ICC
Power Supply Current
All
Differential
Inputs
VP-P
Peak to Peak Input Voltage
VCMR
Common Mode Input
CIN
Input Capacitance
Differential
Inputs with
Pull-down
IIH
Input High Current (Pull-down)
Differential
Inputs with
Pull-up
IIH
Input High Current (Pull-up)
IIL
Input Low Current (Pull-up)
Rpullup
Internal Pull-up Resistance
All LVCMOS
/ LVTTL
Inputs
VIH
Input High Voltage
VIL
Input Low Voltage
CIN
Input Capacitance
LVCMOS /
LVTTL
Inputs with
Pull-down
LVCMOS /
LVTTL
Inputs with
Pull-up
Differential
Outputs
IIH
Input High Current (Pull-down)
IIL
Input Low Current (Pull-down)
IIL
Input Low Current (Pull-down)
Min
Typ
Max
Unit Conditions
3.135
3.3
3.465
V
175
225
0.15
V
0.5
Vcc - .85 V
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
DIF_REF0, DIF_REF1
IIL
Input Low Current (Pull-up)
Rpullup
Internal Pull-up Resistance
VOH
Output High Voltage
VOL
Output Low Voltage
VP-P
Peak to Peak Output Voltage 1
150
µA
µA
µA
Vcc + 0.3 V
2
0.8
V
4
pF
150
µA
-0.3
µA
-5
Integrated Circuit Systems, Inc.
µA
-150
Vcc - 1.4
Vcc - 1.0 V
Vcc - 2.0
Vcc - 1.7 V
0.4
Networking & Communications
VCC = 3.456V
VIN = 0 V
kΩ
50
0.85
V
Table 11: DC Characteristics
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●
µA
5
FOUT0, nFOUT0,
FOUT1, nFOUT1
VCC = VIN =
3.456V
kΩ
50
FEC_SEL3, FEC_SEL2,
FEC_SEL1, FEC_SEL0
VIN =
0 to 3.456V
kΩ
50
Note 1: Single-ended measurement. See Figure 5, Output Rise and Fall Time, on pg. 7.
M2006-02A Datasheet Rev 1.0
µA
-150
REF_SEL, FIN_SEL1, FIN_SEL0,
P1_SEL, P0_SEL
VCC = VIN =
3.456V
kΩ
5
Rpulldown Internal Pull-down Resistance
Input High Current (Pull-up)
pF
50
REF_SEL, FIN_SEL1, FIN_SEL0,
FEC_SEL3, FEC_SEL2,
FEC_SEL1, FEC_SEL0,
P1_SEL, P0_SEL
IIH
4
-5
Rpulldown Internal Pull-down Resistance
nDIF_REF0, nDIF_REF1
mA
Revised 28Jul2004
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Integrated
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VCSO BASED FEC CLOCK PLL
Product Data Sheet
ELECTRICAL SPECIFICATIONS (CONTINUED)
AC Characteristics
Unless stated otherwise, VCC = 3.3V +5%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT = 622-675MHz,
LVPECL outputs terminated with 50Ω to VCC - 2V
Symbol Parameter
Min
Max
Unit Test Conditions
Input
Frequency
Range
FIN
Output
Frequency
FFOUT
Output Frequency
Range
APR
VCSO Pull-Range
KVCO
VCO Gain
800
ppm
ppm
kHz/V
RIN
Internal Loop Resistor
50
kΩ
700
kHz
-73
-103
-126
PLL Loop
Constants 1
Input Frequency
Typ
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
10
700
MHz
FOUT0, nFOUT0,
FOUT1, nFOUT1
100
700
MHz
±120
±50
Commercial
Industrial
BWVCSO VCSO Bandwidth
Φn
Phase Noise
and Jitter
J(t)
tPW
Single Side Band
Phase Noise
@622.08MHz
1kHz Offset
P0, P1 = 1
40
50
60
dBc/Hz
Fin=19.44 MHz
dBc/Hz Mfin=32, Mfec=1, Rfec=1
dBc/Hz
ps rms
ps rms
%
P0, P1 = 4
45
50
55
%
200
450
500
ps
20% to 80%
200
450
500
ps
20% to 80%
10kHz Offset
100kHz Offset
12kHz to 20MHz
Jitter (rms)
@622.08MHz
50kHz to 80MHz
Output Duty Cycle
2
FOUT0, nFOUT0,
FOUT1, nFOUT1
tR
Output Rise Time 2
tF
Output Fall Time 2
±200
±150
FOUT0, nFOUT0,
FOUT1, nFOUT1
0.25
0.5
0.25
0.5
Table 12: AC Characteristics
Note 1: Parameters needed for PLL Simulator software; see Table 8, Example External Loop Filter Component Values, on pg. 5.
Note 2: See Parameter Measurement Information on pg. 7.
PARAMETER MEASUREMENT INFORMATION
Output Rise and Fall Time
Output Duty Cycle
nFOUT
80%
FOUT
80%
VP-P
Clock Output
tPW
(Output Pulse Width)
20%
tF
20%
tR
tPERIOD
odc =
tPW
tPERIOD
Figure 6: Output Duty Cycle
Figure 5: Output Rise and Fall Time
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M2006-02A
Product Data Sheet
VCSO BASED FEC CLOCK PLL
DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER
Mechanical Dimensions:
Refer to the SAW PLL application notes web page at
www.icst.com/products/appnotes/SawPllAppNotes.htm
for application notes, including recommended PCB
footprint, solder mask, and furnace profile.
Figure 7: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier
ORDERING INFORMATION
Standard VCSO Output Frequencies (MHz)*
Consult ICS for the availablity of other VCSO frequencies
Part Numbering Scheme
Part Number:
M2006- 02A - xxx.xxxx
Device Number
Temperature
“ - ” = 0 to +70 oC (commercial)
I = - 40 to +85 oC (industrial)
VCSO Frequency (MHz)
See Table 13, right. Consult ICS for other frequencies.
622.0800
669.3120
625.0000
669.3266
627.3296
669.6429
644.5313
670.8386
666.5143
672.1600
669.1281
690.5692
Table 13: Standard VCSO Output Frequencies (MHz)
Figure 8: Part Numbering Scheme
Note *: Fout can equal Fvcso divided by: 1 or 4
Consult ICS for the availability of other PLL frequencies.
Example Part Numbers
PLL Frequency (MHz)
622.08
625.00
669.3266
669.6429
Temperature
commercial
industrial
commercial
industrial
commercial
industrial
commercial
industrial
Order Part Number
M2006-02A - 622.0800
M2006-02AI622.0800
M2006-02A - 625.0000
M2006-02AI625.0000
M2006-02A - 669.3266
M2006-02AI669.3266
M2006-02A - 669.6429
M2006-02AI669.6429
Table 14: Example Part Numbers
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
M2006-02A Datasheet Rev 1.0
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