Intel L7200 Intel core2 duo mobile processor for intel centrino duo mobile processor technology Datasheet

Intel® Core™2 Duo Mobile Processor
for Intel® Centrino® Duo Mobile
Processor Technology
Datasheet
September 2007
Document Number: 314078-004
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2
Datasheet
Contents
1
Introduction .............................................................................................................. 7
1.1
Terminology ....................................................................................................... 9
1.2
References ....................................................................................................... 10
2
Low Power Features ................................................................................................ 11
2.1
Clock Control and Low Power States .................................................................... 11
2.1.1 Core Low Power State Descriptions ........................................................... 13
2.1.2 Package Low Power State Descriptions ...................................................... 15
2.2
Enhanced Intel SpeedStep® Technology .............................................................. 18
2.3
Extended Low Power States ................................................................................ 19
2.4
FSB Low Power Enhancements ............................................................................ 19
2.5
Processor Power Status Indicator (PSI#) Signal..................................................... 20
3
Electrical Specifications ........................................................................................... 21
3.1
Power and Ground Pins ...................................................................................... 21
3.2
FSB Clock (BCLK[1:0]) and Processor Clocking ...................................................... 21
3.3
Voltage Identification ......................................................................................... 21
3.4
Catastrophic Thermal Protection .......................................................................... 25
3.5
Reserved and Unused Pins.................................................................................. 25
3.6
FSB Frequency Select Signals (BSEL[2:0])............................................................ 26
3.7
FSB Signal Groups............................................................................................. 26
3.8
CMOS Signals ................................................................................................... 28
3.9
Maximum Ratings.............................................................................................. 28
3.10 Processor DC Specifications ................................................................................ 29
4
Package Mechanical Specifications and Pin Information .......................................... 39
4.1
Package Mechanical Specifications ....................................................................... 39
4.2
Processor Pinout and Pin List .............................................................................. 49
4.3
Alphabetical Signals Reference ............................................................................ 73
5
Thermal Specifications and Design Considerations .................................................. 81
5.1
Thermal Specifications ....................................................................................... 85
5.1.1 Thermal Diode ....................................................................................... 85
5.1.2 Thermal Diode Offset .............................................................................. 85
5.1.3 Intel® Thermal Monitor........................................................................... 87
5.1.4 Digital Thermal Sensor............................................................................ 89
5.1.5 Out of Specification Detection .................................................................. 90
5.1.6 PROCHOT# Signal Pin ............................................................................. 90
Datasheet
3
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Core Low Power States..............................................................................................12
Package Low Power States.........................................................................................13
Deeper Sleep VCC and ICC Loadline for Dual-core Standard Voltage Processors..................34
Deeper Sleep VCC and ICC Loadline for Dual-core Low Voltage and
Ultra Low Voltage Processor .......................................................................................35
Active VCC and ICC Loadline for Intel Core 2 Solo Processor, Ultra Low Voltage..................36
4-MB and 2-MB Fused Micro-FCPGA Processor Package Drawing .....................................40
4-MB and 2-MB Fused Micro-FCPGA Processor Package Drawing .....................................41
2-MB Micro-FCPGA Processor Package Drawing.............................................................42
2-MB Micro-FCPGA Processor Package Drawing.............................................................43
4-MB and 2-MB Fused Micro-FCBGA Processor Package Drawing .....................................44
4-MB and 2-MB Fused Micro-FCBGA Processor Package Drawing .....................................45
2-MB Micro-FCBGA Processor Package Drawing ............................................................46
1-MB Micro-FCBGA Processor Package Drawing (2 of 2) .................................................47
1-MB Micro-FCBGA Processor Package Drawing (2 of 2) .................................................48
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
4
Coordination of Core Low Power States at the Package Level ..........................................13
Voltage Identification Definition ..................................................................................22
BSEL[2:0] Encoding for BCLK Frequency......................................................................26
FSB Pin Groups ........................................................................................................27
Processor Absolute Maximum Ratings..........................................................................28
Voltage and Current Specifications for Dual-core Standard Voltage Processors ..................29
Voltage and Current Specifications for Dual-core Low Voltage Processors .........................31
Voltage and Current Specifications for Single and Dual-core Ultra Low Voltage Processors ..32
AGTL+ Signal Group DC Specifications ........................................................................37
CMOS Signal Group DC Specifications..........................................................................38
Open Drain Signal Group DC Specifications ..................................................................38
The Coordinates of the Processor Pins as Viewed from the Top of the Package
(Sheet 1 of 2) ..........................................................................................................50
The Coordinates of the Processor Pins as Viewed from the Top of the Package
(Sheet 2 of 2) ..........................................................................................................51
Pin Listing by Pin Name .............................................................................................53
Pin Listing by Pin Number ..........................................................................................64
Signal Description.....................................................................................................73
Power Specifications for the Dual-core Standard Voltage Processor..................................82
Power Specifications for the Dual-core Low Voltage Processor.........................................83
Power Specifications for the Single and Dual-core Ultra Low Voltage Processor..................84
Thermal Diode ntrim and Diode Correction Toffset ........................................................86
Thermal Diode Interface ............................................................................................86
Thermal Diode Parameters using Diode Mode ...............................................................86
Thermal Diode Parameters Using Transistor Model ........................................................87
Datasheet
Revision History
Revision
Number
-001
Description
Initial release
Revision Date
August 2006
-002
•
•
•
Added Information for L7400 and L7200 Low-Voltage Processors
Updated Table 08 in Chapter 3
Updated Table 17 in Chapter 5
December 2006
-003
•
Added L-2 die package information
May 2007
-004
•
•
•
•
Added Information for U2200 and U2100 Ultra Low-Voltage Processors
Updated Electrical Specifications in Chapter 3 for ULV Processors
Updated Thermal Specifications in Chapter 5 for ULV Processors
Added A-1 die package information
September 2007
§§
Datasheet
5
6
Datasheet
Introduction
1
Introduction
The Intel® Core™2 Duo mobile processor for Intel® Centrino® Duo mobile technology
based on the Intel® 945 Express Chipset family is built on 65-nanometer process
technology and is the next generation high-performance, low-power mobile processor
based on the Intel® Core™ architecture.
Note:
All references to the word “processor” in this document are references to the Intel Core
2 Duo mobile processor with 533- and 667-MHz front side bus (FSB), unless specified
otherwise.
The following list provides some of the key features on this processor:
• Dual-core processor for mobile with enhanced performance
• Intel® 64 architecture
• Supports Intel Architecture with Dynamic Execution
• On-die, primary 32-kB instruction cache and 32-kB write-back data cache per core
• On-die, up to 4-MB second level shared cache with Advanced Transfer Cache
Architecture
• Data Prefetch Logic
• Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3) and
Supplemental Streaming SIMD Extensions 3 (SSSE3)
• 667-MHz, Source-Synchronous FSB for Standard Voltage processors
• Advanced Power Management features including Enhanced Intel SpeedStep®
Technology
• Intel® Enhanced Deeper Sleep state and Dynamic Cache Sizing
• Digital Thermal Sensor
• Micro-FCPGA and Micro-FCBGA packaging technologies
• Intel® Virtualization Technology
• Execute Disable Bit support for enhanced security
Note:
64-bit computing on Intel architecture requires a computer system with a processor,
chipset, BIOS, operating system, device drivers and applications enabled for Intel 64
architecture. Processors will not operate (including 32-bit operation) without an Intel
64 architecture-enabled BIOS. Performance will vary depending on your hardware and
software configurations. Consult with your system vendor for more information.
The Intel Core 2 Duo mobile processor will be manufactured on Intel’s 65-nanometer
process technology. The processor maintains support for MMXTM technology, Streaming
SIMD instructions, and full compatibility with IA-32 software. In addition, the Intel Core
2 Duo mobile processor supports Intel 64 architecture which is enabled by 64-bit
operating systems and consists of 64-bit instructions and registers. Further details on
Intel Extended Memory 64 Technology and its programming model can be found in the
Intel Extended Memory 64 Technology Software Developer’s Guide. The Intel Core 2
Duo mobile processor features on-die, 32-kB level 1 instruction and data caches and
features up to a 4-MB level 2 cache with Advanced Transfer Cache Architecture. The
processor’s Data Prefetch Logic speculatively fetches data to the L2 cache before the L1
cache requests occurs, resulting in reduced bus cycle penalties. The processor includes
the Data Cache Unit Streamer which enhances the performance of the L2 prefetcher by
requesting L1 warm-ups earlier. In addition, the Write Order Buffer depth is enhanced
to help with the write-back latency performance.
Datasheet
7
Introduction
In addition to supporting the existing Streaming SIMD Extensions 2 (SSE2) and
Streaming SIMD Extensions 3 (SSE3), the processor supports Supplemental Streaming
SIMD Extensions 3 (SSSE3) to speed up media algorithms like encoding and decoding.
Advanced Dynamic Execution improves speculative execution and branch prediction
internal to the processor. The floating point and multi-media units include 128-bit wide
registers and a separate register for data movement. Streaming SIMD3 (SSE3)
instructions provide highly efficient double-precision floating point, SIMD integer, and
memory management operations. Also, these instructions enhance the performance of
optimized applications for the digital home such as video, image processing and media
compression technology.
The processor features Enhanced Intel SpeedStep Technology, which enables real-time
dynamic switching between multiple voltage and frequency points. The processor
features the Auto Halt, Stop Grant, Deep Sleep, and Intel Enhanced Deeper Sleep Cstates. Enhanced thermal management capabilities are implemented including Intel®
Thermal Monitor 1 and Intel Thermal Monitor 2 to provide efficient and effective cooling
in high temperatures.
The Intel Core 2 Duo mobile processor utilizes socketable Micro Flip-Chip Pin Grid Array
(Micro-FCPGA) and surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA)
package technology. The Micro-FCPGA package plugs into a 479-hole, surface-mount,
Zero Insertion Force (ZIF) socket, which is referred to as the mPGA479M socket.
Intel Core 2 Duo mobile processor supports the Execute Disable Bit capability. This
feature combined with a supporting operating system allows memory to be marked as
executable or non executable. If code attempts to run in non-executable memory the
processor raises an error to the operating system. This feature can prevent some
classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help
improve the overall security of the system. See the Intel® 64 and IA-32 Intel®
Architectures Software Developer's Manual for more detailed information.
Intel Virtualization Technology is a set of hardware enhancements to Intel server and
client systems that combined with the appropriate software, will enable enhanced
virtualization robustness and performance for both enterprise and consumer uses. Intel
Virtualization Technology forms the foundation of Intel technologies focused on
improved virtualization, safer computing, and system stability. For client systems, Intel
Virtualization Technology’s hardware-based isolation helps provide the foundation for
highly available and more secure client virtualization partitions.
8
Datasheet
Introduction
1.1
Terminology
Term
Datasheet
Definition
#
A “#” symbol after a signal name refers to an active low signal, indicating a
signal is in the active state when driven to a low level. For example, when
RESET# is low, a reset has been requested. Conversely, when NMI is high,
a nonmaskable interrupt has occurred. In the case of signals where the
name does not imply an active state but describes part of a binary
sequence (such as address or data), the “#” symbol implies that the signal
is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and XXXX
means that the specification or value is yet to be determined.
AGTL+
Advanced Gunning Transceiver Logic. Used to refer to Assisted GTL+
signaling technology on some Intel processors.
Front Side Bus
(FSB)
Refers to the interface between the processor and system core logic (also
known as the chipset components).
Intel®
Virtualization
Technology
Processor virtualization which when used in conjunction with Virtual
Machine Monitor software enables multiple, robust independent software
environments inside a single platform.
Processor Core
Processor core die with integrated L1 and L2 cache. All AC timing and
signal integrity specifications are at the pads of the processor core.
Storage
Conditions
Refers to a non-operational state. The processor may be installed in a
platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor lands should not be
connected to any supply voltages, have any I/Os biased or receive any
clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device
removed from packaging material) the processor must be handled in
accordance with moisture sensitivity labeling (MSL) as indicated on the
packaging material.
VCC
The processor core power supply
VSS
The processor ground reference
9
Introduction
1.2
References
Material and concepts available in the following documents may be beneficial when
reading this document. Also note that with Intel Centrino Duo technology, the Intel
Core 2 Duo mobile processor supports Mobile Intel® 945GM/GT/GMS/PM and 940GML
Express Chipset family and Intel® 82801GBM (also known as ICH7M).
Document
Number
Document
Intel® Core™2 Duo Processor for Intel® Centrino® Duo Technology
Specification Update
314079
Mobile Intel® 945 Express Chipset Family Chipset Datasheet
309219
Mobile Intel® 945 Express Chipset Family Chipset Specification Update
309220
Intel® I/O Controller Hub 7 (ICH7) Family Datasheet
307013
Intel® I/O Controller Hub 7 (ICH7) Family Specification Update
307014
Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual
Volume 1: Basic Architecture
253665
Volume 2A: Instruction Set Reference, A-M
253666
Volume 2B: Instruction Set Reference, N-Z
253667
Volume 3A: System Programming Guide
253668
Volume 3B: System Programming Guide
253669
Intel® 64 and IA-32 Architectures Software Developer's Manual
Documentation Changes
252046
AP-485 Intel® Processor Identification and the CPUID Instruction
241618
§§
10
Datasheet
Low Power Features
2
Low Power Features
2.1
Clock Control and Low Power States
The Intel Core 2 Duo mobile processor supports low power states both at the individual
core level and the package level for optimal power management. A core may
independently enter the C1/AutoHALT, C1/MWAIT, C2, C3, and C4 low power states.
Refer to Figure 1 for a visual representation of the core low power states for the
processor. When both cores coincide in a common core low power state, the central
power management logic ensures the entire Intel Core 2 Duo mobile processor enters
the respective package low power state by initiating a P_LVLx (P_LVL2, P_LVL3, and
P_LVL4) I/O read to the Intel 945GM/GT/GMS/PM and 940GML Express Chipset family.
Package low power states include Normal, Stop Grant, Stop Grant Snoop, Sleep, Deep
Sleep, and Deeper Sleep. Refer to Figure 2 for a visual representation of the package
low power states for the Intel Core 2 Duo mobile processor and to Table 1 for a
mapping of core low power states to package low power states.
The Intel Core 2 Duo mobile processor implements two software interfaces for
requesting low power states: MWAIT instruction extensions with sub-state hints and
P_LVLx reads to the ACPI P_BLK register block mapped in the processor’s I/O address
space. The P_LVLx I/O reads are converted to equivalent MWAIT C-state requests
inside the processor and do not directly result in I/O reads on the processor FSB. The
monitor address does not need to be setup before using the P_LVLx I/O read interface.
The sub-state hints used for each P_LVLx read can be configured through a software
programmable Model Specific Register (MSR).
If a core encounters a chipset break event while STPCLK# is asserted, then it asserts
the PBE# output signal. Assertion of PBE# when STPCLK# is asserted indicates to
system logic that individual cores should return to the C0 state and the Intel Core 2
Duo mobile processor should return to the Normal state.
Datasheet
11
Low Power Features
Figure 1.
Core Low Power States
Stop
Grant
STPCLK#
asserted
STPCLK#
de-asserted
C1/
MWAIT
STPCLK#
de-asserted
STPCLK#
de-asserted
STPCLK#
asserted
Core state
break
STPCLK#
asserted
C1/Auto
Halt
HLT instruction
MWAIT(C1)
Halt break
C0
Core State
break
P_LVL2 or
MWAIT(C2)
P_LVL4 or
MWAIT(C4)
C4
†‡
Core state
break
Core
P_LVL3 or
state
MWAIT(C3)
break
C2
†
†
C3
halt break = A20M# transition, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt
core state break = (halt break OR Monitor event) AND STPCLK# high (not asserted)
† — STPCLK# assertion and de-assertion have no effect if a core is in C2, C3, or C4.
‡ — Core C4 state includes the Intel Enhanced Deeper Sleep state.
12
Datasheet
Low Power Features
Figure 2.
Package Low Power States
SLP# asserted
STPCLK# asserted
Stop
Grant
Normal
STPCLK# de-asserted
DPSLP# asserted
Sleep
SLP# de-asserted
Snoop
serviced
DPRSTP# asserted
Deeper
†
Sleep
Deep
Sleep
DPSLP# de-asserted
DPRSTP# de-asserted
Snoop
occurs
Stop
Grant
Snoop
† — Deeper Sleep includes the Deeper Sleep state and Intel Enhanced Deeper Sleep state.
Table 1.
Coordination of Core Low Power States at the Package Level
Package State
Core1 State
Core0 State
C0
C1/Auto
HALT/
MWAIT
C2
C3
C4
C0
Normal
Normal
Normal
Normal
Normal
C1/AutoHALT/
MWAIT
Normal
Normal
Normal
Normal
Normal
C2
Normal
Normal
Stop-Grant
Stop-Grant
Stop-Grant
C3
Normal
Normal
Stop-Grant
Deep Sleep
Deep Sleep
Deeper Sleep/
C4
Normal
Normal
Stop-Grant
2.1.1
Core Low Power State Descriptions
2.1.1.1
Core C0 State
Deep Sleep
Intel®
Enhanced
Deeper Sleep
This is the normal operating state for cores in the processor.
2.1.1.2
Core C1/AutoHALT Powerdown State
C1/AutoHALT is a low power state entered when a core executes the HALT instruction.
The processor core will transition to the C0 state upon occurrence of SMI#, INIT#,
LINT[1:0] (NMI, INTR), or FSB interrupt messages. RESET# will cause the processor to
immediately initialize itself.
A System Management Interrupt (SMI) handler will return execution to either Normal
state or the AutoHALT Powerdown state. See the Intel® 64 and IA-32 Intel®
Architectures Software Developer's Manual, Volume 3A/3B: System Programmer's
Guide for more information.
The system can generate a STPCLK# while the processor is in the AutoHALT
Powerdown state. When the system deasserts the STPCLK# interrupt, the processor
will return execution to the HALT state.
Datasheet
13
Low Power Features
While in AutoHALT Powerdown state, the Intel Core 2 Duo mobile processor will process
bus snoops and snoops from the other core. The processor core will enter a snoopable
sub-state (not shown in Figure 1) to process the snoop and then return to the
AutoHALT Powerdown state.
2.1.1.3
Core C1/MWAIT Powerdown State
C1/MWAIT is a low power state entered when the processor core executes the
MWAIT(C1) instruction. Processor behavior in the MWAIT state is identical to the
AutoHALT state except that Monitor events can cause the processor core to return to
the C0 state. See the Intel® 64 and IA-32 Intel® Architectures Software Developer's
Manual, Volume 2A/2B: Instruction Set Reference for more information.
2.1.1.4
Core C2 State
Individual cores of the Intel Core 2 Duo mobile processor can enter the C2 state by
initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C2) instruction, but the
processor will not issue a Stop-Grant Acknowledge special bus cycle unless the
STPCLK# pin is also asserted.
While in the C2 state, the Intel Core 2 Duo mobile processor will process bus snoops
and snoops from the other core. The processor core will enter a snoopable sub-state
(not shown in Figure 1) to process the snoop and then return to the C2 state.
2.1.1.5
Core C3 State
Individual cores of the Intel Core 2 Duo mobile processor can enter the C3 state by
initiating a P_LVL3 I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering
C3, the processor core flushes the contents of its L1 caches into the processor’s L2
cache. Except for the caches, the processor core maintains all its architectural state in
the C3 state. The Monitor remains armed if it is configured. All of the clocks in the
processor core are stopped in the C3 state.
Because the core’s caches are flushed the processor keeps the core in the C3 state
when the processor detects a snoop on the FSB or when the other core of the Intel
Core 2 Duo mobile processor accesses cacheable memory. The processor core will
transition to the C0 state upon occurrence of a Monitor event, SMI#, INIT#, LINT[1:0]
(NMI, INTR), or FSB interrupt message. RESET# will cause the processor core to
immediately initialize itself.
2.1.1.6
Core C4 State
Individual cores of the Intel Core 2 Duo mobile processor can enter the C4 state by
initiating a P_LVL4 I/O read to the P_BLK or an MWAIT(C4) instruction. The processor
core behavior in the C4 state is nearly identical to the behavior in the C3 state. The
only difference is that if both processor cores are in C4, then the central power
management logic will request that the entire Intel Core 2 Duo mobile processor enter
the Deeper Sleep package low power state (see Section 2.1.2.6).
To enable the package level Intel® Enhanced Deeper Sleep state, Dynamic Cache
Sizing and Intel Enhanced Deeper Sleep state fields must be configured in the software
programmable MSR to enable the Intel Enhanced Deeper Sleep state.
14
Datasheet
Low Power Features
2.1.2
Package Low Power State Descriptions
2.1.2.1
Normal State
This is the normal operating state for the processor. The Intel Core 2 Duo mobile
processor remains in the Normal state when at least one of its cores is in the C0, C1/
AutoHALT, or C1/MWAIT state.
2.1.2.2
Stop-Grant State
When the STPCLK# pin is asserted, each core of the Intel Core 2 Duo mobile processor
enters the Stop-Grant state within 20 bus clocks after the response phase of the
processor-issued Stop-Grant Acknowledge special bus cycle. Processor cores that are
already in the C2, C3, or C4 state remain in their current low power state. When the
STPCLK# pin is deasserted, each core returns to its previous core low power state.
Note:
Since the AGTL+ signal pins receive power from the FSB, these pins should not be
driven (allowing the level to return to VCCP) for minimum power drawn by the
termination resistors in this state. In addition, all other input pins on the FSB should be
driven to the inactive state.
RESET# will cause the processor to immediately initialize itself, but the processor will
stay in Stop-Grant state. When RESET# is asserted by the system, the STPCLK#,
SLP#, DPSLP#, and DPRSTP# pins must be deasserted more than 480 µs prior to
RESET# deassertion (AC Specification T45). When re-entering the Stop-Grant state
from the Sleep state, STPCLK# should be deasserted ten or more bus clocks after the
deassertion of SLP# (AC Specification T75).
While in Stop-Grant state, the processor will service snoops and latch interrupts
delivered on the FSB. The processor will latch SMI#, INIT# and LINT[1:0] interrupts
and will service only one of each upon return to the Normal state.
The PBE# signal may be driven when the processor is in Stop-Grant state. PBE# will be
asserted if there is any pending interrupt or monitor event latched within the processor.
Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause
assertion of PBE#. Assertion of PBE# indicates to system logic that the entire processor
should return to the Normal state.
A transition to the Stop-Grant Snoop state will occur when the processor detects a
snoop on the FSB (see Section 2.1.2.3). A transition to the Sleep state (see
Section 2.1.2.4) will occur with the assertion of the SLP# signal.
2.1.2.3
Stop-Grant Snoop State
The processor will respond to snoop or interrupt transactions on the FSB while in StopGrant state by entering the Stop-Grant Snoop state. The processor will stay in this
state until the snoop on the FSB has been serviced (whether by the processor or
another agent on the FSB) or the interrupt has been latched. The processor will return
to the Stop-Grant state once the snoop has been serviced or the interrupt has been
latched.
2.1.2.4
Sleep State
The Sleep state is a low power state in which the processor maintains its context,
maintains the phase-locked loop (PLL), and stops all internal clocks. The Sleep state is
entered through assertion of the SLP# signal while in the Stop-Grant state. The SLP#
pin should only be asserted when the processor is in the Stop-Grant state. SLP#
assertions while the processor is not in the Stop-Grant state is out of specification and
may result in unapproved operation.
Datasheet
15
Low Power Features
Note:
In the Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals (with the exception of
SLP#, DPSLP# or RESET#) are allowed on the FSB while the processor is in Sleep
state. Snoop events that occur while in Sleep state or during a transition into or out of
Sleep state will cause unpredictable behavior. Any transition on an input signal before
the processor has returned to the Stop-Grant state will result in unpredictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as
specified in the RESET# pin specification, then the processor will reset itself, ignoring
the transition through Stop-Grant state. If RESET# is driven active while the processor
is in the Sleep state, the SLP# and STPCLK# signals should be deasserted immediately
after RESET# is asserted to ensure the processor correctly executes the Reset
sequence.
While in the Sleep state, the processor is capable of entering an even lower power
state, the Deep Sleep state, by asserting the DPSLP# pin (See Section 2.1.2.5.). While
the processor is in the Sleep state, the SLP# pin must be deasserted if another
asynchronous FSB event needs to occur.
2.1.2.5
Deep Sleep State
The Deep Sleep state is entered through assertion of the DPSLP# pin while in the Sleep
state. BCLK may be stopped during the Deep Sleep state for additional platform level
power savings. BCLK stop/restart timings on Intel 945GM/GT/GMS/PM and 940GML
Express Chipset family based platforms with the CK410M clock chip are as follows:
• Deep Sleep entry: the system clock chip may stop/tristate BCLK within 2 BCLKs of
DPSLP# assertion. It is permissible to leave BCLK running during Deep Sleep.
• Deep Sleep exit: the system clock chip must drive BCLK to differential DC levels
within 2-3 ns of DPSLP# deassertion and start toggling BCLK within 10 BCLK
periods.
To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be restarted after DPSLP# deassertion as described above. A period of 15 microseconds (to
allow for PLL stabilization) must occur before the processor can be considered to be in
the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter
the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding tosnoop
transactions or latching interrupt signals. No transitions of signals are allowed on the
FSB while the processor is in Deep Sleep state. When the processor is in Deep Sleep
state, it will not respond to interrupts or snoop transactions. Any transition on an input
signal before the processor has returned to Stop-Grant state will result in unpredictable
behavior.
2.1.2.6
Deeper Sleep State
The Deeper Sleep state is similar to the Deep Sleep state but reduces core voltage to
one of two lower levels. One lower core voltage level is achieved by entering the base
Deeper Sleep state. The Deeper Sleep state is entered through assertion of the
DPRSTP# pin while in the Deep Sleep state. The other lower core voltage level, the
lowest possible in the processor, is achieved by entering the Intel Enhanced Deeper
Sleep state of Deeper Sleep state. The Intel Enhanced Deeper Sleep state is entered
through assertion of the DPRSTP# pin while in the Deep Sleep only when the L2 cache
has been completely shut down. Refer to Section 2.1.2.6.1 and Section 2.1.2.6.2 for
further details on reducing the L2 cache and entering Intel Enhanced Deeper Sleep
state.
In response to entering Deeper Sleep, the Intel Core 2 Duo mobile processor will drive
the VID code corresponding to the Deeper Sleep core voltage on the VID[6:0] pins.
16
Datasheet
Low Power Features
Exit from the Deeper Sleep state or Intel Enhanced Deeper Sleep state is initiated by
DPRSTP# deassertion when either core requests a core state other than C4 or either
core requests a processor performance state other than the lowest operating point.
2.1.2.6.1
Intel Enhanced Deeper Sleep State
Intel Enhanced Deeper Sleep state is a sub-state of Deeper Sleep that extends power
saving capabilities by allowing the processor to further reduce core voltage once the L2
cache has been reduced to zero ways and completely shut down. The following events
occur when the processor enters Intel Enhanced Deeper Sleep state:
• The last core entering C4 issues a P_LVL4 I/O Read or an MWAIT(C4).
• The processor triggers a special chipset sequence to notify the chipset to redirect
all FSB traffic, except APIC messages, to memory. The snoops are replied as misses
by the chipset and are directed to main memory instead of the L2 cache.
• The processor will drive the VID code corresponding to the Intel Enhanced Deeper
Sleep state core voltage on the VID[6:0] pins.
2.1.2.6.2
Dynamic Cache Sizing
Dynamic Cache Sizing allows the processor to flush and disable a programmable
number of L2 cache ways upon each Deeper Sleep entry under the following
conditions:
• The second core is already in C4 and core sub-state Intel Enhanced Deeper Sleep
state is enabled (as specified in Section 2.1.2.6.1).
• The C0 timer, which tracks continuous residency in the Normal package state, has
not expired. This timer is cleared during the first entry into Deeper Sleep to allow
consecutive Deeper Sleep entries to shrink the L2 cache as needed.
• The FSB speed to processor core speed ratio is below the predefined L2 shrink
threshold.
If the FSB speed to processor core speed ratio is above the predefined L2 shrink
threshold, then L2 cache expansion will be requested. If the ratio is zero, then the ratio
will not be taken into account for Dynamic Cache Sizing decisions.
Upon STPCLK# deassertion, the first core exiting the Intel Enhanced Deeper Sleep
state will expand the L2 cache to 2 ways and invalidate previously disabled cache ways.
If the L2 cache reduction conditions stated above still exist when the last core returns
to C4 and the package enters Intel Enhanced Deeper Sleep state, then the L2 will be
shrunk to zero again. If a core requests a processor performance state resulting in a
higher ratio than the predefined L2 shrink threshold, the C0 timer expires, or the
second core (not the one currently entering the interrupt routine) requests the C1, C2,
or C3 states, then the whole L2 will be expanded when the next INTR event would
occur.
L2 cache shrink prevention may be enabled as needed on occasion through an
MWAIT(C4) sub-state field. If shrink prevention is enabled, then the Intel Core 2 Duo
mobile processor does not enter the Intel Enhanced Deeper Sleep state since the L2
cache remains valid and in full size.
Datasheet
17
Low Power Features
2.2
Enhanced Intel SpeedStep® Technology
The Intel Core 2 Duo mobile processor features Enhanced Intel SpeedStep Technology.
Following are the key features of Enhanced Intel SpeedStep Technology:
• Multiple voltage and frequency operating points provide optimal performance at the
lowest power.
• Voltage and frequency selection is software controlled by writing to processor
MSRs:
— . If the target frequency is higher than the current frequency, Vcc is ramped up
in steps by placing new values on the VID pins and the PLL then locks to the
new frequency.
— If the target frequency is lower than the current frequency, the PLL locks to the
new frequency and the VCC is changed through the VID pin mechanism.
— Software transitions are accepted at any time. If a previous transition is in
progress, the new transition is deferred until the previous transition completes.
• The processor controls voltage ramp rates internally to ensure glitch free
transitions.
• Low transition latency and large number of transitions possible per second:
— Processor core (including L2 cache) is unavailable for up to 10 μs during the
frequency transition.
— The bus protocol (BNR# mechanism) is used to block snooping.
• Improved Intel Thermal Monitor mode:
— When the on-die thermal sensor indicates that the die temperature is too high,
the processor can automatically perform a transition to a lower frequency and
voltage specified in a software programmable MSR.
— The processor waits for a fixed time period. If the die temperature is down to
acceptable levels, an up transition to the previous frequency and voltage point
occurs.
— An interrupt is generated for the up and down Intel Thermal Monitor transitions
enabling better system level thermal management.
• Enhanced thermal management features.
— Digital Thermal Sensor and Out of Specification detection.
— Intel Thermal Monitor 1 in addition to Intel Thermal Monitor 2 in case of
unsuccessful Intel Thermal Monitor 2 transition.
— Dual-core thermal management synchronization.
Each core in the processor implements an independent MSR for controlling Enhanced
Intel SpeedStep Technology, but both cores must operate at the same frequency and
voltage. The processor has performance state coordination logic to resolve frequency
and voltage requests from the two cores into a single frequency and voltage request for
the package as a whole. If both cores request the same frequency and voltage, then
the processor will transition to the requested common frequency and voltage. If the
two cores have different frequency and voltage requests, then the processor will take
the highest of the two frequencies and voltages as the resolved request and transition
to that frequency and voltage.
18
Datasheet
Low Power Features
2.3
Extended Low Power States
Extended low power states (C1E, C2E, C3E, C4E) optimize for power by forcibly
reducing the performance state of the processor when it enters a package low power
state. Instead of directly transitioning into the package low power state, the extended
low power state first reduces the performance state of the processor by performing an
Enhanced Intel SpeedStep Technology transition down to the lowest operating point.
Upon receiving a break event from the package low power state, control will be
returned to software while an Enhanced Intel SpeedStep Technology transition up to
the initial operating point occurs. The advantage of this feature is that it significantly
reduces leakage while in the package low power states.
Note:
Long-term reliability may not be assured if Extended Low Power States are not
enabled.
The processor implements two software interfaces for requesting extended package
low power states: MWAIT instruction extensions with sub-state hints and via BIOS by
configuring a software programmable MSR to automatically promote package low
power states to extended package low power states.
Note:
Extended Stop-Grant and Extended Deeper Sleep must be enabled via the BIOS for the
processor to remain within specification.
Enhanced Intel SpeedStep Technology transitions are multistep processes that require
clocked control. These transitions cannot occur when the processor is in the Sleep or
Deep Sleep package low power states since processor clocks are not active in these
states. Extended Deeper Sleep is an exception to this rule when the Hard C4E
configuration is enabled through a software programmable MSR. This Extended Deeper
Sleep state configuration will lower the core voltage to the Deeper Sleep level while in
Deeper Sleep and, upon exit, will automatically transition to the lowest operating
voltage and frequency to reduce snoop service latency. The transition to the lowest
operating point or back to the original software requested point may not be
instantaneous. Furthermore, upon very frequent transitions between active and idle
states, the transitions may lag behind the idle state entry resulting in the processor
either executing for a longer time at the lowest operating point or running idle at a high
operating point. Observations and analyses show this behavior should not significantly
impact total power savings or performance score while providing power benefits in
most other cases.
2.4
FSB Low Power Enhancements
The processor incorporates FSB low power enhancements:
• Dynamic FSB Power Down
• BPRI# control for address and control input buffers
• Dynamic Bus Parking
• Dynamic On-die Termination disabling
• Low VCCP (I/O termination voltage)
Datasheet
19
Low Power Features
The processor incorporates the DPWR# signal that controls the data bus input buffers
on the processor. The DPWR# signal disables the buffers when not used and activates
them only when data bus activity occurs, resulting in significant power savings with no
performance impact. BPRI# control also allows the processor address and control input
buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows
a reciprocal power reduction in chipset address and control input buffers when the
processor deasserts its BR0# pin. The On-die Termination on the processor FSB buffers
is disabled when the signals are driven low, resulting in additional power savings. The
low I/O termination voltage is on a dedicated voltage plane independent of the core
voltage, enabling low I/O switching power at all times.
2.5
Processor Power Status Indicator (PSI#) Signal
The processor incorporates the PSI# signal that is asserted when the processor is in a
reduced power consumption state. PSI# can be used to improve intermediate and light
load efficiency of the voltage regulator, resulting in platform power savings and
extended battery life. The algorithm that the processor uses for determining when to
assert PSI# is different from the algorithm used in previous Intel® Pentium® M
processors. For Intel Core 2 processor with Intel Centrino Duo mobile technology, PSI#
signal functionality is supported only in idle state.
§§
20
Datasheet
Electrical Specifications
3
Electrical Specifications
3.1
Power and Ground Pins
For clean, on-chip power distribution, the processor will have a large number of VCC
(power) and VSS (ground) inputs. All power pins must be connected to VCC power planes
while all VSS pins must be connected to system ground planes. Use of multiple power
and ground planes is recommended to reduce I*R drop. Please contact your Intel
representative for more details. The processor VCC pins must be supplied the voltage
determined by the VID (Voltage ID) pins.
3.2
FSB Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the core frequency is a multiple of the
BCLK[1:0] frequency. The processor uses a differential clocking implementation.
3.3
Voltage Identification
The processor uses seven voltage identification pins, VID[6:0], to support automatic
selection of power supply voltages. The VID pins for processor are CMOS outputs
driven by the processor VID circuitry. Table 2 specifies the voltage level corresponding
to the state of VID[6:0]. A 1 in this refers to a high-voltage level and a 0 refers to lowvoltage level.
Datasheet
21
Electrical Specifications
Table 2.
22
Voltage Identification Definition (Sheet 1 of 4)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Vcc (V)
0
0
0
0
0
0
0
1.5000
0
0
0
0
0
0
1
1.4875
0
0
0
0
0
1
0
1.4750
0
0
0
0
0
1
1
1.4625
0
0
0
0
1
0
0
1.4500
0
0
0
0
1
0
1
1.4375
0
0
0
0
1
1
0
1.4250
0
0
0
0
1
1
1
1.4125
0
0
0
1
0
0
0
1.4000
0
0
0
1
0
0
1
1.3875
0
0
0
1
0
1
0
1.3750
0
0
0
1
0
1
1
1.3625
0
0
0
1
1
0
0
1.3500
0
0
0
1
1
0
1
1.3375
0
0
0
1
1
1
0
1.3250
0
0
0
1
1
1
1
1.3125
0
0
1
0
0
0
0
1.3000
0
0
1
0
0
0
1
1.2875
0
0
1
0
0
1
0
1.2750
0
0
1
0
0
1
1
1.2625
0
0
1
0
1
0
0
1.2500
0
0
1
0
1
0
1
1.2375
0
0
1
0
1
1
0
1.2250
0
0
1
0
1
1
1
1.2125
0
0
1
1
0
0
0
1.2000
0
0
1
1
0
0
1
1.1875
0
0
1
1
0
1
0
1.1750
0
0
1
1
0
1
1
1.1625
0
0
1
1
1
0
0
1.1500
0
0
1
1
1
0
1
1.1375
0
0
1
1
1
1
0
1.1250
0
0
1
1
1
1
1
1.1125
0
1
0
0
0
0
0
1.1000
0
1
0
0
0
0
1
1.0875
0
1
0
0
0
1
0
1.0750
0
1
0
0
0
1
1
1.0625
0
1
0
0
1
0
0
1.0500
Datasheet
Electrical Specifications
Table 2.
Datasheet
Voltage Identification Definition (Sheet 2 of 4)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Vcc (V)
0
1
0
0
1
0
1
1.0375
0
1
0
0
1
1
0
1.0250
0
1
0
0
1
1
1
1.0125
0
1
0
1
0
0
0
1.0000
0
1
0
1
0
0
1
0.9875
0
1
0
1
0
1
0
0.9750
0
1
0
1
0
1
1
0.9625
0
1
0
1
1
0
0
0.9500
0
1
0
1
1
0
1
0.9375
0
1
0
1
1
1
0
0.9250
0
1
0
1
1
1
1
0.9125
0
1
1
0
0
0
0
0.9000
0
1
1
0
0
0
1
0.8875
0
1
1
0
0
1
0
0.8750
0
1
1
0
0
1
1
0.8625
0
1
1
0
1
0
0
0.8500
0
1
1
0
1
0
1
0.8375
0
1
1
0
1
1
0
0.8250
0
1
1
0
1
1
1
0.8125
0
1
1
1
0
0
0
0.8000
0
1
1
1
0
0
1
0.7875
0
1
1
1
0
1
0
0.7750
0
1
1
1
0
1
1
0.7625
0
1
1
1
1
0
0
0.7500
0
1
1
1
1
0
1
0.7375
0
1
1
1
1
1
0
0.7250
0
1
1
1
1
1
1
0.7125
1
0
0
0
0
0
0
0.7000
1
0
0
0
0
0
1
0.6875
1
0
0
0
0
1
0
0.6750
1
0
0
0
0
1
1
0.6625
1
0
0
0
1
0
0
0.6500
1
0
0
0
1
0
1
0.6375
1
0
0
0
1
1
0
0.6250
1
0
0
0
1
1
1
0.6125
1
0
0
1
0
0
0
0.6000
1
0
0
1
0
0
1
0.5875
1
0
0
1
0
1
0
0.5750
23
Electrical Specifications
Table 2.
24
Voltage Identification Definition (Sheet 3 of 4)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Vcc (V)
1
0
0
1
0
1
1
0.5625
1
0
0
1
1
0
0
0.5500
1
0
0
1
1
0
1
0.5375
1
0
0
1
1
1
0
0.5250
1
0
0
1
1
1
1
0.5125
1
0
1
0
0
0
0
0.5000
1
0
1
0
0
0
1
0.4875
1
0
1
0
0
1
0
0.4750
1
0
1
0
0
1
1
0.4625
1
0
1
0
1
0
0
0.4500
1
0
1
0
1
0
1
0.4375
1
0
1
0
1
1
0
0.4250
1
0
1
0
1
1
1
0.4125
1
0
1
1
0
0
0
0.4000
1
0
1
1
0
0
1
0.3875
1
0
1
1
0
1
0
0.3750
1
0
1
1
0
1
1
0.3625
1
0
1
1
1
0
0
0.3500
1
0
1
1
1
0
1
0.3375
1
0
1
1
1
1
0
0.3250
1
0
1
1
1
1
1
0.3125
1
1
0
0
0
0
0
0.3000
1
1
0
0
0
0
1
0.2875
1
1
0
0
0
1
0
0.2750
1
1
0
0
0
1
1
0.2625
1
1
0
0
1
0
0
0.2500
1
1
0
0
1
0
1
0.2375
1
1
0
0
1
1
0
0.2250
1
1
0
0
1
1
1
0.2125
1
1
0
1
0
0
0
0.2000
1
1
0
1
0
0
1
0.1875
1
1
0
1
0
1
0
0.1750
1
1
0
1
0
1
1
0.1625
1
1
0
1
1
0
0
0.1500
1
1
0
1
1
0
1
0.1375
1
1
0
1
1
1
0
0.1250
1
1
0
1
1
1
1
0.1125
1
1
1
0
0
0
0
0.1000
Datasheet
Electrical Specifications
Table 2.
3.4
Voltage Identification Definition (Sheet 4 of 4)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Vcc (V)
1
1
1
0
0
0
1
0.0875
1
1
1
0
0
1
0
0.0750
1
1
1
0
0
1
1
0.0625
1
1
1
0
1
0
0
0.0500
1
1
1
0
1
0
1
0.0375
1
1
1
0
1
1
0
0.0250
1
1
1
0
1
1
1
0.0125
1
1
1
1
0
0
0
0.0000
1
1
1
1
0
0
1
0.0000
1
1
1
1
0
1
0
0.0000
1
1
1
1
0
1
1
0.0000
1
1
1
1
1
0
0
0.0000
1
1
1
1
1
0
1
0.0000
1
1
1
1
1
1
0
0.0000
1
1
1
1
1
1
1
0.0000
Catastrophic Thermal Protection
The processor supports the THERMTRIP# signal for catastrophic thermal protection. An
external thermal sensor should also be used to protect the processor and the system
against excessive temperatures. Even with the activation of THERMTRIP#, which halts
all processor internal clocks and activity, leakage current can be high enough such that
the processor cannot be protected in all conditions without the removal of power to the
processor. If the external thermal sensor detects a catastrophic processor temperature
of 125°C (maximum), or if the THERMTRIP# signal is asserted, the VCC supply to the
processor must be turned off within 500 ms to prevent permanent silicon damage due
to thermal runaway of the processor. THERMTRIP# functionality is not guaranteed if the
PWRGOOD signal is not asserted.
3.5
Reserved and Unused Pins
All RESERVED (RSVD) pins must remain unconnected. Connection of these pins to VCC,
VSS, or to any other signal (including each other) can result in component malfunction
or incompatibility with future processors. See Figure 12 for a pin listing of the processor
and the location of all RSVD pins.
For reliable operation, always connect unused inputs or bidirectional signals to an
appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if
AGTL+ termination is provided on the processor silicon. Unused active high inputs
should be connected through a resistor to ground (VSS). Unused outputs can be left
unconnected.
The TEST1 and TEST2 pin must have a stuffing option connection to VSS separately via
1-kΩ, pull-down resistors.
Datasheet
25
Electrical Specifications
For testing purposes it is recommended, but not required, to route the TEST3 and
TEST4 pins through a ground referenced 55-Ω trace that ends in a via that is near a
GND via and is accessible through an oscilloscope connection.
3.6
FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]). These signals should be connected to the clock chip and the Intel 945GM/
GT/GMS/PM and 940GML Express Chipset family on the platform. The BSEL encoding
for BCLK[1:0] is shown in Table 3.
Table 3.
3.7
BSEL[2:0] Encoding for BCLK Frequency
BSEL[2]
BSEL[1]
BSEL[0]
BCLK
Frequency
L
L
L
RESERVED
L
L
H
133 MHz
L
H
L
RESERVED
L
H
H
166 MHz
FSB Signal Groups
In order to simplify the following discussion, the FSB signals have been combined into
groups by buffer type. AGTL+ input signals have differential input buffers, which use
GTLREF as a reference level. In this document, the term "AGTL+ Input" refers to the
AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+
Output" refers to the AGTL+ output group as well as the AGTL+ I/O group when
driving.
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals which are
dependent upon the rising edge of BCLK0 ADS#, HIT#, HITM#, etc.) and the second
set is for the source synchronous signals which are relative to their respective strobe
lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are
still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle. Table 4 identifies which signals are common clock, source synchronous,
and asynchronous.
26
Datasheet
Electrical Specifications
Table 4.
FSB Pin Groups
Signal Group
Signals1
Type
AGTL+ Common Clock Input
Synchronous
to BCLK[1:0]
BPRI#, DEFER#, PREQ#5, RESET#, RS[2:0]#, DPWR#,
TRDY#
AGTL+ Common Clock I/O
Synchronous
to BCLK[1:0]
ADS#, BNR#, BPM[3:0]#3, BR0#, DBSY#, DRDY#, HIT#,
HITM#, LOCK#, PRDY#3
AGTL+ Source Synchronous I/O
Synchronous
to assoc.
strobe
Signals
Associated Strobe
REQ[4:0]#,
A[16:3]#
ADSTB[0]#
A[35:17]#6
ADSTB[1]#
D[15:0]#, DINV0#
DSTBP0#,
DSTBN0#
D[31:16]#, DINV1#
DSTBP1#,
DSTBN1#
D[47:32]#, DINV2#
DSTBP2#,
DSTBN2#
D[63:48]#, DINV3#
DSTBP3#,
DSTBN3#
AGTL+ Strobes
Synchronous
to BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
CMOS Input
Asynchronous
A20M#, DPRSTP#, DPSLP#, IGNNE#, INIT#, LINT0/INTR,
LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK#
Open Drain Output
Asynchronous
FERR#, IERR#, THERMTRIP#
Open Drain I/O
Asynchronous
PROCHOT#4
CMOS Output
Asynchronous
PSI#, VID[6:0], BSEL[2:0]
CMOS Input
Synchronous
to TCK
TCK, TDI, TMS, TRST#
Open Drain Output
Synchronous
to TCK
FSB Clock
Clock
Power/Other
TDO
BCLK[1:0]
COMP[3:0], DBR#2, GTLREF, RSVD, TEST2, TEST1,
THERMDA, THERMDC, VCC, VCCA, VCCP, VCC_SENSE, VSS,
VSS_SENSE
NOTES:
1.
Refer to Chapter 4, “Package Mechanical Specifications and Pin Information” for signal descriptions and
termination requirements.
2.
In processor systems without a debug port implemented on the board, these signals are used to support
debug port interposers. In systems with the debug port implemented on the board, these signals are no
connects.
3.
BPM[2:1]# and PRDY# are AGTL+ output only signals.
4.
PROCHOT# signal type is open drain output and CMOS input.
5.
On-die termination differs from other AGTL+ signals, please contact your Intel representative for more
details.
6.
When paired with a chipset limited to 32-bit addressing, A[35:32] should remain unconnected.
Datasheet
27
Electrical Specifications
3.8
CMOS Signals
CMOS input signals are shown in Table 4. Legacy output FERR#, IERR# and other nonAGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. These
signals do not have setup or hold time specifications in relation to BCLK[1:0]. However,
all of the CMOS signals are required to be asserted for more than four BCLKs in order
for the processor to recognize them. See Section 3.10 for the DC specifications for the
CMOS signal groups.
3.9
Maximum Ratings
Table 5 specifies absolute maximum and minimum ratings. Within functional operation
limits, functionality and long-term reliability can be expected.
At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time then, when returned to conditions within the
functional operating condition limits, it will either not function or its reliability will be
severely degraded.
Although the processor contains protective circuitry to resist damage from static
electric discharge, precautions should always be taken to avoid high static voltages or
electric fields.
Table 5.
Processor Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes1
-40
85
°C
2,3,4
TSTORAGE
Processor storage temperature
VCC
Any processor supply voltage with
respect to VSS
-0.3
1.55
V
VinAGTL+
AGTL+ buffer DC input voltage with
respect to VSS
-0.1
1.55
V
VinAsynch_CMOS
CMOS buffer DC input voltage with
respect to VSS
-0.1
1.55
V
NOTES:
1.
For functional operation, all processor electrical, signal quality, mechanical and thermal
specifications must be satisfied.
2.
Storage temperature is applicable to storage conditions only. In this scenario, the
processor must not receive a clock, and no lands can be connected to a voltage bias. For
functional operation, please refer to the processor case temperature specifications.
3.
This rating applies to the processor and does not include any tray or packaging.
4.
Failure to adhere to this specification can affect the long term reliability of the processor.
28
Datasheet
Electrical Specifications
3.10
Processor DC Specifications
Note:
The processor DC specifications in this section are defined at the processor
core (pads) unless noted otherwise.
See Table 4 for the pin signal definitions and signal pin assignments. Most of the signals
on the FSB are in the AGTL+ signal group. The DC specifications for these signals are
listed in Table 9. DC specifications for the CMOS group are listed in Table 10.
Table 6 through Table 11 list the DC specifications for the processor and are valid only
while meeting specifications for junction temperature, clock frequency, and input
voltages. The Highest Frequency Mode (HFM) and Lowest Frequency Mode (LFM) refer
to the highest and lowest core operating frequencies supported on the processor. Active
mode load line specifications apply in all states except in the Deep Sleep and Deeper
Sleep states. VCC,BOOT is the default voltage driven by the voltage regulator at power
up in order to set the VID values. Unless specified otherwise, all specifications for the
processor are at Tjunction = 100°C. Care should be taken to read all notes associated
with each parameter.
Table 6.
Voltage and Current Specifications for Dual-core Standard Voltage Processors
(Sheet 1 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
Notes
VCCHFM
VCC at Highest Frequency Mode (HFM)
1.0375
1.3000
V
1, 2
VCCLFM
VCC at Lowest Frequency Mode (LFM)
0.75
0.95
V
1, 2
VCC,BOOT
Default VCC Voltage for Initial Power Up
V
2, 8
VCCP
AGTL+ Termination Voltage
VCCA
PLL Supply Voltage
1.20
1.00
1.05
1.10
V
1.425
1.5
1.575
V
VCCDPRSLP
VCC at Deeper Sleep Voltage
0.60
0.80
V
1, 2, 12
VCCDC4
VCC at Intel® Enhanced Deeper Sleep Voltage
0.55
0.70
V
1,2
44
A
5
ICCDES
ICC for Processors
Recommended Design Targets:
ICC for Processors
ICC
IAH,
ISGNT
Processor
Number
Core Frequency/Voltage
T7600
2.33 GHz and HFM VCC
41
T7400
2.17 GHz and HFM VCC
41
T7200
2.00 GHz and HFM VCC
41
T5600
1.83 GHz and HFM VCC
41
T5500
1.67 GHz and HFM VCC
41
1.00 GHz and LFM VCC
27.3
3, 8, 12
3, 8, 12
A
3, 8, 12
3, 8, 13
3, 8, 13
ICC Auto-Halt and Stop-Grant
LFM
18.0
HFM
26.7
A
3,4
A
3,4
ICC Sleep
ISLP
Datasheet
LFM
17.8
HFM
26.1
29
Electrical Specifications
Table 6.
Voltage and Current Specifications for Dual-core Standard Voltage Processors
(Sheet 2 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
Notes
LFM
17.0
A
3,4
HFM
23.7
12.1
A
3,4
ICC Deep Sleep
IDSLP
IDPRSLP
ICC Deeper Sleep
ICCDC4
ICC Intel Enhanced Deeper Sleep
9.9
dICC/DT
VCC Power Supply Current Slew Rate at CPU
Package Pin
600
A/µs
ICCA
ICC for VCCA Supply
130
mA
ICC for VCCP Supply before VCC Stable
4.5
A
9
ICC for VCCP Supply after VCC Stable
2.5
A
10
ICCP
4
6, 7
NOTES:
1.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Note
that this differs from the VID employed by the processor during a power management event (Intel Thermal
Monitor 2, Enhanced Intel SpeedStep Technology, or Extended Halt State).
2.
The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with
a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance.
The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from
the system is not coupled in the scope probe.
3.
Specified at 100°C Tj.
4.
Specified at the VID voltage.
5.
The ICCDES(max) specification of 44 A comprehends processor ICC design target for Intel Core2 Duo mobile
processor for Intel Centrino Duo mobile technology.
6.
Base on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
7.
Measured at the bulk capacitors on the motherboard.
8.
Specified at nominal VCC.
9.
This is a steady-state ICC current specification, which is applicable when both VCCP and VCC_CORE are high.
10.
This is a power-up peak current specification, which is applicable when VCCP is high and VCC_CORE is low.
11.
If a given Operating System C-State model is not based on the use of MWAIT or I/O Redirection, the Intel
Core 2 Duo mobile processor Deeper Sleep VID will be same as LFM VID.
12.
T7600, T7400, T7200 processors feature 4-MB cache.
13.
T5600, T5500 processors feature 2-MB cache.
30
Datasheet
Electrical Specifications
Table 7.
Voltage and Current Specifications for Dual-core Low Voltage Processors
Symbol
Parameter
Min
VCCHFM
VCC at Highest Frequency Mode (HFM)
0.9
VCCLFM
VCC at Lowest Frequency Mode (LFM)
0.75
VCC,BOOT
Default VCC Voltage for Initial Power Up
VCCP
AGTL+ Termination Voltage
VCCA
PLL Supply Voltage
VCCDPRSLP
VCC at Deeper Sleep Voltage
VCCDC4
VCC at Intel® Enhanced Deeper Sleep
Voltage
ICCDES
IAH,
ISGNT
Max
Unit
Notes
1.1
V
1, 2
0.95
1.20
V
1, 2
V
2, 8
1.00
1.05
1.10
V
1.425
1.5
1.575
V
0.6
0.8
V
1, 2, 12
0.55
0.7
V
1,2
23
A
5
ICC for Processors
Recommended Design Targets:
Processor
Number
ICC
Typ
Core Frequency/Voltage
L7400
1.50 GHz and HFM VCC
23
L7200
1.33 GHz and HFM VCC
23
1.00 GHz and LFM VCC
19.7
A
3,9,13
3,9,13
ICC Auto-Halt & Stop-Grant
LFM
10.4
HFM
11.5
A
3,4
A
3,4
A
3,4
A
3,4
ICC Sleep
ISLP
LFM
10.1
HFM
11.2
ICC Deep Sleep
IDSLP
LFM
9.4
HFM
9.9
IDPRSLP
ICC Deeper Sleep
7.4
IDC4
ICC Intel Enhanced Deeper Sleep State
5.4
dICC/DT
VCC Power Supply Current Slew Rate at CPU
Package Pin
600
A/µs
ICCA
ICC for VCCA Supply
130
mA
ICC for VCCP Supply before VCC Stable
4.5
A
10
ICC for VCCP Supply after VCC Stable
2.5
A
11
ICCP
3,4
6, 7
NOTES:
1.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Note
that this differs from the VID employed by the processor during a power management event (Thermal
Monitor 2, Enhanced Intel SpeedStep Technology, or Extended Halt State).
2.
The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with
a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance.
The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from
the system is not coupled in the scope probe.
3.
Specified at 100°C Tj.
Datasheet
31
Electrical Specifications
4.
5.
6.
7.
8.
9.
10.
11.
12.
Specified at the VID voltage.
The ICCDES(max) specification of 23 A comprehends only Intel Core 2 Duo mobile processor HFM
frequencies with Intel Centrino Duo mobile technology.
Based on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
Measured at the bulk capacitors on the motherboard.
VCC,BOOT tolerance shown in Figure 3.
Specified at nominal VCC.
This is a steady-state Icc current specification, which is applicable when both VCCP and VCC_CORE are high.
This is a power-up peak current specification, which is applicable when VCCP is high and VCC_CORE is low.
If a given Operating System C-State model is not based on the use of MWAIT or I/O Redirection, the Intel
Core 2 Duo mobile processor Deeper Sleep VID will be same as LFM VID
Table 8.
Voltage and Current Specifications for Single and Dual-core Ultra Low Voltage
Processors (Sheet 1 of 2)
Symbol
Parameter
Min
VCCHFM
VCC at Highest Frequency Mode (HFM)
0.8
VCCLFM
VCC at Lowest Frequency Mode (LFM)
0.75
VCC,BOOT
Default VCC Voltage for Initial Power Up
VCCP
AGTL+ Termination Voltage
VCCA
PLL Supply Voltage
Typ
Max
Unit
Notes
0.975
V
1, 2
0.95
1.20
V
1, 2
V
2, 8
1.00
1.05
1.10
V
1.425
1.5
1.575
V
VCCDPRSLP
VCC at Deeper Sleep Voltage
0.60
0.80
V
1, 2, 12
VCCDC4
VCC at Intel® Enhanced Deeper Sleep
Voltage
0.55
0.70
V
1, 2
A
5
A
3, 9
A
3, 4
A
3, 4
A
3, 4
ICCDES
ICC
ICC for Processors
Recommended Design Targets:
Processor
Number
Core Frequency/Voltage
U7600
1.20 GHz and HFM VCC
U7500
1.06 GHz and HFM VCC
U2200
1.20 GHz and HFM VCC
U2100
1.06 GHz and HFM VCC
0.80 GHz and LFM VCC
IAH,
ISGNT
17 (dual
core)
8 (single
core)
16
16
8
8
13.8-DC
6.9-SC
ICC Auto-Halt & Stop-Grant
LFM
6.5
HFM
7.4
ICC Sleep
ISLP
LFM
6.3
HFM
7.3
ICC Deep Sleep
IDSLP
LFM
5.7
HFM
6.2
IDPRSLP
ICC Deeper Sleep
4.9
A
3, 4
ICCDC4
ICC Intel Enhanced Deeper Sleep
4.0
A
3, 4
32
Datasheet
Electrical Specifications
Table 8.
Symbol
Voltage and Current Specifications for Single and Dual-core Ultra Low Voltage
Processors (Sheet 2 of 2)
Parameter
Min
Typ
Max
Unit
Notes
6, 7
dICC/DT
VCC Power Supply Current Slew Rate at CPU
Package Pin
600
A/µs
ICCA
ICC for VCCASupply
130
mA
ICC for VCCPSupply before VCC Stable
4.5
A
10
ICC for VCCP Supply after VCC Stable
2.5
A
11
ICCP
NOTES:
1.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing
such that two processors at the same frequency may have different settings within the VID range. Note
that this differs from the VID employed by the processor during a power management event (Intel Thermal
Monitor 2, Enhanced Intel SpeedStep Technology, or Extended Halt State).
2.
The voltage specifications are assumed to be measured across VCC_SENSE and VSS_SENSE pins at socket with
a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-MΩ minimum impedance.
The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from
the system is not coupled in the scope probe.
3.
Specified at 100°C Tj.
4.
Specified at the VID voltage.
5.
The ICCDES(max) specification of 17 A comprehends only Intel Core 2 Duo mobile processor HFM
frequencies on Intel Centrino Duo mobile technology.
6.
Based on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal VCC. Not 100% tested.
7.
Measured at the bulk capacitors on the motherboard.
8.
VCC,BOOT tolerance shown in Figure 3.
9.
Specified at nominal VCC.
10.
This is a steady-state Icc current specification, which is applicable when both VCCP and VCC_CORE are high.
11.
This is a power-up peak current specification, which is applicable when VCCP is high and VCC_CORE is low.
12.
If a given Operating System C-State model is not based on the use of MWAIT or I/O Redirection, the Intel
Core 2 Duo mobile processor Deeper Sleep VID will be same as LFM VID
13.
2-M cache.
Datasheet
33
Electrical Specifications
Figure 3.
Deeper Sleep VCC and ICC Loadline for Dual-core Standard Voltage Processors
VCC-CORE [V]
Slope = -2.1 mV/A at package
VccSense, VssSense pins.
Differential Remote Sense required.
VCC-CORE max {Deeper Sleep}
VCC-CORE, DC max
{Deeper Sleep}
13mV= RIPPLE
for PSI# Asserted
VCC-CORE nom
{Deeper Sleep}
VCC-CORE, DC min
{Deeper Sleep}
VCC-CORE min {Deeper Sleep}
+/-VCC-CORE Tolerance
= VR St. Pt. Error 1/
0
ICC-CORE max
{Deeper Sleep}
ICC-CORE
[A]
Note 1/ Deeper Sl eep V C C - C O R E Set Poi nt Error Tolerance is per below:
34
Tolerance - PSI# Ripple
-----------------------------+/-[(VID*1.5%) - 3 mV]
V C C - C O R E VID Voltage Range
-------------------------------------------------------V C C - C O R E > 0.7500V
+/-(11.5 mV - 3 mV)
0.7500V < V C C - C O R E < 0.5000V
+/- (25 mV - 3 mV)
0.5000V < V C C - C O R E < 0.4125V
Datasheet
Electrical Specifications
Figure 4.
Deeper Sleep VCC and ICC Loadline for Dual-core Low Voltage and
Ultra Low Voltage Processor
VCC-CORE [V]
Slope = -2.1 mV/A at package
VccSense, VssSense pins.
Differential Remote Sense required.
VCC-CORE max {Deeper Sleep}
VCC-CORE, DC max
{Deeper Sleep}
10 mV= RIPPLE
VCC-CORE nom
{Deeper Sleep}
VCC-CORE, DC min
{Deeper Sleep}
VCC-CORE min {Deeper Sleep}
+/-VCC-CORE Tolerance
= VR St. Pt. Error 1/
0
ICC-CORE max
{Deeper Sleep}
ICC-CORE
[A]
Note 1/ Deeper Sleep V CC- COR E Set Point Error Tolerance is per below:
Tolerance
-----------------------------+/- (VID*1.5%)
V CC-C ORE VID Voltage Range
-------------------------------------------------------V CC-C ORE > 0.7500V
+/- 11.5 mV
0.7500V < V CC- CO RE < 0.5000V
+/- 25 mV
0.5000V < V CC- CO RE < 0.4125V
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the
falling edge of BCLK1.
3.
Threshold Region is defined as a region entered about the crossing voltage in which the
differential receiver switches. It includes input threshold hysteresis.
4.
For Vin (Input Voltage) between 0 V and VH.
5.
Cpad includes die capacitance only. No package parasitics are included.
6.
ΔVCROSS is defined as the total variation of all crossing voltages as defined in note 2.
Datasheet
35
Electrical Specifications
Figure 5.
Active VCC and ICC Loadline for Intel Core 2 Solo Processor, Ultra Low Voltage
VCC-CORE [V]
Slope = -5.1 mV/A at package
VccSense, VssSense pins.
Differential Remote Sense required.
VCC-CORE max {HFM|LFM}
VCC-CORE, DC max {HFM|LFM}
10mV= RIPPLE
VCC-CORE nom {HFM|LFM}
VCC-CORE, DC min {HFM|LFM}
VCC-CORE min {HFM|LFM}
+/-VCC-CORE Tolerance
= VR St. Pt. Error 1/
0
ICC-CORE max
{HFM|LFM}
Note 1/ VCC-CORE Set Point Error Tolerance is per below:
Tolerance
VCC-CORE VID Voltage Range
--------------- -------------------------------------------------------+/-1.5%
VCC-CORE > 0.7500V
+/-11.5mV
36
0.75000V < VCC-CORE < 0.5000V
Datasheet
Electrical Specifications
Table 9.
Symbol
VCCP
GTLREF
RCOMP
RODT
AGTL+ Signal Group DC Specifications
Parameter
I/O Voltage
Compensation Resistor
VIL
Input Low Voltage
VOH
Output High Voltage
ILI
Cpad
Max
Unit
1.00
1.05
1.10
V
2/3 VCCP
27.23
Termination Resistor
Input High Voltage
RON
Typ
Reference Voltage
VIH
RTT
Min
27.5
27.78
55
GTLREF +0.10
Notes1
V
6
Ω
10
Ω
11
VCCP
VCCP +0.10
V
3,6
V
2,4
-0.10
0
GTLREF-0.10
VCCP -0.10
VCCP
VCCP
Termination Resistance
50
55
61
Ω
Buffer On Resistance
22
25
28
Ω
5
±100
µA
8
2.55
pF
9
Input Leakage Current
Pad Capacitance
1.6
2.1
6
7
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low
value.
3.
VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value.
4.
VIH and VOH may experience excursions above VCCP. However, input signal drivers must comply with the
signal quality specifications.
5.
This is the pull-down driver resistance. Measured at 0.31*VCCP. RON (min) = 0.38*RTT. RON (typ) =
0.45*RTT. RON (max) = 0.52*RTT.
6.
GTLREF should be generated from VCCP with a 1% tolerance resistor divider. The VCCP referred to in these
specifications is the instantaneous VCCP.
7.
RTT is the on-die termination resistance measured at VOL of the AGTL+ output driver. Measured at
0.31*VCCP. RTT is connected to VCCP on-die.
8.
Specified with on-die RTT and RON are turned off. Vin (Input Voltage) between 0 and VCCP.
9.
Cpad includes die capacitance only. No package parasitics are included.
10.
This is the external resistor on the comp pins.
11.
On-die termination resistance, measured at 0.33*VCCP.
Datasheet
37
Electrical Specifications
.
Table 10.
CMOS Signal Group DC Specifications
Symbol
VCCP
Parameter
I/O Voltage
Notes1
Min
Typ
Max
Unit
1.00
1.05
1.10
V
0.7*VCCP
VCCP
VCCP+0.1
V
2
-0.10
0.00
0.3*VCCP
V
2
VIH
Input High Voltage
VIL
Input Low Voltage CMOS
VOH
Output High Voltage
0.9*VCCP
VCCP
VCCP+0.1
V
2
VOL
Output Low Voltage
-0.10
0
0.1*VCCP
V
2
IOH
Output High Current
1.5
4.1
mA
4
IOL
Output Low Current
1.5
4.1
mA
3
ILI
Input Leakage Current
± 100
µA
5
pF
6
Cpad1
Pad Capacitance
Cpad2
Pad Capacitance for CMOS Input
1.6
2.1
2.55
0.95
1.2
1.45
7
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
The VCCP referred to in these specifications refers to instantaneous VCCP.
3.
Measured at 0.1*VCCP.
4.
Measured at 0.9*VCCP.
5.
For Vin (Input Voltage) between 0 V and VCCP. Measured when the driver is tristated.
6.
Cpad1 includes die capacitance only for DPRSTP#, DPSLP#, PWRGOOD. No package parasitics are
included.
7.
Cpad2 includes die capacitance for all other CMOS input signals. No package parasitics are included.
Table 11.
Symbol
Open Drain Signal Group DC Specifications
Parameter
Min
Typ
Max
Unit
Notes1
VCCP
VCCP+5%
V
3
VOH
Output High Voltage
VCCP-5%
VOL
Output Low Voltage
0
0.20
V
IOL
Output Low Current
16
50
mA
ILO
Output Leakage Current
± 200
µA
4
2.45
pF
5
Cpad
Pad Capacitance
1.9
2.2
2
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Measured at 0.2 V.
3.
VOH is determined by value of the external pull-up resistor to VCCP.
4.
For Vin (Input Voltage) between 0 V and VOH.
5.
Cpad includes die capacitance only. No package parasitics are included.
§§
38
Datasheet
Package Mechanical Specifications and Pin Information
4
Package Mechanical
Specifications and Pin
Information
4.1
Package Mechanical Specifications
The processor will be available in 4-MB and 2-MB L2 cache versions for 478-pin microFCPGA and 4-MB, 2-MB and 1-MB L2 Cache 479-ball micro-FCBGA packages. The
package mechanical dimensions are shown in Figure 6 through Figure 14. Table 12
shows a top-view of package pinout.
The micro-FCBGA package incorporates land-side capacitors. The land-side capacitors
are electrically conductive so care should be taken to avoid contacting the capacitors
with other electrically conductive materials on the motherboard. Doing so may short
the capacitors and possibly damage the device or render it inactive.
Datasheet
39
Package Mechanical Specifications and Pin Information
Figure 6.
4-MB and 2-MB Fused Micro-FCPGA Processor Package Drawing
/+ 04+, *1,/+, +,/.- *1010/+1, *1,3+.,/+- +,310&/+1,% +/ + + *-1 . +, *1,3+.,*.
, +/ *1,/.,/ &2 ,1/ . + *-1 .7 0.01*.7 + -2. 10 &1+3+.7 4+/1/ /. 0+10
40+//., *1, .,/ 13 +,/.- *1010/+1,
*
*
!"##
%()%
$%( &'
3
% &'
3(
*
$% &'
$
&+--+&./.0
&+,
&'
( % (%
( % (%
*
%
*
(%
%
3
%(
%(
3
(% +*
(% +*
% +*
% +*
%
+*
%
+*
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4
56 2& 1-
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$%( & * $% & *
7
40
Datasheet
Datasheet
'!( ' ' !
!
Figure 7.
" # # $ $ # ## $ # # % ## & & # % $ & # $ Package Mechanical Specifications and Pin Information
4-MB and 2-MB Fused Micro-FCPGA Processor Package Drawing
41
Package Mechanical Specifications and Pin Information
Figure 8.
2-MB Micro-FCPGA Processor Package Drawing
G1
B1
B
H1
G2
C2
B2
H2
J2
C1
A
Bottom View
Top View
A
J1
478 Pins
Front View
Side View
SYMBOL
Die
Underfill
Package Substrate
MIN
MAX
B1
34.95
35.05
B2
34.95
10
C2
10.3
F3
F2
G1
F3
0.65 MAX
2.03±0.08 C
oP
0.65 MAX
Detail A
Scale 20
0.89
1.823
2.063
31.75 BASIC
G2
31.75 BASIC
H1
15.875 BASIC
H2
15.875 BASIC
J1
1.27 BASIC
J2
P
P DIE
W
COMMENTS
35.05
C1
F2
0.37 MAX
MILLIMETERS
ø0.356
ø0.254
M C A B
M C
1.27 BASIC
0.255
0.355
689 kPa
6g
Keying Pins
A1, B1
B6152-02
42
Datasheet
Package Mechanical Specifications and Pin Information
Figure 9.
2-MB Micro-FCPGA Processor Package Drawing
! ! "# $ %&
' !
! Top View
ø0.305±0.25
ø0.406 M C A B
ø0.254 M C
(( $ %&
' !
Side View
Bottom View
Datasheet
43
Package Mechanical Specifications and Pin Information
Figure 10.
4-MB and 2-MB Fused Micro-FCBGA Processor Package Drawing
Top View
Bottom View
M
Front View
Detail B
Side View
!"# $%
&%
0.203
Detail A
() *+
).++.),-,/
'
'
'
'
'
'1
'1
'
'
' .
' .
'1 .
'1 .
' .
' .
'
'
'
'1
1 )
&.,
2
).
) 0
*)),-
ø0.203 L C A B
ø0.071 L
44
Datasheet
Package Mechanical Specifications and Pin Information
Figure 11.
4-MB and 2-MB Fused Micro-FCBGA Processor Package Drawing
)*+ ,-.*/0 %/)*/+ */)"1 %-2%-)*%/ %/3*,"/)*1 */3%-)*%/ *) *+ ,*+1%+", */ %/3*,"/"
/, *)+ %/)"/)+ 4 /%) " ,*+1%+",5 -"2-%,6",5 ,*+214", %- %,*3*",5 .*)%6) )" 2-*%.-*))"/ %/+"/) %3 */)"1 %-2%-)*%/
"# $ %&
'
Side View
(( $ %&
'
Top View
!
!
Bottom View
Datasheet
45
Package Mechanical Specifications and Pin Information
Figure 12.
2-MB Micro-FCBGA Processor Package Drawing
Top View
Bottom View
M
Front View
Detail B
() *+
Side View
!"# $%
&%
0.203
Detail A
)
&.,
2
).++.),-,/
).
' ' ) 0
*)),-
'
'
'
'1
' '
' .
' .
'1 .
'1 .
'
.
'
.
'
'
'
'1
1 ø0.203 L C A B
ø0.071 L
46
Datasheet
Datasheet
'#$( )
Detail B
OM
Front View
Top View
&
&
4
)
)
) ) "
)
)
" *#
+
") )"
) "
"
"
Side View
ø0.203 L
ø0.071 L
CAB
" #$$%
&
#'*#+( ,-%./#.(
&
!01(/23$$
'#$( )
Detail A
3(
Bottom View
))
Figure 13.
Package Mechanical Specifications and Pin Information
1-MB Micro-FCBGA Processor Package Drawing (2 of 2)
47
Top View
!
""
!
""
48
""
# $ !
!
Side View
" ! %
Bottom View
%
%
%
Figure 14.
# $ !
Package Mechanical Specifications and Pin Information
1-MB Micro-FCBGA Processor Package Drawing (2 of 2)
Datasheet
Package Mechanical Specifications and Pin Information
4.2
Processor Pinout and Pin List
Table 12 shows the top view pinout of the processor. The pin list, arranged in two
different formats, is shown in the following pages.
Datasheet
49
Package Mechanical Specifications and Pin Information
Table 12. The Coordinates of the Processor Pins as Viewed from the Top of the Package
(Sheet 1 of 2)
1
2
A
B
C
RESET#
RSVD]
RSVD
VSS
3
4
5
6
7
8
9
10
11
12
13
SMI#
VSS
FERR#
A20M#
VCC
VSS
VCC
VCC
VSS
VCC
VCC
A
INIT#
LINT1
DPSLP#
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
B
RSVD
IGNNE
#
VSS
LINT0
THERM
TRIP#
VSS
VCC
VCC
VSS
VCC
VCC
C
PWRGO
OD
D
VSS
RSVD
RSVD
VSS
STPCLK
#
SLP#
VSS
VCC
VCC
VSS
VCC
VSS
D
E
DBSY#
BNR#
VSS
HITM#
DPRSTP
#
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VCC
E
F
BR0#
VSS
RS[0]#
RS[1]#
VSS
RSVD
VCC
VSS
VCC
VCC
VSS
VCC
VSS
F
G
VSS
TRDY#
RS[2]#
VSS
BPRI#
HIT#
G
H
ADS#
REQ[1]
#
VSS
LOCK#
DEFER#
VSS
H
J
A[9]#
VSS
REQ[3]
#
A[3]#
VSS
VCCP
J
K
VSS
REQ[2]
#
REQ[0]
#
VSS
A[6]#
VCCP
K
L
A[13]#
ADSTB[
0]#
VSS
A[4]#
REQ[4]
#
VSS
L
M
A[7]#
VSS
A[5]#
RSVD
VSS
VCCP
M
N
VSS
A[8]#
A[10]#
VSS
RSVD
VCCP
N
P
A[15]#
A[12]#
VSS
A[14]#
A[11]#
VSS
P
R
A[16]#
VSS
A[19]#
A[24]#
VSS
VCCP
R
T
VSS
RSVD
A[26]#
VSS
A[25]#
VCCP
T
U
COMP[2]
A[23]#
VSS
A[21]#
A[18]#
VSS
U
V
COMP[3]
VSS
RSVD
ADSTB[
1]#
VSS
VCCP
V
W
VSS
A[30]#
A[27]#
VSS
A[28]#
A[20]#
W
Y
A[31]#
A[17]#
VSS
A[29]#
A[22]#
VSS
AA
A[32]#
VSS
A[35]#
A[33]#
VSS
TDI
AB
VSS
A[34]#
TDO
VSS
TMS
TRST#
VCC
VSS
VCC
VCC
VSS
AC
PREQ#
PRDY#
VSS
BPM[3]
#
TCK
VSS
VCC
VSS
VCC
VCC
VSS
AD
BPM[2]#
VSS
BPM[1]
#
BPM[0]
#
VSS
VID[0]
VCC
VSS
VCC
VCC
VSS
Y
VCC
VSS
VCC
VCC
VSS
VCC
VCC
AA
VCC
VSS
AB
VCC
VCC
AC
VCC
VSS
AD
AE
VSS
VID[6]
VID[4]
VSS
VID[2]
PSI#
VSS
SENSE
VSS
VCC
VCC
VSS
VCC
VCC
AE
AF
TEST3
VID[5]
VSS
VID[3]
VID[1]
VSS
VCC
SENSE
VSS
VCC
VCC
VSS
VCC
VSS
AF
1
2
3
4
5
6
7
8
9
10
11
12
13
50
Datasheet
Package Mechanical Specifications and Pin Information
Table 13.
The Coordinates of the Processor Pins as Viewed from the Top of the Package
(Sheet 2 of 2)
14
15
16
17
18
19
20
21
22
23
24
25
26
A
VSS
VCC
VSS
VCC
VCC
VSS
VCC
BCLK[1]
BCLK[0]
VSS
THRMDA
THRMDC
VSS
A
B
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
BSEL[0]
BSEL[1]
VSS
TEST4
VCCA
B
C
VSS
VCC
VSS
VCC
VCC
VSS
DBR#
BSEL[2]
VSS
RSVD
RSVD
VSS
TEST1
C
IERR#
PROCHO
T#
RSVD
VSS
DPWR#
TEST2
VSS
D
D
VCC
VCC
VSS
VCC
VCC
VSS
E
VSS
VCC
VSS
VCC
VCC
VSS
VCC
VSS
D[0]#
D[7]#
VSS
D[6]#
D[2]#
E
F
VCC
VCC
VSS
VCC
VCC
VSS
VCC
DRDY#
VSS
D[4]#
D[1]#
VSS
D[13]#
F
VCCP
DSTBP[0]
#
VSS
D[9]#
D[5]#
VSS
G
D[3]#
DSTBN[0]
#
VSS
D[15]#
D[12]#
H
VSS
DINV[0
]#
J
G
H
VSS
J
VCCP
VSS
K
VCCP
L
VSS
M
VCCP
D[11]#
D[10]#
D[14]#
VSS
D[8]#
D[17]#
VSS
K
D[21]#
D[22]#
VSS
D[20]#
D[29]#
L
D[23]#
DSTBN[1]
#
VSS
DINV[1
]#
M
VSS
N
VSS
N
VCCP
D[16]#
VSS
D[31]#
DSTBP[1]
#
P
VSS
D[25]#
D[26]#
VSS
D[24]#
D[18]#
P
R
R
VCCP
VSS
D[19]#
D[28]#
VSS
COMP
[0]
T
VCCP
RSVD
VSS
D[27]#
D[30]#
VSS
T
VSS
D[38]#
COMP[1
]
U
VSS
D[35]#
V
U
VSS
D[39]#
D[37]#
V
VCCP
VSS
DINV[2]#
D[34]#
W
VCCP
D[41]#
VSS
DSTBN[2]
#
D[36]#
VSS
W
Y
VSS
D[45]#
D[42]#
VSS
DSTBP[2]
#
D[44]#
Y
AA
VSS
VCC
VSS
VCC
VCC
VSS
VCC
D[51]#
VSS
D[32]#
D[47]#
VSS
D[43]#
A
A
AB
VCC
VCC
VSS
VCC
VCC
VSS
VCC
D[52]#
D[50]#
VSS
D[33]#
D[40]#
VSS
A
B
AC
VSS
VCC
VSS
VCC
VCC
VSS
DINV[3
]#
VSS
D[48]#
D[49]#
VSS
D[53]#
D[46]#
AC
D[57]#
VSS
GTLREF
A
D
A
D
VCC
VCC
VSS
VCC
VCC
VSS
D[54]#
D[59]#
VSS
DSTBN[3]
#
AE
VSS
VCC
VSS
VCC
VCC
VSS
VCC
D[58]#
D[55]#
VSS
DSTBP[3]
#
D[60]#
VSS
AE
AF
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
D[62]#
D[56]#
VSS
D[61]#
D[63]#
AF
14
15
16
17
18
19
20
21
22
23
24
25
26
Datasheet
51
Package Mechanical Specifications and Pin Information
This page is intentionally left blank.
52
Datasheet
Package Mechanical Specifications and Pin Information
Table 14.
Pin Name
Pin Listing by Pin Name
(Sheet 1 of 22)
Pin
Number
Signal
Buffer
Type
Direction
A[3]#
J4
Source
Synch
A[4]#
L4
Source
Synch
Input/Output
A[5]#
M3
Source
Synch
Input/Output
K5
Source
Synch
A[7]#
M1
Source
Synch
Input/Output
A[8]#
N2
Source
Synch
Input/Output
A[9]#
J1
Source
Synch
Input/Output
N3
Source
Synch
A[11]#
P5
Source
Synch
Input/Output
A[12]#
P2
Source
Synch
Input/Output
A[13]#
L1
Source
Synch
Input/Output
P4
Source
Synch
Input/Output
A[15]#
P1
Source
Synch
Input/Output
A[16]#
R1
Source
Synch
Input/Output
Y2
Source
Synch
Input/Output
A[18]#
U5
Source
Synch
Input/Output
A[19]#
R3
Source
Synch
Input/Output
A[20]#
W6
Source
Synch
Input/Output
U4
Source
Synch
Input/Output
Y5
Source
Synch
Input/Output
Source
Synch
Input/Output
A[6]#
A[10]#
A[14]#
A[17]#
A[21]#
A[22]#
A[23]#
Datasheet
U2
Input/Output
Input/Output
Input/Output
Table 14.
Pin Name
Pin Listing by Pin Name
(Sheet 2 of 22)
Pin
Number
Signal
Buffer
Type
Direction
A[24]#
R4
Source
Synch
Input/Output
A[25]#
T5
Source
Synch
Input/Output
A[26]#
T3
Source
Synch
Input/Output
A[27]#
W3
Source
Synch
Input/Output
A[28]#
W5
Source
Synch
Input/Output
A[29]#
Y4
Source
Synch
Input/Output
A[30]#
W2
Source
Synch
Input/Output
A[31]#
Y1
Source
Synch
Input/Output
A[32]#
AA1
Source
Synch
Input/Output
A[33]#
AA4
Source
Synch
Input/Output
A[34]#
AB2
Source
Synch
Input/Output
A[35]#
AA3
Source
Synch
Input/Output
A20M#
A6
CMOS
Input
ADS#
H1
Common
Clock
Input/Output
ADSTB[0]#
L2
Source
Synch
Input/Output
ADSTB[1]#
V4
Source
Synch
Input/Output
BCLK[0]
A22
Bus Clock
Input
BCLK[1]
A21
Bus Clock
Input
BNR#
E2
Common
Clock
Input/Output
BPM[0]#
AD4
Common
Clock
Input/Output
BPM[1]#
AD3
Common
Clock
Output
BPM[2]#
AD1
Common
Clock
Output
53
Package Mechanical Specifications and Pin Information
Table 14.
Pin Name
Pin Listing by Pin Name
(Sheet 3 of 22)
Pin
Number
Signal
Buffer
Type
Direction
Table 14.
Pin Name
Pin Listing by Pin Name
(Sheet 4 of 22)
Pin
Number
Signal
Buffer
Type
Direction
BPM[3]#
AC4
Common
Clock
Input/Output
D[12]#
H26
Source
Synch
Input/Output
BPRI#
G5
Common
Clock
Input
D[13]#
F26
Source
Synch
Input/Output
BR0#
F1
Common
Clock
Input/Output
D[14]#
K22
Source
Synch
Input/Output
BSEL[0]
B22
CMOS
Output
D[15]#
H25
Input/Output
BSEL[1]
B23
CMOS
Output
Source
Synch
BSEL[2]
C21
CMOS
Output
D[16]#
N22
Source
Synch
Input/Output
COMP[0]
R26
Power/
Other
Input/Output
D[17]#
K25
Source
Synch
Input/Output
COMP[1]
U26
Power/
Other
Input/Output
D[18]#
P26
Source
Synch
Input/Output
COMP[2]
U1
Power/
Other
Input/Output
D[19]#
R23
Source
Synch
Input/Output
COMP[3]
V1
Power/
Other
Input/Output
D[20]#
L25
Source
Synch
Input/Output
D[0]#
E22
Source
Synch
Input/Output
D[21]#
L22
Source
Synch
Input/Output
D[1]#
F24
Source
Synch
Input/Output
D[22]#
L23
Source
Synch
Input/Output
D[2]#
E26
Source
Synch
Input/Output
D[23]#
M23
Source
Synch
Input/Output
D[3]#
H22
Source
Synch
Input/Output
D[24]#
P25
Source
Synch
Input/Output
D[4]#
F23
Source
Synch
Input/Output
D[25]#
P22
Source
Synch
Input/Output
D[5]#
G25
Source
Synch
Input/Output
D[26]#
P23
Source
Synch
Input/Output
D[6]#
E25
Source
Synch
Input/Output
D[27]#
T24
Source
Synch
Input/Output
D[7]#
E23
Source
Synch
Input/Output
D[28]#
R24
Source
Synch
Input/Output
D[8]#
K24
Source
Synch
Input/Output
D[29]#
L26
Source
Synch
Input/Output
D[9]#
G24
Source
Synch
Input/Output
D[30]#
T25
Source
Synch
Input/Output
D[10]#
J24
Source
Synch
Input/Output
D[31]#
N24
Source
Synch
Input/Output
D[11]#
J23
Source
Synch
Input/Output
D[32]#
AA23
Source
Synch
Input/Output
54
Datasheet
Package Mechanical Specifications and Pin Information
Table 14.
Pin Name
Pin Listing by Pin Name
(Sheet 5 of 22)
Pin
Number
Signal
Buffer
Type
Direction
Table 14.
Pin Name
Pin Listing by Pin Name
(Sheet 6 of 22)
Pin
Number
Signal
Buffer
Type
Direction
D[33]#
AB24
Source
Synch
Input/Output
D[54]#
AD20
Source
Synch
Input/Output
D[34]#
V24
Source
Synch
Input/Output
D[55]#
AE22
Source
Synch
Input/Output
D[35]#
V26
Source
Synch
Input/Output
D[56]#
AF23
Source
Synch
Input/Output
D[36]#
W25
Source
Synch
Input/Output
D[57]#
AD24
Source
Synch
Input/Output
D[37]#
U23
Source
Synch
Input/Output
D[58]#
AE21
Source
Synch
Input/Output
D[38]#
U25
Source
Synch
Input/Output
D[59]#
AD21
Source
Synch
Input/Output
D[39]#
U22
Source
Synch
Input/Output
D[60]#
AE25
Source
Synch
Input/Output
D[40]#
AB25
Source
Synch
Input/Output
D[61]#
AF25
Source
Synch
Input/Output
D[41]#
W22
Source
Synch
Input/Output
D[62]#
AF22
Source
Synch
Input/Output
D[42]#
Y23
Source
Synch
Input/Output
D[63]#
AF26
Source
Synch
Input/Output
D[43]#
AA26
Source
Synch
Input/Output
DBR#
C20
CMOS
Output
E1
Input/Output
Common
Clock
Input/Output
Y26
Source
Synch
DBSY#
D[44]#
DEFER#
H5
Common
Clock
Input
Y22
Source
Synch
DINV[0]#
J26
Source
Synch
Input/Output
AC26
Source
Synch
DINV[1]#
M26
AA24
Input/Output
Source
Synch
Input/Output
D[47]#
Source
Synch
V23
Input/Output
Source
Synch
Input/Output
AC22
Source
Synch
DINV[2]#
D[48]#
DINV[3]#
AC20
Input/Output
Source
Synch
Input/Output
AC23
Source
Synch
DPRSTP#
E5
CMOS
Input
D[50]#
AB22
Source
Synch
Input/Output
DPSLP#
B5
CMOS
Input
D[51]#
AA21
Source
Synch
Input/Output
DPWR#
D24
Common
Clock
Input
D[52]#
AB21
Source
Synch
Input/Output
DRDY#
F21
Common
Clock
Input/Output
D[53]#
AC25
Source
Synch
Input/Output
DSTBN[0]#
H23
Source
Synch
Input/Output
D[45]#
D[46]#
D[49]#
Datasheet
Input/Output
Input/Output
55
Package Mechanical Specifications and Pin Information
Table 14.
Pin Name
Pin Listing by Pin Name
(Sheet 7 of 22)
Pin
Number
Signal
Buffer
Type
Direction
Table 14.
Pin Name
Pin Listing by Pin Name
(Sheet 8 of 22)
Pin
Number
Signal
Buffer
Type
Direction
DSTBN[1]#
M24
Source
Synch
Input/Output
REQ[3]#
J3
Source
Synch
Input/Output
DSTBN[2]#
W24
Source
Synch
Input/Output
REQ[4]#
L5
Source
Synch
Input/Output
DSTBN[3]#
AD23
Source
Synch
Input/Output
RESET#
B1
Common
Clock
Input
DSTBP[0]#
G22
Source
Synch
Input/Output
RS[0]#
F3
Common
Clock
Input
DSTBP[1]#
N25
Source
Synch
Input/Output
RS[1]#
F4
Common
Clock
Input
DSTBP[2]#
Y25
Source
Synch
Input/Output
RS[2]#
G3
Common
Clock
Input
DSTBP[3]#
AE24
Source
Synch
Input/Output
RSVD
D2
Reserved
RSVD
F6
Reserved
FERR#
A5
Open Drain
Output
RSVD
D3
Reserved
GTLREF
AD26
Power/
Other
Input
RSVD
C1
Reserved
D22
Reserved
G6
Common
Clock
RSVD
HIT#
Input/Output
RSVD
C23
Reserved
HITM#
E4
Common
Clock
Input/Output
RSVD
C24
Reserved
RSVD
M4
Reserved
IERR#
D20
Open Drain
Output
RSVD
N5
Reserved
IGNNE#
C4
CMOS
Input
RSVD
T2
Reserved
INIT#
B3
CMOS
Input
RSVD
V3
Reserved
LINT0
C6
CMOS
Input
RSVD
B2
Reserved
LINT1
B4
CMOS
Input
RSVD
C3
Reserved
H4
Common
Clock
Input/Output
RSVD
T22
Reserved
SLP#
D7
CMOS
Input
SMI#
A3
CMOS
Input
STPCLK#
D5
CMOS
Input
LOCK#
PRDY#
AC2
Common
Clock
Output
PREQ#
AC1
Common
Clock
Input
PROCHOT#
D21
Open Drain
Input/Output
PSI#
AE6
CMOS
Output
PWRGOOD
D6
CMOS
Input
K3
Source
Synch
Input/Output
REQ[0]#
REQ[1]#
H2
Source
Synch
Input/Output
REQ[2]#
K2
Source
Synch
Input/Output
56
TCK
AC5
CMOS
Input
TDI
AA6
CMOS
Input
TDO
AB3
Open Drain
Output
TEST1
C26
Test
TEST2
D25
Test
TEST3
AF1
Test
TEST4
B25
Test
THERMDA
A24
Power/
Other
Datasheet
Package Mechanical Specifications and Pin Information
Table 14.
Pin Name
Pin Listing by Pin Name
(Sheet 9 of 22)
Pin
Number
Signal
Buffer
Type
Direction
THERMDC
A25
Power/
Other
THERMTRIP#
C7
Open Drain
Output
TMS
AB5
CMOS
Input
TRDY#
G2
Common
Clock
Input
TRST#
AB6
CMOS
Input
VCC
AB20
VCC
Table 14.
Pin Name
Pin Listing by Pin Name
(Sheet 10 of 22)
Pin
Number
Signal
Buffer
Type
VCC
AA15
Power/
Other
VCC
AD15
Power/
Other
VCC
AC15
Power/
Other
VCC
AF15
Power/
Other
Power/
Other
VCC
AE15
Power/
Other
AA20
Power/
Other
VCC
AB14
Power/
Other
VCC
AF20
Power/
Other
VCC
AA13
Power/
Other
VCC
AE20
Power/
Other
VCC
AD14
Power/
Other
VCC
AB18
Power/
Other
VCC
AC13
Power/
Other
VCC
AB17
Power/
Other
VCC
AF14
Power/
Other
VCC
AA18
Power/
Other
VCC
AE13
Power/
Other
VCC
AA17
Power/
Other
VCC
AB12
Power/
Other
VCC
AD18
Power/
Other
VCC
AA12
Power/
Other
VCC
AD17
Power/
Other
VCC
AD12
Power/
Other
VCC
AC18
Power/
Other
VCC
AC12
Power/
Other
VCC
AC17
Power/
Other
VCC
AF12
Power/
Other
VCC
AF18
Power/
Other
VCC
AE12
Power/
Other
VCC
AF17
Power/
Other
VCC
AB10
Power/
Other
VCC
AE18
Power/
Other
VCC
AB9
Power/
Other
VCC
AE17
Power/
Other
VCC
AA10
Power/
Other
VCC
AB15
Power/
Other
VCC
AA9
Power/
Other
Datasheet
Direction
57
Package Mechanical Specifications and Pin Information
Table 14.
Pin Name
Pin Listing by Pin Name
(Sheet 11 of 22)
Pin
Number
Signal
Buffer
Type
Direction
Table 14.
Pin Name
Pin Listing by Pin Name
(Sheet 12 of 22)
Pin
Number
Signal
Buffer
Type
VCC
AD10
Power/
Other
VCC
D17
Power/
Other
VCC
AD9
Power/
Other
VCC
C18
Power/
Other
VCC
AC10
Power/
Other
VCC
C17
Power/
Other
VCC
AC9
Power/
Other
VCC
F18
Power/
Other
VCC
AF10
Power/
Other
VCC
F17
Power/
Other
VCC
AF9
Power/
Other
VCC
E18
Power/
Other
VCC
AE10
Power/
Other
VCC
E17
Power/
Other
VCC
AE9
Power/
Other
VCC
B15
Power/
Other
VCC
AB7
Power/
Other
VCC
A15
Power/
Other
VCC
AA7
Power/
Other
VCC
D15
Power/
Other
VCC
AD7
Power/
Other
VCC
C15
Power/
Other
VCC
AC7
Power/
Other
VCC
F15
Power/
Other
VCC
B20
Power/
Other
VCC
E15
Power/
Other
VCC
A20
Power/
Other
VCC
B14
Power/
Other
VCC
F20
Power/
Other
VCC
A13
Power/
Other
VCC
E20
Power/
Other
VCC
D14
Power/
Other
VCC
B18
Power/
Other
VCC
C13
Power/
Other
VCC
B17
Power/
Other
VCC
F14
Power/
Other
VCC
A18
Power/
Other
VCC
E13
Power/
Other
VCC
A17
Power/
Other
VCC
B12
Power/
Other
VCC
D18
Power/
Other
VCC
A12
Power/
Other
58
Direction
Datasheet
Package Mechanical Specifications and Pin Information
Table 14.
Pin Name
Pin Listing by Pin Name
(Sheet 13 of 22)
Pin
Number
Signal
Buffer
Type
Direction
Table 14.
Pin Name
Pin Listing by Pin Name
(Sheet 14 of 22)
Pin
Number
Signal
Buffer
Type
Direction
VCC
D12
Power/
Other
VCCP
K6
Power/
Other
VCC
C12
Power/
Other
VCCP
J6
Power/
Other
VCC
F12
Power/
Other
VCCP
M6
Power/
Other
VCC
E12
Power/
Other
VCCP
N6
Power/
Other
VCC
B10
Power/
Other
VCCP
T6
Power/
Other
VCC
B9
Power/
Other
VCCP
R6
Power/
Other
VCC
A10
Power/
Other
VCCP
K21
Power/
Other
VCC
A9
Power/
Other
VCCP
J21
Power/
Other
VCC
D10
Power/
Other
VCCP
M21
Power/
Other
VCC
D9
Power/
Other
VCCP
N21
Power/
Other
VCC
C10
Power/
Other
VCCP
T21
Power/
Other
VCC
C9
Power/
Other
VCCP
R21
Power/
Other
VCC
F10
Power/
Other
VCCP
V21
Power/
Other
VCC
F9
Power/
Other
VCCP
W21
Power/
Other
VCC
E10
Power/
Other
VCCP
V6
Power/
Other
VCC
E9
Power/
Other
VCCP
G21
Power/
Other
VCC
B7
Power/
Other
VCCSENSE
AF7
Power/
Other
VCC
A7
Power/
Other
VID[0]
AD6
CMOS
Output
VID[1]
AF5
CMOS
Output
VID[2]
AE5
CMOS
Output
VID[3]
AF4
CMOS
Output
VID[4]
AE3
CMOS
Output
VID[5]
AF2
CMOS
Output
VID[6]
AE2
CMOS
Output
VCC
F7
Power/
Other
VCC
E7
Power/
Other
B26
Power/
Other
VCCA
Datasheet
59
Package Mechanical Specifications and Pin Information
Table 14.
Pin Name
Pin Listing by Pin Name
(Sheet 15 of 22)
Pin
Number
Signal
Buffer
Type
Direction
Table 14.
Pin Name
Pin Listing by Pin Name
(Sheet 16 of 22)
Pin
Number
Signal
Buffer
Type
VSS
AB26
Power/
Other
VSS
AC16
Power/
Other
VSS
AA25
Power/
Other
VSS
AF16
Power/
Other
VSS
AD25
Power/
Other
VSS
AE16
Power/
Other
VSS
AE26
Power/
Other
VSS
AB13
Power/
Other
VSS
AB23
Power/
Other
VSS
AA14
Power/
Other
VSS
AC24
Power/
Other
VSS
AD13
Power/
Other
VSS
AF24
Power/
Other
VSS
AC14
Power/
Other
VSS
AE23
Power/
Other
VSS
AF13
Power/
Other
VSS
AA22
Power/
Other
VSS
AE14
Power/
Other
VSS
AD22
Power/
Other
VSS
AB11
Power/
Other
VSS
AC21
Power/
Other
VSS
AA11
Power/
Other
VSS
AF21
Power/
Other
VSS
AD11
Power/
Other
VSS
AB19
Power/
Other
VSS
AC11
Power/
Other
VSS
AA19
Power/
Other
VSS
AF11
Power/
Other
VSS
AD19
Power/
Other
VSS
AE11
Power/
Other
VSS
AC19
Power/
Other
VSS
AB8
Power/
Other
VSS
AF19
Power/
Other
VSS
AA8
Power/
Other
VSS
AE19
Power/
Other
VSS
AD8
Power/
Other
VSS
AB16
Power/
Other
VSS
AC8
Power/
Other
VSS
AA16
Power/
Other
VSS
AF8
Power/
Other
VSS
AD16
Power/
Other
VSS
AE8
Power/
Other
60
Direction
Datasheet
Package Mechanical Specifications and Pin Information
Table 14.
Pin Name
Pin Listing by Pin Name
(Sheet 17 of 22)
Pin
Number
Signal
Buffer
Type
Direction
Table 14.
Pin Name
Pin Listing by Pin Name
(Sheet 18 of 22)
Pin
Number
Signal
Buffer
Type
VSS
AA5
Power/
Other
VSS
R5
Power/
Other
VSS
AD5
Power/
Other
VSS
V5
Power/
Other
VSS
AC6
Power/
Other
VSS
U6
Power/
Other
VSS
AF6
Power/
Other
VSS
Y6
Power/
Other
VSS
AB4
Power/
Other
VSS
A4
Power/
Other
VSS
AC3
Power/
Other
VSS
D4
Power/
Other
VSS
AF3
Power/
Other
VSS
E3
Power/
Other
VSS
AE4
Power/
Other
VSS
H3
Power/
Other
VSS
AB1
Power/
Other
VSS
G4
Power/
Other
VSS
AA2
Power/
Other
VSS
K4
Power/
Other
VSS
AD2
Power/
Other
VSS
L3
Power/
Other
VSS
AE1
Power/
Other
VSS
P3
Power/
Other
VSS
B6
Power/
Other
VSS
N4
Power/
Other
VSS
C5
Power/
Other
VSS
T4
Power/
Other
VSS
F5
Power/
Other
VSS
U3
Power/
Other
VSS
E6
Power/
Other
VSS
Y3
Power/
Other
VSS
H6
Power/
Other
VSS
W4
Power/
Other
VSS
J5
Power/
Other
VSS
D1
Power/
Other
VSS
M5
Power/
Other
VSS
C2
Power/
Other
VSS
L6
Power/
Other
VSS
F2
Power/
Other
VSS
P6
Power/
Other
VSS
G1
Power/
Other
Datasheet
Direction
61
Package Mechanical Specifications and Pin Information
Table 14.
Pin Name
Pin Listing by Pin Name
(Sheet 19 of 22)
Pin
Number
Signal
Buffer
Type
Direction
Table 14.
Pin Name
Pin Listing by Pin Name
(Sheet 20 of 22)
Pin
Number
Signal
Buffer
Type
VSS
K1
Power/
Other
VSS
A19
Power/
Other
VSS
J2
Power/
Other
VSS
D19
Power/
Other
VSS
M2
Power/
Other
VSS
C19
Power/
Other
VSS
N1
Power/
Other
VSS
F19
Power/
Other
VSS
T1
Power/
Other
VSS
E19
Power/
Other
VSS
R2
Power/
Other
VSS
B16
Power/
Other
VSS
V2
Power/
Other
VSS
A16
Power/
Other
VSS
W1
Power/
Other
VSS
D16
Power/
Other
VSS
A26
Power/
Other
VSS
C16
Power/
Other
VSS
D26
Power/
Other
VSS
F16
Power/
Other
VSS
C25
Power/
Other
VSS
E16
Power/
Other
VSS
F25
Power/
Other
VSS
B13
Power/
Other
VSS
B24
Power/
Other
VSS
A14
Power/
Other
VSS
A23
Power/
Other
VSS
D13
Power/
Other
VSS
D23
Power/
Other
VSS
C14
Power/
Other
VSS
E24
Power/
Other
VSS
F13
Power/
Other
VSS
B21
Power/
Other
VSS
E14
Power/
Other
VSS
C22
Power/
Other
VSS
B11
Power/
Other
VSS
F22
Power/
Other
VSS
A11
Power/
Other
VSS
E21
Power/
Other
VSS
D11
Power/
Other
VSS
B19
Power/
Other
VSS
C11
Power/
Other
62
Direction
Datasheet
Package Mechanical Specifications and Pin Information
Table 14.
Pin Name
Pin Listing by Pin Name
(Sheet 21 of 22)
Pin
Number
Signal
Buffer
Type
Direction
Table 14.
Pin Name
Pin Listing by Pin Name
(Sheet 22 of 22)
Pin
Number
Signal
Buffer
Type
VSS
F11
Power/
Other
VSS
P24
Power/
Other
VSS
E11
Power/
Other
VSS
N23
Power/
Other
VSS
B8
Power/
Other
VSS
T23
Power/
Other
VSS
A8
Power/
Other
VSS
U24
Power/
Other
VSS
D8
Power/
Other
VSS
Y24
Power/
Other
VSS
C8
Power/
Other
VSS
W23
Power/
Other
VSS
F8
Power/
Other
VSS
H21
Power/
Other
VSS
E8
Power/
Other
VSS
J22
Power/
Other
VSS
G26
Power/
Other
VSS
M22
Power/
Other
VSS
K26
Power/
Other
VSS
L21
Power/
Other
VSS
J25
Power/
Other
VSS
P21
Power/
Other
VSS
M25
Power/
Other
VSS
R22
Power/
Other
VSS
N26
Power/
Other
VSS
V22
Power/
Other
VSS
T26
Power/
Other
VSS
U21
Power/
Other
VSS
R25
Power/
Other
VSS
Y21
Power/
Other
VSS
V25
Power/
Other
VSSSENSE
AE7
Power/
Other
VSS
W26
Power/
Other
VSS
H24
Power/
Other
VSS
G23
Power/
Other
VSS
K23
Power/
Other
VSS
L24
Power/
Other
Datasheet
Direction
Output
63
Package Mechanical Specifications and Pin Information
Table 15.
Table 15.
Pin
Number
Pin Listing by Pin Number
(Sheet 1 of 17)
Pin Name
Signal
Buffer
Type
Direction
Input
Pin
Number
Pin Listing by Pin Number
(Sheet 2 of 17)
Pin Name
Signal
Buffer
Type
AA9
VCC
Power/Other
AA10
VCC
Power/Other
AA11
VSS
Power/Other
AA12
VCC
Power/Other
AA13
VCC
Power/Other
AA14
VSS
Power/Other
AA15
VCC
Power/Other
AA16
VSS
Power/Other
AA17
VCC
Power/Other
AA18
VCC
Power/Other
AA19
VSS
Power/Other
AA20
VCC
Power/Other
Source
Synch
Direction
A3
SMI#
CMOS
A4
VSS
Power/Other
A5
FERR#
Open Drain
Output
A6
A20M#
CMOS
Input
A7
VCC
Power/Other
A8
VSS
Power/Other
A9
VCC
Power/Other
A10
VCC
Power/Other
A11
VSS
Power/Other
A12
VCC
Power/Other
A13
VCC
Power/Other
A14
VSS
Power/Other
AA21
D[51]#
A15
VCC
Power/Other
AA22
VSS
Power/Other
A16
VSS
Power/Other
A17
VCC
Power/Other
AA23
D[32]#
Source
Synch
Input/
Output
A18
VCC
Power/Other
AA24
D[47]#
A19
VSS
Power/Other
Source
Synch
Input/
Output
A20
VCC
Power/Other
AA25
VSS
Power/Other
A21
BCLK[1]
Bus Clock
Input
AA26
D[43]#
Source
Synch
A22
BCLK[0]
Bus Clock
Input
AB1
VSS
Power/Other
A23
VSS
Power/Other
A24
THERMDA
Power/Other
AB2
A[34]#
Source
Synch
Input/
Output
A25
THERMDC
Power/Other
AB3
TDO
Open Drain
Output
A26
VSS
Power/Other
AB4
VSS
Power/Other
AB5
TMS
CMOS
Input
AB6
TRST#
CMOS
Input
Power/Other
AA1
A[32]#
Source
Synch
AA2
VSS
Power/Other
AB7
VCC
A[35]#
Source
Synch
Input/
Output
AB8
VSS
Power/Other
Input/
Output
AB9
VCC
Power/Other
AB10
VCC
Power/Other
AB11
VSS
Power/Other
AB12
VCC
Power/Other
VSS
Power/Other
VCC
Power/Other
AA3
AA4
A[33]#
Source
Synch
AA5
VSS
Power/Other
AA6
TDI
CMOS
Input/
Output
Input
AA7
VCC
Power/Other
AB13
AA8
VSS
Power/other
AB14
64
Input/
Output
Input/
Output
Datasheet
Package Mechanical Specifications and Pin Information
Table 15.
Pin
Number
Pin Listing by Pin Number
(Sheet 3 of 17)
Pin Name
Signal
Buffer
Type
Direction
AB15
VCC
Power/Other
AB16
VSS
Power/Other
AB17
VCC
Power/Other
AB18
VCC
Power/Other
AB19
VSS
Power/Other
AB20
VCC
Power/Other
AB21
D[52]#
Source
Synch
Input/
Output
AB22
D[50]#
Source
Synch
Input/
Output
AB23
VSS
Power/Other
AB24
D[33]#
Source
Synch
Input/
Output
AB25
D[40]#
Source
Synch
Input/
Output
AB26
VSS
Power/Other
AC1
PREQ#
Common
Clock
Input
AC2
PRDY#
Common
Clock
Output
AC3
VSS
Power/Other
AC4
BPM[3]#
Common
Clock
Input/
Output
AC5
TCK
CMOS
Input
AC6
VSS
Power/Other
AC7
VCC
Power/Other
AC8
VSS
Power/Other
AC9
VCC
Power/Other
AC10
VCC
Power/Other
AC11
VSS
Power/Other
AC12
VCC
Power/Other
AC13
VCC
Power/Other
AC14
VSS
Power/Other
AC15
VCC
Power/Other
AC16
VSS
Power/Other
AC17
VCC
Power/Other
AC18
VCC
Power/Other
AC19
VSS
Power/Other
Datasheet
Table 15.
Pin
Number
Pin Listing by Pin Number
(Sheet 4 of 17)
Pin Name
Signal
Buffer
Type
Direction
AC20
DINV[3]#
Source
Synch
Input/
Output
AC21
VSS
Power/Other
AC22
D[48]#
Source
Synch
Input/
Output
AC23
D[49]#
Source
Synch
Input/
Output
AC24
VSS
Power/Other
AC25
D[53]#
Source
Synch
Input/
Output
AC26
D[46]#
Source
Synch
Input/
Output
AD1
BPM[2]#
Common
Clock
Output
AD2
VSS
Power/Other
AD3
BPM[1]#
Common
Clock
Output
AD4
BPM[0]#
Common
Clock
Input/
Output
AD5
VSS
Power/Other
AD6
VID[0]
CMOS
AD7
VCC
Power/Other
AD8
VSS
Power/Other
Output
AD9
VCC
Power/Other
AD10
VCC
Power/Other
AD11
VSS
Power/Other
AD12
VCC
Power/Other
AD13
VSS
Power/Other
AD14
VCC
Power/Other
AD15
VCC
Power/Other
AD16
VSS
Power/Other
AD17
VCC
Power/Other
AD18
VCC
Power/Other
AD19
VSS
Power/Other
AD20
D[54]#
Source
Synch
Input/
Output
AD21
D[59]#
Source
Synch
Input/
Output
AD22
VSS
Power/Other
65
Package Mechanical Specifications and Pin Information
Table 15.
Pin
Number
Pin Listing by Pin Number
(Sheet 5 of 17)
Pin Name
Signal
Buffer
Type
Direction
DSTBN[3]#
Source
Synch
Input/
Output
AD24
D[57]#
Source
Synch
Input/
Output
AD25
VSS
Power/Other
AD23
AD26
GTLREF
Power/Other
AE1
VSS
Power/Other
Input
AE2
VID[6]
CMOS
Output
AE3
VID[4]
CMOS
Output
AE4
VSS
Power/Other
AE5
VID[2]
CMOS
Output
AE6
PSI#
CMOS
Output
AE7
VSSSENSE
Power/Other
Output
AE8
VSS
Power/Other
AE9
VCC
Power/Other
AE10
VCC
Power/Other
AE11
VSS
Power/Other
Table 15.
Pin
Number
Pin Listing by Pin Number
(Sheet 6 of 17)
Pin Name
Signal
Buffer
Type
Direction
AF3
VSS
Power/Other
AF4
VID[3]
CMOS
Output
AF5
VID[1]
CMOS
Output
AF6
VSS
Power/Other
AF7
VCCSENSE
Power/Other
AF8
VSS
Power/Other
AF9
VCC
Power/Other
AF10
VCC
Power/Other
AF11
VSS
Power/Other
AF12
VCC
Power/Other
AF13
VSS
Power/Other
AF14
VCC
Power/Other
AF15
VCC
Power/Other
AF16
VSS
Power/Other
AF17
VCC
Power/Other
AF18
VCC
Power/Other
AF19
VSS
Power/Other
AF20
VCC
Power/Other
AF21
VSS
Power/Other
AF22
D[62]#
Source
Synch
Input/
Output
AF23
D[56]#
Source
Synch
Input/
Output
AF24
VSS
Power/Other
AF25
D[61]#
Source
Synch
Input/
Output
AE12
VCC
Power/Other
AE13
VCC
Power/Other
AE14
VSS
Power/Other
AE15
VCC
Power/Other
AE16
VSS
Power/Other
AE17
VCC
Power/Other
AE18
VCC
Power/Other
AE19
VSS
Power/Other
AE20
VCC
Power/Other
AE21
D[58]#
Source
Synch
Input/
Output
AF26
D[63]#
Source
Synch
Input/
Output
AE22
D[55]#
Source
Synch
Input/
Output
B1
RESET#
Common
Clock
Input
AE23
VSS
Power/Other
B2
RSVD
Reserved
B3
INIT#
CMOS
Input
B4
LINT1
CMOS
Input
B5
DPSLP#
CMOS
Input
B6
VSS
Power/Other
B7
VCC
Power/Other
B8
VSS
Power/Other
AE24
DSTBP[3]#
Source
Synch
Input/
Output
AE25
D[60]#
Source
Synch
Input/
Output
AE26
VSS
Power/Other
AF1
TEST3
Test
AF2
VID[5]
CMOS
66
Output
Datasheet
Package Mechanical Specifications and Pin Information
Table 15.
Pin
Number
Pin Listing by Pin Number
(Sheet 7 of 17)
Pin Name
Signal
Buffer
Type
Direction
Table 15.
Pin
Number
Pin Listing by Pin Number
(Sheet 8 of 17)
Pin Name
Signal
Buffer
Type
Direction
B9
VCC
Power/Other
C19
VSS
Power/Other
B10
VCC
Power/Other
C20
DBR#
CMOS
Output
B11
VSS
Power/Other
C21
BSEL[2]
CMOS
Output
B12
VCC
Power/Other
C22
VSS
Power/Other
B13
VSS
Power/Other
C23
RSVD
Reserved
B14
VCC
Power/Other
C24
RSVD
Reserved
B15
VCC
Power/Other
C25
VSS
Power/Other
B16
VSS
Power/Other
C26
TEST1
Test
B17
VCC
Power/Other
D1
VSS
Power/Other
B18
VCC
Power/Other
D2
RSVD
Reserved
B19
VSS
Power/Other
D3
RSVD
Reserved
B20
VCC
Power/Other
D4
VSS
Power/Other
B21
VSS
Power/Other
D5
STPCLK#
CMOS
Input
B22
BSEL[0]
CMOS
Output
D6
PWRGOOD
CMOS
Input
B23
BSEL[1]
CMOS
Output
D7
SLP#
CMOS
Input
B24
VSS
Power/Other
D8
VSS
Power/Other
B25
TEST4
Test
D9
VCC
Power/Other
B26
VCCA
Power/Other
D10
VCC
Power/Other
C1
RSVD
Reserved
D11
VSS
Power/Other
C2
VSS
Power/Other
D12
VCC
Power/Other
C3
RSVD
Reserved
D13
VSS
Power/Other
C4
IGNNE#
CMOS
D14
VCC
Power/Other
C5
VSS
Power/Other
D15
VCC
Power/Other
C6
LINT0
CMOS
Input
D16
VSS
Power/Other
C7
THERMTRIP#
Open Drain
Output
D17
VCC
Power/Other
C8
VSS
Power/Other
D18
VCC
Power/Other
C9
VCC
Power/Other
D19
VSS
Power/Other
C10
VCC
Power/Other
D20
IERR#
Open Drain
Output
C11
VSS
Power/Other
PROCHOT#
Open Drain
C12
VCC
Power/Other
Input/
Output
C13
VCC
Power/Other
D22
RSVD
Reserved
D23
VSS
Power/Other
D24
DPWR#
Common
Clock
D25
TEST2
Test
D26
VSS
Power/Other
C14
VSS
Power/Other
C15
VCC
Power/Other
C16
VSS
Power/Other
C17
VCC
Power/Other
C18
VCC
Power/Other
Datasheet
Input
D21
Input
67
Package Mechanical Specifications and Pin Information
Table 15.
Pin
Number
Pin Listing by Pin Number
(Sheet 9 of 17)
Pin Name
Signal
Buffer
Type
Direction
Pin
Number
F4
E1
DBSY#
Common
Clock
Input/
Output
E2
BNR#
Common
Clock
Input/
Output
E3
VSS
Power/Other
E4
HITM#
Common
Clock
Input/
Output
E5
DPRSTP#
CMOS
Input
E6
VSS
Power/Other
E7
VCC
Power/Other
E8
VSS
Power/Other
E9
VCC
Power/Other
E10
VCC
Power/Other
E11
VSS
Power/Other
E12
VCC
Power/Other
E13
VCC
Power/Other
Table 15.
Pin Listing by Pin Number
(Sheet 10 of 17)
Pin Name
RS[1]#
Signal
Buffer
Type
Common
Clock
Direction
Input
F5
VSS
Power/Other
F6
RSVD
Reserved
F7
VCC
Power/Other
F8
VSS
Power/Other
F9
VCC
Power/Other
F10
VCC
Power/Other
F11
VSS
Power/Other
F12
VCC
Power/Other
F13
VSS
Power/Other
F14
VCC
Power/Other
F15
VCC
Power/Other
F16
VSS
Power/Other
F17
VCC
Power/Other
F18
VCC
Power/Other
F19
VSS
Power/Other
F20
VCC
Power/Other
F21
DRDY#
Common
Clock
F22
VSS
Power/Other
F23
D[4]#
Source
Synch
Input/
Output
F24
D[1]#
Source
Synch
Input/
Output
F25
VSS
Power/Other
F26
D[13]#
Source
Synch
G1
VSS
Power/Other
E14
VSS
Power/Other
E15
VCC
Power/Other
E16
VSS
Power/Other
E17
VCC
Power/Other
E18
VCC
Power/Other
E19
VSS
Power/Other
E20
VCC
Power/Other
E21
VSS
Power/Other
E22
D[0]#
Source
Synch
Input/
Output
E23
D[7]#
Source
Synch
Input/
Output
E24
VSS
Power/Other
E25
D[6]#
Source
Synch
Input/
Output
G2
TRDY#
Common
Clock
Input
E26
D[2]#
Source
Synch
Input/
Output
G3
RS[2]#
Common
Clock
Input
F1
BR0#
Common
Clock
Input/
Output
G4
VSS
Power/Other
F2
VSS
Power/Other
G5
BPRI#
Common
Clock
Input
F3
RS[0]#
Common
Clock
G6
HIT#
Common
Clock
Input/
Output
G21
VCCP
Power/Other
68
Input
Input/
Output
Input/
Output
Datasheet
Package Mechanical Specifications and Pin Information
Table 15.
Pin
Number
Pin Listing by Pin Number
(Sheet 11 of 17)
Pin Name
Signal
Buffer
Type
Input/
Output
J24
D[10]#
J25
VSS
Power/Other
J26
DINV[0]#
Source
Synch
K1
VSS
Power/Other
K2
REQ[2]#
Source
Synch
Input/
Output
K3
REQ[0]#
Source
Synch
Input/
Output
K4
VSS
Power/Other
K5
A[6]#
Source
Synch
K6
VCCP
Power/Other
K21
VCCP
Power/Other
K22
D[14]#
Source
Synch
K23
VSS
Power/Other
K24
D[8]#
Source
Synch
Input/
Output
K25
D[17]#
Source
Synch
Input/
Output
K26
VSS
Power/Other
L1
A[13]#
Source
Synch
Input/
Output
L2
ADSTB[0]#
Source
Synch
Input/
Output
L3
VSS
Power/Other
L4
A[4]#
Source
Synch
Input/
Output
L5
REQ[4]#
Source
Synch
Input/
Output
L6
VSS
Power/Other
L21
VSS
Power/Other
L22
D[21]#
Source
Synch
Input/
Output
L23
D[22]#
Source
Synch
Input/
Output
L24
VSS
Power/Other
L25
D[20]#
Source
Synch
Source
Synch
G23
VSS
Power/Other
G24
D[9]#
Source
Synch
Input/
Output
G25
D[5]#
Source
Synch
Input/
Output
G26
VSS
Power/Other
H1
ADS#
Common
Clock
Input/
Output
H2
REQ[1]#
Source
Synch
Input/
Output
H3
VSS
Power/Other
H4
LOCK#
Common
Clock
Input/
Output
H5
DEFER#
Common
Clock
Input
H6
VSS
Power/Other
H21
VSS
Power/Other
H22
D[3]#
Source
Synch
Input/
Output
H23
DSTBN[0]#
Source
Synch
Input/
Output
H24
VSS
Power/Other
H25
D[15]#
Source
Synch
Input/
Output
D[12]#
Source
Synch
Input/
Output
J1
A[9]#
Source
Synch
Input/
Output
J2
VSS
Power/Other
REQ[3]#
Source
Synch
Input/
Output
J4
A[3]#
Source
Synch
Input/
Output
J5
VSS
Power/Other
J6
VCCP
Power/Other
J21
VCCP
Power/Other
J22
VSS
Power/Other
J23
D[11]#
Source
Synch
Datasheet
Signal
Buffer
Type
Pin
Number
DSTBP[0]#
J3
Pin Listing by Pin Number
(Sheet 12 of 17)
Direction
G22
H26
Table 15.
Input/
Output
Pin Name
Source
Synch
Direction
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
69
Package Mechanical Specifications and Pin Information
Table 15.
Pin
Number
Pin Listing by Pin Number
(Sheet 13 of 17)
Pin Name
Signal
Buffer
Type
Direction
D[29]#
Source
Synch
Input/
Output
M1
A[7]#
Source
Synch
Input/
Output
M2
VSS
Power/Other
M3
A[5]#
Source
Synch
L26
M4
RSVD
Reserved
M5
VSS
Power/Other
M6
VCCP
Power/Other
M21
VCCP
Power/Other
M22
VSS
Power/Other
Input/
Output
Table 15.
Pin
Number
Pin Listing by Pin Number
(Sheet 14 of 17)
Pin Name
Signal
Buffer
Type
Direction
P3
VSS
Power/Other
P4
A[14]#
Source
Synch
Input/
Output
P5
A[11]#
Source
Synch
Input/
Output
P6
VSS
Power/Other
P21
VSS
Power/Other
P22
D[25]#
Source
Synch
Input/
Output
P23
D[26]#
Source
Synch
Input/
Output
P24
VSS
Power/Other
Input/
Output
M23
D[23]#
Source
Synch
Input/
Output
P25
D[24]#
Source
Synch
M24
DSTBN[1]#
Source
Synch
Input/
Output
P26
D[18]#
Source
Synch
Input/
Output
M25
VSS
Power/Other
R1
A[16]#
Source
Synch
Input/
Output
M26
DINV[1]#
Source
Synch
R2
VSS
Power/Other
N1
VSS
Power/Other
R3
A[19]#
Source
Synch
Input/
Output
N2
A[8]#
Source
Synch
Input/
Output
R4
A[24]#
Source
Synch
Input/
Output
N3
A[10]#
Source
Synch
Input/
Output
R5
VSS
Power/Other
N4
VSS
Power/Other
R6
VCCP
Power/Other
N5
RSVD
Reserved
R21
VCCP
Power/Other
N6
VCCP
Power/Other
R22
VSS
Power/Other
R23
D[19]#
Source
Synch
Input/
Output
R24
D[28]#
Source
Synch
Input/
Output
R25
VSS
Power/Other
R26
COMP[0]
Power/Other
T1
VSS
Power/Other
T2
RSVD
Reserved
T3
A[26]#
Source
Synch
T4
VSS
Power/Other
Input/
Output
N21
VCCP
Power/Other
N22
D[16]#
Source
Synch
N23
VSS
Power/Other
N24
D[31]#
Source
Synch
Input/
Output
N25
DSTBP[1]#
Source
Synch
Input/
Output
N26
VSS
Power/Other
P1
A[15]#
Source
Synch
Input/
Output
P2
A[12]#
Source
Synch
Input/
Output
70
Input/
Output
Input/
Output
Input/
Output
Datasheet
Package Mechanical Specifications and Pin Information
Table 15.
Pin
Number
Pin Listing by Pin Number
(Sheet 15 of 17)
Pin Name
Signal
Buffer
Type
T5
A[25]#
Source
Synch
T6
VCCP
Power/Other
T21
VCCP
Power/Other
T22
RSVD
Reserved
T23
VSS
Power/Other
Direction
Input/
Output
T24
D[27]#
Source
Synch
Input/
Output
T25
D[30]#
Source
Synch
Input/
Output
T26
VSS
Power/Other
U1
COMP[2]
Power/Other
Input/
Output
U2
A[23]#
Source
Synch
Input/
Output
U3
VSS
Power/Other
U4
A[21]#
Source
Synch
Input/
Output
U5
A[18]#
Source
Synch
Input/
Output
Table 15.
Pin
Number
Pin Listing by Pin Number
(Sheet 16 of 17)
Pin Name
Signal
Buffer
Type
Direction
V22
VSS
Power/Other
V23
DINV[2]#
Source
Synch
Input/
Output
V24
D[34]#
Source
Synch
Input/
Output
V25
VSS
Power/Other
V26
D[35]#
Source
Synch
W1
VSS
Power/Other
W2
A[30]#
Source
Synch
Input/
Output
W3
A[27]#
Source
Synch
Input/
Output
W4
VSS
Power/Other
W5
A[28]#
Source
Synch
Input/
Output
W6
A[20]#
Source
Synch
Input/
Output
W21
VCCP
Power/Other
W22
D[41]#
Source
Synch
W23
VSS
Power/Other
Input/
Output
Input/
Output
U6
VSS
Power/Other
U21
VSS
Power/Other
U22
D[39]#
Source
Synch
Input/
Output
W24
DSTBN[2]#
Source
Synch
Input/
Output
U23
D[37]#
Source
Synch
Input/
Output
W25
D[36]#
Source
Synch
Input/
Output
U24
VSS
Power/Other
W26
VSS
Power/Other
U25
D[38]#
Source
Synch
Input/
Output
Y1
A[31]#
Source
Synch
Input/
Output
U26
COMP[1]
Power/Other
Input/
Output
Y2
A[17]#
Source
Synch
Input/
Output
VSS
Power/Other
COMP[3]
Power/Other
Input/
Output
Y3
V1
Y4
A[29]#
Source
Synch
Input/
Output
Y5
A[22]#
Source
Synch
Input/
Output
Y6
VSS
Power/Other
Y21
VSS
Power/Other
Y22
D[45]#
Source
Synch
V2
VSS
Power/Other
V3
RSVD
Reserved
V4
ADSTB[1]#
Source
Synch
V5
VSS
Power/Other
V6
VCCP
Power/Other
V21
VCCP
Power/Other
Datasheet
Input/
Output
Input/
Output
71
Package Mechanical Specifications and Pin Information
Table 15.
Pin
Number
Pin Listing by Pin Number
(Sheet 17 of 17)
Signal
Buffer
Type
Pin Name
Direction
Y23
D[42]#
Source
Synch
Input/
Output
Y24
VSS
Power/Other
Y25
DSTBP[2]#
Source
Synch
Input/
Output
Y26
D[44]#
Source
Synch
Input/
Output
§
72
Datasheet
Package Mechanical Specifications and Pin Information
4.3
Alphabetical Signals Reference
Table 16.
Signal Description (Sheet 1 of 8)
Name
A[35:3]#
Type
Input/
Output
Description
A[35:3]# (Address) define a 236-byte physical memory address
space. In sub-phase 1 of the address phase, these pins transmit
the address of a transaction. In sub-phase 2, these pins transmit
transaction type information. These signals must connect the
appropriate pins of both agents on the processor FSB. A[35:3]#
are source synchronous signals and are latched into the receiving
buffers by ADSTB[1:0]#. Address signals are used as straps which
are sampled before RESET# is deasserted.
NOTE: When paired with a chipset limited to 32-bit addressing,
A[35:32] should remain unconnected.
A20M#
Input
If A20M# (Address-20 Mask) is asserted, the processor masks
physical address bit 20 (A20#) before looking up a line in any
internal cache and before driving a read/write transaction on the
bus. Asserting A20M# emulates the 8086 processor's address
wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only
supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition
of this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
ADS#
Input/
Output
ADS# (Address Strobe) is asserted to indicate the validity of the
transaction address on the A[35:3]# and REQ[4:0]# pins. All bus
agents observe the ADS# activation to begin parity checking,
protocol checking, address decode, internal snoop, or deferred
reply ID match operations associated with the new transaction.
Address strobes are used to latch A[35:3]# and REQ[4:0]# on
their rising and falling edges. Strobes are associated with signals
as shown below.
ADSTB[1:0]#
BCLK[1:0]
Input/
Output
Input
Signals
Associated Strobe
REQ[4:0]#, A[16:3]#
ADSTB[0]#
A[35:17]#
ADSTB[1]#
The differential pair BCLK (Bus Clock) determines the FSB
frequency. All FSB agents must receive these signals to drive their
outputs and latch their inputs.
All external timing parameters are specified with respect to the
rising edge of BCLK0 crossing VCROSS.
BNR#
Datasheet
Input/
Output
BNR# (Block Next Request) is used to assert a bus stall by any bus
agent who is unable to accept new bus transactions. During a bus
stall, the current bus owner cannot issue any new transactions.
73
Package Mechanical Specifications and Pin Information
Table 16.
Signal Description (Sheet 2 of 8)
Name
BPM[2:1]#
BPM[3,0]#
Type
Output
Input/
Output
Description
BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance
monitor signals. They are outputs from the processor which
indicate the status of breakpoints and programmable counters
used for monitoring processor performance. BPM[3:0]# should
connect the appropriate pins of all processor FSB agents.This
includes debug or performance monitoring tools.
BPRI#
Input
BPRI# (Bus Priority Request) is used to arbitrate for ownership of
the FSB. It must connect the appropriate pins of both FSB agents.
Observing BPRI# active (as asserted by the priority agent) causes
the other agent to stop issuing new requests, unless such requests
are part of an ongoing locked operation. The priority agent keeps
BPRI# asserted until all of its requests are completed, then
releases the bus by deasserting BPRI#.
BR0#
Input/
Output
BR0# is used by the processor to request the bus. The arbitration
is done between processor (Symmetric Agent) and GMCH-M (High
Priority Agent).
BSEL[2:0]
Output
BSEL[2:0] (Bus Select) are used to select the processor input clock
frequency. Table 3 defines the possible combinations of the signals
and the frequency associated with each combination. The required
frequency is determined by the processor, chipset and clock
synthesizer. All agents must operate at the same frequency. The
processor operates at 667-MHz system bus frequency (166-MHz
BCLK[1:0] frequency).
COMP[3:0]
Analog
COMP[3:0] must be terminated on the system board using
precision (1% tolerance) resistors.
D[63:0]# (Data) are the data signals. These signals provide a 64bit data path between the FSB agents, and must connect the
appropriate pins on both agents. The data driver asserts DRDY# to
indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will thus be driven four
times in a common clock period. D[63:0]# are latched off the
falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of
16 data signals correspond to a pair of one DSTBP# and one
DSTBN#. The following table shows the grouping of data signals to
data strobes and DINV#.
Quad-Pumped Signal Groups
D[63:0]#
Input/
Output
Data
Group
DSTBN#/
DSTBP#
DINV#
D[15:0]#
0
0
D[31:16]#
1
1
D[47:32]#
2
2
D[63:48]#
3
3
Furthermore, the DINV# pins determine the polarity of the data
signals. Each group of 16 data signals corresponds to one DINV#
signal. When the DINV# signal is active, the corresponding data
group is inverted and therefore sampled active high.
74
Datasheet
Package Mechanical Specifications and Pin Information
Table 16.
Signal Description (Sheet 3 of 8)
Name
Type
Description
DBR#
Output
DBR# (Data Bus Reset) is used only in processor systems where no
debug port is implemented on the system board. DBR# is used by
a debug port interposer so that an in-target probe can drive system
reset. If a debug port is implemented in the system, DBR# is a no
connect in the system. DBR# is not a processor signal.
DBSY#
Input/
Output
DBSY# (Data Bus Busy) is asserted by the agent responsible for
driving data on the FSB to indicate that the data bus is in use. The
data bus is released after DBSY# is deasserted. This signal must
connect the appropriate pins on both FSB agents.
Input
DEFER# is asserted by an agent to indicate that a transaction
cannot be guaranteed in-order completion. Assertion of DEFER# is
normally the responsibility of the addressed memory or Input/
Output agent. This signal must connect the appropriate pins of
both FSB agents.
DEFER#
DINV[3:0]# (Data Bus Inversion) are source synchronous and
indicate the polarity of the D[63:0]# signals. The DINV[3:0]#
signals are activated when the data on the data bus is inverted.
The bus agent will invert the data bus signals if more than half the
bits, within the covered group, would change level in the next
cycle.
DINV[3:0]# Assignment To Data Bus
DINV[3:0]#
Datasheet
Input/
Output
Bus Signal
Data Bus
Signals
DINV[3]#
D[63:48]#
DINV[2]#
D[47:32]#
DINV[1]#
D[31:16]#
DINV[0]#
D[15:0]#
DPRSTP#
Input
DPRSTP# when asserted on the platform causes the processor to
transition from the Deep Sleep State to the Deeper Sleep state. In
order to return to the Deep Sleep State, DPRSTP# must be
deasserted. DPRSTP# is driven by the ICH7M chipset.
DPSLP#
Input
DPSLP# when asserted on the platform causes the processor to
transition from the Sleep State to the Deep Sleep state. In order to
return to the Sleep State, DPSLP# must be deasserted. DPSLP# is
driven by the ICH7M chipset.
DPWR#
Input
DPWR# is a control signal from the Intel® 945GM/GT/GMS/PM and
940GML Express Chipset family used to reduce power on the
processor data bus input buffers.
DRDY#
Input/
Output
DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-common
clock data transfer, DRDY# may be deasserted to insert idle clocks.
This signal must connect the appropriate pins of both FSB agents.
75
Package Mechanical Specifications and Pin Information
Table 16.
Signal Description (Sheet 4 of 8)
Name
Type
Description
Data strobe used to latch in D[63:0]#.
DSTBN[3:0]#
Input/
Output
Signals
Associated Strobe
D[15:0]#, DINV[0]#
DSTBN[0]#
D[31:16]#, DINV[1]#
DSTBN[1]#
D[47:32]#, DINV[2]#
DSTBN[2]#
D[63:48]#, DINV[3]#
DSTBN[3]#
Data strobe used to latch in D[63:0]#.
DSTBP[3:0]#
FERR#/PBE#
Input/
Output
Output
Signals
Associated Strobe
D[15:0]#, DINV[0]#
DSTBP[0]#
D[31:16]#, DINV[1]#
DSTBP[1]#
D[47:32]#, DINV[2]#
DSTBP[2]#
D[63:48]#, DINV[3]#
DSTBP[3]#
FERR# (Floating-point Error)PBE#(Pending Break Event) is a
multiplexed signal and its meaning is qualified with STPCLK#.
When STPCLK# is not asserted, FERR#/PBE# indicates a floating
point when the processor detects an unmasked floating-point error.
FERR# is similar to the ERROR# signal on the Intel 387
coprocessor, and is included for compatibility with systems using
MS-DOS*-type floating-point error reporting. When STPCLK# is
asserted, an assertion of FERR#/PBE# indicates that the processor
has a pending break event waiting for service. The assertion of
FERR#/PBE# indicates that the processor should be returned to
the Normal state. When FERR#/PBE# is asserted, indicating a
break event, it will remain asserted until STPCLK# is deasserted.
Assertion of PREQ# when STPCLK# is active will also cause an
FERR# break event.
For additional information on the pending break event functionality,
including identification of support of the feature and enable/disable
information, refer to Volumes 3A/3B of the Intel® 64 and IA-32
Intel® Architectures Software Developer's Manual and AP-485
Intel® Processor Identification and the CPUID Instruction
application note.
GTLREF
HIT#
HITM#
76
Input
Input/
Output
Input/
Output
GTLREF determines the signal reference level for AGTL+ input pins.
GTLREF should be set at 2/3 VCCP. GTLREF is used by the AGTL+
receivers to determine if a signal is a logical 0 or logical 1.
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction
snoop operation results. Either FSB agent may assert both HIT#
and HITM# together to indicate that it requires a snoop stall, which
can be continued by reasserting HIT# and HITM# together.
Datasheet
Package Mechanical Specifications and Pin Information
Table 16.
Signal Description (Sheet 5 of 8)
Name
IERR#
IGNNE#
Type
Description
Output
IERR# (Internal Error) is asserted by a processor as the result of
an internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the FSB. This transaction may
optionally be converted to an external error signal (e.g., NMI) by
system core logic. The processor will keep IERR# asserted until the
assertion of RESET#, BINIT#, or INIT#.
Input
IGNNE# (Ignore Numeric Error) is asserted to force the processor
to ignore a numeric error and continue to execute noncontrol
floating-point instructions. If IGNNE# is deasserted, the processor
generates an exception on a noncontrol floating-point instruction if
a previous floating-point instruction caused an error. IGNNE# has
no effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition
of this signal following an Input/Output write instruction, it must be
valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
INIT#
Input
INIT# (Initialization), when asserted, resets integer registers
inside the processor without affecting its internal caches or
floating-point registers. The processor then begins execution at the
power-on Reset vector configured during power-on configuration.
The processor continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal. However, to ensure
recognition of this signal following an Input/Output Write
instruction, it must be valid along with the TRDY# assertion of the
corresponding Input/Output Write bus transaction. INIT# must
connect the appropriate pins of both FSB agents.
If INIT# is sampled active on the active to inactive transition of
RESET#, then the processor executes its Built-in Self-Test (BIST)
LINT[1:0]
Input
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins
of all APIC Bus agents. When the APIC is disabled, the LINT0 signal
becomes INTR, a maskable interrupt request signal, and LINT1
becomes NMI, a nonmaskable interrupt. INTR and NMI are
backward compatible with the signals of those names on the
Pentium processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS
programming of the APIC register space to be used either as NMI/
INTR or LINT[1:0]. Because the APIC is enabled by default after
Reset, operation of these pins as LINT[1:0] is the default
configuration.
Datasheet
LOCK#
Input/
Output
PRDY#
Output
LOCK# indicates to the system that a transaction must occur
atomically. This signal must connect the appropriate pins of both
FSB agents. For a locked sequence of transactions, LOCK# is
asserted from the beginning of the first transaction to the end of
the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of
the FSB, it will wait until it observes LOCK# deasserted. This
enables symmetric agents to retain ownership of the FSB
throughout the bus locked operation and ensure the atomicity of
lock.
Probe Ready signal used by debug tools to determine processor
debug readiness.
77
Package Mechanical Specifications and Pin Information
Table 16.
Signal Description (Sheet 6 of 8)
Name
PREQ#
PROCHOT#
Type
Input
Input/
Output
Description
Probe Request signal used by debug tools to request debug
operation of the processor.
As an output, PROCHOT# (Processor Hot) will go active when the
processor temperature monitoring sensor detects that the
processor has reached its maximum safe operating temperature.
This indicates that the processor Thermal Control Circuit (TCC) has
been activated, if enabled. As an input, assertion of PROCHOT# by
the system will activate the TCC, if enabled. The TCC will remain
active until the system deasserts PROCHOT#.
This signal may require voltage translation on the motherboard.
PSI#
PWRGOOD
Output
Input
Processor Power Status Indicator signal. This signal is asserted
when the processor is in a lower state (Deep Sleep and Deeper
Sleep).
PWRGOOD (Power Good) is a processor input. The processor
requires this signal to be a clean indication that the clocks and
power supplies are stable and within their specifications. ‘Clean’
implies that the signal will remain low (capable of sinking leakage
current), without glitches, from the time that the power supplies
are turned on until they come within specification. The signal must
then transition monotonically to a high state.
The PWRGOOD signal must be supplied to the processor; it is used
to protect internal circuits against voltage sequencing issues. It
should be driven high throughout boundary scan operation.
Input/
Output
REQ[4:0]# (Request Command) must connect the appropriate pins
of both FSB agents. They are asserted by the current bus owner to
define the currently active transaction type. These signals are
source synchronous to ADSTB[0]#.
RESET#
Input
Asserting the RESET# signal resets the processor to a known state
and invalidates its internal caches without writing back any of their
contents. For a power-on Reset, RESET# must stay active for at
least two milliseconds after VCC and BCLK have reached their
proper specifications. On observing active RESET#, both FSB
agents will deassert their outputs within two clocks. All processor
straps must be valid within the specified setup time before RESET#
is deasserted.
RS[2:0]#
Input
RS[2:0]# (Response Status) are driven by the response agent (the
agent responsible for completion of the current transaction), and
must connect the appropriate pins of both FSB agents.
Reserved
/No
Connect
These pins are RESERVED and must be left unconnected on the
board. However, it is recommended that routing channels to these
pins on the board be kept open for possible future use.
REQ[4:0]#
RSVD
78
Datasheet
Package Mechanical Specifications and Pin Information
Table 16.
Signal Description (Sheet 7 of 8)
Name
SLP#
SMI#
Type
Description
Input
SLP# (Sleep), when asserted in Stop-Grant state, causes the
processor to enter the Sleep state. During Sleep state, the
processor stops providing internal clock signals to all units, leaving
only the Phase-Locked Loop (PLL) still operating. Processors in this
state will not recognize snoops or interrupts. The processor will
recognize only assertion of the RESET# signal, deassertion of
SLP#, and removal of the BCLK input while in Sleep state. If SLP#
is deasserted, the processor exits Sleep state and returns to StopGrant state, restarting its internal clock signals to the bus and
processor core units. If DPSLP# is asserted while in the Sleep
state, the processor will exit the Sleep state and transition to the
Deep Sleep state.
Input
SMI# (System Management Interrupt) is asserted asynchronously
by system logic. On accepting a System Management Interrupt,
the processor saves the current state and enter System
Management Mode (SMM). An SMI Acknowledge transaction is
issued, and the processor begins program execution from the SMM
handler.
If SMI# is asserted during the deassertion of RESET# the
processor will tristate its outputs.
STPCLK#
Input
STPCLK# (Stop Clock), when asserted, causes the processor to
enter a low power Stop-Grant state. The processor issues a StopGrant Acknowledge transaction, and stops providing internal clock
signals to all processor core units except the FSB and APIC units.
The processor continues to snoop bus transactions and service
interrupts while in Stop-Grant state. When STPCLK# is deasserted,
the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus
clock; STPCLK# is an asynchronous input.
TCK
Input
TCK (Test Clock) provides the clock input for the processor Test Bus
(also known as the Test Access Port).
TDI
Input
TDI (Test Data In) transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.
TDO
Output
TDO (Test Data Out) transfers serial test data out of the processor.
TDO provides the serial output needed for JTAG specification
support.
TEST1,
TEST2, TEST3,
TEST4
Input
THERMDA
Other
Thermal Diode Anode.
THERMDC
Other
Thermal Diode Cathode.
THERMTRIP#
Datasheet
TEST1 and TEST2 must have a stuffing option of separate pull
down resistors to VSS.
Output
For testing purposes it is recommended, but not required, to route
the TEST3 and TEST4 pins through a ground referenced 55-Ω trace
that ends in a via that is near a GND via and is accessible through
an oscilloscope connection.
The processor protects itself from catastrophic overheating by use
of an internal thermal sensor. This sensor is set well above the
normal operating temperature to ensure that there are no false
trips. The processor will stop all execution when the junction
temperature exceeds approximately 125°C. This is signalled to the
system by the THERMTRIP# (Thermal Trip) pin.
79
Package Mechanical Specifications and Pin Information
Table 16.
Signal Description (Sheet 8 of 8)
Name
Type
Description
TMS (Test Mode Select) is a JTAG specification support signal used
by debug tools.
TMS
Input
TRDY#
Input
TRDY# (Target Ready) is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins of both FSB agents.
TRST#
Input
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.
VCC
Input
Processor core power supply.
VCCA
Input
VCCA provides isolated power for the internal processor core PLL’s.
VCCP
Input
VCC_SENSE
VID[6:0]
VSS_SENSE
Please contact your Intel representative for termination
requirements
Processor I/O Power Supply.
Output
VCC_SENSE together with VSS_SENSE are voltage feedback signals to
Intel® MVP 6 that control the 2.1-mΩ loadline at the processor die.
It should be used to sense or measure power near the silicon with
little noise.
Output
VID[6:0] (Voltage ID) pins are used to support automatic selection
of power supply voltages (VCC). Unlike some previous generations
of processors, these are CMOS signals that are driven by the
processor. The voltage supply for these pins must be valid before
the VR can supply VCC to the processor. Conversely, the VR output
must be disabled until the voltage supply for the VID pins becomes
valid. The VID pins are needed to support the processor voltage
specification variations. See Table 2 for definitions of these pins.
The VR must supply the voltage that is requested by the pins, or
disable itself.
Output
VSS_SENSE together with VCC_SENSE are voltage feedback signals to
Intel MVP 6 that control the 2.1-mΩ loadline at the processor die. It
should be used to sense or measure ground near the silicon with
little noise.
§§
80
Datasheet
Thermal Specifications and Design Considerations
5
Thermal Specifications and
Design Considerations
The processor requires a thermal solution to maintain temperatures within operating
limits as set forth in Section 5.1. Any attempt to operate the processor outside these
operating limits may result in permanent damage to the processor and potentially other
components in the system. As processor technology changes, thermal management
becomes increasingly crucial when building computer systems. Maintaining the proper
thermal environment is key to reliable, long-term system operation. A complete
thermal solution includes both component and system level thermal management
features. Component level thermal solutions include active or passive heatsinks or heat
exchangers attached to the exposed processor die. The solution should make firm
contact to the die while maintaining processor mechanical specifications such as
pressure. A typical system level thermal solution may consist of a processor fan ducted
to a heat exchanger that is thermally-coupled to the processor via a heat pipe or direct
die attachment. A secondary fan or air from the processor fan may also be used to cool
other platform components or to lower the internal ambient temperature within the
system.
To allow for the optimal operation and long-term reliability of Intel processor-based
systems, the system/processor thermal solution should be designed such that the
processor remains within the minimum and maximum junction temperature (Tj)
specifications at the corresponding thermal design power (TDP) value listed in Table 17.
Thermal solutions not designed to provide this level of thermal capability may affect the
long-term reliability of the processor and system.
The maximum junction temperature is defined by an activation of the processor Intel
Thermal Monitor. Refer to Section 5.1.3 for more details. Analysis indicates that real
applications are unlikely to cause the processor to consume the theoretical maximum
power dissipation for sustained time periods. Intel recommends that complete thermal
solution designs target the TDP indicated in Table 17. The Intel Thermal Monitor feature
is designed to help protect the processor in the unlikely event that an application
exceeds the TDP recommendation for a sustained period of time. For more details on
the usage of this feature, refer to Section 5.1.3. In all cases, the Intel Thermal Monitor
feature must be enabled for the processor to remain within specification.
Datasheet
81
Thermal Specifications and Design Considerations
Table 17.
Power Specifications for the Dual-core Standard Voltage Processor
Symbol
Processor
Number
Core Frequency &
Voltage
T7600
T7400
TDP
T7200
T5600
T5500
Symbol
PAH,
PSGNT
Thermal Design
Power
2.33 GHz & HFM VCC
34
2.17 GHz & HFM VCC
34
2.00 GHz & HFM VCC
34
1.83 GHz & HFM VCC
34
1.67 GHz & HFM VCC
34
1.00 GHz & LFM VCC
20
Parameter
Min
Typ
Unit
Notes
1,4,5,7
1,4,5,7
W
1,4,5,7
1,4,6,7
1,4,6,7
Max
Unit
at HFM VCC
13.0
W
2, 8
at LFM VCC
7.3
W
2, 8
W
2, 9
Auto Halt, Stop Grant Power
Sleep Power
PSLP
at HFM VCC
12.4
at LFM VCC
7.0
Deep Sleep Power
PDSLP
at HFM VCC
7.6
at LFM VCC
4.5
PDPRSLP
Deeper Sleep Power
2.0
W
2, 9
PDC4
Intel® Enhanced Deeper Sleep Power
1.2
W
2, 9
TJ
Junction Temperature
100
°C
3, 4
0
NOTES:
1.
The TDP specification should be used to design the processor thermal solution. The TDP is
not the maximum theoretical power the processor can generate.
2.
Not 100% tested. These power specifications are determined by characterization of the
processor currents at higher temperatures and extrapolating the values for the
temperature indicated.
3.
As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal
Monitor’s automatic mode is used to indicate that the maximum TJ has been reached.
Refer to Section 5.1 for more details.
4.
The Intel Thermal Monitor automatic mode must be enabled for the processor to operate
within specifications.
5.
T7600, T7400, T7200 processors feature 4-MB cache.
6.
T5600, T5500 processors feature 2-MB cache.
7.
At Tj of 100°C.
8.
At Tj of 50°C.
9.
At Tj of 35°C.
82
Datasheet
Thermal Specifications and Design Considerations
Table 18.
Power Specifications for the Dual-core Low Voltage Processor
Symbol
TDP
Processor
Number
PSGNT
Thermal Design
Power
L7400
1.50 GHz & HFM VCC
L7200
1.33 GHz & HFM VCC
17
1.00 GHz & LFM VCC
15.1
Symbol
PAH,
Core Frequency &
Voltage
Parameter
Unit
Notes
W
1, 4, 7
17
Min
Typ
Max
Unit
at HFM VCC
5.2
W
2, 8
at LFM VCC
4.6
W
2, 8
W
2, 9
Auto Halt, Stop Grant Power
Sleep Power
PSLP
at HFM VCC
4.9
at LFM VCC
4.4
Deep Sleep Power
PDSLP
at HFM VCC
2.9
at LFM VCC
2.8
PDPRSLP
Deeper Sleep Power
1.5
W
2, 9
PDC4
Intel Enhanced Deeper Sleep Power
0.9
W
2, 9
TJ
Junction Temperature
100
°C
3, 4
0
NOTES:
1.
The TDP specification should be used to design the processor thermal solution. The TDP is
not the maximum theoretical power the processor can generate.
2.
Not 100% tested. These power specifications are determined by characterization of the
processor currents at higher temperatures and extrapolating the values for the
temperature indicated.
3.
As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal
Monitor’s automatic mode is used to indicate that the maximum TJ has been reached.
Refer to Section 5.1 for more details.
4.
The Intel Thermal Monitor automatic mode must be enabled for the processor to operate
within specifications.
5.
4-M cache.
6.
2-M cache.
7.
At Tj of 100°C.
8.
At Tj of 50°C.
9.
At Tj of 35°C.
Datasheet
83
Thermal Specifications and Design Considerations
Table 19.
Power Specifications for the Single and Dual-core Ultra Low Voltage Processor
Symbol
Processor
Number
U7600
TDP
U7500
U2200
U2100
Symbol
PAH,
PSGNT
Core Frequency &
Voltage
Thermal Design Power
5.5
1.20 GHz & HFM VCC
5.5
1.06 GHz & HFM VCC
4.6-SC
Min
1.7-SC
at LFM VCC
2.5-DC
1.6- SC
W
2, 8
W
2, 9
W
2, 9
W
2, 9
°C
3, 4
1.5-DC
1.3-DC
0.8-SC
at LFM VCC
Junction Temperature
2, 8
1.3-SC
at HFM VCC
TJ
W
3.0-DC
Deep Sleep Power
Intel® Enhanced Deeper Sleep Power
Unit
1.4-SC
at HFM VCC
PDC4
Max
2.6-DC
at HFM VCC
Deeper Sleep Power
Typ
3.1- DC
Auto Halt, Stop Grant Power
PDPRSLP
1, 4, 7
9.2- DC
0.80 GHz & LFM VCC
at LFM VCC
PDSLP
W
10
1.06 GHz & HFM VCC
Sleep Power
PSLP
Notes
10
1.20 GHz & HFM VCC
Parameter
Unit
0.7-SC
1.0-DC
0.6-SC
0.7-DC
0.4-SC
0
100
NOTES:
1.
The TDP specification should be used to design the processor thermal solution. The TDP is
not the maximum theoretical power the processor can generate.
2.
Not 100% tested. These power specifications are determined by characterization of the
processor currents at higher temperatures and extrapolating the values for the
temperature indicated.
3.
As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal
Monitor’s automatic mode is used to indicate that the maximum TJ has been reached.
Refer to Section 5.1 for more details.
4.
The Intel Thermal Monitor automatic mode must be enabled for the processor to operate
within specifications.
5.
4-M cache.
6.
2-M cache.
7.
At Tj of 100°C.
8.
At Tj of 50°C.
9.
At Tj of 35°C.
84
Datasheet
Thermal Specifications and Design Considerations
5.1
Thermal Specifications
The processor incorporates three methods of monitoring die temperature: the digital
thermal sensor, Intel Thermal Monitor and the thermal “diode.” The Intel Thermal
Monitor (detailed in Section 5.1.3) must be used to determine when the maximum
specified processor junction temperature has been reached.
5.1.1
Thermal Diode
The processor incorporates an on-die PNP transistor whose base emitter junction is
used as a thermal diode, with its collector shorted to Ground. The thermal diode can be
read by an off-die analog/digital converter (a thermal sensor) located on the
motherboard or a stand-alone measurement kit. The thermal diode may be used to
monitor the die temperature of the processor for thermal management or
instrumentation purposes but is not a reliable indication that the maximum operating
temperature of the processor has been reached. When using the thermal diode, a
temperature offset value must be read from a processor Model Specific Register (MSR)
and applied. See Section 5.1.2 for more details. Please see Section 5.1.3 for thermal
diode usage recommendation when the PROCHOT# signal is not asserted.
Note:
The reading of the external thermal sensor (on the motherboard) connected to the
processor thermal diode signals will not necessarily reflect the temperature of the
hottest location on the die. This is due to inaccuracies in the external thermal sensor,
on-die temperature gradients between the location of the thermal diode and the hottest
location on the die, and time based variations in the die temperature measurement.
Time based variations can occur when the sampling rate of the thermal diode (by the
thermal sensor) is slower than the rate at which the TJ temperature can change.
Offset between the thermal diode based temperature reading and the Intel Thermal
Monitor reading may be characterized using the Intel Thermal Monitor’s Automatic
mode activation of the thermal control circuit. This temperature offset must be taken
into account when using the processor thermal diode to implement power management
events. This offset is different than the diode Toffset value programmed into the
processor MSR.
Table 20 through Table 23 provides the diode interface and specifications. Two different
sets of diode parameters are listed in Table 22 and Table 23. The diode model
parameters apply to the traditional thermal sensors that use the diode equation to
determine the processor temperature. Transistor model parameters have been added
to support thermal sensors that use the transistor equation method. The Transistor
model may provide more accurate temperature measurements when the diode ideality
factor is closer to the maximum or minimum limits. Please contact your external sensor
supplier for their recommendation. The thermal diode is separate from the Intel
Thermal Monitor’s thermal sensor and cannot be used to predict the behavior of the
Intel Thermal Monitor.
5.1.2
Thermal Diode Offset
In order to improve the accuracy of the diode based temperature measurements, a
temperature offset value (specified as Toffset) will be programmed in the processor
Model Specific Register (MSR) which will contain thermal diode characterization data.
During manufacturing each processor thermal diode will be evaluated for its behavior
relative to the theoretical diode. Using the equation above, the temperature error
created by the difference ntrim and the actual ideality of the particular processor will be
calculated.
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If the ntrim value used to calculate the Toffset differs from the ntrim value used to in a
temperature sensing device, the Terror(nf) may not be accurate. If desired, the Toffset
can be adjusted by calculating nactual and then recalculating the offset using the ntrim as
defined in the temperature sensor manufacturer’s datasheet.
The ntrim used to calculate the Diode Correction Toffset are listed in Table 20.
Table 20.
Table 21.
Table 22.
Thermal Diode ntrim and Diode Correction Toffset
Symbol
Parameter
Unit
ntrim
Diode Ideality used to calculate Toffset
1.01
Thermal Diode Interface
Signal Name
Pin/Ball Number
Signal Description
THERMDA
A24
Thermal diode anode
THERMDC
A25
Thermal diode cathode
Thermal Diode Parameters using Diode Mode
Symbol
Parameter
Min
Typ
Max
Unit
Notes
IFW
Forward Bias Current
5
N/A
200
µA
1
n
Diode Ideality Factor
1.000
1.009
1.050
N/A
2, 3, 4
RTT
Series Resistance
2.79
4.52
6.24
Ω
2, 3, 5
NOTES:
1.
Intel does not support or recommend operation of the thermal diode under reverse bias.
Intel does not support or recommend operation of the thermal diode when the processor
power supplies are not within their specified tolerance range.
2.
Characterized across a temperature range of 50-100 °C.
3.
Not 100% tested. Specified by design characterization.
4.
The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by
the diode equation:
IFW=Is *(e(qVD/nkT) -1),
where IS = saturation current, q = electronic charge, VD = voltage across the diode, k =
Boltzmann Constant, and T = absolute temperature (Kelvin).
5.
The series resistance, RTT, is provided to allow for a more accurate measurement of the
diode junction temperature. RTT as defined includes the pins of the processor but does not
include any socket resistance or board trace resistance between the socket and the
external remote diode thermal sensor. RTT can be used by remote diode thermal sensors
with automatic series resistance cancellation to calibrate out this error term. Another
application is that a temperature offset can be manually calculated and programmed into
an offset register in the remote diode thermal sensors as exemplified by the equation:
Terror = [RTT*(N-1)*IFWmin]/[(no/q)*ln N]
where Terror = sensor temperature error, N = sensor current ratio, k = Boltzmann
Constant, and q = electronic charge.
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Table 23.
Thermal Diode Parameters Using Transistor Model
Symbol
Parameter
IFW
Forward Bias Current
IE
Emitter Current
nQ
Transistor Ideality
Min
5
5
0.997
Beta
RTT
Typ
1.001
0.3
Series Resistance
2.79
4.52
Max
Unit
Notes
200
µA
1, 2
200
µA
1
1.005
3, 4, 5
0.760
3, 4
6.24
Ω
3, 6
NOTES:
1.
Intel does not support or recommend operation of the thermal diode under reverse bias.
2.
Same as IFW in Table 22
3.
Characterized across a temperature range of 50-100 °C.
4.
Not 100% tested. Specified by design characterization.
5.
The ideality factor, nQ, represents the deviation from ideal diode behavior as exemplified
by the equation for the collector current:
IC=Is *(e(qVBE/nQkT) -1)
where IS = saturation current, q = electronic charge, VBE = voltage across the transistor
base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute
temperature (Kelvin).
6.
The series resistance, RTT, provided in the Diode Model Table (Table 22) can be used for
more accurate readings as needed.
When calculating a temperature based on the thermal diode measurements, a number
of parameters must be either measured or assumed. Most devices measure the diode
ideality and assume a series resistance and ideality trim value, although are capable of
also measuring the series resistance. Calculating the temperature is then accomplished
using the equations listed under Table 22. In most sensing devices, an expected value
for the diode ideality is designed-in to the temperature calculation equation. If the
designer of the temperature sensing device assumes a perfect diode, the ideality value
(also called ntrim) will be 1.000. Given that most diodes are not perfect, the designers
usually select an ntrim value that more closely matches the behavior of the diodes in
the processor. If the processor diode ideality deviates from that of the ntrim, each
calculated temperature will be offset by a fixed amount. This temperature offset can be
calculated with the equation:
Terror(nf) = Tmeasured * (1 - nactual/ntrim)
Where Terror(nf) is the offset in degrees C, Tmeasured is in Kelvin, nactual is the measured
ideality of the diode, and ntrim is the diode ideality assumed by the temperature
sensing device.
5.1.3
Intel® Thermal Monitor
The Intel Thermal Monitor helps control the processor temperature by activating the
TCC (Thermal Control Circuit) when the processor silicon reaches its maximum
operating temperature. The temperature at which the Intel Thermal Monitor activates
the TCC is not user configurable. Bus traffic is snooped in the normal manner and
interrupt requests are latched (and serviced during the time that the clocks are on)
while the TCC is active.
With a properly designed and characterized thermal solution, it is anticipated that the
TCC would only be activated for very short periods of time when running the most
power intensive applications. The processor performance impact due to these brief
periods of TCC activation is expected to be minor and hence not detectable. An under-
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designed thermal solution that is not able to prevent excessive activation of the TCC in
the anticipated ambient environment may cause a noticeable performance loss and
may affect the long-term reliability of the processor. In addition, a thermal solution that
is significantly under designed may not be capable of cooling the processor even when
the TCC is active continuously.
The Intel Thermal Monitor controls the processor temperature by modulating (starting
and stopping) the processor core clocks or by initiating an Enhanced Intel SpeedStep
Technology transition when the processor silicon reaches its maximum operating
temperature. The Intel Thermal Monitor uses two modes to activate the TCC:
Automatic mode and on-demand mode. If both modes are activated, automatic mode
takes precedence.
Note:
The Intel Thermal Monitor automatic mode must be enabled through BIOS for the
processor to be operating within specifications.
There are two automatic modes called Intel Thermal Monitor 1 and Intel Thermal
Monitor 2. These modes are selected by writing values to the MSRs of the processor.
After automatic mode is enabled, the TCC will activate only when the internal die
temperature reaches the maximum allowed value for operation.
Likewise, when Intel Thermal Monitor 2 is enabled and a high temperature situation
exists, the processor will perform an Enhanced Intel SpeedStep Technology transition
to a lower operating point. When the processor temperature drops below the critical
level, the processor will make an Enhanced Intel SpeedStep Technology transition to
the last requested operating point.
Intel Thermal Monitor 1 and Intel Thermal Monitor 2 can co-exist within the processor.
If both Intel Thermal Monitor 1 and Intel Thermal Monitor 2 bits are enabled in the
auto-throttle MSR, Intel Thermal Monitor 2 will take precedence over Intel Thermal
Monitor 1. However, if Intel Thermal Monitor 2 is not sufficient to cool the processor
below the maximum operating temperature then Intel Thermal Monitor 1 will also
activate to help cool down the processor. Intel recommends Intel Thermal Monitor 1
and Intel Thermal Monitor 2 be enabled on the processors.
If a processor load based Enhanced Intel SpeedStep Technology transition (through
MSR write) is initiated when an Intel Thermal Monitor 2 period is active, there are two
possible results:
1. If the processor load based Enhanced Intel SpeedStep Technology transition target
frequency is higher than the Intel Thermal Monitor 2 transition based target
frequency, the processor load-based transition will be deferred until the Intel
Thermal Monitor 2 event has been completed.
2. If the processor load-based Enhanced Intel SpeedStep Technology transition target
frequency is lower than the Intel Thermal Monitor 2 transition based target
frequency, the processor will transition to the processor load-based Enhanced Intel
SpeedStep Technology target frequency point.
When Intel Thermal Monitor 1 is enabled while a high temperature situation exists, the
clocks will be modulated by alternately turning the clocks off and on at a 50% duty
cycle. Cycle times are processor speed dependent and will decrease linearly as
processor core frequencies increase. Once the temperature has returned to a noncritical level, modulation ceases and TCC goes inactive. A small amount of hysteresis
has been included to prevent rapid active/inactive transitions of the TCC when the
processor temperature is near the trip point. The duty cycle is factory configured and
cannot be modified. Also, automatic mode does not require any additional hardware,
software drivers, or interrupt handling routines. Processor performance will be
decreased by the same amount as the duty cycle when the TCC is active.
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The TCC may also be activated via on-demand mode. If bit 4 of the ACPI Intel Thermal
Monitor control register is written to a 1, the TCC will be activated immediately
independent of the processor temperature. When using on-demand mode to activate
the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the
same ACPI Intel Thermal Monitor control register. In automatic mode, the duty cycle is
fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be
programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments.
On-demand mode may be used at the same time automatic mode is enabled, however,
if the system tries to enable the TCC via on-demand mode at the same time automatic
mode is enabled and a high temperature condition exists, automatic mode will take
precedence.
An external signal, PROCHOT# (processor hot) is asserted when the processor detects
that its temperature is above the thermal trip point. Bus snooping and interrupt
latching are also active while the TCC is active.
Besides the thermal sensor and thermal control circuit, the Intel Thermal Monitor also
includes one ACPI register, one performance counter register, three MSR, and one I/O
pin (PROCHOT#). All are available to monitor and control the state of the Intel Thermal
Monitor feature. The Intel Thermal Monitor can be configured to generate an interrupt
upon the assertion or deassertion of PROCHOT#.
Note:
PROCHOT# will not be asserted when the processor is in the Stop Grant, Sleep, Deep
Sleep, and Deeper Sleep low power states, hence the thermal diode reading must be
used as a safeguard to maintain the processor junction temperature within maximum
specification. If the platform thermal solution is not able to maintain the processor
junction temperature within the maximum specification, the system must initiate an
orderly shutdown to prevent damage. If the processor enters one of the above low
power states with PROCHOT# already asserted, PROCHOT# will remain asserted until
the processor exits the low power state and the processor junction temperature drops
below the thermal trip point.
If Intel Thermal Monitor automatic mode is disabled, the processor will be operating out
of specification. Regardless of enabling the automatic or on-demand modes, in the
event of a catastrophic cooling failure, the processor will automatically shut down when
the silicon has reached a temperature of approximately 125°C. At this point the
THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor
activity and does not generate any bus cycles. When THERMTRIP# is asserted, the
processor core voltage must be shut down within the time specified in Chapter 3.
5.1.4
Digital Thermal Sensor
The processor also contains an on-die digital thermal sensor that can be read via a MSR
(no I/O interface). In a dual-core implementation of the processor, each core will have
a unique digital thermal sensor whose temperature is accessible via processor MSR.
The digital thermal sensor is the preferred method of reading the processor die
temperature since it can be located much closer to the hottest portions of the die and
can thus more accurately track the die temperature and potential activation of
processor core clock modulation via the Intel Thermal Monitor. The digital thermal
sensor is only valid while the processor is in the normal operating state (C0 state).
Unlike traditional thermal devices, the Digital Thermal sensor will output a temperature
relative to the maximum supported operating temperature of the processor (TJ,max). It
is the responsibility of software to convert the relative temperature to an absolute
temperature. The temperature returned by the digital thermal sensor will always be at
or below TJ,max. Over temperature conditions are detectable via an Out Of Spec status
bit. This bit is also part of the Digital Thermal sensor MSR. When this bit is set, the
processor is operating out of specification and immediate shutdown of the system
should occur. The processor operation and code execution is not guaranteed once the
activation of the Out of Spec status bit is set.
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The Digital Thermal Sensor (DTS) relative temperature readout corresponds to the
Intel Thermal Monitor (Intel Thermal Monitor 1/Intel Thermal Monitor 2) trigger point.
When the DTS indicates maximum processor core temperature has been reached the
Intel Thermal Monitor 1 or Intel Thermal Monitor 2 hardware thermal control
mechanism will activate. The DTS and Intel Thermal Monitor 1/Intel Thermal Monitor 2
temperature may not correspond to the thermal diode reading since the thermal diode
is located in a separate portion of the die and thermal gradient between the individual
core DTS. Additionally, the thermal gradient from DTS to thermal diode can vary
substantially due to changes in processor power, mechanical and thermal attach and
software application. The system designer is required to use the DTS to guarantee
proper operation of the processor within its temperature operating specifications.
Changes to the temperature can be detected via two programmable thresholds located
in the processor MSRs. These thresholds have the capability of generating interrupts
via the core's local APIC. Refer to the Intel® 64 and IA-32 Intel® Architectures
Software Developer's Manual for specific register and programming details.
5.1.5
Out of Specification Detection
Overheat detection is performed by monitoring the processor temperature and
temperature gradient. This feature is intended for graceful shut down before the
THERMTRIP# is activated. If the processor’s Intel Thermal Monitor 1 or Intel Thermal
Monitor 2 are triggered and the temperature remains high, an “Out Of Spec” status and
sticky bit are latched in the status MSR register and generates thermal interrupt.
5.1.6
PROCHOT# Signal Pin
An external signal, PROCHOT# (processor hot), is asserted when the processor die
temperature has reached its maximum operating temperature. If the Intel Thermal
Monitor 1 or Intel Thermal Monitor 2 is enabled (note that the Intel Thermal Monitor 1
or Intel Thermal Monitor 2 must be enabled for the processor to be operating within
specification), the TCC will be active when PROCHOT# is asserted. The processor can
be configured to generate an interrupt upon the assertion or deassertion of
PROCHOT#.
The processor implements a bi-directional PROCHOT# capability to allow system
designs to protect various components from over-heating situations. The PROCHOT#
signal is bi-directional in that it can either signal when the processor has reached its
maximum operating temperature or be driven from an external source to activate the
TCC. The ability to activate the TCC via PROCHOT# can provide a means for thermal
protection of system components.
In a dual-core implementation, only a single PROCHOT# pin exists at a package level.
When either core's thermal sensor trips, PROCHOT# signal will be driven by the
processor package. If only Intel Thermal Monitor 1 is enabled, PROCHOT# will be
asserted and only the core that is above TCC temperature trip point will have its core
clocks modulated. If Intel Thermal Monitor 2 is enabled, then regardless of which
core(s) are above TCC temperature trip point, both cores will enter the lowest
programmed Intel Thermal Monitor 2 performance state. It is important to note that
Intel recommends both Intel Thermal Monitor 1 and Intel Thermal Monitor 2 to be
enabled.
When PROCHOT# is driven by an external agent, if only Intel Thermal Monitor 1 is
enabled on both cores, then both processor cores will have their core clocks modulated.
If Intel Thermal Monitor 2 is enabled on both cores, then both processor core will enter
the lowest programmed Intel Thermal Monitor 2 performance state.
One application is the thermal protection of voltage regulators (VR). System designers
can create a circuit to monitor the VR temperature and activate the TCC when the
temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low) and
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activating the TCC, the VR can cool down as a result of reduced processor power
consumption. Bi-directional PROCHOT# can allow VR thermal designs to target
maximum sustained current instead of maximum current. Systems should still provide
proper cooling for the VR, and rely on bi-directional PROCHOT# only as a backup in
case of system cooling failure. The system thermal design should allow the power
delivery circuitry to operate within its temperature specification even while the
processor is operating at its TDP. With a properly designed and characterized thermal
solution, it is anticipated that bi-directional PROCHOT# would only be asserted for very
short periods of time when running the most power intensive applications. An underdesigned thermal solution that is not able to prevent excessive assertion of PROCHOT#
in the anticipated ambient environment may cause a noticeable performance loss.
§§
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