Data Sheet PD60232 revC
IR22381QPBF/IR21381Q(PbF)
3-PHASE AC MOTOR CONTROLLER IC
Features
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Product Summary
Floating channel up to +600V or +1200V
“soft” over-current shutdown turns off desaturated output
Integrated desaturation circuit
Active biasing on sensing desaturation input
Two stage turn on output for di/dt control
Integrated brake IGBT driver with protection
Voltage feedback sensing function
Separate pull-up/pull-down output drive pins
Matched delay outputs
Under voltage lockout with hysteresis band
Programmable deadtime
Hard shutdown function
VOFFSET (max)
IO +/- (min.)
VOUT
Brake (IO +/- min.)
Deadtime Asymmetry
Skew (max.)
Deadtime (typ. with
RDT=39KΩ)
DESAT Blanking time (typ.)
Description
The IR22381Q and IR21381Q are high voltage, 3-phase IGBT
driver best suited for AC motor drive applications. Integrated
desaturation logic provides all mode of overcurrent protection,
including ground fault protection. The sensing desaturation input is
provided by active bias stage to reject noise. Soft shutdown is
predominantly initiated in the event of overcurrent followed by turnoff of all six outputs. A shutdown input is provided for a customized
shutdown function. The DT pin allows external resistor to program
the deadtime. Output drivers have separate turn on/off pins with
two stage turn-on output to achieve the desired di/dt switching level
of IGBT. Voltage feedback provides accurate volt x second
measurement.
DESAT filter time (typ.)
Active bias on Desat input
pin
DSH, DSL input voltage
threshold (typ.)
Soft shutdown duration
time (typ.)
Voltage feedback matching
delay time (max.)
600V or 1200V
220mA / 460mA
12.5V-20V
40mA/80mA
125nsec
1µsec
4.5µsec
3.0µsec
90Ω
8.0V
6.0µsec
400nsec
Package
64-Lead MQFP w/o 13 leads
Typical Connection
To controller
DC bus
LIN1,2,3
HIN1,2,3
FAULT
BRIN
SD
3
VFH1,2,3
VFL1,2,3
DSB
BR
(Refer to Lead
Assignments for
correct pin
configuration. This
diagram shows
electrical
connections only)
DT
VSS
1
VB1,2,3
DSH1,2,3
IR22381QPBF
VCC
3
HOP1,2,3
HOQ1,2,3
HON1,2,3
VS1,2,3
DSL1,2,3
LOP1,2,3
LOQ1,2,3
LON1,2,3
COM
U
V
W
To motor
15V
IR22381QPBF/IR21381Q(PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to VSS, all currents are defined positive into any lead. The thermal
resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
VS
VB
VHO
VCC
COM
VLO
VIN
VFLT
VF
VDSH
VDSL
VBR
dVs/dt
PD
RthJA
TJ
TS
TL
Definition
Min.
Max.
Units
High side offset voltage
VB 1,2,3 - 25
VB 1,2,3 + 0.3
(IR22381)
-0.3
1225
High side floating supply voltage
(IR21381)
-0.3
625
High side floating output voltage (HOP, HON, HOQ)
VS1,2,3 - 0.3
VB 1,2,3 + 0.3
Low side and logic fixed supply voltage
-0.3
25
Power ground
VCC - 25
VCC + 0.3
Low side output voltage (LOP, LON, LOQ)
VCOM -0.3
VCC + 0.3
V
Logic input voltage (HIN/N, LIN, BRIN/N, SD)
-0.3
VCC + 0.3 or VSS +15
Which ever is lower
FAULT/N output voltage
-0.3
VCC + 0.3
Feedback output voltage
-0.3
VCC + 0.3
High side desat/feedback input voltage
VB 1,2,3 - 25
VB 1,2,3 + 0.3
Low side desat/feedback input voltage
VCC - 25
VCC + 0.3
Brake output voltage
VCOM -0.3
VCC + 0.3
Allowable offset voltage slew rate
—
50
V/ns
Package power dissipation @ TA ≤ +25°C
—
2.0
W
Thermal resistance, junction to ambient
—
60
°C/W
Junction temperature
—
125
Storage temperature
°C
-55
150
Lead temperature (soldering, 10 seconds)
—
300
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. All voltage parameters are
absolute voltages referenced to VSS. The VS offset rating is tested with all supplies biased at 15V differential.
Symbol
Definition
Min.
VB 1,2,3
VS1,2,3
High side floating supply voltage (Note 1)
High side floating supply offset voltage
VHO 1,2,3
VLO1,2,3
VIN
VCC
COM
VFLT
VF
VDSH
VDSL
VBR
TA
High side (HOP/HOQ/HON) output voltage
Low side (LOP/LOQ/LON) output voltage
Logic input voltage (HIN/N, LIN, BRIN/N SD)
Low side supply voltage (Note 1)
Power ground
FAULT/N output voltage
Feedback output voltage
High side desat/feedback input voltage
Low side desat/feedback input voltage
BR output voltage
Ambient temperature
VS1,2,3+12.5
(IR21381) Note 2
(IR22381) Note 2
VS1,2,3
VCOM
0
12.5
-5
0
0
VB 1,2,3 - 20
VCC - 20
VCOM
-40
Max.
Units
VS1,2,3 + 20
600
1200
VS1,2,3 + VB
VCC
VSS + 5
20
+5
VCC
VCC
VB 1,2,3
VCC
VCC
115
V
°C
Note 1: While internal circuitry is operational below the indicated supply voltages, the UV lockout disables the output drivers if the UV
thresholds are not reached.
Note 2: Logic operational for VS from VSS-5V to VSS+600V (IR21381) or 1200V (IR22381). Logic state held for VS from VSS-5V to VSSVBS. (Please refer to the Design Tip DT97-3 for more details).
2
IR22381QPBF/IR21381Q(PbF)
Static Electrical Characteristics
VBIAS (VCC, VBS1,2,3 ) = 15V and TA = 25 °C unless otherwise specified.
I/O diagrams don’t show ESD protection circuits.
Pin: VCC, VSS, VB, VS
Symbol
VCCUV+
VCCUVVCCUVH
VBSUV+
VBSUVVBSUVH
ILK
Definition
Min Typ Max Units
Vcc1 supply undervoltage positive going threshold
Vcc1 supply undervoltage negative going threshold
Vcc1 supply undervoltage lockout hysteresis
VBS supply undervoltage positive going threshold
VBS supply undervoltage negative going threshold
VBS supply undervoltage lockout hysteresis
(IR21381Q)
Offset supply leakage current
(IR22381Q)
10.3
9.5
10.3
9.5
-
11.2
10.2
1.0
11.2
10.2
1.0
-
12.5
11.3
11.9
10.9
50
-
-
50
IQBS
Quiescent VBS supply current
-
150
300
IQCC
Quiescent Vcc supply current
-
3
6
Test
Conditions
V
VB1,2,3 =VS1,2,3 =
600V
VB1,2,3 =VS1,2,3 =
µA
1200V
VLIN=0V,VHIN=5V,
DSH1,2,3= VS1,2,3
mA VLIN=0V,VHIN=5V
DT=1µsec
Comparator
VCC/VB
UV
VCCUV/VBSUV
VSS/VS
Figure 1: Undervoltage diagram
Pin: HIN/N, LIN, BRIN/N, SD
The VIN, VTH and IIN parameters are referenced to VSS and are applicable to all six channels (HOP/HOQ/ HON1,2,3
and LOP/LOQ/LON1,2,3).
Symbol
VIH
VIL
Vt+
Vt∆VT
IIN+
IIN-
Definition
Min Typ Max Units
Logic "0" input voltage
(HIN/N, LIN, BRIN/N, SD)(OUT=LO)
Logic "1" input voltage
(HIN/N, LIN, BRIN/N, SD)(OUT=HI)
Logic input positive going threshold
(HIN/N, LIN, BRIN/N, SD)
Logic input negative going threshold
(HIN/N, LIN, BRIN/N, SD)
Logic input hysteresis(HIN/N, LIN, BRIN/N, SD)
2.0
-
-
-
-
0.8
1.2
1.6
2.0
0.8
1.2
1.6
-
0.4
-
Logic "1" input bias current (HIN/N, BRIN/N)
Logic "1" input bias current (LIN, SD)
Logic "0" input bias current (HIN/N, BRIN/N)
Logic "0" input bias current (LIN, SD)
-2
-2
85
85
-
0
140
140
0
3
Test
Conditions
V
VCC = 12.5V to
20V
µA
VIN = 0V
VIN = 5V
VIN = 5V
VIN = 0V
IR22381QPBF/IR21381Q(PbF)
Figure 2: HIN/N, LIN and BRIN/N diagram
Pin: FAULT/N, VFH, VFL
VOLVF is referenced to Vss
Symbol
Definition
VOLVF
VFH or VFL low level output voltage
RON,VF
RON,FLT
Min Typ Max Units Test Conditions
0.8
V
IVF = 10mA
VFH or VFL output on resistance
FAULT/N low on resistance
-
60
60
-
Ω
______
FAULT /
VFL/VFH
RON
Internal signal
VSS
Figure 3: FAULT/N, VFH, VFL diagram
Pin: DSL, DSH, DSB
VDESAT and IDESAT parameters are referenced to COM and VS1,2,3
Symbol
Definition
VDESAT+
High DSH1,2,3 and DSL1,2,3 and DSB
input threshold voltage
VDESATLow DSH1,2,3 and DSL1,2,3 or DSB
input threshold voltage
DS input voltage hysteresis
VDSTH
High
DSH, DSL, DSB input bias current
IDS+
Low DSH, DSL input bias current
IDSLow DSB input bias current
IDSBRIDSB
DSH or DSL input bias current
Min Typ Max Units Test Conditions
8.0
-
7.0
-
V
-
1.0
15
-150
-250
-11.1
-
µA
Figure 4: DSH, DSL and DSB diagram
4
mA
VDESAT = 15V
VDESAT = 0V
VDESAT = 0V
VDESAT =
(VCC or VBS) – 1V
IR22381QPBF/IR21381Q(PbF)
Pin: HOP, LOP, HOQ, LOQ
The VO and IO parameters are referenced to COM and VS1,2,3 and are applicable to the respective output leads:
HO1,2,3 and LO1,2,3.
Symbol
Definition
Min Typ Max Units Test Conditions
VOH
High level output voltage, VBIAS – VO (normal
2
V
IO = -20mA
switching). HOP=HOQ, LOP=LOQ.
IO1+
Output high first stage short circuit pulsed current.
HOP=HOQ, LOP=LOQ
200
350
-
IO2+
Output high second stage short circuit pulsed current. 100
HOP=HOQ, LOP=LOQ
200
-
mA
V O=0V, VIN=1
(Note 1) PW≤ton1
Figure 16
VO=0V, VIN=1
(Note 1)
PW≤10µs
Note 1: for HOx Æ HINx/N = 0V, for LOx Æ LIN = 5V
Figure 5: HOP/HOQ and LOP/LOQ diagram
Pin: HON, LON, SSDH, SSDL
The VO and IO parameters are referenced to COM and VS1,2,3 and are applicable to the respective output leads:
HO1,2,3 and LO1,2,3 .
Symbol
VOL
RON,SS
IO-
Definition
Low level output voltage, VO (normal switching)
HON, LON
Soft shutdown on resistance (see Note 2)
Output low short circuit pulsed current
Min Typ Max Units Test Conditions
2
V
IO = 20mA
500
250 540
Note 2: SSD operation only
Note 3: for HOx Æ HINx/N = 5V, for LOx Æ LIN = 0V
Figure 6: HON, LON diagram
5
-
Ω
mA
PW ≤ tSS
VO=15V, VIN=0
(Note 3)
PW≤10µs
IR22381QPBF/IR21381Q(PbF)
Pin: BR
The VO and IO parameters are referenced to COM and are applicable to BR output .
Symbol
Definition
Min Typ Max Units
VOHB
BR high level output voltage, VCC- VBR
6
V
VOLB
BR low level output voltage, VBR
3
IOBR+
BR output high short circuit pulsed current
40
70
-
IOBR-
BR output low short circuit pulsed current
80
125
-
mA
Test Conditions
IBR = -20mA
IBR = 20mA
VBR=15V, VBRIN/N=0V
PW≤10µs
VBR=0V, VBRIN/N=5V
PW≤10µs
AC Electrical Characteristics
VBIAS (VCC, VBS ) = 15V, VS1,2,3 =VSS, TA = 25 °C and CL= 1000pF unless otherwise specified.
Symbol
Definition
Min. Typ. Max. Units
Propagation Delay Characteristics
ton1
Turn-on first stage duration time
ton
toff
tr
—
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
200
250 550
250 550
— 80
—
Turn-off fall time
DSH to HO soft shutdown propagation delay at
HO turn-on
— 25
— 4500
tDESAT2
DSH to HO soft shutdown propagation delay
after blanking
— 3000
—
tDESAT3
DSL to LO soft shutdown propagation delay at
LO turn-on
— 4500
—
tDESAT4
DSL to LO soft shutdown propagation delay
after blanking
— 3000
—
tDESAT5
DSB to HO hard shutdown propagation delay
— 3300
—
tDESAT6
DSB to LO hard shutdown propagation delay
— 3300
—
tDESAT7
DSB to BR hard shutdown propagation delay
— 3000
—
tVFHL1,2,3
VFH high to low propagation delay
—
550
—
tVFHHL1,2,3
VFH low to high propagation delay
—
550
—
tVFLH1,2,3
VFL low to high propagation delay
—
550
—
tVFLL1,2,3
VFL high to low propagation delay
—
550
—
Minimum pulse width of VFH and VFL
—
400
—
tPWVF
VIN = 0 & 5V
RL(HOQ/LOQ)=10Ω
VIN = 0 & 5V
VS1,2,3 = 0 to 600 or
1200V
HOP=HON,LOP=LON
Figure 7
750
750
—
tf
tDESAT1
—
—
VHIN = 0V,
VDESAT = 15V,
Figure 11
VLIN = 5V
VDESAT = 15V,
Figure 11
ns
6
Test Conditions
VHIN = 0V,
VDESAT = 15V,
Figure 11
VLIN = 5V
VDESAT = 15V,
Figure 11
VBRIN = 0V
VDSB = 15V,
Figure 11
VDESAT = 15V to 0V
Figure 12
VDESAT = 0V to 15V
Figure 12
VDESAT = 0V to 15V
Figure 12
VDESAT = 15V to 0V
Figure 12
VDESAT = 15V to 0V
or 0V to 15V
Figure 12
IR22381QPBF/IR21381Q(PbF)
AC Electrical Characteristics cont.
VBIAS (VCC, VBS ) = 15V, VS1,2,3 =VSS, TA = 25 °C and CL= 1000pF unless otherwise specified.
Symbol
Definition
Min. Typ. Max. Units
Propagation Delay Characteristics cont.
tDS
Soft shutdown minimum pulse width of desat
tSS
tFLT,DESAT1
tFLT,DESAT2
tFLT,DESAT3
tFLT,DESAT4
tFLTDSB
tFLTCLR
Soft shutdown duration period
DSH to FAULT propagation delay at HO turn-on
DSH to FAULT propagation delay after
blanking
DSL to FAULT propagation delay at LO turn-on
DSL to FAULT propagation delay after
blanking
DSB to FAULT propagation delay
— 3000
—
— 6000
— 4800
— 3300
—
—
—
— 4500
— 3000
—
—
— 3000
—
CL=1000pF,
VDS=15V Figure 8-9
VHIN = 0V,
VDS=15V, Figure 11
ns
LIN1=LIN2=LIN3=0 to FAULT
9.0 —
—
9.0 15.0 21.0
tfault
Minimum FAULT duration period
tBL
DS blanking time at turn on
— 4500
tSD
SD to output shutdown propagation delay
—
600
900
tEN
SD disable propagation delay
—
600
900
tonBR
toffBR
trBR
tfBR
BR output turn-on propagation
BR output turn-off propagation
BR output turn-on rise time
BR output turn-off fall time
—
—
—
—
110
125
235
130
200
200
400
250
Test Conditions
µs
—
ns
VLIN = 5V,
VDS=15V, Figure 11
VBRIN/N = 0V
VDESAT = 15V,
Figure 11
VDESAT=15V,
Figure 11
VDESAT=15V,
Figure 15
FLTCLR pending
VIN = on
VDESAT=15V,
Figure 11
VIN = on
VDESAT=0V, Figure 14
VIN = on
VDESAT=0V, Figure 14
Figure 7
Dead-time/Delay Matching Characteristics
DT
Deadtime
800 1000 1200
76
100
124
4500 5000 5500
MDT
PM
VM
Deadtime asymmetry skew, any of
DTLoff1,2,3-DTHoff1,2,3
PWM propagation delay matching max {ton/toff}
-min {ton/toff}, (ton/toff are applicable to all six
channels)
Voltage feedback delay matching, I any of
tVFHL1,2,3 , tVFHHL1,2,3 , tVFLL1,2,3 , tVFLH1,2,3
- any of tVFHL1,2,3 , tVFHHL1,2,3 , tVFLL1,2,3 , tVFLH1,2,3
7
—
—
125
—
—
125
—
—
400
ns
Figure 12, External
resistor=39kΩ
Figure 12,External
resistor=0kΩ
Figure 12, External
resistor=220kΩ
DT=1000ns
Figure 12
DT=1000ns
Figure 12
Input pulse width
>400nsec, Figure 13
IR22381QPBF/IR21381Q(PbF)
Figure 7: Switching Time Waveforms
Figure 8: Low Side Desat Soft Shutdown Timing Waveform
8
IR22381QPBF/IR21381Q(PbF)
Figure 9: High Side Desat Soft Shutdown Timing Waveform
Figure 10: Brake Desat Timing Waveform
9
IR22381QPBF/IR21381Q(PbF)
Figure 11: Desat Timing Diagram
10
IR22381QPBF/IR21381Q(PbF)
HIN
LIN
HO
(HOP=HOQ=HON)
DTLoff
DTHoff
90%
50%
50%
10%
DT
90%
DT
50%
10%
50%
LO
(LOP=LOQ=LON)
Figure 12: Internal Dead-Time Timing
VB1,2,3
DSH1,2,3
VDESAT+
VDESAT-
VS1,2,3
VB1,2,3
DSL1,2,3
VDESAT+
VDESAT-
VS1,2,3
tVFHL1,2,3
tVFHH1,2,3
VCC
90%
VFH1,2,3
10%
VSS
tVFLH1,2,3
tVFLL1,2,3
VCC
90%
VFL1,2,3
10%
VSS
Figure 13: Voltage Feedback Timing
11
IR22381QPBF/IR21381Q(PbF)
Figure 14: Shutdown Timing
Figure 15: Fault Duration with Pending Faultclear Waveform
(See paragraph 1.4.5 on page 21)
Figure 16: Output source current
12
IR22381QPBF/IR21381Q(PbF)
Lead Assignments
Figure 17: Package pin out
Lead Definitions
Symbol
VCC
VSS
HIN1,2,3 /N
LIN1,2,3
FAULT/N
SD
DT
DSB
BRIN/N
Description
Low side supply voltage
Logic Ground
Logic inputs for high side gate driver outputs (HOP1,2,3/HOQ1,2,3/HON1,2,3)
Logic input for low side gate driver outputs (LOP1,2,3/LOQ1,2,3/LON1,2,3)
Fault output (latched and open drain)
Shutdown input
Programmable deadtime resistor pin
Brake IGBT desaturation protection input
Logic input for brake driver
13
IR22381QPBF/IR21381Q(PbF)
Lead Definitions continued
Symbol
BR
COM
VB1,2,3
HOP1,2,3
HOQ1,2,3
HON1,2,3
DSH1,2,3
VS1,2,3
LOP1,2,3
LOQ1,2,3
LON1,2,3
DSL1,2,3
VFH1,2,3
VFL1,2,3
Description
Brake driver output
Brake and Low side drivers return
High side gate driver floating supply
High side driver sourcing output
High side driver boost sourcing output
High side driver sinking output
IGBT desaturation protection input and high side voltage feedback input
(see par. 1.4.3 on page 19)
High voltage floating supply return
Low side driver sourcing output
Low side driver boost sourcing output
Low side driver sinking output
IGBT desaturation protection input and low side voltage feedback input
(see par. 1.4.3 on page 19)
High side voltage feedback logic output
Low side voltage feedback logic output
14
IR22381QPBF/IR21381Q(PbF)
Functional block diagram
VB1
HOQ1
LAT CH
SCHMITT
T RIGGER
INPUT &
SHOOT
THROUGH
PREVENTION
HIN1
LIN1
HIN1
100nsec
minimum
Deadtime
LEVEL
SHIFTERS
SHUTDOWN
VFB
LOCAL DESAT
PROTECTION
SOFT
SHUTDOWN
VOLTAGE
FEEDBACK
HIN1
di/dt control
DRIVER
HOP1
HON1
VS1
DSH1
UV DETECT
VFH1
VB2
HIN2
SCHMITT
T RIGGER
INPUT &
SHOOT
THROUGH
PREVENTION
HIN2
LIN2
100nsec
minimum
Deadtime
LEVEL
SHIFTERS
SHUTDOWN
VFB
HOQ2
LAT CH
LOCAL DESAT
PROTECTION
SOFT
SHUTDOWN
VOLTAGE
FEEDBACK
HIN2
di/dt control
DRIVER
HOP2
HON2
VS2
DSH2
UV DETECT
VFH2
VB3
HOQ3
HIN3
SCHMITT
T RIGGER
INPUT &
SHOOT
THROUGH
PREVENTION
HIN3
LIN3
100nsec
minimum
Deadtime
LEVEL
SHIFTERS
SHUTDOWN
VFB
LAT CH
LOCAL DESAT
PROTECTION
SOFT
SHUTDOWN
VOLTAGE
FEEDBACK
HIN3
di/dt control
DRIVER
VS3
DSH3
UV DETECT
VFH3
SOFT
SHUTDOWN
SD
DT
LOCAL DESAT
PROTECTION
LOQ1
LIN1
di/dt control
SOFT
SHUTDOWN
VFL1
DRIVER
VOLTAGE
FEEDBACK
VFL2
HOP3
HON3
LOP1
LON1
DSL1
VFL3
LOCAL DESAT
PROTECTION
di/dt control
SOFT
SHUTDOWN
FAULT
LOGIC
CLEAR
LOGIC
LOP2
LIN2
DRIVER
LOP2
LON2
VOLTAGE
FEEDBACK
DSL2
FAULT
LOCAL DESAT
PROTECTION
VCC
SOFT
SHUTDOWN
To Low Side Logic
UV
DETECT
LOQ3
LIN3
di/dt control
DRIVER
LOP3
LON3
VOLTAGE
FEEDBACK
DSL3
BRIN
VSS
SHUTDOWN
DESAT
DETECTION
BRAKE
DRIVER
BR
DSB
COM
15
IR22381QPBF/IR21381Q(PbF)
State diagram
Stable States
Temporary States
System Variables
−
FAULT CLEAR indicates:
LIN1=LIN2=LIN3=0
− HIN/N /LIN/BRIN/N
− UV_VCC
− UV_VBS
− DSH/L, DSB
− SD
NOTE 1: a change of logic value of the signal labeled on lines (system variable) generates a state transition.
NOTE 2: Exiting from UNDERVOLTAGE VBS state, the HO goes high only if a falling edge event happens in
HIN/N.
−
−
−
−
−
FAULT
Normal operation
UNDERVOLTAGE VCC
SHUTDOWN (SD)
UNDERVOLTAGE VBS
−
SOFT SHUTDOWN
16
IR22381QPBF/IR21381Q(PbF)
Logic Table
Output drivers status description
HO/LO/BR
status
HOP/LOP
HOQ/LOQ
HON/LON
BR
0
HiZ
HiZ
0
1
1
1 (after ton1)
SSD
HiZ
HiZ
HiZ
SSD pulldown
0
1
LO/HO/BR
N/A
Output follows inputs
INPUTS
Operation
OUTPUT
Under
Voltage
Driver
OUTPUTS
HIN/N
LIN
BRIN/N
SD
FAULT/N
VCC
VBS
HO
LO
BR
0
0
BRIN/N
0
1
No
No
1
0
BR
Normal
Operation
1
1
BRIN/N
0
1
No
No
0
1
BR
1
0
BRIN/N
0
1
No
No
0
0
BR
Anti Shoot
Through
0
1
BRIN/N
0
1
No
No
0
0
BR
Shut Down
X
X
BRIN/N
1
1
X
X
0
0
BR
Under
Voltage
X
(NOTE1)
LIN
BRIN/N
0
1
No
Yes
0
LO
BR
X
X
X
0
1
Yes
X
0
0
0
Soft SD
(after DSL/H)
X
X
BRIN/N
X
1
No
No
SSD
SSD
BR
Hard SD
(after DSB)
X
X
X
X
0
No
No
0
0
0
FAULT
X
X
X
X
0
No
No
0
0
0
Fault Clear
X ÆHIN/N
BRIN/N
X
No
No
0 Æ HO
0
BR
(NOTE2)
LIN1=
LIN2=
LIN3= 0
(after tFLTCLR)
NOTE1: Unless in Anti Shoot Through condition.
NOTE2: FAULT duration is at least tfault when LIN1=LIN2=LIN3=0. Device stays in FAULT condition in all other
cases.
17
IR22381QPBF/IR21381Q(PbF)
Timing and logic state diagrams description
The following picture (Figure 18) shows the input/output logic diagram.
Figure 18: I/O timing diagram
E. The LO signal is on and the low side
IGBT desaturates, the low side behaviour
is the same as described in point B.
F. As C.
G. As D.
H. As A.
I. The BR signal is on and the brake IGBT
desaturates. The driver goes in FAULT
condition tuning off all the IGBTs (Hard
shut down).
Referred to timing diagram of Figure 18:
A. When the input signals are on together
the outputs go off (anti-shoot through).
B. The HO signal is on and the high side
IGBT desaturates, the HO turn off softly.
FAULT goes low. While in SSD, if LIN
goes up, LO does not change (freeze).
C. When FAULT is latched low (see FAULT
section) it can be disabled by
LIN1=LIN2=LIN3=0 condition.
D. SD disable HO and LO outputs.
18
IR22381QPBF/IR21381Q(PbF)
1
forcing FAULT pin low (see FAULT section and
Figure 20). This event disables both low side and
floating drivers and the diagnostic signal holds until
the under voltage condition is over. Fault condition
is not latched and the FAULT pin is released once
VCC becomes higher than UVVCC+.
The undervoltage on the VBS works disabling only
the floating driver. Undervoltage on VBS does not
prevent the low side driver to activate its output nor
generate diagnostic signals. VBS undervoltage
condition (VBS < UVVBS-) latches the high side
output stage in the low state. VBS must be
reestablished higher than UVVBS+ to return in
normal operating mode. To turn on the floating
driver HIN must be re-asserted high (rising edge
event on HIN is required).
FEATURES DESCRIPTION
1.1
Start-up sequence
Device starts in FAULT condition at power-up
unless FAULT clear condition is forced (i.e.
LIN1=LIN2=LIN3=0 for at least tFLTCLR – in this
case FAULT is asserted for tfltclr, then resets).
In FAULT condition driver outputs are insensitive
to inputs: any noise on input pins is then rejected
during system power-up.
As soon as the controller awakes, a FAULT clear
action can be taken to enter the normal operating
condition.
1.2
Normal operation mode
After clearing FAULT condition and supplies are
stable the device becomes fully operative (see
grey blocks in the State Diagram).
HIN/N1,2,3, LIN1,2,3 and BRIN/N produce driver
outputs to switch accordingly, while the input logic
checks the input signals preventing shoot-through
events and including Dead-time (DT).
1.3
1.4.2
4.2 Power devices desaturation
Different causes can generate a power inverter
failure: phase and/or rail supply short-circuit,
overload conditions induced by the load, etc… In
all these fault conditions a large current increase is
produced in the IGBT.
The IR22381/IR21381 fault detection circuit
monitors the IGBT emitter to collector voltage (VCE)
by means of an external high voltage diode. High
current in the IGBT may cause the transistor to
desaturate, i.e. VCE to increase.
Once in desaturation, the current in power
transistor can be as high as 10 times the nominal
current. Whenever the transistor is switched off,
this high current generates relevant voltage
transients in the power stage that need to be
smoothed out in order to avoid destruction (by
over-voltages). The IR22381/IR21381 gate driver
accomplish the transients control by smoothly
turning off the desaturated transistor by means of
the LON pin activating a so called Soft ShutDown
sequence (SSD).
Shut down
The system controller can asynchronously
command the Shutdown through the 3.3 V
compatible CMOS I/O SD pin. This event is not
latched.
1.4
Fault management
IR22381 is able to manage both the supply failure
(undervoltage lockout on both low and high side
circuits) and the desaturation of power transistors
connected to its drivers outputs.
1.4.1
Undervoltage (UV)
The Undervoltage protection function disables the
output stage of each driver preventing the power
device being driven with too low voltages.
Both the low side (VCC supplied) and the floating
side (VBS supplied) are controlled by a dedicate
undervoltage function.
Undervoltage event on the VCC (when
VCC < UVVCC-) generates a diagnostic signal by
1.4.3
Desaturation detection: DSH/L and
DSB pin function
Figure 19 shows the structure of the desaturation
sensing and soft shutdown block. This
configuration is the same for both high and low
side output stages.
19
IR22381QPBF/IR21381Q(PbF)
Figure 19: high and low side output stage for channels 1, 2, 3
VB1
HOQ1
UV detect
____
HIN1
HIN1
Schmitt trigger
input
&
shoot through
prevention
LIN1
100ns
minimum
deadtime
Input
latch
Level
Shifters
Shutdown
VFH1
HOLD
latch
oneshot
Clear
logic
LIN2
LIN3
_____
FAULT
di/dt control
DRIVER
HOP1
Local DESAT
protection
HON1
Soft ShutDown
VS1
Voltage feedback
DSH1
Desat H1
Shutdown
HOLD
HIN1
Latch
LIN1
R
Q
VSS
S
Desat H2
Desat H3
Fault
duration
(tfault)
Desat L2
Desat L3
UV_VCC
LIN1
Desat L1
Soft Shutdown
Local DESAT
protection
LOQ1
di/dt control
DRIVER
LOP1
LON1
Soft ShutDown
Voltage feedback
UV
detect
VCC
VFL1
FAULT
logic
DSL1
di/dt control
DRIVER
Hard Shutdown
BR
DESAT protection
Shutdown
____
BRIN
COM
DSB
Figure 20: Fault management diagram
20
IR22381QPBF/IR21381Q(PbF)
It must be noted that while in Soft Shut Down, both
Under Voltage fault and external Shut Down (SD)
are masked until the end of SSD. Desaturation
protection is working independently by the other
control pins and it is disabled only when the output
status is off.
The external sensing diode should have BV>600V
(or 1200V depending on application) and low stray
capacitance (in order to minimize noise coupling and
switching delays). The diode is biased by a
dedicated circuit for IGBT driver outputs (see the
active-bias section) and by a pull-up resistor for
Brake output. When VCE increases, the voltage at
DSH/L pin increases too. Being internally biased to
the local supply, DSH/L or DSB voltage is
automatically clamped. When DSH/L or DSB exceed
the VDESAT+ threshold the comparator triggers (see
Figure 19). Comparator output is filtered in order to
avoid false desaturation detection by externally
induced noise; pulses shorter than tDS are filtered
out. To avoid detecting a false desaturation during
IGBT turn on, the desaturation circuit is disabled by a
Blanking signal (TBL, see Blanking block in Figure
19). Blanking time is the estimated maximum IGBT
turn on time and must be not exceeded by proper
gate resistance sizing. When the IGBT is not
completely saturated after TBL, desaturation is
detected and the driver will turn off.
Brake IGBT
Brake desaturation causes a hard shutdown for all
the IGBTs.
Fault condition is asserted and hold until cleared by
controller.
1.4.5
Fault Clear
Fault is cleared by forcing low simultaneously LIN1,
LIN2 and LIN3 for at least tFLTCLR.
When LIN inputs are simultaneously low and a
desaturation event happens, FAULT is activated for
a minimum amount of time of tfault.
1.5
Active bias
For the purpose of sensing the power transistor
desaturation the collector voltage is read by an
external HV diode. The diode is normally biased by
an internal pull up resistor connected to the local
supply line (VB or VCC). When the transistor is “on”
the diode is conducting and the amount of current
flowing in the circuit is determined by the internal pull
up resistor value.
In the high side circuit, the desaturation biasing
current may become relevant for dimensioning the
bootstrap capacitor (see Figure 23). In fact, too low
pull up resistor value may result in high current
discharging significantly the bootstrap capacitor. For
that reason typical pull up resistor are in the range of
100 kΩ. This is the value of the internal pull up.
While the impedance of DSH/DSL pins is very low
when the transistor is on (low impedance path
through the external diode down to the power
transistor), the impedance is only controlled by the
pull up resistor when the transistor is off. In that case
relevant dV/dt applied by the power transistor during
the commutation at the output results in a
considerable current injected through the stray
capacitance of the diode into the desaturation
detection pin (DSH/L). This coupled noise may be
easily reduced using an active bias for the sensing
diode.
An Active Bias structure is available DSH/L pin. The
DSH/L pins present an active pull-up respectively to
VB/VCC, and a pull-down respectively to VS/COM.
The dedicated biasing circuit reduces the impedance
on the DSH/L pin when the voltage exceeds the
VDESAT threshold (see Figure 21). This low
impedance helps in rejecting the noise providing the
current inject by the parasitic capacitance. When the
1.4.4
SSD and Fault management
Output bridge
Desaturation event implies a large amount of current.
For that reason, IR22381 turn off strategy is based
on soft shutdown.
Eligible desaturation signals coming from DSH/L
inputs initiate the Soft Shutdown sequence (SSD).
While in SSD, the SSD pull-down is activated (RON,SS
for tss – see Figure 19) to turn off the IGBT through
HON/LON.
Figure 20 shows the fault management circuit. In this
diagram Desat_H1,2,3 and Desat_L1,2,3 are the
internal signals triggered by the desaturation event.
IR22381 accomplishes output bridge turn off in the
following way:
- if the desaturated IGBT is a low side, all the
low side IGBTs are softly turned off (SSD),
while the high side IGBTs are kept in the
state they were just before the desaturation
event.
- If the desaturated IGBT is a high side, it is
soflty turned off simultaneously with all the
low side IGBTs. While the remaining HS
IGBTs are kept in the state they were just
before the desaturation event.
In any case, after the soft shutdown period (tSS), all
IGBTs are hardly shut down (brake IGBT included).
Desaturation event generates a FAULT signal (see
Figure 11) that is latched until fault clear condition is
verified.
21
IR22381QPBF/IR21381Q(PbF)
and one turn off stage for SSD operation (both
connected to HON/LON).
When the driver turns on the IGBT (see Figure 16), a
first stage is constantly activated (HOP/LOP) while
an additional stage is maintained active only for a
limited time (tON1, HOQ/LOQ). This feature boost the
total driving capability in order to accommodate both
fast gate charge to the plateau voltage and dV/dt
control in switching.
At turn off, a single n-channel sinks up to 460mA (IO-)
and offers a low impedance path to prevent the selfturn on due to the parasitic Miller capacitance in the
power switch.
power transistor is fully on, the sensing diode gets
forward biased and the voltage at the DSH/L pin
decreases. At this point the biasing circuit
deactivates, in order to reduce the bias current of the
diode as shown in Figure 21.
1.7
Figure 21: RDSH/L Active Biasing
1.6
Voltage FeedBack
Voltage feedback pins provide information about the
state of the corresponding IGBT by means of
sensing its collector.
The VDESAT threshold discriminates whether the
sensed IGBT can be considered on (DSH/L <
VDESAT) or off (DSH/L > VDESAT).
IGBT state information is then sent to VFH/L1,2,3
open collector outputs, which are tied to Vss
ground.
See Figure 22 for functional details.
Output stage
The structure is shown in Figure 19 and consists of
two turn on stages (connected to HOP/LOP and
HOQ/LOQ), one turn off stage for normal operation
Figure 22: Voltage feedback functional diagram
22
IR22381QPBF/IR21381Q(PbF)
2
Now we must consider the influencing factors
contributing VBS to decrease:
Sizing tips
2.1
−
−
−
−
−
−
−
IGBT turn on required Gate charge (QG);
IGBT gate-source leakage current (ILK_GE);
Floating section quiescent current (IQBS);
Floating section leakage current (ILK)
Bootstrap diode leakage current (ILK_DIODE);
Desat diode bias when on (IDS- )
Charge required by the internal level shifters
(QLS); typical 20nC
− Bootstrap capacitor leakage current (ILK_CAP);
− High side on time (THON).
Bootstrap supply
The VBS1,2,3 voltage provides the supply to the high
side drivers circuitry of the IR22381/IR21381. VBS
supply sit on top of the VS voltage and so it must be
floating.
The bootstrap method to generate VBS supply can
be used with IR22381/IR21381 high side drivers.
The bootstrap supply is formed by a diode and a
capacitor connected as in Figure 23.
IR22381Q
or
IR21381Q
ILK_CAP is only relevant when using an electrolytic
capacitor and can be ignored if other types of
capacitors are used. It is strongly recommend using
at least one low ESR ceramic capacitor (paralleling
electrolytic and low ESR ceramic may result in an
efficient solution).
Then we have:
QTOT = QG + Q LS + ( I LK _ GE + I QBS +
+ I LK + I LK _ DIODE + I LK _ CAP + I DS − ) ⋅ THON
The minimum size of bootstrap capacitor is:
Figure 23: bootstrap supply schematic
This method has the advantage of being simple and
low cost but may force some limitations on dutycycle and on-time since they are limited by the
requirement to refresh the charge in the bootstrap
capacitor.
Proper capacitor choice can reduce drastically
these limitations.
C BOOT min =
QTOT
∆V BS
An example follows:
using a 15A @ 100°C IGBT (GB15XP120K):
•
•
•
•
•
•
•
•
•
Bootstrap capacitor sizing
To size the bootstrap capacitor, the first step is to
establish the minimum voltage drop (∆VBS) that we
have to guarantee when the high side IGBT is on.
If VGEmin is the minimum gate emitter voltage we
want to maintain, the voltage drop must be:
∆VBS ≤ VCC − VF − VGE min − VCEon
IQBS = 250 µA
ILK = 50 µA
QLS = 20 nC;
QG = 58 nC
ILK_GE = 250 nA
ILK_DIODE = 100 µA
ILK_CAP = 0
IDS- = 150 µA
THON = 100 µs.
(See Static Electrical Charact.);
(See Static Electrical Charact.);
(Qge+Qgc Datasheet GB15XP120K);
(Datasheet GB15XP120K);
(with reverse recovery time <100 ns);
(neglected for ceramic capacitor);
(see Static Electrical Charact.);
And:
•
•
•
•
under the condition:
VGE min > VBSUV −
VCC = 18 V
VF = 1 V
VCEonmax = 2.5 V
VGEmin = 11.9 V
the maximum voltage drop ∆VBS becomes
where VCC is the IC voltage supply, VF is bootstrap
diode forward voltage, VCEon is emitter-collector
voltage of low side IGBT and VBSUV- is the high-side
supply undervoltage negative going threshold.
∆VBS ≤ VCC − VF − VGEmin − VCEon =
23
IR22381QPBF/IR21381Q(PbF)
= 18V − 1V − 11.9V − 2.5V = 2.6V
constant. The minimum on time for charging the
bootstrap capacitor or for refreshing its charge must
be verified against this time-constant.
And the bootstrap capacitor must be:
C BOOT ≥
133 nC
= 51 nF
2.6 V
c. Bootstrap Capacitor
For high THON designs where is used an electrolytic
tank capacitor, its ESR must be considered. This
parasitic resistance forms a voltage divider with
Rboot generating a voltage step on VBS at the first
charge of bootstrap capacitor. The voltage step and
the related speed (dVBS/dt) should be limited. As a
general rule, ESR should meet the following
constraint:
NOTICE: Here above VCC has been chosen to
be 18V as an example. IGBTs can be supplied
with higher/lower supply accordingly to design
requirements. Vcc variations due to low voltage
power supply must be accounted in the above
formulas.
ESR
⋅ VCC ≤ 3V
ESR + RBOOT
Some important considerations
a. Voltage ripple
There are three different cases making the
bootstrap circuit get conductive (see Figure 23)
Parallel combination of small ceramic and large
electrolytic capacitors is normally the best
compromise, the first acting as fast charge thank for
the gate charge only and limiting the dVBS/dt by
reducing the equivalent resistance while the second
keeps the VBS voltage drop inside the desired ∆VBS.
ILOAD < 0; the load current flows in the low side
IGBT displaying relevant VCEon
VBS = VCC − VF − VCEon
d. Bootstrap Diode
The diode must have a BV> 600V (or 1200V
depending on application) and a fast recovery time
(trr < 100 ns) to minimize the amount of charge fed
back from the bootstrap capacitor to VCC supply.
In this case we have the lowest value for VBS.
This represents the worst case for the bootstrap
capacitor sizing. When the IGBT is turned off the
Vs node is pushed up by the load current until the
high side freewheeling diode get forwarded
biased
ILOAD = 0; the IGBT is not loaded while being
on and VCE can be neglected
2.2
Gate resistances
The switching speed of the output transistor can be
controlled by properly size the resistors controlling
the turn-on and turn-off gate current. The following
section provides some basic rules for sizing the
resistors to obtain the desired switching time and
speed by introducing the equivalent output
resistance of the gate driver (RDRp and RDRn).
The examples always use IGBT power transistor.
Figure 24 shows the nomenclature used in the
following paragraphs. In addition, Vge* indicates the
plateau voltage, Qgc and Qge indicate the gate to
collector and gate to emitter charge respectively.
V BS = VCC − VF
ILOAD > 0; the load current flows through the
freewheeling diode
V BS = VCC − VF + VFP
In this case we have the highest value for VBS.
Turning on the high side IGBT, ILOAD flows into it
and VS is pulled up.
To minimize the risk of undervoltage, bootstrap
capacitor should be sized according to the ILOAD<0
case.
b. Bootstrap Resistor
A resistor (Rboot) is placed in series with bootstrap
diode (see Figure 23) so to limit the current when
the bootstrap capacitor is initially charged. We
suggest not exceeding some Ohms (typically 5,
maximum 10 Ohm) to avoid increasing the VBS time-
24
IR22381QPBF/IR21381Q(PbF)
IC
CRES
RGon = gate on-resistor
RDRp = driver equivalent on-resistance
VGE
t1,QGE
IR22381Q/IR21381Q HOP/LOP and HOQ/LOQ
pins can be used to configure gate charge circuit.
Fast turn on can be configured using HOP and LOP
pins (up to tON1 switching time).
For slower turn on times HOQ and LOQ can be
used.
Current partitioning can be changed acting on the
output resistors.
t2,QGC
VCE
dV/dt
IC
90%
CRESon
CRES
VGE
Vge*
In particular, shorting HOP to HOQ and LOP to
LOQ, RDRp is defined by
CRESoff
10%
10%
t,Q
RDRp
tSW
tDon
tR
Figure 24: Nomenclature
2.2.1
(IO1+ ,IO2+ and
Characteristics”).
Sizing the turn-on gate resistor
For the matters of the calculation included
hereafter, the switching time tsw is defined as the
time spent to reach the end of the plateau voltage
(a total Qgc+Qge has been provided to the IGBT
gate). To obtain the desired switching time the gate
resistance can be sized starting from Qge and Qgc,
Vcc, Vge* (see Figure 25):
from
“static
Electrical
- Output voltage slope
Turn-on gate resistor RGon can be sized to control
output slope (dVOUT/dt).
While the output voltage has a non-linear
behaviour, the maximum output slope can be
approximated by:
Qgc + Qge
t sw
I avg
dVout
=
dt
C RESoff
and
RTOT =
ton1
Table 1 reports the gate resistance size for two
commonly used IGBTs (calculation made using
typical datasheet values and assuming Vcc=15V).
- Switching-time
I avg =
⎧ ton1 ⎛ Vcc Vcc ⎛ t SW
⎞⎞
⎜
⎟ ⎟ when t SW > ton1
⎜⎜
+
−
1
⎪
⎪ t SW ⎜⎝ I o1+ I o 2+ ⎝ ton1 ⎟⎠ ⎟⎠
=⎨
Vcc
⎪
when t SW ≤ ton1
⎪⎩
I o1+
inserting the
rearranging:
Vcc − V ge*
I avg
expression
yielding
Iavg
and
*
Vcc/Vb
RTOT =
Iavg
CRES
Vcc − Vge
dV
C RESoff ⋅ out
dt
RDRp
As an example, Table 2 shows the sizing of gate
resistance to get dVout/dt=5V/ns when using two
popular IGBTs, typical datasheet values and
assuming Vcc=15V.
RGon
COM/Vs
NOTICE: Turn on time must be lower than TBL to
avoid improper desaturation detection and SSD
triggering.
Figure 25: RGon sizing
where RTOT = RDRp + RGon
25
IR22381QPBF/IR21381Q(PbF)
As a result, when τ is faster than the collector rise
time (to be verified after calculation) the transfer
function can be approximated by:
Sizing the turn-off gate resistor
The worst case in sizing the turn-off resistor RGoff is
when the collector of the IGBT in off state is forced
to commutate by external events (i.e. the turn-on of
the companion IGBT).
In this case the dV/dt of the output node induces a
parasitic current through CRESoff flowing in RGoff and
RDRn (see Figure 26).
If the voltage drop at the gate exceeds the threshold
voltage of the IGBT, the device may self turn on
causing large oscillation and relevant cross
conduction.
Vge
Vde
So that Vge = ( RGoff + RDRn ) ⋅ C RESoff ⋅
Vth > Vge = (RGoff + RDRn ) ⋅ CRESoff
Rearranging the equation yields:
RGoff
OFF
RDRn
(1)
C IES
Vge = Vde ⋅
The transfer function between IGBT collector and
IGBT gate then becomes:
Vde
=
CRESoff
dV
⋅
dt
− RDRn
CRESoff
(CRESoff + CIES )
As an example, table 3 reports RGoff (calculated with
the above mentioned equation (1)) for two popular
IGBTs to withstand dVout/dt = 5V/ns.
1 + s ⋅ ( RGoff + RDRn ) ⋅ (CRESoff + CIES )
( RGoff
Vth
which is driven only by IGBT characteristics.
s ⋅ ( RGoff + RDRn ) ⋅ CRESoff
Which yields to a high pass filter with a pole at:
1/τ =
RGoff <
In any case, the worst condition for a spurious turn
on is with very fast steps on IGBT collector.
In that case collector to gate transfer function can
be approximated with the capacitor divider:
Figure 26: RGoff sizing: current path when Low
Side is off and High Side turns on
Vge
dVout
dt
must be verified to avoid spurious turn on.
CRESoff
ON
dVde
in the
dt
time domain.
Then the condition:
dV/dt
HS Turning ON
= s ⋅ ( RGoff + RDRn ) ⋅ CRESoff
1
+ RDRn ) ⋅ (CRESoff + CIES )
NOTICE: the above-described equations are
intended being an approximated way for the gate
resistances sizing. More accurate sizing may
account more precise device modelling and
parasitic component dependent on the PCB and
power section layout and related connections.
Table 1: RGon sizing driven by tsw constraint
IGBT
Qge
Qgc
Vge*
tsw
Iavg
Rtot
RGon → std commercial value
Tsw
GB15XP120K*
GB05XP120K
12nC
3.7nC
46nC
14nC
9V
9.5V
500ns
400ns
116mA
44mA
77Ω
124Ω
Rtot - RDRp = 15 Ω → 10 Ω
Rtot - RDRp = 65 Ω → 68 Ω
→465ns
→408ns
IRGB5B120KD
3.7nC
13nC
9.5V
500ns
33mA
164Ω
Rtot - RDRp = 102 Ω → 100 Ω
→502ns
Table 2: Table 2: RGon sizing driven by dVOUT/dt constraint
IGBT
Qge
Qgc
Vge*
CRESoff
Rtot
RGon → std commercial value
dVout/dt
GB15XP120K*
GB05XP120K
IRGB120KD
12nC
3.7nC
3.7nc
46nC
14nC
13nC
9V
9.5V
9.5V
38pF
12pF
11pF
47Ω
91Ω
100Ω
Rtot - RDRp = 4.5 Ω → 4.7Ω
Rtot - RDRp = 48.8 Ω → 47Ω
Rtot - RDRp = 57 Ω → 56 Ω
→5V/ns
→5.1V/ns
→5V/ns
26
IR22381QPBF/IR21381Q(PbF)
Table 3: RGoff sizing
IGBT
Vth(min)
GB15XP120K*
5
GB05XP120K
5
IRG4PH20K(D)
5
* sized with 18V supply
3
CRESoff
RGoff
38pF
12pF
11pF
RGoff = 0 Ω
RGoff ≤ 55 Ω
RGoff ≤ 63 Ω
PCB LAYOUT TIPS
3.1
Distance from H to L voltage
The IR22381/IR21381Q pin out lacks some pins
(see Figure 17) maximizing the distance between
floating (from DC- to DC+) and low voltage pins . It’s
strongly recommended to place components tied to
floating voltage in the respective high voltage
portions of the device (VB1,2,3, VS1,2,3) side.
3.2
Figure 27: gate drive loop
Ground plane
Ground plane must not be placed under or nearby
the high voltage floating side to minimize noise
coupling.
3.3
3.4
Supply capacitors
IR22381 output stages are able to quickly turn on
IGBT with up to 460mA of output current. The
supply capacitors must be placed as close as
possible to the device pins (VCC and VSS for the
ground tied supply, VB and VS for the floating
supply)
in
order
to
minimize
parasitic
inductance/resistance.
Gate drive loops
Current loops behave like an antenna able to
receive and transmit EM noise. In order to reduce
EM coupling and improve the power switch turn
on/off performances, gate drive loops must be
reduced as much as possible. Figure 23 shows the
high and low side gate loops.
Moreover, current can be injected inside the gate
drive loop via the IGBT collector-to-gate parasitic
capacitance. The parasitic auto-inductance of the
gate loop contributes to develop a voltage across
the gate-emitter increasing the possibility of self
turn-on effect. For this reason is strongly
recommended to place the three gate resistances
close together and to minimize the loop area (see
Figure 27).
3.5
Routing and placement
example
Figure 28 shows one of the possible layout
solutions using a 3 layer PCB (low voltage signals
not shown) on an ECONO PIM module. This
example takes into account all the previous
considerations. Placement and routing for supply
capacitors and gate resistances in the high and low
voltage side minimize respectively supply path and
gate drive loop. The bootstrap diode is placed under
the device to have the cathode as close as possible
to bootstrap capacitor and the anode far from high
voltage and close to VCC.
27
IR22381QPBF/IR21381Q(PbF)
a) TOP(Gate Drive)
b) BOTTOM (GND)
28
IR22381QPBF/IR21381Q(PbF)
c) MID (VCC/COM/DCP)
Figure 28: layout example: top (a), internal layer (b) and bottom (c) layer
29
IR22381QPBF/IR21381Q(PbF)
Case Outline
Qualification Level: Industrial level, MSL3, Lead-free.
ESD Classification:
Human Body Model (HBM): Class 2, per JESD22-A114-B
Machine Model (MM): Class B, per EIA/JESD22-A115-A
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
This product has been qualified for the industrial market.
Data and specifications are subject to change without notice. 08/11/05.
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