ISSI IS31AP4833 Treble and bass control with 3d enhancement audio power driver Datasheet

IS31AP4833
TREBLE AND BASS CONTROL WITH 3D ENHANCEMENT AUDIO POWER DRIVER
August 2012
GENERAL DESCRIPTION
FEATURES
The IS31AP4833 is a treble and bass control with 3D
enhancement audio power driver. The IS31AP4833
provides tone (bass and treble) controls and volume
control as well as a stereo audio power amplifier
capable of delivering 2.8W into 4Ω with less than 10%
THD with a 5V supply.
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The IS31AP4833 uses flexible I2C control interface for
multiple application requirements. It also features 3D
sound circuitry which can be externally adjusted via a
simple RC network.
The IS31AP4833 features a 13 steps tone control
(-12dB ~ +12dB, 2dB/step) and a 29 steps volume
control (mute, -42dB ~ +12dB, 2dB/step) for the
headphone and stereo outputs. The volume and tone
are controlled through an I2C compatible interface.
The IS31AP4833 can get independent volume control
for two channels.
IS31AP4833 is available in QFN-36(4mm × 4mm) and
TQFP-48(7mm × 7mm) package. It operates from 3.0V
to 5.5V over the temperature range of -40°C to +85°C.
3.0V to 5.5V supply
Mute control
Treble and bass control
Independent volume control for two channels
Stereo input MUX
I2C control interface
3D enhancement
Thermal shutdown protection
Click-and-pop suppression
QFN-36(4mm × 4mm) and TQFP-48(7mm × 7mm)
package
APPLICATIONS
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Cell phones, PDA, MP4, PMP
Portable and desktop computers
Desktops audio system
Multimedia monitors
TYPICAL APPLICATION CIRCUIT
Figure 1
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Rev. A, 07/22/2012
Typical Application Circuit
1
IS31AP4833
PIN CONFIGURATION
Package
Pin Configuration (Top View)
37 INR2
38 NC
39 INR3
40 INR+
41 INR-
42 GND
43 GND
44 INL-
45 INL+
46 INL3
47 NC
48 INL2
QFN-36
INL1 1
36 INR1
NC 2
35 NC
LOL 3
34 LOR
TIL 4
33 TIR
OUTL+ 5
32 OUTR+
NC 6
TQFP-48
31 NC
VCC 7
30 VCC
NC 8
29 NC
OUTL- 9
28 OUTR-
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NC 24
3DP 23
3DN 22
3D_EN 21
HP 20
GND 19
GND 18
RST 17
NC 16
25 SCL
BYPASS 15
26 TOR
SDA 12
NC 13
27 LIR
TOL 11
SDB 14
LIL 10
2
IS31AP4833
PIN DESCRIPTION
No.
Pin
Description
QFN-36
TQFP-48
1
1
INL1
Left channel single-ended input1.
2
3
LOL
Left channel tone control loop out.
3
4
TIL
Left channel tone control in.
4
5
OUTL+
5, 23
7,30
VCC
6
9
OUTL-
7
10
LIL
Left channel tone control loop in.
8
11
TOL
Left channel tone control out.
9
12
SDA
I2C serial data.
10
14
SDB
It will into shutdown mode when pull low.
11
15
BYPASS
12
2,6,8,13,16,24,
29,31,35,38,47
NC
No connection.
13
17
RST
Reset chip logic and states. Active low.
14,32
18,19,42,43
GND
Ground.
15
20
HP
16
21
3D_EN
17
22
3DN
Negative channel 3D input.
18
23
3DP
Positive channel 3D input.
19
25
SCL
I2C serial clock.
20
26
TOR
Right channel tone control out.
21
27
LIR
Right channel tone control loop in.
22
28
OUTR-
Negative output of right channel.
24
32
OUTR+
Positive output of right channel.
25
33
TIR
Right channel tone control in.
26
34
LOR
Right channel tone control loop out.
27
36
INR1
Right channel single-ended input1.
28
37
INR2
Right channel single-ended input2.
29
39
INR3
Right channel single-ended input3.
30
40
INR+
Right channel positive differential input.
31
41
INR-
Right channel negative differential input.
33
44
INL-
Left channel negative differential input.
34
45
INL+
Left channel positive differential input.
35
46
INL3
Left channel single-ended input3.
36
48
INL2
Left channel single-ended input2.
Thermal Pad
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Positive output of left channel.
Power supply.
Negative output of left channel.
Bypass capacitor which provides the common
mode voltage.
Detect HP insert or not.
It will into 3D enhance mode when pull high.
Connect to GND.
3
IS31AP4833
ORDERING INFORMATION
INDUSTRIAL RANGE: -40°C TO +85°C
Order Part No.
Package
QTY
IS31AP4833-QFLS2-TR
IS31AP4833-TQLS2
QFN-36, Lead-free
TQFP-48, Lead-free
2500/Reel
250/Tray
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any
time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are
advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the
product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not
authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
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Rev. A, 07/22/2012
4
IS31AP4833
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VCC
Voltage at any input pin
Maximum junction temperature, TJMAX
Storage temperature range, TSTG
Operating temperature range, TA
-0.3V ~ +6.0V
-0.3V ~ VCC+0.3V
150°C
-65°C ~ +150°C
-40°C ~ +85°C
Note:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
TA = 25°C, unless otherwise noted. Typical value are TA = 25°C, VCC = 3.6V.
Symbol
Parameter
Condition
VCC
Supply voltage
ISD
Shutdown current
ICC
Quiescent
power
supply current
VIH_HP
HP input high-voltage
VIL_HP
HP input low-voltage
VIH
Input high-voltage
VIL
Input low-voltage
Min.
Typ.
3.0
VSDB = 0V
1
VSDB = VCC, software shutdown
1
VIN = 0V, IO = 0A, VHP = 0V, no load
6
VIN = 0V, IO = 0A, VHP = 5V, no load
4
VCC = 5.0V
4.1
VCC = 3.0V
2.3
Max.
Unit
5.5
V
μA
mA
V
VCC = 5.0V
3.4
VCC = 3.0V
1.54
1.4
V
V
0.4
V
Max.
Unit
AC CHARACTERISTICS (Note 1)
TA = 25°C, VCC = 5.0V, unless otherwise noted.
Symbol
Po
THD+N
tWU
PSRR
VNO
Parameter
Output power
Condition
Min.
Typ.
THD+N = 10%, f = 1kHz, RL = 4Ω, speaker
2.80
THD+N = 1%, f = 1kHz, RL = 4Ω, speaker
2.20
THD+N = 10%, f = 1kHz, RL = 8Ω, speaker
1.75
THD+N = 1%, f = 1kHz, RL = 8Ω, speaker
1.45
THD+N = 10%, f = 1kHz, RL = 32Ω,
headphone
0.11
THD+N = 1%, f = 1kHz, RL = 32Ω,
headphone
0.091
PO = 1.5W, f = 1kHz, RL = 4Ω, speaker
Total
harmonic
PO = 0.9W, f = 1kHz, RL = 8Ω, speaker
distortion plus noise
PO = 75mW, f = 1kHz, RL = 32Ω, headphone
W
0.069
0.046
%
0.022
Wake-up time from
shutdown
130
ms
Power
supply
VCC = 3.0V, f = 217Hz, RL = 8Ωk, speaker
rejection ratio
-67
dB
Noise
60
μV
VCC = 3.0V~5.0V, VIN = 0V, RL = 4Ω, speaker
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Rev. A, 07/22/2012
5
IS31AP4833
DIGITAL INPUT SWITCHING CHARACTERISTICS (Note 1)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
400
kHz
fSCL
Serial-Clock frequency
tBUF
Bus free time between a STOP and a START
condition
1.3
μs
tHD, STA
Hold time (repeated) START condition
0.6
μs
tSU, STA
Repeated START condition setup time
0.6
μs
tSU, STO
STOP condition setup time
0.6
μs
tHD, DAT
Data hold time
tSU, DAT
Data setup time
100
ns
tLOW
SCL clock low period
1.3
μs
tHIGH
SCL clock high period
0.7
μs
0.9
μs
tR
Rise time of both SDA and SCL signals,
receiving
(Note 2)
20+0.1Cb
300
ns
tF
Fall time of both SDA and SCL signals,
receiving
(Note 2)
20+0.1Cb
300
ns
Note 1: Guaranteed by design.
Note 2: Cb = total capacitance of one bus line in pF. ISINK ≤ 6mA. tR and tF measured between 0.3 × VCC and 0.7 × VCC.
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6
IS31AP4833
TYPICAL PERFORMANCE CHARACTERISTICS
20
20
10
RL = 4Ω
f = 1kHz
10
5
THD+N(%)
THD+N(%)
5
2
1
0.5
2
1
0.5
VCC = 3.0V
PO = 450mW
0.2
0.1
VCC = 3.0V
0.2
VCC = 5.0V
PO = 1.5W
0.05
VCC = 5.0V
0.1
0.05
10m
RL = 4Ω
0.02
20m
50m
100m
200m
500m
1
2
0.01
3 4
20
50
100
200
THD+N vs. Output Power
5
Figure 3
10
RL = 8Ω
f = 1kHz
THD+N(%)
THD+N(%)
1
0.2
THD+N vs. Frequency
RL = 8Ω
1
0.5
VCC = 3.0V
PO = 270mW
0.2
0.1
0.1
0.05
0.05
VCC = 5.0V
0.02
20m
50m
100m
200m
500m
1
VCC = 5.0V
PO = 900mW
0.02
0.01
2
20
50
100
200
Figure 4
THD+N vs. Output Power
Figure 5
RL = 32Ω
f = 1kHz
10
2k
5k
10k 20k
THD+N vs. Frequency
RL = 32Ω
5
2
THD+N(%)
2
THD+N(%)
1k
20
20
1
0.5
VCC = 3.0V
0.2
1
0.5
VCC = 3.0V
PO = 25mW
0.2
0.1
0.1
0.05
0.05
VCC = 5.0V
PO = 75mW
0.02
0.02
0.01
1m
500
Frequency(Hz)
Output Power(W)
5
10k 20k
2
VCC = 3.0V
0.5
10
5k
5
2
0.01
10m
2k
20
20
10
1k
Frequency(Hz)
Output Power(W)
Figure 2
500
VCC = 5.0V
2m
5m
10m
20m
50m
100m 200m
0.01
20
50
100
THD+N vs. Output Power
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Rev. A, 07/22/2012
500
1k
2k
5k
10k 20k
Frequency(Hz)
Output Power(W)
Figure 6
200
Figure 7
THD+N vs. Frequency
7
IS31AP4833
+0
200u
RL = 8Ω
-20
100u
VCC = 3.0V
-40
70u
PSRR(dB)
Output Voltage(V)
VCC = 3.0V, 5.0V
RL = 4Ω
50u
30u
-60
-80
VCC = 5.0V
20u
-100
10u
20
50
100
200
500
1k
2k
5k
10k
-120
20
20k
50
100
500
1k
2k
5k
10k
20k
Frequency(Hz)
Frequency(Hz)
Figure 8
200
Noise vs. Frequency
Figure 9
PSRR vs. Frequency
2.5
3.5
RL = 4Ω
f = 1kHz
3
RL = 8Ω
f = 1kHz
THD+N = 10%
THD+N = 10%
Output Power(W)
Output Power(W)
2
2.5
2
1.5
THD+N = 1%
1.5
1
THD+N = 1%
1
0.5
0.5
0
3
3.5
4
4.5
5
5.5
0
3
3.5
4.5
5
5.5
Power Supply(V)
Power Supply(V)
Figure 10
4
Output Power vs. Power Supply
Figure 11
Output Power vs. Power Supply
+20
VCC = 5.0V
RL = 8Ω
Output Level(dB)
+15
+10
+5
+0
-5
-10
-15
20
50
100
200
500
1k
2k
5k
10k
20k
Frequency(Hz)
Figure 12
Bass and Treble Response vs. Frequency
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Rev. A, 07/22/2012
8
IS31AP4833
FUNCTIONAL BLOCK DIAGRAM
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Rev. A, 07/22/2012
9
IS31AP4833
DETAILED DESCRIPTION
I2C INTERFACE
The IS31AP4833 uses a serial bus, which conforms to
the I2C protocol, to control the chip’s functions with two
wires: SCL and SDA. The IS31AP4833’s slave address
is “1000 0000”. It only supports write operations.
The SCL line is uni-directional. The SDA line is
bi-directional (open-collector) with a pull-up resistor
(typically 4.7kΩ). The maximum clock frequency
specified by the I2C standard is 400kHz. In this
discussion, the master is the microcontroller and the
slave is the IS31AP4833.
After the last bit of the chip address is sent, the master
checks for the IS31AP4833’s acknowledge. The
master releases the SDA line high (through a pull-up
resistor). Then the master sends an SCL pulse. If the
IS31AP4833 has received the address correctly, then it
holds the SDA line low during the SCL pulse. If the SDA
line is not low, then the master should send a “STOP”
signal (discussed later) and abort the transfer.
Following acknowledge of IS31AP4833, the register
address byte is sent, most significant bit first.
IS31AP4833 must generate another acknowledge
indicating that the register address has been received.
The timing diagram for the I2C is shown in Figure 13.
The SDA is latched in on the stable high level of the
SCL. When there is no interface activity, the SDA line
should be held high.
The “START” signal is generated by lowering the SDA
signal while the SCL signal is high. The start signal will
alert all devices attached to the I2C bus to check the
incoming address against their own chip address.
Then 8-bit of data byte are sent next, most significant
bit first. Each data bit should be valid while the SCL
level is stable high. After the data byte is sent, the
IS31AP4833 must generate another acknowledge to
indicate that the data was received.
The “STOP” signal ends the transfer. To signal “STOP”,
the SDA signal goes high while the SCL signal is high.
The 8-bit chip address is sent next, most significant bit
first. Each address bit must be stable while the SCL
level is high.
Figure 13
Figure 14
Figure 15
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Interface timing
Bit transfer
Writing to IS31AP4833
10
IS31AP4833
REGISTER DESCRIPTION
Table 1 Byte Function
Address Bit
D7:D5
Data Bit
D4
000
D3
D2
D1
-
Table
Default
IGS
Audio input gain control
2
0000 0110
001
-
BGS
Bass control
3
0010 0110
010
-
TGS
Treble control
4
0100 0110
011
LVS
Left channel gain control
5
0111 0000
100
RVS
Right channel gain control
6
1001 0000
Audio input MUX control
7
1010 0000
Operating mode control
8
1110 0000
101
111
Table 2
ME
-
IMS
3DE
SE
Audio Input Gain Control Byte
Address Bit
Bit
Data Bit
D4:D3
D2:D0
Name
000
-
IGS
Default
000
00
110
Configure the input gain.
Input Gain Select
-15dB
-12dB
-9dB
-6dB
-3dB
+0dB
+3dB
+6dB
SSD
Table 3
D7:D5
IGS
000
001
010
011
100
101
110
111
Function
D0
Bass Control Byte
Bit
Address Bit
Data Bit
D7:D5
D4
D3:D0
Name
001
-
BGS
Default
001
0
0110
Configure the bass gain.
Input Resistor
85kΩ
80kΩ
74kΩ
67kΩ
59kΩ
50kΩ
41kΩ
33kΩ
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BGS
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Bass Gain Select
-12dB
-10dB
-8dB
-6dB
-4dB
-2dB
0dB
+2dB
+4dB
+6dB
+8dB
+10dB
+12dB
11
IS31AP4833
Table 4
Treble Control Byte
Table 6
Address Bit
Bit
Data Bit
Right Channel Gain Control Byte
Bit
Address Bit
Data Bit
D7:D5
D4:D0
D7:D5
D4
D3:D0
Name
010
-
TGS
Name
100
RVS
Default
010
0
0110
Default
100
10000
Configure the treble gain.
Configure the right channel gain (see Table 9).
Treble Gain Select
-12dB
-10dB
-8dB
-6dB
-4dB
-2dB
0dB
+2dB
+4dB
+6dB
+8dB
+10dB
+12dB
TGS
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
Table 5
Address Bit
Data Bit
D7:D5
D4:D0
Name
011
LVS
Default
011
10000
Configure the left channel gain (see Table 9).
LVS
00000
00001
00010
00011
……
10000
……
10110
10111
……
111xx
-12dB
+0dB
+2dB
+12dB
Table 7
Left Volume Select
Mute
-42dB
-40dB
-38dB
Audio Input MUX Control Byte
Address Bit
Bit
Left Channel Gain Control Byte
Bit
Right Volume Select
Mute
-42dB
-40dB
-38dB
RVS
00000
00001
00010
00011
……
10000
……
10110
10111
……
111xx
Data Bit
D7:D5
D4:D2
D1:D0
Name
101
-
IMS
Default
101
000
00
Single-ended or differential input selected.
IMS
00
01
10
11
Input MUX Select
Single-ended Input 1
Single-ended Input 2
Single-ended Input 3
Differential Input
-12dB
+0dB
+2dB
+12dB
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IS31AP4833
Table 8
Bit
Table 9
Operating Mode Control Byte
Address Bit
Data Bit
D7:D5
D4
D3
D2
D1
D0
Name
111
ME
-
3DE
SE
SSD
Default
111
0
0
0
0
0
Configure the operating mode for IS31AP4833.
Left/Right Channel Gain Control
Data
Gain
Data
Gain
00000
Mute
01111
-14
00001
-42
10000
-12
00010
-40
10001
-10
00011
-38
10010
-8
SSD
0
1
Shutdown Enable
Operating Mode
Shutdown Mode
00100
-36
10011
-6
00101
-34
10100
-4
00110
-32
10101
-2
SE
0
1
Speaker Enable
Speaker Enable
Speaker Disable
00111
-30
10110
+0
01000
-28
10111
+2
01001
-26
11000
+4
3DE
0
1
3D Enable
3D Off
3D On
01010
-24
11001
+6
01011
-22
11010
+8
01100
-20
11011
+10
ME
0
1
Mute Enable
Mute Disable
Mute Enable
01101
-18
111xx
+12
01110
-16
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13
IS31AP4833
APPLICATION INFORMATION
3D ENHANCEMENT
The IS31AP4833 has a 3D audio enhancement effect
that helps improve the apparent stereo channel
separation when, because of cabinet or equipment
limitations, the left and right speakers are closer to
each other than optimal.
Decreasing the resistor size will make the 3D effect
more pronounced and decreasing the capacitor size
will raise the cutoff frequency for the effect. A 68nF
capacitor is used to reduce the effect at frequencies
below 1kHz. Increasing the value of the capacitor will
decrease the low cutoff frequency at which the stereo
enhanced effect starts to occur as shown below
f
3D

1
2R3 D C 3 D
(1)
For example, according to the Figure 1,
R3D = 2.7kΩ, C3D = 68nF
So, f
3D

1
 867 Hz
2  2.7 k  68 nF
The 3D enhancement effect enabled by setting the
3DE bit of the control byte “111x xxxx”. When setting
the 3DE bit to “1”, 3D enhancement enabled. When
setting the 3DE bit to “0”, 3D enhancement disabled.
Pulling the 3D_EN pin to high will enable the 3D
enhancement either.
Set the 3DE bit to “1” or pull the 3D_EN pin to high will
enable the 3D enhancement. Shutdown the 3D
enhancement should set the 3DE bit to “0” and pull the
3D_EN pin to low.
TONE CONTROL RESPONSE
Bass and treble tone controls are included in the
IS31AP4833. The tone controls use two external
capacitors for each stereo channel (C1L，C2L，C1R，C2R).
Each has a corner frequency determined by the value
of C1, C2 and internal resistors in the feedback loop of
the internal tone amplifier.
With C = C1 = C2, the treble turn-over frequency is
nominally
1

f
TT
2  56 k  C
(2)
and the bass turn-over frequency is nominally
f
BT

1
2  113 .3k  C
(3)
So, f
f
BT
TT


1
 1.3kHz
2  56 k  2.2 nF
1
 639 Hz
2  113 .3k  2.2 nF
The bass and treble gain can be adjusted
independently by the control byte “010x xxxx” and
“001x xxxx” (Table 3, 4).
GAIN SELECTION
The left/right channel gain can be adjusted by the LVS
bit of the control byte “011x xxxx” and the RVS bit of
the control byte “100x xxxx” (Table 5, 6).
In the speaker mode the output gain is equaled to
audio input gain(IGS)+left/right channel
gain(LVS/RVS)+6dB.
In the headphone mode the output gain is equaled to
audio input gain(IGS)+left/right channel
gain(LVS/RVS).
INPUT CAPACITORS (CIN)
The input capacitors (CIN) and internal resistor (RIN)
form a high-pass filter with the corner frequency, fC,
determined in Equation (4).
1
f 
c 2R C
IN IN
(4)
The value of RIN is following the audio input gain (see
Table 2).
For example, in figure 1,
CIN = 220nF, the audio input gain is set to -3dB, so the
RIN = 59kΩ,
then,
1
f 
 12 Hz
c 2  59 k  220 nF
The capacitors should have a tolerance of  10% or
better, because any mismatch in capacitance causes
an impedance mismatch at the corner frequency and
below.
MUTE FUNCTION
By setting the LVS/RVS bit to “00000” the left/right
channel output will be mute independently (see Table 5,
6). The ME bit of the control byte “111x xxxx” sets the
mute function for left and right channels. When the ME
bit is set to “1”, the left and right channels are both
mute (see Table 8). When the ME bit is set to “0”, the
left and right channels will resume the volume before.
For example, according to the Figure 1,
C1 = C2 = 2.2nF
Integrated Silicon Solution, Inc. – www.issi.com
Rev. A, 07/22/2012
14
IS31AP4833
INPUT SIGNAL SELECTION
SHUTDOWN MODE
IS31AP4833 can choose single-ended or differential
signal for the input source. Single-ended input 1,
single-ended input 2, single-ended input 3 and
differential input signal can be chosen by the IMS bit of
control byte “101x xxxx”(see Table 7).
Shutdown mode can either be used as a means of
reducing power consumption. During shutdown mode
all registers retain their data.
HEADPHONE MODE
IS31AP4833 can also be used to drive headphone. The
IC will shut off the positive output if headphone plug-in
has been detected. Then the speaker will stop working
and switch to the headphone mode.
Integrated Silicon Solution, Inc. – www.issi.com
Rev. A, 07/22/2012
SOFTWARE SHUTDOWN
By setting SSD bit of the control byte “111x xxxx” to “1”,
the IS31AP4833 will operate in software shutdown
mode, wherein they consume only 1μA (Typ.) current.
HARDWARE SHUTDOWN
The chip enters hardware shutdown mode when the
SDB pin is pulled low, wherein they consume only 1μA
(Typ.) current.
15
IS31AP4833
CLASSIFICATION REFLOW PROFILES
Profile Feature
Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
150°C
200°C
60-120 seconds
Average ramp-up rate (Tsmax to Tp)
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
217°C
60-150 seconds
Peak package body temperature (Tp)*
Max 260°C
Time (tp)** within 5°C of the specified
classification temperature (Tc)
Max 30 seconds
Average ramp-down rate (Tp to Tsmax)
6°C/second max.
Time 25°C to peak temperature
8 minutes max.
Figure 16
Classification Profile
Integrated Silicon Solution, Inc. – www.issi.com
Rev. A, 07/22/2012
16
IS31AP4833
PACKAGING INFORMATION
QFN-36
Integrated Silicon Solution, Inc. – www.issi.com
Rev. A, 07/22/2012
17
IS31AP4833
TQFP-48
Note: All dimensions in millimeters unless otherwise stated.
Integrated Silicon Solution, Inc. – www.issi.com
Rev. A, 07/22/2012
18