a Complete 10-Bit, 20 MSPS, 80 mW CMOS A/D Converter AD9200 FEATURES CMOS 10-Bit, 20 MSPS Sampling A/D Converter Pin-Compatible with AD876 Power Dissipation: 80 mW (3 V Supply) Operation Between 2.7 V and 5.5 V Supply Differential Nonlinearity: 0.5 LSB Power-Down (Sleep) Mode Three-State Outputs Out-of-Range Indicator Built-In Clamp Function (DC Restore) Adjustable On-Chip Voltage Reference IF Undersampling to 135 MHz A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary output format. An out-of-range signal (OTR) indicates an overflow condition which can be used with the most significant bit to determine low or high overflow. The AD9200 can operate with supply range from 2.7 V to 5.5 V, ideally suiting it for low power operation in high speed portable applications. The AD9200 is specified over the industrial (–40°C to +85°C) and commercial (0°C to +70°C) temperature ranges. PRODUCT HIGHLIGHTS Low Power PRODUCT DESCRIPTION The AD9200 is a monolithic, single supply, 10-bit, 20 MSPS analog-to-digital converter with an on-chip sample-and-hold amplifier and voltage reference. The AD9200 uses a multistage differential pipeline architecture at 20 MSPS data rates and guarantees no missing codes over the full operating temperature range. The AD9200 consumes 80 mW on a 3 V supply (excluding the reference power). In sleep mode, power is reduced to below 5 mW. Very Small Package The AD9200 is available in both a 28-lead SSOP and 48-lead LQFP packages. The input of the AD9200 has been designed to ease the development of both imaging and communications systems. The user can select a variety of input ranges and offsets and can drive the input either single-ended or differentially. Pin Compatible with AD876 The AD9200 is pin compatible with the AD876, allowing older designs to migrate to lower supply voltages. 300 MHz On-Board Sample-and-Hold The sample-and-hold (SHA) amplifier is equally suited for both multiplexed systems that switch full-scale voltage levels in successive channels and sampling single-channel inputs at frequencies up to and beyond the Nyquist rate. AC coupled input signals can be shifted to a predetermined level, with an onboard clamp circuit (AD9200ARS, AD9200KST). The dynamic performance is excellent. The versatile SHA input can be configured for either singleended or differential inputs. Out-of-Range Indicator The OTR output bit indicates when the input signal is beyond the AD9200’s input range. Built-In Clamp Function Allows dc restoration of video signals with AD9200ARS and AD9200KST. The AD9200 has an onboard programmable reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. FUNCTIONAL BLOCK DIAGRAM CLAMP CLAMP IN CLK AVDD DRVDD STBY SHA SHA GAIN SHA GAIN SHA GAIN SHA GAIN AIN MODE A/D REFTS A/D REFBS D/A A/D REFTF D/A A/D D/A A/D D/A THREESTATE CORRECTION LOGIC REFBF OUTPUT BUFFERS VREF REFSENSE 1V AD9200 OTR D9 (MSB) D0 (LSB) AVSS DRVSS REV. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD9200–SPECIFICATIONS Parameter (AVDD = +3 V, DRVDD = +3 V, FS = 20 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input Span from 0.5 V to 2.5 V, External Reference, TMIN to TMAX unless otherwise noted) Symbol Min RESOLUTION FS DC ACCURACY Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error DNL INL EZS EFS ANALOG INPUT Input Voltage Range Input Capacitance Aperture Delay Aperture Uncertainty (Jitter) Input Bandwidth (–3 dB) Full Power (0 dB) DC Leakage Current INTERNAL REFERENCE Output Voltage (1 V Mode) Output Voltage Tolerance (1 V Mode) Output Voltage (2 V Mode) Load Regulation (1 V Mode) POWER SUPPLY Operating Voltage Supply Current Power Consumption Power-Down Gain Error Power Supply Rejection Max 10 CONVERSION RATE REFERENCE VOLTAGES Top Reference Voltage Bottom Reference Voltage Differential Reference Voltage Reference Input Resistance1 Typ REFTS REFBS AIN CIN tAP tAJ BW MHz ± 0.5 ± 0.75 0.4 1.4 ±1 ±2 1.2 3.5 LSB LSB % FSR % FSR 2 10 4.2 AVDD V AVDD – 1 V V p-p kΩ kΩ REFBS 1 4 2 REFTS V pF ns ps 300 23 MHz µA 1 ± 10 2 0.5 VREF ± 25 2 3 3 26.6 80 4 PSRR 1 % FS 57 54 dB dB 9.1 8.6 Bits Bits 55 57 56 dB dB –59 –66 –58 dB dB –61 –69 –61 dB dB 68 0.1 0.05 dB Degree % 54.5 5.5 5.5 33.3 100 V mV V mV AVDD 2.7 DRVDD 2.7 IAVDD PD DYNAMIC PERFORMANCE (AIN = 0.5 dBFS) Signal-to-Noise and Distortion SINAD f = 3.58 MHz f = 10 MHz Effective Bits f = 3.58 MHz f = 10 MHz Signal-to-Noise SNR f = 3.58 MHz f = 10 MHz Total Harmonic Distortion THD f = 3.58 MHz f = 10 MHz Spurious Free Dynamic Range SFDR f = 3.58 MHz f = 10 MHz Two-Tone Intermodulation Distortion IMD Differential Phase DP Differential Gain DG Condition Bits 20 1 GND VREF Units –2– V V mA mW mW REFTS = 2.5 V, REFBS = 0.5 V REFTS, REFBS: MODE = AVDD Between REFTF and REFBF: MODE = AVSS REFBS Min = GND: REFTS Max = AVDD Switched Input = ± FS REFSENSE = VREF REFSENSE = GND 1 mA Load Current AVDD = 3 V, MODE = AVSS AVDD = DRVDD = 3 V, MODE = AVSS STBY = AVDD, MODE and CLOCK = AVSS f = 44.49 MHz and 45.52 MHz NTSC 40 IRE Mod Ramp REV. E AD9200 Parameter Symbol Min DIGITAL INPUTS High Input Voltage Low Input Voltage VIH VIL 2.4 DIGITAL OUTPUTS High-Z Leakage Data Valid Delay Data Enable Delay Data High-Z Delay IOZ tOD tDEN tDHZ –10 LOGIC OUTPUT (with DRVDD = 3 V) High Level Output Voltage (IOH = 50 µA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Low Level Output Voltage (IOL = 50 µA) VOH VOH VOL VOL +2.95 +2.80 LOGIC OUTPUT (with DRVDD = 5 V) High Level Output Voltage (IOH = 50 µA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Low Level Output Voltage (IOL = 50 µA) VOH VOH VOL VOL +4.5 +2.4 tCH tCL 22.5 22.5 CLOCKING Clock Pulsewidth High Clock Pulsewidth Low Pipeline Latency Typ Max Units 0.3 V V +10 25 25 13 +0.4 +0.05 V V V V +0.4 +0.1 V V V V ± 20 2 EOC tCPW Output = GND to VDD CL = 20 pF ns ns Cycles 3 CLAMP2 Clamp Error Voltage Clamp Pulsewidth µA ns ns ns Condition ± 40 mV µs CLAMPIN = 0.5 V–2.7 V, R IN = 10 Ω CIN = 1 µF (Period = 63.5 µs) NOTES 1 See Figures 1a and 1b. 2 Available only in AD9200ARS and AD9200KST. Specifications subject to change without notice. 10kV REFTS REFTS AD9200 AD9200 REFTF REFBS 4.2kV 10kV REFBF 0.4 3 VDD AVDD REFBS MODE MODE Figure 1a. REV. E Figure 1b. –3– AD9200 ABSOLUTE MAXIMUM RATINGS* Parameter With Respect to AVDD AVSS DRVDD DRVSS AVSS DRVSS AVDD DRVDD MODE AVSS CLK AVSS Digital Outputs DRVSS AIN AVSS VREF AVSS REFSENSE AVSS REFTF, REFTB AVSS REFTS, REFBS AVSS Junction Temperature Storage Temperature Lead Temperature 10 sec Min Max Units –0.3 –0.3 –0.3 –6.5 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 +6.5 +6.5 +0.3 +6.5 AVDD + 0.3 AVDD + 0.3 DRVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +150 +150 V V V V V V V V V V V V °C °C +300 °C –65 *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. ORDERING GUIDE Temperature Range Model AD9200JRS 0°C to +70°C AD9200ARS –40°C to +85°C AD9200JST 0°C to +70°C AD9200KST 0°C to +70°C AD9200JRSRL 0°C to +70°C AD9200ARSRL –40°C to +85°C AD9200JSTRL 0°C to +70°C AD9200KSTRL 0°C to +70°C AD9200 SSOP-EVAL AD9200 LQFP-EVAL Package Description Package Options* 28-Lead SSOP 28-Lead SSOP 48-Lead LQFP 48-Lead LQFP 28-Lead SSOP (Reel) 28-Lead SSOP (Reel) 48-Lead LQFP (Reel) 48-Lead LQFP (Reel) Evaluation Board Evaluation Board RS-28 RS-28 ST-48 ST-48 RS-28 RS-28 ST-48 ST-48 *RS = Shrink Small Outline; ST = Thin Quad Flatpack. AVDD DRVDD AVDD AVDD AVDD AVDD DRVSS AVSS AVSS DRVSS AVSS AVSS a. D0–D9, OTR AVSS b. Three-State, Standby, Clamp c. CLK AVDD AVDD REFTF REFBS AVDD AVSS AVSS AVDD AVDD REFTS REFBF AVSS AVSS AVSS d. AIN e. Reference AVDD AVDD AVDD AVSS f. CLAMPIN AVDD AVSS AVSS g. MODE h. REFSENSE AVSS i. VREF Figure 2. Equivalent Circuits CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9200 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. E AD9200 PIN CONFIGURATIONS VREF NC AIN NC NC NC AVDD 27 AIN AVSS NC 28 AVDD AVSS 1 DRVDD 2 NC DRVDD 48-Lead Plastic Thin Quad Flatpack (LQFP) NC 28-Lead Shrink Small Outline (SSOP) 48 47 46 45 44 43 42 41 40 39 38 37 D0 3 26 VREF D1 4 25 REFBS D0 1 36 NC 35 REFBS D2 3 34 REFBF TOP VIEW D4 7 (Not to Scale) 22 REFTF D3 4 33 NC D4 5 32 21 REFTS NC 6 AD9200 MODE D5 8 31 20 CLAMPIN NC 7 TOP VIEW (Not to Scale) NC D6 9 30 REFTF D5 8 D7 10 29 19 CLAMP REFTS D6 9 28 CLAMPIN D8 11 18 REFSENSE D7 10 27 CLAMP D9 12 17 STBY D8 11 26 REFSENSE 16 THREE-STATE D9 12 25 NC STBY CLK THREE-STATE NC 13 14 15 16 17 18 19 20 21 22 23 24 NC NC = NO CONNECT NC 15 CLK NC DRVSS 14 NC OTR 13 DRVSS 23 MODE NC 24 REFBF OTR AD9200 D3 6 NC D2 5 PIN 1 IDENTIFIER D1 2 PIN FUNCTION DESCRIPTIONS REV. E SSOP Pin No. LQFP Pin No. Name Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 44 45 1 2 3 4 5 8 9 10 11 12 16 17 22 23 24 26 27 28 29 30 32 34 35 38 39 42 AVSS DRVDD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 OTR DRVSS CLK THREE-STATE STBY REFSENSE CLAMP CLAMPIN REFTS REFTF MODE REFBF REFBS VREF AIN AVDD Analog Ground Digital Driver Supply Bit 0, Least Significant Bit Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9, Most Significant Bit Out-of-Range Indicator Digital Ground Clock Input HI: High Impedance State. LO: Normal Operation HI: Power-Down Mode. LO: Normal Operation Reference Select HI: Enable Clamp Mode. LO: No Clamp Clamp Reference Input Top Reference Top Reference Decoupling Mode Select Bottom Reference Decoupling Bottom Reference Internal Reference Output Analog Input Analog Supply –5– AD9200 DEFINITIONS OF SPECIFICATIONS Integral Nonlinearity (INL) Offset Error The first transition should occur at a level 1 LSB above “zero.” Offset is defined as the deviation of the actual first code transition from that point. Integral nonlinearity refers to the deviation of each individual code from a line drawn from “zero” through “full scale”. The point used as “zero” occurs 1/2 LSB before the first code transition. “Full scale” is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line. Gain Error The first code transition should occur for an analog value 1 LSB above nominal negative full scale. The last transition should occur for an analog value 1 LSB below the nominal positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between the first and last code transitions. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. It is often specified in terms of the resolution for which no missing codes (NMC) are guaranteed. Pipeline Delay (Latency) The number of clock cycles between conversion initiation and the associated output data being made available. New output data is provided every rising edge. (AVDD = +3 V, DRVDD = +3 V, FS = 20 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input Typical Characterization Curves Span from 0.5 V to 2.5 V, External Reference, unless otherwise noted) 60 1.0 –0.5 AMPLITUDE 55 –6.0 AMPLITUDE 50 0.5 SNR– dB DNL 45 0 –20.0 AMPLITUDE 40 35 30 –0.5 25 –1.0 0 128 256 384 512 640 CODE OFFSET 768 896 20 1.00E+05 1024 1.00E+06 1.00E+07 INPUT FREQUENCY – Hz 1.00E+08 Figure 5. SNR vs. Input Frequency Figure 3. Typical DNL 60 1.0 –0.5 AMPLITUDE 55 50 0.5 –6.0 AMPLITUDE SINAD – dB INL 45 0 40 –20.0 AMPLITUDE 35 30 –0.5 25 –1.0 0 128 256 384 512 640 CODE OFFSET 768 896 20 1.00E+05 1024 1.00E+06 1.00E+07 INPUT FREQUENCY – Hz 1.00E+08 Figure 6. SINAD vs. Input Frequency Figure 4. Typical INL –6– REV. E AD9200 –30 80.5 CLOCK = 20MHz –35 POWER CONSUMPTION – mW 80.0 –40 –20.0 AMPLITUDE THD – dB –45 –50 –6.0 AMPLITUDE –55 –60 –65 –0.5 AMPLITUDE –70 79.5 79.0 78.5 78.0 77.5 –75 –80 1.00E+05 77.0 1.00E+06 1.00E+07 INPUT FREQUENCY – Hz 1.00E+08 0 Figure 7. THD vs. Input Frequency 2 4 6 8 10 12 14 CLOCK FREQUENCY – MHz 16 18 20 Figure 10. Power Consumption vs. Clock Frequency (MODE = AVSS) –70 1M 900k FIN = 1MHz –60 800k 700k 600k –40 HITS THD – dB –50 –30 499856 500k 400k 300k –20 200k –10 100k 0 100E+03 10E+06 1E+06 CLOCK FREQUENCY – Hz 0 100E+06 Figure 8. THD vs. Clock Frequency 54383 N–1 54160 N CODE N+1 Figure 11. Grounded Input Histogram 1.005 20 1.004 0 CLOCK = 20MHz –20 1.003 VREF – V –40 1.002 –60 1.001 –80 1.000 –100 0.999 0.998 –40 –120 –20 0 20 40 TEMPERATURE – °C 60 80 –140 0E+0 1E+6 2E+6 3E+6 4E+6 5E+6 6E+6 7E+6 8E+6 9E+6 10E+6 SINGLE TONE FREQUENCY DOMAIN 100 Figure 9. Voltage Reference Error vs. Temperature REV. E Figure 12. Single-Tone Frequency Domain –7– SIGNAL AMPLITUDE – dB AD9200 0 APPLYING THE AD9200 –3 THEORY OF OPERATION The AD9200 implements a pipelined multistage architecture to achieve high sample rate with low power. The AD9200 distributes the conversion over several smaller A/D subblocks, refining the conversion with progressively higher accuracy as it passes the results from stage to stage. As a consequence of the distributed conversion, the AD9200 requires a small fraction of the 1023 comparators used in a traditional flash type A/D. A sample-and-hold function within each of the stages permits the first stage to operate on a new input sample while the second, third and fourth stages operate on the three preceding samples. –6 –9 –12 –15 –18 –21 –24 –27 1.0E+6 100.0E+6 10.0E+6 FREQUENCY – Hz OPERATIONAL MODES 1.0E+9 The AD9200 is designed to allow optimal performance in a wide variety of imaging, communications and instrumentation applications, including pin compatibility with the AD876 A/D. To realize this flexibility, internal switches on the AD9200 are used to reconfigure the circuit into different modes. These modes are selected by appropriate pin strapping. There are three parts of the circuit affected by this modality: the voltage reference, the reference buffer, and the analog input. The nature of the application will determine which mode is appropriate: the descriptions in the following sections, as well as the Table I should assist in picking the desired mode. Figure 13. Full Power Bandwidth 25 20 15 10 REFBS = 0.5V REFTS = 2.5V CLOCK = 20MHz IB – mA 5 0 –5 –10 –15 –20 –25 0 0.5 1.0 2.0 1.5 INPUT VOLTAGE – V 2.5 3.0 Figure 14. Input Bias Current vs. Input Voltage Table I. Mode Selection Modes Input Connect Input Span MODE Pin REFSENSE Pin TOP/BOTTOM AIN 1V AVDD AIN 2V AVDD CENTER SPAN AIN 1V AVDD/2 Short VREF and REFSENSE Together AIN 2V AVDD/2 AGND AIN Is Input 1 1V Differential REFTS and REFBS Are Shorted Together for Input 2 2V External Ref AIN REFBS Figure Short REFSENSE, REFTS and VREF Together AGND 18 AGND AGND 19 AVDD/2 AVDD/2 20 AVDD/2 AVDD/2 AVDD/2 Short VREF and REFSENSE Together AVDD/2 AVDD/2 AVDD/2 AGND No Connect AVDD/2 AVDD/2 No Connect Span = REFTS – REFBS (2 V max) 21, 22 Short to VREFTF Short to VREFBF 23 Short to VREFTF Short to VREFBF 30 2 V max AVDD REF Short REFTS and VREF Together No Connect AVDD AGND AD876 AIN 2V Float or AVSS REFTS AVDD No Connect –8– 29 REV. E AD9200 SUMMARY OF MODES VOLTAGE REFERENCE AIN 1 V Mode the internal reference may be set to 1 V by connecting REFSENSE and VREF together. REFTS 2 V Mode the internal reference my be set to 2 V by connecting REFSENSE to analog ground REFERENCE BUFFER Center Span Mode midscale is set by shorting REFTS and REFBS together and applying the midscale voltage to that point The MODE pin is set to AVDD/2. The analog input will swing about that midscale point. A/D CORE AD9200 External Divider Mode the internal reference may be set to a point between 1 V and 2 V by adding external resistors. See Figure 16f. External Reference Mode enables the user to apply an external reference to REFTS, REFBS and VREF pins. This mode is attained by tying REFSENSE to VDD. SHA REFBS Figure 15. AD9200 Equivalent Functional Input Circuit In single-ended operation, the input spans the range, REFBS ≤ AIN ≤ REFTS where REFBS can be connected to GND and REFTS connected to VREF. If the user requires a different reference range, REFBS and REFTS can be driven to any voltage within the power supply rails, so long as the difference between the two is between 1 V and 2 V. Top/Bottom Mode sets the input range between two points. The two points are between 1 V and 2 V apart. The Top/Bottom Mode is enabled by tying the MODE pin to AVDD. In differential operation, REFTS and REFBS are shorted together, and the input span is set by VREF, ANALOG INPUT where VREF is determined by the internal reference or brought in externally by the user. Differential Mode is attained by driving the AIN pin as one differential input and shorting REFTS and REFBS together and driving them as the second differential input. The MODE pin is tied to AVDD/2. Preferred mode for optimal distortion performance. Single-Ended is attained by driving the AIN pin while the REFTS and REFBS pins are held at dc points. The MODE pin is tied to AVDD. Single-Ended/Clamped (AC Coupled) the input may be clamped to some dc level by ac coupling the input. This is done by tying the CLAMPIN to some dc point and applying a pulse to the CLAMP pin. MODE pin is tied to AVDD. SPECIAL AD876 Mode enables users of the AD876 to drop the AD9200 into their socket. This mode is attained by floating or grounding the MODE pin. INPUT AND REFERENCE OVERVIEW Figure 16, a simplified model of the AD9200, highlights the relationship between the analog input, AIN, and the reference voltages, REFTS, REFBS and VREF. Like the voltages applied to the resistor ladder in a flash A/D converter, REFTS and REFBS define the maximum and minimum input voltages to the A/D. (REFTS – VREF/2) ≤ AIN ≤ (REFTS + VREF/2) The best noise performance may be obtained by operating the AD9200 with a 2 V input range. The best distortion performance may be obtained by operating the AD9200 with a 1 V input range. REFERENCE OPERATION The AD9200 can be configured in a variety of reference topologies. The simplest configuration is to use the AD9200’s onboard bandgap reference, which provides a pin-strappable option to generate either a 1 V or 2 V output. If the user desires a reference voltage other than those two, an external resistor divider can be connected between VREF, REFSENSE and analog ground to generate a potential anywhere between 1 V and 2 V. Another alternative is to use an external reference for designs requiring enhanced accuracy and/or drift performance. A third alternative is to bring in top and bottom references, bypassing VREF altogether. Figures 16d, 16e and 16f illustrate the reference and input architecture of the AD9200. In tailoring a desired arrangement, the user can select an input configuration to match drive circuit. Then, moving to the reference modes at the bottom of the figure, select a reference circuit to accommodate the offset and amplitude of a full-scale signal. Table I outlines pin configurations to match user requirements. The input stage is normally configured for single-ended operation, but allows for differential operation by shorting REFTS and REFBS together to be used as the second input. REV. E –9– AD9200 V* +FS MIDSCALE AD9200 AIN –FS SHA +F/S RANGE OBTAINED FROM VREF PIN OR EXTERNAL REF AD9200 AIN AVDD/2 REFTF 0.1mF 10kV REFTF 0.1mF 10kV MODE SHA MODE (AVDD) 10kV REFTS 10kV REFTS A2 REFBS A/D CORE 10kV –F/S RANGE OBTAINED FROM VREF PIN OR EXTERNAL REF 4.2kV TOTAL 0.1mF A2 REFBS 10kV 10mF INTERNAL REF 0.1mF 10kV A/D CORE 4.2kV TOTAL 0.1mF 10mF 0.1mF 10kV REFBF REFBF MIDSCALE OFFSET VOLTAGE IS DERIVED FROM INTERNAL OR EXTERNAL REF a. Top/Bottom Mode * MAXIMUM MAGNITUDE OF V IS DETERMINED BY INTERNAL REFERENCE b. Center Span Mode MAXIMUM MAGNITUDE OF V IS DETERMINED BY INTERNAL REFERENCE AND TURNS RATIO V AD9200 AIN MODE SHA AVDD/2 AVDD/2 REFTF 0.1mF 10kV 10kV REFTS A2 REFBS 10kV A/D CORE 0.1mF 4.2kV TOTAL 10mF INTERNAL 10kV REF 0.1mF REFBF c. Differential Mode VREF (2V) VREF (1V) A1 1V A1 0.01mF 1V 0.1mF 10kV 1.0mF 1.0mF REFSENSE REFSENSE AD9200 AVSS d. 1 V Reference A1 10kV AD9200 AVSS e. 2 V Reference VREF (= 1 + RA/RB) 1V RA 0.1mF 1.0mF A1 1V REFSENSE REFSENSE AVDD RB AD9200 VREF AD9200 AVSS INTERNAL 10K REF RESISTORS ARE SWITCHED OPEN BY THE PRESENSE OF RA AND RB. f. Variable Reference (Between 1 V and 2 V) g. Internal Reference Disable (Power Reduction) Figure 16. –10– REV. E AD9200 The actual reference voltages used by the internal circuitry of the AD9200 appear on REFTF and REFBF. For proper operation, it is necessary to add a capacitor network to decouple these pins. The REFTF and REFBF should be decoupled for all internal and external configurations as shown in Figure 17. Figure 19 shows the single-ended configuration for 2 V p-p operation. REFSENSE is connected to GND, resulting in a 2 V reference output. 2V AIN AD9200 SHA 0V REFTF 10mF 10kV AD9200 0.1mF REFTS REFBF 0.1mF AVDD 0.1mF REFTF 10kV A2 REFBS 0.1mF MODE A/D CORE 10kV 4.2kV TOTAL 0.1mF 10mF 0.1mF 10kV Figure 17. Reference Decoupling Network REFBF VREF Note: REFTF = reference top, force REFBF = reference bottom, force REFTS = reference top, sense REFBS = reference bottom, sense 1.0mF A1 1V 0.1mF REF SENSE INTERNAL REFERENCE OPERATION Figures 18, 19 and 20 show example hookups of the AD9200 internal reference in its most common configurations. (Figures 18 and 19 illustrate top/bottom mode while Figure 20 illustrates center span mode). Figure 29 shows how to connect the AD9200 for 1 V p-p differential operation. Shorting the VREF pin directly to the REFSENSE pin places the internal reference amplifier, A1, in unity-gain mode and the resultant reference output is 1 V. In Figure 18 REFBS is grounded to give an input range from 0 V to 1 V. These modes can be chosen when the supply is either +3 V or +5 V. The VREF pin must be bypassed to AVSS (analog ground) with a 1.0 µF tantalum capacitor in parallel with a low inductance, low ESR, 0.1 µF ceramic capacitor. 1V AIN AD9200 SHA 0V MODE Figure 19. Internal Reference, 2 V p-p Input Span (Top/Bottom Mode) Figure 20 shows the single-ended configuration that gives the good high frequency dynamic performance (SINAD, SFDR). To optimize dynamic performance, center the common-mode voltage of the analog input at approximately 1.5 V. Connect the shorted REFTS and REFBS inputs to a low impedance 1.5 V source. In this configuration, the MODE pin is driven to a voltage at midsupply (AVDD/2). Maximum reference drive is 1 mA. An external buffer is required for heavier loads. 2V AVDD AIN AD9200 SHA 1V REFTF 10kV REFTF A2 10kV REFTS A/D CORE 4.2kV TOTAL 0.1mF 10mF +1.5V A/D CORE 4.2kV TOTAL 0.1mF 10mF 0.1mF 10kV REFBF A1 VREF 1V REF SENSE 1.0mF Figure 18. Internal Reference 1 V p-p Input Span (Top/Bottom Mode) REV. E A2 10kV REFBF 0.1mF 10kV REFBS 0.1mF 10kV 1.0mF 0.1mF 10kV REFBS VREF AVDD/2 0.1mF 10kV REFTS MODE 0.1mF REF SENSE A1 1V Figure 20. Internal Reference 1 V p-p Input Span, (Center Span Mode) –11– AD9200 EXTERNAL REFERENCE OPERATION 4V VIN Using an external reference may provide more flexibility and improve drift and accuracy. Figures 21 through 23 show examples of how to use an external reference with the AD9200. To use an external reference, the user must disable the internal reference amplifier by connecting the REFSENSE pin to VDD. The user then has the option of driving the VREF pin, or driving the REFTS and REFBS pins. 2V REFTS REFTF 4V 10 F REFBF 2V 0.1 F 0.1 F MODE Figure 23a. External Reference—2 V p-p Input Span REFTS +5V 6 AD9200 SHA 1V REFT 10kV REFTF REFSENSE AVDD Figure 21 shows an example of the user driving the top and bottom references. REFTS is connected to a low impedance 2 V source and REFBS is connected to a low impedance 1 V source. REFTS and REFBS may be driven to any voltage within the supply as long as the difference between them is between 1 V and 2 V. AIN REFBS VREF The AD9200 contains an internal reference buffer (A2), that simplifies the drive requirements of an external reference. The external reference must simply be able to drive a 10 kΩ load. 2V AD9200 0.1 F 8 C4 0.1 F 7 REFTF 5 C3 0.1 F 0.1mF C2 10 F C6 0.1 F AD9200 REFBS 10kV REFTS 2V A2 REFBS 1V A/D CORE 10kV REF SENSE AVDD 4.2kV TOTAL C5 0.1 F 2 0.1mF 6 10mF REFB 3 4 REFBF C1 0.1 F 0.1mF 10kV MODE REFBF Figure 23b. Kelvin Connected Reference Using the AD9200 Figure 21. External Reference Mode—1 V p-p Input Span STANDBY OPERATION The ADC may be placed into a powered down (sleep) mode by driving the STBY (standby) pin to logic high potential and holding the clock at logic low. In this mode the typical power drain is approximately 4 mW. If there is no connection to the STBY pin, an internal pull-down circuit will keep the ADC in a “wake-up” mode of operation. Figure 22 shows an example of an external reference generating 2.5 V at the shorted REFTS and REFBS inputs. In this instance, a REF43 2.5 V reference drives REFTS and REFBS. A resistive divider generates a 1 V VREF signal that is buffered by A3. A3 must be able to drive a 10 kΩ, capacitive load. Choose this op amp based on noise and accuracy requirements. The ADC will “wake up” in 400 ns (typ) after the standby pulse goes low. AD9200 3.0V 2.5V 2.0V AIN AVDD CLAMP OPERATION AVDD REFTS 0.1mF REFBS 10mF REFTF 0.1mF 1.5kV 0.1mF A3 10mF VREF 1.0mF 0.1mF 0.1mF 0.1mF 1kV MODE +5V AVDD REFBF REFSENSE REF43 0.1mF AVDD/2 Figure 22. External Reference Mode—1 V p-p Input Span 2.5 VCM Figure 23a shows an example of the external references driving the REFTF and REFBF pins that is compatible with the AD876. REFTS is shorted to REFTF and driven by an external 4 V low impedance source. REFBS is shorted to REFBF and driven by a 2 V source. The MODE pin is connected to GND in this configuration. The AD9200ARS and AD9200KST parts feature an optional clamp circuit for dc restoration of video or ac coupled signals. Figure 24 shows the internal clamp circuitry and the external control signals needed for clamp operation. To enable the clamp, apply a logic high to the CLAMP pin. This will close the switch SW1. The clamp amplifier will then servo the voltage at the AIN pin to be equal to the clamp voltage applied at the CLAMPIN pin. After the desired clamp level is attained, SW1 is opened by taking CLAMP back to a logic low. Ignoring the droop caused by the input bias current, the input capacitor CIN will hold the dc voltage at AIN constant until the next clamp interval. The input resistor RIN has a minimum recommended value of 10 Ω, to maintain the closed-loop stability of the clamp amplifier. The allowable voltage range that can be applied to CLAMPIN depends on the operational limits of the internal clamp amplifier. When operating off of 3 volt supplies, the recommended clamp range is between 0.5 volts and 2.0 volts. –12– REV. E AD9200 The input capacitor should be sized to allow sufficient acquisition time of the clamp voltage at AIN within the CLAMP interval, but also be sized to minimize droop between clamping intervals. Specifically, the acquisition time when the switch is closed will equal: V T ACQ = RIN CIN ln C VE where VC is the voltage change required across CIN, and VE is the error voltage. VC is calculated by taking the difference between the initial input dc level at the start of the clamp interval and the clamp voltage supplied at CLAMPIN. VE is a systemdependent parameter, and equals the maximum tolerable deviation from VC. For example, if a 2-volt input level needs to be clamped to 1 volt at the AD9200’s input within 10 millivolts, then VC equals 2 – 1 or 1 volt, and VE equals 10 mV. Note that once the proper clamp level is attained at the input, only a very small voltage change will be required to correct for droop. back porch to truncate the SYNC below the AD9200’s minimum input voltage. With a CIN = 1 µF, and RIN = 20 Ω, the acquisition time needed to set the input dc level to one volt with 1 mV accuracy is about 140 µs, assuming a full 1 volt VC. With a 1 µF input coupling capacitor, the droop across one horizontal can be calculated: IBIAS = 10 µA, and t = 63.5 µs, so dV = 0.635 mV, which is less than one LSB. After the input capacitor is initially charged, the clamp pulsewidth only needs to be wide enough to correct small voltage errors such as the droop. The fine scale settling characteristics of the clamp circuitry are shown in Table II. Depending on the required accuracy, a CLAMP pulsewidth of 1 µs–3 µs should work in most applications. The OFFSET values ignore the contribution of offset from the clamp amplifier; they simply compare the output code with a “final value” measured with a much longer CLAMP pulse duration. The voltage droop is calculated with the following equation: Table II. () I dV = BIAS t CIN where t = time between clamping intervals. The bias current of the AD9200 will depend on the sampling rate, FS. The switched capacitor input AIN appears resistive over time, with an input resistance equal to 1/CSFS. Given a sampling rate of 20 MSPS and an input capacitance of 1 pF, the input resistance is 50 kΩ. This input resistance is equivalently terminated at the midscale voltage of the input range. The worst case bias current will thus result when the input signal is at the extremes of the input range, that is, the furthest distance from the midscale voltage level. For a 1-volt input range, the maximum bias current will be ± 0.5 volts divided by 50 kΩ, which is ± 10 µA. CLAMP OFFSET 10 µs 5 µs 4 µs 3 µs 2 µs 1 µs <1 LSB 5 LSBs 7 LSBs 11 LSBs 19 LSBs 42 LSBs AD9200 CLAMP IN CLAMP If droop is a critical parameter, then the minimum value of CIN should be calculated first based on the droop requirement. Acquisition time—the width of the CLAMP pulse—can be adjusted accordingly once the minimum capacitor value is chosen. A tradeoff will often need to be made between droop and acquisition time, or error voltage VE. CIN RIN SW1 AIN TO SHA Figure 24a. Clamp Operation Clamp Circuit Example AIN A single supply video amplifier outputs a level-shifted video signal between 2 and 3 volts with the following parameters: 0.1 F horizontal period = 63.56 µs, horizontal sync interval = 10.9 µs, horizontal sync pulse = 4.7 µs, sync amplitude = 0.3 volts, video amplitude of 0.7 volts, reference black level = 2.3 volts 10 F 0.1 F AD9200 0.1 F REFBF REFBS AVDD 2 MODE CLAMP The video signal must be dc restored from a 2- to 3-volt range down to a 1- to 2-volt range. Configuring the AD9200 for a one volt input span with an input range from 1 to 2 volts (see Figure 24), the CLAMPIN voltage can be set to 1 volt with an external voltage or by direct connection to REFBS. The CLAMP pulse may be applied during the SYNC pulse, or during the REV. E REFTF REFTS SHORT TO REFBS OR EXTERNAL DC CLAMPIN Figure 24b. Video Clamp Circuit –13– AD9200 DRIVING THE ANALOG INPUT Figure 25 shows the equivalent analog input of the AD9200, a sample-and-hold amplifier (switched capacitor input SHA). Bringing CLK to a logic low level closes Switches 1 and 2 and opens Switch 3. The input source connected to AIN must charge capacitor CH during this time. When CLK transitions from logic “low” to logic “high,” Switches 1 and 2 open, placing the SHA in hold mode. Switch 3 then closes, forcing the output of the op amp to equal the voltage stored on CH. When CLK transitions from logic “high” to logic “low,” Switch 3 opens first. Switches 1 and 2 close, placing the SHA in track mode. The structure of the input SHA places certain requirements on the input drive source. The combination of the pin capacitance, CP, and the hold capacitance, CH, is typically less than 5 pF. The input source must be able to charge or discharge this capacitance to 10-bit accuracy in one half of a clock cycle. When the SHA goes into track mode, the input source must charge or discharge capacitor CH from the voltage already stored on CH to the new voltage. In the worst case, a full-scale voltage step on the input, the input source must provide the charging current through the RON (50 Ω) of Switch 1 and quickly (within 1/2 CLK period) settle. This situation corresponds to driving a low input impedance. On the other hand, when the source voltage equals the value previously stored on CH, the hold capacitor requires no input current and the equivalent input impedance is extremely high. Adding series resistance between the output of the source and the AIN pin reduces the drive requirements placed on the source. Figure 26 shows this configuration. The bandwidth of the particular application limits the size of this resistor. To maintain the performance outlined in the data sheet specifications, the resistor should be limited to 20 Ω or less. For applications with signal bandwidths less than 10 MHz, the user may proportionally increase the size of the series resistor. Alternatively, adding a shunt capacitance between the AIN pin and analog ground can lower the ac load impedance. The value of this capacitance will depend on the source resistance and the required signal bandwidth. The input span of the AD9200 is a function of the reference voltages. For more information regarding the input range, see the Internal and External Reference sections of the data sheet. In many cases, particularly in single-supply operation, ac coupling offers a convenient way of biasing the analog input signal at the proper signal range. Figure 25 shows a typical configuration for ac-coupling the analog input signal to the AD9200. Maintaining the specifications outlined in the data sheet requires careful selection of the component values. The most important is the f –3 dB high-pass corner frequency. It is a function of R2 and the parallel combination of C1 and C2. The f –3 dB point can be approximated by the equation: f –3 dB = 1/(2 × pi × [R2] CEQ) where CEQ is the parallel combination of C1 and C2. Note that C1 is typically a large electrolytic or tantalum capacitor that becomes inductive at high frequencies. Adding a small ceramic or polystyrene capacitor (on the order of 0.01 µF) that does not become inductive until negligibly higher frequencies, maintains a low impedance over a wide frequency range. NOTE: AC coupled input signals may also be shifted to a desired level with the AD9200’s internal clamp. See Clamp Operation. C1 R1 VIN AIN R2 IB AD9200 C2 VBIAS Figure 27. AC Coupled Input There are additional considerations when choosing the resistor values. The ac-coupling capacitors integrate the switching transients present at the input of the AD9200 and cause a net dc bias current, IB, to flow into the input. The magnitude of the bias current increases as the signal magnitude deviates from V midscale and the clock frequency increases; i.e., minimum bias current flow when AIN = V midscale. This bias current will result in an offset error of (R1 + R2) × IB. If it is necessary to compensate this error, consider making R2 negligibly small or modifying VBIAS to account for the resultant offset. In systems that must use dc coupling, use an op amp to levelshift a ground-referenced signal to comply with the input requirements of the AD9200. Figure 28 shows an AD8041 configured in noninverting mode. CH +VCC AIN 0.1 F S1 CP SHA S3 S2 (REFTS REFBS) NC 0VDC CH 2 CP 1 AD8041 AD9200 Figure 25. AD9200 Equivalent Input Structure 20 6 AIN 5 3 MIDSCALE OFFSET VOLTAGE AD9200 7 1V p-p 4 NC Figure 28. Bipolar Level Shift < 20V AIN VS AD9200 Figure 26. Simple AD9200 Drive Configuration –14– REV. E AD9200 DIFFERENTIAL INPUT OPERATION The AD9200 will accept differential input signals. This function may be used by shorting REFTS and REFBS and driving them as one leg of the differential signal (the top leg is driven into AIN). In the configuration below, the AD9200 is accepting a 1 V p-p signal. See Figure 29. AD9200 2V AIN 1V AVDD/2 0.1mF REFTF REFTS 0.1mF REFBS The pipelined architecture of the AD9200 operates on both rising and falling edges of the input clock. To minimize duty cycle variations the recommended logic family to drive the clock input is high speed or advanced CMOS (HC/HCT, AC/ACT) logic. CMOS logic provides both symmetrical voltage threshold levels and sufficient rise and fall times to support 20 MSPS operation. The AD9200 is designed to support a conversion rate of 20 MSPS; running the part at slightly faster clock rates may be possible, although at reduced performance levels. Conversely, some slight performance improvements might be realized by clocking the AD9200 at slower clock rates. 10mF S1 0.1mF VREF 1.0mF 0.1mF S4 tC tCH REFSENSE S3 tCL INPUT CLOCK MODE AVDD/2 S2 ANALOG INPUT REFBF 25ns Figure 29. Differential Input DATA OUTPUT DATA 1 AD876 MODE OF OPERATION The AD9200 may be dropped into the AD876 socket. This will allow AD876 users to take advantage of the reduced power consumption realized when running the AD9200 on a 3.0 V analog supply. Figure 30 shows the pin functions of the AD876 and AD9200. The grounded REFSENSE pin and floating MODE pin effectively put the AD9200 in the external reference mode. The external reference input for the AD876 will now be placed on the reference pins of the AD9200. The clamp controls will be grounded by the AD876 socket. The AD9200 has a 3 clock cycle delay compared to a 3.5 cycle delay of the AD876. Figure 31. Timing Diagram The power dissipated by the output buffers is largely proportional to the clock frequency; running at reduced clock rates provides a reduction in power consumption. DIGITAL INPUTS AND OUTPUTS Each of the AD9200 digital control inputs, THREE-STATE and STBY are reference to analog ground. The clock is also referenced to analog ground. The format of the digital output is straight binary (see Figure 32). A low power mode feature is provided such that for STBY = HIGH and the clock disabled, the static power of the AD9200 will drop below 5 mW. 4V AIN 2V OTR AD9200 REFTS 4V REFTF 10mF 0.1mF REFBF 2V 0.1mF 0.1mF REFBS NC AVDD MODE REFSENSE CLAMP CLAMPIN OTR –FS+1LSB VREF 0.1mF Figure 30. AD876 Mode REV. E +FS–1LSB Figure 32. Output Data Format THREESTATE tDHZ CLOCK INPUT The AD9200 clock input is buffered internally with an inverter powered from the AVDD pin. This feature allows the AD9200 to accommodate either +5 V or +3.3 V CMOS logic input signal swings with the input threshold for the CLK pin nominally at AVDD/2. +FS –FS DATA (D0–D9) tDEN HIGH IMPEDANCE Figure 33. Three-State Timing Diagram –15– AD9200 APPLICATIONS DIRECT IF DOWN CONVERSION USING THE AD9200 Sampling IF signals above an ADC’s baseband region (i.e., dc to FS/2) is becoming increasingly popular in communication applications. This process is often referred to as Direct IF Down Conversion or Undersampling. There are several potential benefits in using the ADC to alias (i.e., or mix) down a narrowband or wideband IF signal. First and foremost is the elimination of a complete mixer stage with its associated amplifiers and filters, reducing cost and power dissipation. Second is the ability to apply various DSP techniques to perform such functions as filtering, channel selection, quadrature demodulation, data reduction, detection, etc. A detailed discussion on using this technique in digital receivers can be found in Analog Devices Application Notes AN-301 and AN-302. In Direct IF Down Conversion applications, one exploits the inherent sampling process of an ADC in which an IF signal lying outside the baseband region can be aliased back into the baseband region in a similar manner that a mixer will downconvert an IF signal. Similar to the mixer topology, an image rejection filter is required to limit other potential interfering signals from also aliasing back into the ADC’s baseband region. A tradeoff exists between the complexity of this image rejection filter and the sample rate as well as dynamic range of the ADC. The AD9200 is well suited for various narrowband IF sampling applications. The AD9200’s low distortion input SHA has a full-power bandwidth extending to 300 MHz thus encompassing many popular IF frequencies. A DNL of ± 0.5 LSB (typ) combined with low thermal input referred noise allows the AD9200 in the 2 V span to provide 60 dB of SNR for a baseband input sine wave. Also, its low aperture jitter of 2 ps rms ensures minimum SNR degradation at higher IF frequencies. In fact, the AD9200 is capable of still maintaining 56 dB of SNR at an IF of 135 MHz with a 1 V (i.e., 4 dBm) input span. Note, although the AD9200 will typically yield a 3 to 4 dB improvement in SNR when configured for the 2 V span, the 1 V span provides the optimum full-scale distortion performance. Furthermore, the 1 V span reduces the performance requirements of the input driver circuitry and thus may be more practical for system implementation purposes. G1 = 20dB SAW FILTER OUTPUT G2 = 12dB To maximize its distortion performance, the AD9200 is configured in the differential mode with a 1 V span using a transformer. The center tap of the transformer is biased at midsupply via a resistor divider. Preceding the AD9200 is a bandpass filter as well as a 32 dB gain stage. A large gain stage may be required to compensate for the high insertion losses of a SAW filter used for image rejection. The gain stage will also provide adequate isolation for the SAW filter from the charge “kick back” currents associated with AD9200’s input stage. The gain stage can be realized using one or two cascaded AD8009 op amps amplifiers. The AD8009 is a low cost, 1 GHz, current-feedback op amp having a 3rd order intercept characterized up to 250 MHz. A passive bandpass filter following the AD8009 attenuates its dominant 2nd order distortion products which would otherwise be aliased back into the AD9200’s baseband region. Also, it reduces any out-of-band noise which would also be aliased back due to the AD9200’s noise bandwidth of 220+ MHz. Note, the bandpass filters specifications are application dependent and will affect both the total distortion and noise performance of this circuit. The distortion and noise performance of an ADC at the given IF frequency is of particular concern when evaluating an ADC for a narrowband IF sampling application. Both single-tone and dual-tone SFDR vs. amplitude are very useful in an assessing an ADC’s noise performance and noise contribution due to aperture jitter. In any application, one is advised to test several units of the same device under the same conditions to evaluate the given applications sensitivity to that particular device. L-C 50V 50V 50V Figure 34 shows a simplified schematic of the AD9200 configured in an IF sampling application. To reduce the complexity of the digital demodulator in many quadrature demodulation applications, the IF frequency and/or sample rate are selected such that the bandlimited IF signal aliases back into the center of the ADC’s baseband region (i.e., FS/4). For example, if an IF signal centered at 45 MHz is sampled at 20 MSPS, an image of this IF signal will be aliased back to 5.0 MHz which corresponds to one quarter of the sample rate (i.e., FS/4). This demodulation technique typically reduces the complexity of the post digital demodulator ASIC which follows the ADC. BANDPASS FILTER MINI CIRCUITS T4 - 6T 1:4 200V AD9200 AIN 200V 280V REFTS REFBS 22.1V 93.1V VREF 1.0mF 0.1mF REFSENSE 1kV AVDD 1kV 0.1mF Figure 34. Simplified AD9200 IF Sampling Circuit –16– REV. E AD9200 Figures 35–38 combine the dual-tone SFDR as well as single tone SFDR and SNR performance at IF frequencies of 45 MHz, 70 MHz, 85 MHz and 135 MHz. Note, the SFDR vs. amplitude data is referenced to dBFS while the single tone SNR data is referenced to dBc. The performance characteristics in these figures are representative of the AD9200 without the AD8009. The AD9200 was operated in the differential mode (via transformer) with a 1 V span at 20 MSPS. The analog supply (AVDD) and the digital supply (DRVDD) were set to +5 V and 3.3 V, respectively. Although not presented, data was also taken with the insertion of an AD8009 gain stage of 32 dB in the signal path. No degradation in two-tone SFDR vs. amplitude was noted at an IF of 45 MHz, 70 MHz and 85 MHz. However, at 135 MHz, the AD8009 became the limiting factor in the distortion performance until the two input tones were decreased to –15 dBFS from their full-scale level of –6.5 dBFS. Note: the SNR performance in each case degraded by approximately 0.5 dB due to the AD8009’s in-band noise contribution. 90 80 DUAL TONE SFDR 70 SINGLE TONE SFDR 80 WORST CASE SPURIOUS – dBFS SNR – dBc WORST CASE SPURIOUS – dBFS SNR – dBc 90 60 50 40 30 SNR 20 10 0 –60 –50 CLK = 20MSPS SINGLE TONE – 45.52MHz DUAL TONE – F1 = 44.49MHz – F2 = 45.52MHz –40 –20 –30 INPUT POWER LEVEL – dBFS –10 50 40 30 SNR 20 CLK = 20MSPS SINGLE TONE – 85.52MHz DUAL TONE – F1 = 84.49MHz – F2 = 85.52MHz –50 –40 –20 –30 INPUT POWER LEVEL – dBFS –10 0 Figure 37. SNR/SFDR for IF @ 85 MHz 90 SINGLE TONE SFDR 80 WORST CASE SPURIOUS – dBFS SNR – dBc 80 WORST CASE SPURIOUS – dBFS SNR – dBc DUAL TONE SFDR 60 0 –60 0 90 70 DUAL TONE SFDR 60 50 40 30 SNR 20 CLK = 21.538MSPS SINGLE TONE – 70.55MHz DUAL TONE – F1 = 69.50MHz – F2 = 70.55MHz 10 –50 –40 –20 –30 INPUT POWER LEVEL – dBFS –10 DUAL TONE SFDR 70 60 SINGLE TONE SFDR 50 40 30 SNR 20 CLK = 20MSPS SINGLE TONE – 135.52MHz DUAL TONE – F1 = 134.44MHz – F2 = 135.52MHz 10 0 –60 0 Figure 36. SNR/SFDR for IF @ 70 MHz REV. E 70 10 Figure 35. SNR/SFDR for IF @ 45 MHz 0 –60 SINGLE TONE SFDR –50 –30 –40 –20 INPUT POWER LEVEL – dBFS –10 Figure 38. SNR/SFDR for IF @ 135 MHz –17– 0 AD9200 R11 15kV R10 5kV +3–5A +3–5A TP14 R7 5.49kV 5 XXXX ADJ. R8 10kV D1 AD1580 2 3 CW 4 6 1 AD822 U2 7 AD822 U2 8 C7 0.1mF C8 10/10V R9 1.5kV R17 316V R15 1kV 0.626V TO 4.8V Q1 2N3906 TP16 EXTT C11 0.1mF C13 10/10V C12 0.1mF R19 178V +3–5A CM R13 11kV R12 10kV XXXX ADJ. 2 R14 10kV 3 CW R20 178V C29 0.1mF TP17 4 8 5 C10 0.1mF C9 10/10V EXTB 6 1 AD822 U3 7 AD822 U3 C14 0.1mF Q2 2N3904 R16 1kV C15 10/10V R18 316kV +3–5A TP11 J7 JP5 CLAMP R37 1kV R53 49.9V DRVDD B JP17 R38 1kV 1 S3 2 THREE-STATE 3 B1 A S4 2 3 A GND JP18 R39 1kV STBY 7 DRVDD AVDD C16 0.1mF 2 DRVDD U1 AD9200 OTR 15 16 17 18 19 20 21 22 23 24 25 26 27 6 CLK THREE-STATE STBY REFSENSE CLAMP CLAMPIN REFTS REFTF MODE REFBF REFBS VREF AIN AVSS 1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 11 27 J8 25 J8 11 J8 RN1 22V C18 10/10V 28 AVDD C33 + 10/10V 13 J8 C19 0.1mF C17 10/10V DUTCLK THREE-STATE STBY REFSENSE CLAMP CLAMPIN REFTS REFTF MODE REFBF REFBS VREF AIN 10 RN1 22V 5 12 9 J8 RN1 22V OTR TP19 WHITE D5 D6 D7 D8 D9 13 3 4 5 6 7 8 9 10 11 12 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DRVDD C40 0.1mF 16 15 21 20 19 18 17 14 24 23 22 13 GND GND B U4 A B U4 A B U4 A B U4 A B U4 A B U4 A B U4 A B U4 A VCCB VCCA NC1 T/R OE GD2 GD1 U4 GD3 8 9 3 4 5 6 7 10 1 2 11 12 4 2 B1 +3–5D CLK D0 D1 D2 D3 D4 DRVSS 14 DRVDD C41 0.1mF GND GND B U5 A B U5 A B U5 A B U5 A B U5 A B U5 A B U5 A B U5 A VCCB VCCA NC1 T/R GD2 OE GD1 U5 GD3 74LVXC4245WM 3 GND J8 S2 2 15 5 +3–5D 2 J8 16 C42 0.1mF J8 20 J8 24 J8 33 J8 5 12 26 J8 NC +3–5D 28 J8 23 J8 29 J8 31 J8 RN2 22V 34 J8 3 14 NC 19 J8 RN2 22V C43 0.1mF 35 J8 36 J8 NC 37 J8 38 J8 15 17 J8 RN2 22V 1 GND 32 J8 21 J8 GND 2 1 JP20 30 J8 13 2 39 J8 CLK_OUT RN2 22V C21 0.1mF J8 22 J8 11 RN2 22V 4 J8 8 18 J8 1 CLK WHITE 6 J8 6 14 J8 RN1 22V GND 5 4 3 6 7 8 9 10 1 2 11 12 J8 4 16 J8 1 A JP21 1 J8 2 10 J8 12 J8 RN1 22V 3 C20 0.1mF 3 19 20 21 18 17 16 15 14 24 23 22 13 7 RN1 22V GND 74LVXC4245WM 13 3 16 RN2 22V 40 J8 15 J8 Figure 39a. Evaluation Board Schematic –18– REV. E AD9200 REFSENSE JP1 JP10 AVDD TP1 JP2 C3 0.1 F JP3 C5 10/10V JP14 AVDD EXTB R5 10k TP3 MODE JP15 REFBF JP9 C4 TP4 0.1 F + C6 0.1 F JP4 VREF TP5 B 1 S5 JP16 GND EXTT 2 JP11 TP6 AVDD R34 2k REFTS JP12 C37 C38 C36 C35 10/10V 0.1 F 0.1 F 0.1 F TP7 GND R35 4.99k EXTT JP6 GND CW R36 4.99k 1 REFBS JP7 C30 0.1 F AIN J5 4 2 S8 1 B R1 49.9 TP8 JP8 C2 47/10V R2 100 A 3 S1 1 B S7 2 A A R3 100 TP9 3 CM U6 TP10 DCIN L4 U6 DECOUPLING AVDDCLK +3–5D J9 C31 10/10V C32 0.1 F 74AHC14 L1 J2 DRVDD C22 0.1 F 14 PWR U6 GND C23 10/10V 9 7 11 13 AVDD C24 0.1 F C25 33/16V TP22 L3 +3–5A J4 C26 0.1 F C27 10/10V TP23 TP24 TP25 TP26 TP27 TP28 GND J6 GND J10 Figure 39b. Evaluation Board Schematic REV. E –19– U6 8 C28 0.1 F L2 J3 R51 49.9 CLK TP29 TP21 S6 2 3 3 1 B TP20 6 REFBS T1 2 U6 R4 49.9 1 JP26 C1 0.1 F 5 TP12 1B ADC_CLK 6 P S 2 EXTB 3 A 3 U6 GND JP13 T1–1T 2 AVDDCLK JP22 CLAMPIN 3 A J1 R6 10k REFTF U6 U6 10 12 4 R52 49.9 TP13 DUTCLK AD9200 Figure 40a. Evaluation Board, Component Signal (Not to Scale) Figure 40b. Evaluation Board, Solder Signal (Not to Scale) –20– REV. E AD9200 Figure 40c. Evaluation Board Power Plane (Not to Scale) Figure 40d. Evaluation Board Ground Plane (Not to Scale) REV. E –21– AD9200 Figure 40e. Evaluation Board Component Silk (Not to Scale) Figure 40f. Evaluation Board Solder Silk (Not to Scale) –22– REV. E AD9200 GROUNDING AND LAYOUT RULES DIGITAL OUTPUTS As is the case for any high performance device, proper grounding and layout techniques are essential in achieving optimal performance. The analog and digital grounds on the AD9200 have been separated to optimize the management of return currents in a system. Grounds should be connected near the ADC. It is recommended that a printed circuit board (PCB) of at least four layers, employing a ground plane and power planes, be used with the AD9200. The use of ground and power planes offers distinct advantages: Each of the on-chip buffers for the AD9200 output bits (D0–D9) is powered from the DRVDD supply pins, separate from AVDD. The output drivers are sized to handle a variety of logic families while minimizing the amount of glitch energy generated. In all cases, a fan-out of one is recommended to keep the capacitive load on the output data bits below the specified 20 pF level. 1. The minimization of the loop area encompassed by a signal and its return path. 2. The minimization of the impedance associated with ground and power paths. 3. The inherent distributed capacitor formed by the power plane, PCB insulation and ground plane. These characteristics result in both a reduction of electromagnetic interference (EMI) and an overall improvement in performance. It is important to design a layout that prevents noise from coupling onto the input signal. Digital signals should not be run in parallel with the input signal traces and should be routed away from the input circuitry. Separate analog and digital grounds should be joined together directly under the AD9200 in a solid ground plane. The power and ground return currents must be carefully managed. A general rule of thumb for mixed signal layouts dictates that the return currents from digital circuitry should not pass through critical analog circuitry. REV. E For DRVDD = 5 V, the AD9200 output signal swing is compatible with both high speed CMOS and TTL logic families. For TTL, the AD9200 on-chip, output drivers were designed to support several of the high speed TTL families (F, AS, S). For applications where the clock rate is below 20 MSPS, other TTL families may be appropriate. For interfacing with lower voltage CMOS logic, the AD9200 sustains 20 MSPS operation with DRVDD = 3 V. In all cases, check your logic family data sheets for compatibility with the AD9200 Digital Specification table. THREE-STATE OUTPUTS The digital outputs of the AD9200 can be placed in a high impedance state by setting the THREE-STATE pin to HIGH. This feature is provided to facilitate in-circuit testing or evaluation. –23– AD9200 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead Plastic Thin Quad Flatpack (LQFP) (ST-48) 0.063 (1.60) MAX 37 36 0.276 (7.0) BSC 48 1 SEATING PLANE TOP VIEW (PINS DOWN) 0.006 (0.15) 0.002 (0.05) 0° – 7° 0° MIN 0.007 (0.18) 0.004 (0.09) C3033e–0–8/99 0.276 (7.0) BSC 12 13 0.354 (9.00) BSC 0.030 (0.75) 0.018 (0.45) 0.354 (9.00) BSC 0.030 0.057 (0.75) (1.45) 0.018 (1.35) (0.45) 0.053 25 24 0.019 (0.5) BSC 0.011 (0.27) 0.006 (0.17) 28-Lead Shrink Small Outline Package (SSOP) (RS-28) 0.407 (10.34) 0.397 (10.08) 15 1 14 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.21) 28 0.07 (1.79) 0.066 (1.67) 0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC 0.015 (0.38) 0.010 (0.25) SEATING 0.009 (0.229) PLANE 0.005 (0.127) 8° 0° 0.03 (0.762) 0.022 (0.558) PRINTED IN U.S.A. 0.078 (1.98) PIN 1 0.068 (1.73) –24– REV. E