B9947 3.3V, 160-MHz, 1:9 Clock Distribution Buffer Product Features • • • • • • • • • Description 160-MHz Clock Support LVCMOS/LVTTL Compatible Inputs 9 Clock Outputs: Drive up to 18 Clock Lines Synchronous Output Enable Output Three-state Control 350-ps Maximum Output-to-Output Skew Pin Compatible with MPC947 Industrial Temp. Range: –40°C to +85°C 32-Pin TQFP Package The B9947 is a low-voltage clock distribution buffer with the capability to select one of two LVCMOS/LVTTL compatible clock inputs. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible. The nine outputs are 3.3V LVCMOS or LVTTL compatible and can drive two series terminated 50Ω transmission lines. With this capability the B9947 has an effective fanout of 1:18. The outputs can also be three-stated via the three-state input TS#. Low output-to-output skews make the B9947 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. The B9947 also provides a synchronous output enable input for enabling or disabling the output clocks. Since this input is internally synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. Pin Configuration TCLK0 TCLK1 VDDC 0 9 32 31 30 29 28 27 26 25 VDD VSS VDDC Q0 VSS Q1 VDDC Q2 VSS Block Diagram Q0-Q8 VSS TCLK_SEL TCLK0 TCLK1 SYNC_OE TS# VDD VSS 1 TCLK_SEL SYNC_OE B9947 24 23 22 21 20 19 18 17 VSS Q3 VDDC Q4 VSS Q5 VDDC VSS VSS VDDC Q8 VSS Q7 VDDC Q6 VSS 9 10 11 12 13 14 15 16 TS# 1 2 3 4 5 6 7 8 Cypress Semiconductor Corporation Document #: 38-07078 Rev. *C • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 22, 2002 B9947 Pin Description Pin Name PWR I/O Description 3 TCLK0 I, PU Test Clock Input 4 TCLK1 I, PU Test Clock Input 2 TCLK_SEL I, PU Test Clock Select Input. When LOW, TCLK0 is selected. When asserted HIGH, TCLK1 is selected. 11, 13, 15, 19, 21, 23, 26, 28, 30 Q(8:0) 5 SYNC_OE I, PU Output Enable Input. When asserted HIGH, the outputs are enabled and when set LOW the outputs are disabled in a LOW state. 6 TS# I, PU Three-state Control Input. When asserted LOW, the output buffers are three-stated. When set HIGH, the output buffers are enabled. 10, 14, 18, 22, 27, 31 VDDC 3.3V Power Supply for Output Clock Buffers 7 VDD 3.3V Power Supply 1, 8, 9, 12, 16, 17, 20, 24, 25, 29, 32 VSS Common Ground VDDC O Clock Outputs Note: 1. PU = Internal Pull-Up. Output Enable/Disable The B9947 features a control input to enable or disable the outputs. This data is latched on the falling edge of the input clock. When SYNC_OE is asserted LOW, the outputs are disabled in a LOW state. When SYNC_OE is set HIGH, the outputs are enabled as shown in Figure 1. TCLK SYNC_OE Q Figure 1. SYNC_OE Timing Diagram Document #: 38-07078 Rev. *C Page 2 of 5 B9947 Maximum Ratings[2] Maximum Input Voltage Relative to VDD:............. VDD + 0.3V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: Storage Temperature: ................................–65°C to + 150°C VSS < (Vin or Vout) < VDD Operating Temperature: ................................ –40°C to +85°C Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Maximum Input Voltage Relative to VSS: ............ VSS – 0.3V Maximum ESD protection .............................................. 2 KV Maximum Power Supply: ................................................5.5V Maximum Input Current:..................................................±20 mA DC Parameters: VDDC = 3.3V ±10%, VDD = 3.3V ±10%, TA = –40°C to +85°C Parameter Description Conditions Min. Typ. Max. Unit Input Low Voltage VSS 0.8 V Input High Voltage 2.0 VDD V –100 µA 10 µA 0.4 V IIL Input Low Current (@VIL = VSS) Note 3 IIH Input High Current (@VIL =VDD) VOL Output Low Voltage IOL = 20 mA, Note 4 VOH Output High Voltage IOH = –20 mA, VDDC = 3.3V, Note 4 IDD Quiescent Supply Current All VDDC and VDD Cin Input Capacitance 2.5 V 1 2 mA 4 pF AC Parameters[5]: VDDC = 3.3V ±10%, VDD = 3.3V ±10%, TA = –40°C to +85°C Parameter Description Conditions Min. Typ. Max. Unit Fmax Maximum Input Frequency[6] 160 Tpd TCLK to Q Delay[6] 4.75 FoutDC Output Duty Cycle[6,7] tpZL, tpZH Output Enable Time (all outputs) 2 10 ns tpLZ, tpHZ Output Disable Time (all outputs) 2 10 ns Tskew Output-to-Output Skew[6,9] 350 ps Tskew (pp) Part to Part Skew[10] 2.0 ns Ts Set-up Time[6,8] SYNC_OE to TCLK 0.0 ps Th Hold Time[6,8] TCLK to SYNC_OE 1.0 ps Tr/Tf Output Clocks Rise/Fall Time[9] 0.8V to 2.0V 0.20 Measured at VDDC/2 TCYCLE/2 – 800 MHz 9.25 ns TCYCLE/2 + 800 ps 1.0 ns Notes: 2. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Inputs have pull-up resistors that effect input current. 4. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines. 5. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 6. Outputs driving 50Ω transmission lines. 7. 50% input duty cycle. 8. Set-up and Hold times are relative to the falling edge of the input clock 9. Outputs loaded with 30pF each 10. Part to Part Skew at a given temperature and voltage Document #: 38-07078 Rev. *C Page 3 of 5 B9947 Package Drawing and Dimensions 32-Pin TQFP Outline Dimensions Inches D D1 12° A1 Symbol Min. Nom. Max. Min. Nom. Max. A - - 0.047 - - 1.20 A1 0.002 - 0.006 0.05 - 0.15 A2 0.037 - 0.041 0.95 - 1.05 D - 0.354 - - 9.00 - D1 - 0.276 - - 7.00 - b 0.012 - 0.018 0.30 - 0.45 e L L e Millimeters 0.031 BSC 0.018 - 0.80 BSC 0.030 0.45 - 0.75 b Ordering Information Part Number[11] B9947CA Package Type 32-Pin TQFP Production Flow Industrial, –40°C to +85°C Note: 11. The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: Cypress B9947CA Date Code, Lot # B9947CA Package A = TQFP Revision Device Number Document #: 38-07078 Rev. *C Page 4 of 5 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. B9947 Document Title: B9947 3.3V, 160-MHz, 1:9 Clock Distribution Buffer Document Number: 38-07078 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 107114 06/06/01 IKA Convert from IMI to Cypress *A 108058 07/03/01 NDP Changed Commercial to Industrial (See page 6) *B 109804 01/31/02 DSG Convert from Word to Frame *C 122763 12/22/02 RBI Add power up requirements to maximum ratings information Document #: 38-07078 Rev. *C Page 5 of 5