HANBit HDD32M64F8K DDR SDRAM Module 256Mbyte (32Mx64bit), based on16Mx8,4Banks, 4K Ref., SMM, Part No. HDD32M64F8K GENERAL DESCRIPTION The HDD32M64F8K is a 32M x 64 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory module. The module consists of sixteen CMOS 16M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages and 2K EEPROM in 8-pin TSSOP package on a 200-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The HSD32M64F8K is a SMM(Stackable Memory Module type) .Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. All module components may be powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible. FEATURES • Part Identification HDD32M64F8K – 10A : 100MHz (CL=2) HDD32M64F8K – 13A : 133MHz (CL=2) HDD32M64F8K – 13B : 133MHz (CL=2.5) • 256MB(32Mx64) Unbuffered DDR SMM based on 16Mx8 DDR SDRSM • 2.5V ± 0.2V VDD and VDDQ power supply • Auto & self refresh capability (4096 Cycles/64ms) • All input and output are compatible with SSTL_2 interface • Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock • All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock • MRS cycle with address key programs - Latency (Access from column address) : 2, 2.5 - Burst length : 2, 4, 8 - Data scramble : Sequential & Interleave • Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock • All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock • The used device is 4M x 8bit x 4Banks DDR SDRAM URL : www.hbe.co.kr REV 1.0 (August.2002) 1 HANBit Electronics Co.,Ltd. HANBit HDD32M64F8K PIN ASSIGNMENT P1 P2 PIN Symbol PIN Symbol PIN Symbol PIN Symbol PIN Symbol PIN Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 /CS0 /CS1 VSS CKE0 CKE1 NC VDD CK0 CK1 NC VSS NC DM0 DM4 VDDQ NC NC VSS NC DQS0 DQS4 VDD NC DQ0 DQ1 VSS DQ2 DQ3 VDDQ DQ4 DQ5 DQ6 VSS DQ7 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 DQ15 DQ14 VDDQ DQ13 DQ12 DQ11 VSS DQ10 DQ9 DQ8 VDD *SA0 *SA1 VSS *SA2 VDDQ VDD /RAS VSS /CAS /CK0 /CK1 VDD /CK2 CK2 /WE VSS NC DM1 DM5 VDDQ NC VREF VSS 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 NC DQS1 DQS5 VDD NC DQ39 DQ38 VSS DQ37 DQ36 VDDQ DQ35 DQ34 DQ33 VSS DQ32 DQ40 DQ41 VDDQ DQ42 DQ43 DQ44 VSS DQ45 DQ46 DQ47 *SCL *WP *VSPD VSS *SDA VDDIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VDDQ A3 VSS A2 A1 A0 VDD A10 A11 BA0 VSS BA1 DM2 DM6 VDDQ NC NC VSS DQS7 DQS2 NC VDD DQ31 DQ30 DQ29 VSS DQ28 DQ27 VDDQ DQ26 DQ25 DQ24 VSS DQ16 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 DQ17 DQ18 VDDQ DQ19 DQ20 DQ21 VSS DQ22 DQ23 NC(CB6) VDD NC(CB4) NC(CB2) VSS NC(CB0) VDDQ VDD A4 VSS A5 A6 A7 VDD A8 A9 NC(A12) VSS DM3 DM7 NC(DM8) VDDQ NC NC(A13) VSS 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 NC(DQS8) DQS3 DQS6 VDD DQ56 DQ57 DQ58 VSS DQ59 DQ60 VDDQ DQ61 DQ62 DQ63 VSS DQ55 DQ54 DQ53 VDDQ DQ52 DQ51 DQ50 VSS DQ49 DQ48 NC(CB7) VDD NC(CB5) NC(CB3) VSS NC(CB1) VDD * These pins should be NC in the system which does not support SPD PIN PIN DESCRIPTION PIN PIN DESCRIPTION A0~A11 Address input VDD Power supply(2.5V) BA0~BA1 Bank Select Address VDDQ Power supply for DQs(2.5V) DQ0~DQ63 Data input/output VREF Power supply for reference Serial EEPROM Power supply(3.3) CB0~CB7 Check bit(Data input/output) VSPD DQS0~DQS7 Data Strobe input/output VSS Ground DM0~DM7 Data-in Mask SA0~SA2 Address in EEPROM CK0~CK2,/CK0~/CK2 Clock input SDA Serial data I/O CKE0~CKE1 Clock enable input SCL Serial clock /CS0~/CS1 Chip Select input WP Write protection /RAS Row Address strobe VDDIN VDD indentification flag /CAS Column Address strobe NC No connection URL : www.hbe.co.kr REV 1.0 (August.2002) 2 HANBit Electronics Co.,Ltd. HANBit HDD32M64F8K FUNCTIONAL BLOCK DIAGRAM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 U1 U2 U3 U4 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 U10 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 U11 U5 U6 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 U13 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 U14 U8 U9 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 U15 U16 U18 U19 Stacking 의 상 위 URL : www.hbe.co.kr REV 1.0 (August.2002) 3 부분 위 치 HANBit Electronics Co.,Ltd. HANBit HDD32M64F8K PIN FUNCTION DESCRIPTION Pin CK, /CK Name Clock Input Function CK and CK are differential clock inputs. All address and control input signals are sam-pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/CK. CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE CKE Clock Enable POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled during power-down and self refresh modes, providing low standby power. CKE will recognizean LVCMOS LOW level prior to VREF being stable on power-up. CS enables(registered LOW) and disables(registered HIGH) the command decoder. /CS Chip Select All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Row/column addresses are multiplexed on the same pins. A0 ~ A11 Address BA0 ~ BA1 Bank select address /RAS Row address strobe /CAS Columnaddress strobe /WE Write enable DQS0 ~ 7 Data Strobe Row address : RA0 ~ RA11, Column address : CA0 ~ CA9 BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE command is being applied. Latches row addresses on the positive going edge of the CLK with /RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with /CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from /CAS, /WE active. Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled DM0~7 Input Data Mask on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load-ing. DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. WP pin is connected to Vcc. WP Write Protection When WP is “high”, EEPROM Programming will be inhibited and the entire memory will be write-protected. VDDQ Supply DQ Power Supply : +2.5V ± 0.2V. VDD Supply Power Supply : +2.5V ± 0.2V (device specific). VSS Supply DQ Ground. VREF Supply SSTL_2 reference voltage. URL : www.hbe.co.kr REV 1.0 (August.2002) 4 HANBit Electronics Co.,Ltd. HANBit HDD32M64F8K ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNTE VIN, VOUT -o.5 ~ 3.6 V Voltage on VDD supply relative to Vss VDD -1.0 ~ 3.6 V Voltage on VDDQ supply relative to Vss VDDQ -0.5 ~ 3.6 V Storage temperature TSTG -55 ~ +150 °C PD 16.0 W Voltage on any pin relative to Vss Power dissipation Short circuit current IOS 50 Notes: Operation at above absolute maximum rating can adversely affect device reliability mA DC OPERATING CONDITIONS (Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C) ) PARAMETER SYMBOL MIN MAX UNIT VDD 2.3 2.7 V VDDQ 2.3 2.7 V I/O Reference Voltage VREF 1.15 1.35 V 1 I/O Termination Voltage(system) VTT VREF – 0.04 VREF + 0.04 V 2 Input High Voltage VIH (DC) VREF + 0.15 VREF + 0.3 V Input Low Voltage VIL (DC) -0.3 VREF - 0.15 V Input Voltage Level, CK and /CK inputs VIN (DC) -0.3 VDDQ + 0.3 V Input Differential Voltage, CK and /CK inputs VID (DC) 0.3 VDDQ + 0.6 V Input leakage current I LI -2 2 uA Output leakage current I OZ -5 5 uA Output High current (VOUT = 1.95V) I OH -16.8 Supply Voltage I/O Supply Voltage 3 mA Output Low current (VOUT = 0.35V) I OL 16.8 Notes : 1.Typically, the value of VREF is expected to be about 0.5* VDD of the transmitting device. VREF is expected to track variation in VDDQ . 2.Peak to peak AC noise on VREF may not exceed 2% VREF (DC). 3.VTT of the transmitting device must track VREF of the receiving device. CAPACITANCE NOTE mA (VDD = min to max, VDDQ = 2.5V to 2.7V, TA = 25°C, f = 100MHz) DESCRIPTION SYMBO MIN MAX UNITS L Input capacitance(A0~A11, BA0~BA1, /RAS, /CAS,/WE) CIN1 93 107 pF Input capacitance(CKE0,CKE1) CIN2 63 77 pF Input capacitance(/CS0~/CS1) CIN3 58 72 pF Input capacitance(CLK0, CLK1,CLK2) CIN4 30 45 pF Input capacitance(DM0~DM7) CIN5 10 15 pF COUT1 10 15 pF Data input/output capacitance (DQ0 ~ DQ63, DQS0~DQS7) URL : www.hbe.co.kr REV 1.0 (August.2002) 5 HANBit Electronics Co.,Ltd. HANBit HDD32M64F8K DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, VDD = 2.5V, T =25°C) SYMBO TEST VERSION L CONDITION UNIT NOTE PARAMETER -10A -13A -13B mA Burst length = 2 Operating current (One bank active) tRC ≥ tRC(min), CL=2.5 IOUT = 0mA, Active-Read-Presharge Precharge standby CKE ≤ VIL(max) IDD1 current in IDD2P power-down mode 1520 1600 1600 mA tCK = tCK(min), All banks 48 56 56 idle Precharge mA CKE ≥ VIH(min) standby current in IDD2N 288 320 320 480 560 560 /CS≥VIH(min), tCK = tCK(min) non power-down mode All Active standby current in banks idle, CKE ≤ IDD3P power-down mode mA VIL(max), tCK = tCK(min) Onel banks, mA Active standby current in Active-Read-Presharge, non power-down mode IDD3N tRC=tRAS(max), tCK 720 800 800 1840 2160 2160 mA 1840 2240 2240 mA 2720 2880 2880 mA 32 32 32 mA = (One bank active) tCK(min) Operating current (Read) IDD4R Burst length = 2 CL=2. tRC = tRC(min), 5 IOUT = 0mA, CL=2 CL=2. Burst length = 2 Operating current (Write) IDD4W 5 tRC = tRC(min) CL=2 Auto refresh current IDD5 tRC ≥ tREF(min) Self refresh current IDD6 CKE ≤ 0.2V AC OPERATING CONDITIONS PARAMETER STMBOL MIN MAX UNIT Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH (AC) VREF + 0.35 Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL (AC) VREF - 0.35 V Input Differential Voltage, CK and CK inputs VID (AC) 0.7 VDDQ+0.6 V 1 Input Crossing Point Voltage, CK and CK inputs VIX (AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2 NOTE Notes: 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5* VDDQ of the transmitting device and must track variations in the DC level of the same URL : www.hbe.co.kr REV 1.0 (August.2002) 6 HANBit Electronics Co.,Ltd. HANBit HDD32M64F8K AC OPERATING TEST CONDITIONS PARAMETER VALUE UNIT Input reference voltage for Clock 0.5 * VDDQ V Input signal maximum peak swing 1.5 V Input signal minimum slew rate 1.0 V VREF+0.35/VREF V Input timing measurement reference level VREF V Output timing measurement reference level VTT V See Load Circuit V Input Levels(VIH/VIL) Output load condition NOTE AC CHARACTERISTICS (These AC charicteristics were tested on the Component) DDR200 DDR266A DDR266B -10A -13A -13B SYMBO PARAMETER L MIN MAX MIN MAX MIN UNIT NOTE MAX Row cycle time tRC 70 65 65 ns 1 Refresh row cycle time tRFC 80 75 75 ns 1,2 Row active time tRAS 48 ns 1,2 /RAS to /CAS delay tRCD 20 20 20 ns 3 Row precharge time tRP 20 20 20 ns 3 Row active to Row active delay tRRD 15 15 15 ns 3 Write recovery time tWR 2 2 2 tCK 3 Last data in to Read command tCDLR 1 1 1 tCK 2 Col. address to Col. address delay tCCD 1 1 1 tCK Clock cycle time CL=2.0 120K 10 45 120K 45 120K 12 7.5 12 10 12 ns 12 7.5 12 7.5 12 ns tCK CL=2.5 URL : www.hbe.co.kr REV 1.0 (August.2002) 7 HANBit Electronics Co.,Ltd. HANBit HDD32M64F8K Clock high level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK Clock low level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK tDQSCK -0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns Output data access time from CK/CK tAC -0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns Data strobe edge to ouput data edge tDQSQ - +0.6 - +0.5 - +0.5 ns Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK tHZQ -0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS-in setup time tWPRES 0 0 0 ns DQS-in hold time tWPREH 0.25 0.25 0.25 tCK tDSS 0.2 0.2 0.2 tCK tDSH 0.2 0.2 0.2 tCK DQS-in high level width tDQSH 0.35 0.35 0.35 tCK DQS-in low level width tDQSL 0.35 0.35 0.35 tCK DQS-in cycle time tDSC 0.9 Address and Control Input setup time tIS 1.1 0.9 0.9 ns Address and Control Input hold time tIH 1.1 0.9 0.9 ns Mode register set cycle time tMRD 16 15 15 ns DQ & DM setup time to DQS tDS 0.6 0.5 0.5 ns DQ & DM hold time to DQS tDH 0.6 0.5 0.5 ns DQ & DM input pulse width tDIPW 2 1.75 1.75 ns Power down exit time tPDEX 10 10 10 ns Exit self refresh to write command tXSW 116 95 tXSA 80 Exit self refresh to read command tXSR 200 200 200 Cycle Refresh interval time TREF 15.6 15.6 15.6 us Output DQS valid window TQH 0.35 0.35 0.35 tCK DQS write postamble time TWPST 0.25 0.25 0.25 tCK DQS-out access time from CK/CK Data out high impedence time from CK2 /CK 3 DQS-in falling edge to CK rising-setup time DQS-in falling edge to CK rising hold time 1.1 0.9 75 Exit self refresh to bank active 1.1 0.9 1.1 tCK ns 75 ns command 1 4 Notes : 1. 2. Maximum burst refresh of 8. tHZQ transitions occurs in the same assess time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving. 3. The specific requirement is that DQS be valid(High-Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. URL : www.hbe.co.kr REV 1.0 (August.2002) 8 HANBit Electronics Co.,Ltd. HANBit 4. HDD32M64F8K The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. SIMPLIFIED TRUTH TABLE COMMAND CKE n-1 CKE n /CS /R A S /C A S /WE DM X L L L L X OP code 1,2 X L L L L X OP code 1,2 L L L H X X X X Register Extended MRS H Register Mode register set H Auto refresh Refresh Entry Self refres Exit h Bank active & row addr. Read & column address Write & column address Auto L L H H H H X X X X L L H H X V X L H L H X V L H H H precharge disable Auto H H BA 0,1 precharge Auto precharge H H X L H L Burst Stop H Precharg Bank selection e All banks Clock suspend or active power down Precharge power down mode V L enable H X X Entry H L Exit L H Entry H L Exit L H DM H No operation command H L H H L L L H L H X X X L V V V X X X X H X X X L H H H H X X X V V V L X X H X X X L H H H X X 3 3 3 4 (A0 ~ A9) 4 Column 4 Address (A0 ~ A9) H X 3 Column L X NOTE Address H precharge disable A11 A9~A0 Row address L eable Auto A10/ AP X V L X H 4,6 7 X 5 X X X X X V X X X 8 (V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. URL : www.hbe.co.kr REV 1.0 (August.2002) 9 HANBit Electronics Co.,Ltd. HANBit HDD32M64F8K 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0) PACKAGING INFORMATION Unit : mm Front – Side Rear-Side URL : www.hbe.co.kr REV 1.0 (August.2002) 10 HANBit Electronics Co.,Ltd. HANBit HDD32M64F8K ORDERING INFORMATION Part Number Density Org. Package Ref. Vcc MODE MAX.frq HDD32M64F8K-10A 256MByte 32M x 64 200PIN SMM 4K 2.5V DDR 100MHz/CL2 HDD32M64F8K-13A 256MByte 32M x 64 200PIN SMM 4K 2.5V DDR 133MHz/CL2 HDD32M64F8K-13B 256MByte 32M x 64 200PIN SMM 4K 2.5V DDR 133MHz/CL2.5 URL : www.hbe.co.kr REV 1.0 (August.2002) 11 HANBit Electronics Co.,Ltd.