5MHz, Dual Precision Rail-to-Rail Input-Output (RRIO) Op Amps ISL28236 Features The ISL28236 is a low-power dual operational amplifier optimized for single supply operation from 2.4V to 5.5V, allowing operation from one lithium cell or two Ni-Cd batteries. The device features a gain-bandwidth product of 5MHz. • 5MHz gain bandwidth product at AV = 100 The ISL28236 features an Input Range Enhancement Circuit (IREC), which enables the amplifier to maintain CMRR performance for input voltages greater than the positive supply. The input signal is capable of swinging 0.25V above the positive supply and to the negative supply with only a slight degradation of the CMRR performance. The output operation is rail-to-rail. The part typically draws less than 1mA supply current per amplifier while meeting excellent DC accuracy, AC performance, noise and output drive specifications. The ISL28236 is available in the 8 Ld SOIC and the 8 Ld MSOP. Operation is guaranteed over the -40°C to +125°C temperature range. PART MARKING • 240µV maximum offset voltage (SOIC package) • 6nA typical input bias current (SOIC package) • Down to 2.4V single supply voltage range • Rail-to-rail input and output • -40°C to +125°C operation • Pb-Free (RoHS compliant) Applications • Low-end audio • 4mA to 20mA current loops • Medical devices • Sensor amplifiers • ADC Buffers Ordering Information PART NUMBER (Notes 2, 3) • 2mA typical supply current • DAC output amplifiers PACKAGE (Pb-Free) PKG. DWG. # ISL28236FBZ 28236 FBZ 8 Ld SOIC M8.15E ISL28236FBZ-T7 (Note 1) 28236 FBZ 8 Ld SOIC M8.15E ISL28236FBZ-T7A (Note 1) 28236 FBZ 8 Ld SOIC M8.15E ISL28236FUZ 8236Z 8 Ld MSOP M8.118A ISL28236FUZ-T7 (Note 1) 8236Z 8 Ld MSOP M8.118A ISL28236FUZ-T7A (Note 1) 8236Z 8 Ld MSOP M8.118A Related Literature • AN1420, “ISL282x6EVAL1Z Evaluation Board User’s Guide” ISL28236SOICEVAL1Z Evaluation Board NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see product information page for ISL28236. For more information on MSL, please see tech brief TB363. July 24, 2014 FN6921.2 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2009, 2014. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL28236 Pin Configurations ISL28236 (8 LD MSOP) TOP VIEW ISL28236 (8 LD SOIC) TOP VIEW OUT_A 1 IN-_A 2 IN+_A 3 8 V+ - + + - V- 4 OUT_A 1 7 OUT_B IN-_A 2 6 IN-_B IN+_A 3 5 IN+_B V- 4 8 V+ 7 OUT_B - + + - 6 IN-_B 5 IN+_B Pin Descriptions ISL28236 (8 Ld SOIC) ISL28236 (8 Ld MSOP) PIN NAME 2 2 IN-_A 6 6 IN-_B FUNCTION EQUIVALENT CIRCUIT inverting input V+ IN- IN+ VCircuit 1 3 3 IN+_A 5 5 IN+_B 4 4 V- Non-inverting input Negative supply See Circuit 1 V+ CAPACITIVELY COUPLED ESD CLAMP VCircuit 2 1 1 OUT_A 7 7 OUT_B Output V+ OUT VCircuit 3 8 Submit Document Feedback 8 V+ 2 Positive supply See Circuit 2 FN6921.2 July 24, 2014 ISL28236 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75V Supply Turn-on Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V Thermal Resistance (Typical Notes 4, 5) JA (°C/W) JC (°C/W) 8 Ld SOIC Package. . . . . . . . . . . . . . . . . . . . 120 60 8 Ld MSOP Package . . . . . . . . . . . . . . . . . . 160 55 Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Operating Conditions Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For JC, the “case temp” location is taken at the package top center. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +125°C. Temperature data established by characterization. PARAMETER DESCRIPTION TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS DC SPECIFICATIONS VOS Input Offset Voltage V OS --------------T Input Offset Voltage vs Temperature IOS Input Offset Current IB Input Bias Current 8 Ld SOIC -240 -250 20 240 250 µV 8 Ld MSOP -270 -530 20 270 530 µV 0.4 µV/°C 8 Ld SOIC TA = -40°C to +125°C -10 -30 2 10 30 nA 8 Ld MSOP TA = -40°C to +125°C -23 -50 2 23 50 nA 8 Ld SOIC TA = -40°C to +125°C -40 -50 6 40 50 nA 8 Ld MSOP TA = -40°C to +125°C -50 -70 6 50 70 nA 5 V VCM Common-Mode Voltage Range Guaranteed by CMRR 0 CMRR Common-Mode Rejection Ratio VCM = 0V to 5V 90 90 115 dB PSRR Power Supply Rejection Ratio V+ = 2.4V to 5.5V 90 90 100 dB AVOL Large Signal Voltage Gain 8 Ld SOIC VO = 0.5V to 4V, RL = 100KΩto VCM 600 500 1600 V/mV 8 Ld MSOP VO = 0.5V to 4V, RL = 100kΩto VCM 600 400 1600 V/mV 100 V/mV VO = 0.5V to 4V, RL = 1kΩto VCM Submit Document Feedback 3 FN6921.2 July 24, 2014 ISL28236 Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open, TA = +25°C unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued) PARAMETER VOUT DESCRIPTION Maximum Output Voltage Swing TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS Output low, RL = 100kΩto VCM 1 10 10 mV Output low, RL = 1kΩto VCM 47 70 90 mV Output high, RL = 100kΩto VCM 4.99 4.99 4.997 V Output high, RL = 1kΩto VCM 4.93 4.91 4.952 V IS Supply Current IO+ Short-Circuit Output Source Current RL = 10Ωto VCM 50 40 70 mA IO- Short-Circuit Output Sink Current RL = 10Ωto VCM 50 40 70 mA VSUPPLY Supply Operating Range V+ to V- 2.4 2 2.5 2.6 5.5 mA V AC SPECIFICATIONS GBW Gain Bandwidth Product AV = 100, RF = 100kΩRG = RL = 10kΩto VCM eN Input Noise Voltage Peak-to-Peak f = 0.1Hz to 10Hz,RL = 10kΩto VCM 5 MHz 0.4 µVP-P Input Noise Voltage Density fO = 1kHz,RL = 10kΩto VCM 15 nV/√Hz iN Input Noise Current Density fO = 10kHz,RL = 10kΩto VCM 0.35 pA/√Hz CMRR at 120Hz Input Common Mode Rejection Ratio VCM = 0.1VP-P, RL = 10kΩto VCM 90 dB PSRR+ at 120Hz Power Supply Rejection Ratio (V+) V+, V- = ±1.2V and ±2.5V, VSOURCE = 0.1VP-P, RL = 10kΩto VCM 88 dB PSRRat 120Hz Power Supply Rejection Ratio (V-) V+, V- = ±1.2V and ±2.5V VSOURCE = 0.1VP-P, RL = 10kΩto VCM 105 dB Crosstalk at 10kHz Channel A to Channel B V+, V- = ±2.5V; AV = 1 VSOURCE = 0.4VP-P, RL = 10kΩto VCM 140 dB ±1.8 V/µs TRANSIENT RESPONSE SR Slew Rate VOUT = ±1.5V; Rf = 50kΩ RG = 50kΩto VCM tr, tf, Large Signal Rise Time, 10% to 90%, VOUT AV = -1, VOUT = 4VP-P, RL = 10kΩto VCM 2.1 µs Fall Time, 90% to 10%, VOUT AV = -1, VOUT = 4VP-P, RL = 10kΩto VCM 2 µs tr, tf, Small Signal Rise Time, 10% to 90%, VOUT AV = +1, VOUT = 100mVP-P, RL = 10kΩto VCM 60 ns Fall Time, 90% to 10%, VOUT AV = +1 VOUT = 100mVP-P, RL = 10kΩto VCM 50 ns Settling Time to 0.01%; 4V Step VOUT = 4VP-P; RL = 10kΩto VCM 5.1 µs ts, NOTE: 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Submit Document Feedback 4 FN6921.2 July 24, 2014 ISL28236 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. Plots labeled Min, Median, and Max correspond to a distribution of devices in the SOIC package. 8 60 6 40 4 GAIN (dB) 10 80 VOS (µV) 100 20 0 -20 V+ = 5V RL = OPEN Rf = 100k, Rg = 100 AV = +1000 -40 -60 -80 -1 0 1 2 3 VCM (V) VS = 5V CL = 4pF AV = +2 VOUT = 10mVP-P -10 100 6 10k 1k 1M 10M 100M FIGURE 2. GAIN vs FREQUENCY vs FEEDBACK RESISTOR VALUES Rf/Rg 1 1 0 NORMALIZED GAIN (dB) 0 -1 -2 VOUT = 100mV -3 -4 VOUT = 10mV -5 -6 VS = 5V RL = 10k -7 CL = 4pF -8 A = +1 V -9 10k VOUT = 50mV VOUT = 1V 100k 1M 10M RL = 10k -1 -2 RL = 100k -3 -4 -5 V+ = 5V CL = 4pF -7 AV = +1 -8 VOUT = 10mVP-P -6 -9 10k 100M 100k FIGURE 3. GAIN vs FREQUENCY vs VOUT, RL = 10k AV = 1001, Rg = 1k, Rf = 1M V+ = 5V CL = 16.3pF RL = 10k VOUT = 10mVP-P AV = 10 AV = 10, Rg = 1k, Rf = 9.09k AV = 1 -10 100 AV = 1, Rg = INF, Rf = 0 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M FIGURE 5. FREQUENCY RESPONSE vs CLOSED LOOP GAIN Submit Document Feedback 5 NORMALIZED GAIN (dB) AV = 101 10 0 100M 0 AV = 101, Rg = 1k, Rf = 100k 30 20 10M 1 AV = 1001 50 40 1M FIGURE 4. GAIN vs FREQUENCY vs RL 70 60 RL = 1k FREQUENCY (Hz) FREQUENCY (Hz) GAIN (dB) 100k FREQUENCY (Hz) FIGURE 1. INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE NORMALIZED GAIN (dB) -2 -8 5 Rf = Ri = 1k 0 -6 4 Rf = Ri = 10k 2 -4 -100 Rf = Ri = 100k -1 -2 -3 -4 VS = 2.4V -5 -6 RL = 10k CL = 4pF -7 AV = +1 -8 V OUT = 10mVP-P -9 10k 100k VS = 5V 1M 10M 100M FREQUENCY (Hz) FIGURE 6. GAIN vs FREQUENCY vs SUPPLY VOLTAGE FN6921.2 July 24, 2014 ISL28236 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. Plots labeled Min, Median, and Max correspond 8 7 6 5 4 3 2 1 0 -1 -2 -3 V = 5V S -4 R = 10k -5 L A -6 V = +1 -7 VOUT = 10mVP-P -8 10k 100k 120 CL = 37pF 100 CL = 26pF 80 CMRR (dB) NORMALIZED GAIN (dB) to a distribution of devices in the SOIC package. (Continued) CL = 16pF VS = 2.4V 60 VS = 5V 40 RL = 10k CL = 4pF AV = +1 VCM = 100mVP-P 20 CL = 4pF 0 1M 10M -20 0.1 100M 10 1 FREQUENCY (Hz) FIGURE 7. GAIN vs FREQUENCY vs CL 10k 100k 1M 10M 120 100 100 PSRR+ PSRR+ 80 PSRR (dB) 80 PSRR (dB) 1k FIGURE 8. CMRR vs FREQUENCY; V+ = 2.4V AND 5V 120 60 PSRR40 V+, V- = ±1.2V RL = 10k CL = 4pF AV = +1 VSOURCE = 100mVP-P 20 0 -20 0.1 1 10 60 PSRR40 V+, V- = ±2.5V RL = 10k CL = 4pF AV = +1 VSOURCE = 100mVP-P 20 0 100 1k 10k 100k 1M -20 0.1 10M 1 10 FREQUENCY (Hz) 160 INPUT NOISE VOLTAGE (nVÖHz) 120 100 60 40 20 0 10 100k 1M 10M 100 140 80 100 1k 10k FREQUENCY (Hz) FIGURE 10. PSRR vs FREQUENCY, V+, V- = ±2.5V FIGURE 9. PSRR vs FREQUENCY, V+, V- = ±1.2V CROSSTALK (dB) 100 FREQUENCY (Hz) V+, V- = ±2.5V RL = OPEN TRANSMIT CHANNEL RL = 10k RECEIVING CHANNEL CL = 4pF AV = +1 VSOURCE = 400mVP-P 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M FIGURE 11. CROSSTALK vs FREQUENCY, V+, V- = ±2.5V Submit Document Feedback 6 V+ = 5V RL = 1k CL = 16.3pF AV = +1 10 1 10 100 1k FREQUENCY (Hz) 10k 100k FIGURE 12. INPUT NOISE VOLTAGE DENSITY vs FREQUENCY FN6921.2 July 24, 2014 ISL28236 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. Plots labeled Min, Median, and Max correspond to a distribution of devices in the SOIC package. (Continued) INPUT CURRENT NOISE (pAÖHz) 10 0.5 V+ = 5V RL = 1k CL = 16.3pF AV = +1 INPUT NOISE (µV) 0.3 1 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 0.1 1 10 100 1k FREQUENCY (Hz) 10k -0.5 100k 2.0 SMALL SIGNAL (V) 1.5 1.0 V+, V- = ±2.5V RL = 1k and 10k CL = 4pF AV = 2 VOUT = 4VP-P 0 -0.5 -1.0 -1.5 -2.0 -2.5 0 10 20 30 40 50 TIME (µs) 1 2 3 4 5 6 7 8 9 10 FIGURE 14. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz 2.5 0.5 0 TIME (s) FIGURE 13. INPUT CURRENT NOISE DENSITY vs FREQUENCY LARGE SIGNAL (V) V+ = 5V RL = 10k CL = 16.3pF Rg = 10, Rf = 100k AV = 10000 0.4 60 70 80 60 50 40 30 20 10 0 -10 -20 -30 -40 -50 -60 V+, V- = ±1.2V AND ±2.5V RL = 1k and 10k CL = 4pF AV = 1 VOUT = 100mVP-P 0 FIGURE 15. LARGE SIGNAL STEP RESPONSE 0.1 0.2 0.3 0.4 0.5 0.6 TIME (µs) 0.7 0.8 0.9 1.0 FIGURE 16. SMALL SIGNAL STEP RESPONSE 2.6 -1.5 2.4 MAX VS = ±2.875V -1.7 2.0 VS = ±2.5V 1.8 1.6 VS = ±1.5V CURRENT (mA) CURRENT (mA) 2.2 -1.9 MEDIAN -2.1 1.4 -2.3 1.2 1.0 -40 MIN -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 17. SUPPLY CURRENT vs TEMPERATURE vs SUPPLY VOLTAGE Submit Document Feedback 7 -2.5 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 18. NEGATIVE SUPPLY CURRENT vs TEMPERATURE, V+, V- = ±2.5V FN6921.2 July 24, 2014 ISL28236 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. Plots labeled Min, Median, and Max correspond to a distribution of devices in the SOIC package. (Continued) 200 200 150 150 MAX MAX 100 50 VOS (µV) VOS (µV) 100 MEDIAN 0 -50 MEDIAN 0 -50 MIN -100 -150 -40 50 -20 0 20 40 MIN -100 60 80 100 120 -150 -40 -20 0 20 40 FIGURE 19. VOS vs TEMPERATURE, V+, V- = ±1.2V 5 5 0 0 -5 IBIAS- (nA) IBIAS+ (nA) 120 10 MAX MEDIAN -10 -15 MAX -5 -10 MEDIAN -15 -20 MIN -20 MIN -25 -25 -20 0 20 40 60 80 100 -30 -40 120 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 21. IBIAS+ vs TEMPERATURE, V+, V- = ±2.5V FIGURE 22. IBIAS- vs TEMPERATURE, V+, V- = ±2.5V 30 30 25 25 MAX MAX 20 20 15 15 IBIAS- (nA) IBIAS- (nA) 100 15 10 10 MEDIAN 5 0 10 MEDIAN 5 0 MIN -5 -10 -40 80 FIGURE 20. VOS vs TEMPERATURE, V+, V- = ±2.5V 15 -30 -40 60 TEMPERATURE (°C) TEMPERATURE (°C) MIN -5 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 23. IBIAS+ vs TEMPERATURE, V+, V- = ±1.2V Submit Document Feedback 8 -10 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 24. IBIAS- vs TEMPERATURE, V+, V- = ±1.2V FN6921.2 July 24, 2014 ISL28236 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. Plots labeled Min, Median, and Max correspond to a distribution of devices in the SOIC package. (Continued) 12 12 10 10 MAX 8 2 IOS (nA) IOS (nA) 6 4 MEDIAN 0 4 2 -2 -4 -4 -6 -6 MIN -8 -20 0 20 40 60 80 100 MEDIAN 0 -2 -10 -40 MAX 8 6 MIN -8 -10 -40 120 -20 0 TEMPERATURE (°C) FIGURE 25. IOS vs TEMPERATURE, V+, V- = ±2.5V 150 MAX 140 140 PSRR (dB) CMRR (dB) 150 130 120 MEDIAN 130 MAX 120 110 110 MIN -20 0 20 40 MEDIAN 100 100 60 80 100 90 -40 120 MIN -20 0 TEMPERATURE (°C) 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 28. PSRR vs TEMPERATURE, V+, V- = ±1.2V FIGURE 27. CMRR vs TEMPERATURE, V+, V- = ±2.5V 4060 220 3560 200 MAX MAX 3060 180 AVOL (V/mV) AVOL (V/mV) 120 160 160 2560 2060 MEDIAN 1560 1060 160 140 MEDIAN 120 MIN 100 MIN 560 60 -40 100 FIGURE 26. IOS vs TEMPERATURE, V+, V- = ±1.2V 170 90 -40 20 40 60 80 TEMPERATURE (°C) 80 -20 0 20 40 60 80 TEMPERATURE (°C) FIGURE 29. AVOL vs TEMPERATURE, V+, V- = ±2.5V, VO = -2V TO +2V, RL = 100k Submit Document Feedback 9 100 120 60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 30. AVOL vs TEMPERATURE, V+, V- = ±2.5V, VO = -2V TO +2V, RL = 1k FN6921.2 July 24, 2014 ISL28236 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. Plots labeled Min, Median, and Max correspond to a distribution of devices in the SOIC package. (Continued) 70 4.965 65 4.960 MAX VOUT (mV) VOUT (V) MEDIAN 4.950 4.945 50 40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 35 -40 120 -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 32. VOUT LOW vs TEMPERATURE, V+, V- = ±2.5V, RL = 1k 4.9985 1.75 4.9980 1.55 MAX MAX 1.35 4.9970 MIN VOUT (mV) 4.9975 MEDIAN 4.9965 1.15 0.95 0.75 4.9960 4.9955 -40 MEDIAN 45 FIGURE 31. VOUT HIGH vs TEMPERATURE, V+, V- = ±2.5V, RL = 1k VOUT (V) 55 MIN MIN 4.940 4.935 -40 MAX 60 4.955 MIN MEDIAN 0.55 -20 0 20 40 60 80 TEMPERATURE (°C) 100 0.35 -40 120 FIGURE 33. VOUT HIGH vs TEMPERATURE, V+, V- = ±2.5V, RL = 100k -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 FIGURE 34. VOUT LOW vs TEMPERATURE, V+, V- = ±2.5V, RL = 100k 2.9 SLEW RATE RISE (V/µs) 2.7 MAX 2.5 2.3 2.1 1.9 MEDIAN 1.7 MIN 1.5 1.3 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 35. SLEW RATE RISE vs TEMPERATURE, VOUT = ±1.5V, VP-P V+, V- = ±2.5V, RL = 100k Submit Document Feedback 10 FN6921.2 July 24, 2014 ISL28236 Applications Information Introduction The ISL28236 is a dual channel Bi-CMOS rail-to-rail input, output (RRIO) micropower precision operational amplifier. The part is designed to operate from a single supply (2.4V to 5.5V) or a dual supply (±1.2V to ±2.75V). The ISL28236 has an input common mode range that extends 0.25V above the positive rail and down to the negative supply rail. The output operation can swing within about 3mV of the supply rails with a 100kΩ load. Rail-to-Rail Input Many rail-to-rail input stages use two differential input pairs, a long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties have to be paid for this circuit topology. As the input signal moves from one supply rail to another, the operational amplifier switches from one input pair to the other. Thus causing drastic changes in input offset voltage and an undesired change in magnitude and polarity of input offset current. The ISL28236 solves this problem using an internal charge pump to provide a voltage boost to the V+ supply rail driving the input differential pair. This results in extending the input common voltage rails to 0.25V beyond the V+ positive rail. The input offset voltage exhibits a smooth behavior throughout the extended common-mode input range. The input bias current versus the common-mode voltage range gives an undistorted behavior from the negative rail to 0.25V higher than the positive rail. Power Supply Decoupling The internal charge pump operates at approximately 27MHz and oscillator ripple doesn’t show up in the 5MHz bandwidth of the amplifier. Good power supply decoupling with 0.01µF capacitors at each device power supply pin, is the most effective way to reduce oscillator ripple at the amplifier output. Figure 36 shows the electrical connection of these capacitors using split power supplies. For single supply operation with V- tied to a ground plane, only a single 0.01µF capacitor from V+ is needed. When multiple ISL28236 op amps are used on a single PC board, each op amp will require a 0.01µF decoupling capacitor at each supply pin. Rail-to-Rail Output The rail-to-rail output stage uses CMOS devices that typically swing to within 3mV of the supply rails with a 100kΩ load. The NMOS sinks current to swing the output in the negative direction. The PMOS sources current to swing the output in the positive direction. Current Limiting These devices have no internal current limiting circuitry. If the output is shorted, it is possible to exceed the absolute maximum rating for output current or power dissipation, potentially resulting in the destruction of the device. Results Of Overdriving The Output 2. The output current required is higher than the output stage can deliver. These conditions can result in a shift in the Input Offset Voltage (VOS) (as much as 1µV/hr. of exposure) under these conditions. IN+ and IN- Input Protection All input terminals have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. They also contain back-to-back diodes across the input terminals (see “Pin Descriptions” on page 2 - Circuit 1). For applications where the input differential voltage is expected to exceed 0.5V, an external series resistor must be used to ensure the input currents never exceed 5mA (Figure 36). V+ 0.01µF DECOUPLING CAPACITORS VIN VOUT RIN + RL 0.01µF V- FIGURE 36. LOCAL POWER SUPPLY DECOUPLING AND INPUT CURRENT LIMITING Limitations of the Differential Input Protection If the input differential voltage is expected to exceed 0.5V, an external current limiting resistor must be used to ensure the input current never exceeds 5mA. For non-inverting unity gain applications, the current limiting can be via a series IN+ resistor, or via a feedback resistor of appropriate value. For other gain configurations, the series IN+ resistor is the best choice, unless the feedback (RF) and gain setting (RG) resistors are both sufficiently large to limit the input current to 5mA. Large differential input voltages can arise from several sources: 1. During open loop (comparator) operation. Used this way, the IN+ and IN- voltages don’t track, so differentials arise. 2. When the amplifier is disabled but an input signal is still present. An RL or RG to GND keeps the IN- at GND, while the varying IN+ signal creates a differential voltage. Mux Amp applications are similar, except that the active channel VOUT determines the voltage on the IN- terminal. 3. When the slew rate of the input pulse is considerably faster than the op amp’s slew rate. If the VOUT can’t keep up with the IN+ signal, a differential voltage results, and visible distortion occurs on the input and output signals. To avoid this issue, keep the input slew rate below 1.9V/µs, or use appropriate current limiting resistors. Large (>2V) differential input voltages can also cause an increase in disabled ICC. Caution should be used when overdriving the output for long periods of time. Overdriving the output can occur in two ways. 1. The input voltage times the gain of the amplifier exceeds the supply voltage by a large value or, Submit Document Feedback 11 FN6921.2 July 24, 2014 ISL28236 Using Only One Channel If the application only requires one channel, the user must configure the unused channel to prevent it from oscillating. The unused channel will oscillate if the input and output pins are floating. This will result in higher than expected supply currents and possible noise injection into the channel being used. The proper way to prevent this oscillation is to short the output to the negative input and ground the positive input (as shown in Figure 37). (EQ. 1) T JMAX = T MAX + JA xPD MAXTOTAL where: • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) • PDMAX for each amplifier can be calculated using Equation 2: V OUTMAX PD MAX = V S I SMAX + V S - V OUTMAX ---------------------------R - (EQ. 2) L + FIGURE 37. PREVENTING OSCILLATIONS IN UNUSED CHANNELS Power Dissipation It is possible to exceed the +125°C maximum junction temperatures under certain load and power supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be Submit Document Feedback modified to remain in the safe operating area. These parameters are related in Equation 1: 12 where: • TMAX = Maximum ambient temperature • JA = Thermal resistance of the package • PDMAX = Maximum power dissipation of 1 amplifier • VS = Total supply voltage • ISMAX = Maximum supply current of 1 amplifier • VOUTMAX = Maximum output voltage swing of the application • RL = Load resistance FN6921.2 July 24, 2014 ISL28236 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE July 24, 2014 FN6921.2 Ordering information table on page 1: Added T7A parts and Evaluation Board. Thermal Information table on page 3: Added theta JC values to SOIC and MSOP package and updated the notes. May 20, 2014 FN6921.1 Updated to New Template Updated Ordering Information Table by removing “coming soon” from FUZ parts, Pkg DWG #’s changed from MDP0027 to M8.15E (SOIC) and MDP0043 to M8.118A (MSOP), numbered all notes, added MSL note Updated Electrical Specifications Table by adding conditions for package extension. Added Rev History and About Intersil verbiage. June 11, 2009 FN6921.0 Initial Release. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Submit Document Feedback 13 FN6921.2 July 24, 2014 ISL28236 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25 M C A B SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.175 ± 0.075 SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (0.60) (1.27) NOTES: (1.50) (5.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN Submit Document Feedback 14 FN6921.2 July 24, 2014 ISL28236 Package Outline Drawing M8.118A 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP) Rev 0, 9/09 A 3.0±0.1 8 0.25 CAB 3.0±0.1 4.9±0.15 DETAIL "X" 1.10 Max PIN# 1 ID B SIDE VIEW 2 1 0.18 ± 0.05 2 0.65 BSC TOP VIEW 0.95 BSC 0.86±0.09 GAUGE PLANE H C 0.25 SEATING PLANE 0.33 +0.07/ -0.08 0.08 C A B 0.10 ± 0.05 3°±3° 0.10 C 0.55 ± 0.15 DETAIL "X" SIDE VIEW 1 5.80 NOTES: 4.40 3.00 1. Dimensions are in millimeters. 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSE Y14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.25mm max per side are not included. 5. Dimensions “D” and “E1” are measured at Datum Plane “H”. 6. This replaces existing drawing # MDP0043 MSOP 8L. 0.65 0.40 1.40 TYPICAL RECOMMENDED LAND PATTERN Submit Document Feedback 15 FN6921.2 July 24, 2014