TI DAC3282IRGZT 16-bit, 625 msps, 2x interpolating, dual-channel digital-to-analog converter (dac) Datasheet

DAC3282
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SLAS646 – DECEMBER 2009
16-Bit, 625 MSPS, 2x Interpolating, Dual-Channel Digital-to-Analog Converter (DAC)
Check for Samples: DAC3282
FEATURES
1
•
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Dual, 16-Bit, 625 MSPS DACs
8-Bit Input LVDS Data Bus
– Byte-Wide Interleaved Data Load
– 8 Sample Input FIFO
– Optional Data Pattern Checker
Multi-DAC Synchronization
Optional 2x Interpolation Filter
Zero-IF Sinc Correction Filter
Fs/2 and ± Fs/4 Coarse Mixer
Digital Offset Adjustment for LO Correction
Temperature Sensor
3- or 4-Wire Serial Control Interface
On Chip 1.2-V reference
Differential Scalable Output: 2 to 20 mA
Low Power: 950 mW at 625 MSPS, 845 mW at
500 MHz, Full Operating Conditions
Space Saving Package: 48-pin 7×7mm QFN
•
•
•
•
•
•
•
•
•
•
•
APPLICATIONS
DESCRIPTION
The DAC3282 is a dual-channel 16-bit 625 MSPS
digital-to-analog converter (DAC) with an 8-bit LVDS
input data bus with on-chip termination, optional 2x
interpolation filter, and internal voltage reference. The
DAC3282 offers superior linearity, noise and crosstalk
performance.
Input data can be interpolated by 2x through an
on-chip interpolating FIR filter with over 85 dB of
stop-band attenuation. Multiple DAC3282 devices can
be fully synchronized.
The DAC3282 allows either a complex or real output.
An optional coarse mixer in complex mode provides
frequency upconversion and the dual DAC output
produces a complex Hilbert Transform pair. The
digital offset correction feature allows optimization of
LO feed-through of an external quadrature modulator
performing
the
final
single
sideband
RF
up-conversion.
The DAC3282 is characterized for operation over the
entire industrial temperature range of –40°C to 85°C
and is available in a 48-pin 7×7mm QFN package.
• Cellular Base Stations
• Diversity Transmit
• Wideband Communications
• Digital Synthesis
spacer for space above the ordering information table
spacer for space above the ordering information table
ORDERING INFORMATION
TA
–40°C to 85°C
(1)
(2)
ORDER CODE
DAC3282IRGZT
DAC3282IRGZR
PACKAGE
DRAWING/TYPE (1)
(2)
RGZ / 48QFN Quad Flatpack
No-Lead
TRANSPORT
MEDIA
Tape and Reel
QUANTITY
250
2500
Thermal Pad Size: 5,6 mm x 5,6 mm
MSL Peak Temperature: Level-3-260C-168 HR
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
DAC3282
SLAS646 – DECEMBER 2009
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DACVDD18
VFUSE
DIGVDD18
CLKVDD18
FUNCTIONAL BLOCK DIAGRAM
DACCLKP
Clock Distribution
LVPECL
1.2 V
Reference
DACCLKN
A
offset
DATACLKN
FIR4
x
sin(x)
D0N
Coarse Mixer
Fs/4, -Fs/4, Fs/2
5 taps
59 taps
x
sin(x)
16-b
DAC
16-b
DAC
x2
LVDS
B
offset
Frame Strobe
100
FRAMEP
16
x2
Programmable Delay
(0-15T)
100
LVDS
16
8 Sample FIFO
Pattern
Test
De-interleave
D7N
D0P
A
gain
FIR0
LVDS
100
D7P
BIASJ
LVDS
100
DATACLKP
EXTIO
IOUTA1
IOUTA2
IOUTB1
IOUTB2
B
gain
FRAMEN
OSTRP
Temp
Sensor
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RESETB
TXENABLE
SCLK
SDENB
SDIO
ALARM_SDO
2
AVDD33
GND
Control Interface
LVPECL
OSTRN
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SLAS646 – DECEMBER 2009
AVDD33
IOUTB1
IOUTB2
AVDD33
EXTIO
BIASJ
AVDD33
VFUSE
AVDD33
IOUTA2
IOUTA1
AVDD33
48
47
46
45
44
43
42
41
40
39
38
37
PINOUT
CLKVDD18
1
36
RESETB
DACVDD18
2
35
DACVDD18
DACCLKP
3
34
ALARM_SDO
DACCLKN
4
33
SDENB
GND
5
32
SCLK
OSTRP
6
31
SDIO
30
TXENABLE
29
DIGVDD18
DAC3282
RGZ Package
48-QFN 7x7mm
(Top View )
22
23
24
D2P
D2N
D1P
D3N
25
21
12
D3P
D6N
20
D1N
FRAMEN
26
19
11
FRAMEP
D6P
18
D0P
DATACLKN
27
17
10
DATACLKP
D7N
16
D0N
D4N
28
15
9
D4P
D7P
14
8
D5N
DIGVDD18
13
7
D5P
OSTRN
PIN FUNCTIONS
PIN
NAME
NO.
I/O
DESCRIPTION
37, 40, 42,
45, 48
I
Analog supply voltage. (3.3 V)
ALARM_SDO
34
O
1.8V CMOS output for ALARM condition. The ALARM output functionality is defined through the
CONFIG6 register. Default polarity is active low, but can be changed to active high via CONFIG0
alarm_pol control bit. Optionally, it can be used as the uni-directional data output in 4-pin serial
interface mode (CONFIG 23 sif4_ena = ‘1’).
BIASJ
43
O
Full-scale output current bias. For 20mA full-scale output current, connect a 960 Ω resistor to GND.
CLKVDD18
1
I
Internal clock buffer supply voltage. (1.8 V)
It is recommended to isolate this supply from DACVDD18 and DIGVDD18.
AVDD33
D[7..0]P
9, 11, 13,
15, 21, 23,
25, 27
I
LVDS positive input data bits 0 through 7. Each positive/negative LVDS pair has an internal 100 Ω
termination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR) with two
data transfers per DATACKP/N clock cycle. Dual channel 16-bit data is transferred byte-wide on this
single 8-bit data bus using FRAMEP/N as a frame strobe indicator.
D7P is most significant data bit (MSB) – pin 9
D0P is least significant data bit (LSB) – pin 27
The order of the bus can be reversed via CONFIG19 rev bit.
D[7..0]N
10, 12, 14,
16, 22, 24,
26, 28
LVDS negative input data bits 0 through 15. (See D[7:0]P description above)
I
D7N is most significant data bit (MSB) – pin 10
D0N is least significant data bit (LSB) – pin 28
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PIN FUNCTIONS (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
DACCLKP
3
I
Positive external LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18/2.
DACCLKN
4
I
Complementary external LVPECL clock input for DAC core. (see the DACCLKP description)
DACVDD18
2, 35
I
DAC core supply voltage. (1.8 V)
It is recommended to isolate this supply from CLKVDD18 and DIGVDD18.
DATACLKP
17
I
LVDS positive input data clock. This positive/negative pair has an internal 100 Ω termination resistor.
Input data D[7:0]P/N is latched on both edges of DATACLKP/N (Double Data Rate) with two data
transfers input per DATACLKP/N clock cycle.
DATACLKN
18
I
LVDS negative input data clock. (See DATACLKP description)
DIGVDD18
8, 29
I
Digital supply voltage. (1.8V)
It is recommended to isolate this supply from CLKVDD18 and DACVDD18.
EXTIO
44
I/O
Used as external reference input when internal reference is disabled through CONFIG25 extref_ena =
‘1’. Used as internal reference output when CONFIG25 extref_ena = ‘0’ (default). Requires a 0.1 μF
decoupling capacitor to AGND when used as reference output.
FRAMEP
19
I
LVDS frame indicator positive input. This positive/negative pair has an internal 100 Ω termination
resistor. This signal is captured with the rising edge of DATACLKP/N and used to indicate the
beginning of the frame. It is also used as a reset signal by the FIFO. The FRAMEP/N signal should be
edge-aligned with D[7:0]P/N.
FRAMEN
20
I
LVDS frame indicator negative input. (See the FRAMEN description)
FIFO_OSTRP
6
I
LVPECL FIFO output strobe positive input. Similar to FIFO_ISTR but it is captured with the rising edge
of DACCLKP/N. It is used to reset the clock dividers as well as the FIFO read pointer. If unused it can
be left floating.
FIFO_OSTRN
7
I
LVPECL FIFO output strobe negative input. (See the FIFO_OSTRP description)
5, Thermal
Pad
I
Pin 5 and the Thermal Pad located on the bottom of the QFN package is ground for all supplies.
IOUTA1
38
O
A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a
full scale current sink and the least positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data input
results in a 0 mA current sink and the most positive voltage on the IOUTA1 pin.
IOUTA2
39
O
A-Channel DAC complementary current output. The IOUTA2 has the opposite behavior of the IOUTA1
described above. An input data value of 0x0000 results in a 0 mA sink and the most positive voltage
on the IOUTA2 pin.
IOUTB1
47
O
B-Channel DAC current output. Refer to IOUTA1 description above.
IOUTB2
46
O
B-Channel DAC complementary current output. Refer to IOUTA2 description above.
OSTRP
6
I
LVPECL output strobe positive input. This positive/negative pair is captured with the rising edge of
DACCLKP/N. It is used to reset the clock dividers and for multiple DAC synchronization. If unused it
can be left floating.
OSTRN
7
I
LVPECL output strobe negative input. (See the OSTRP description)
RESETB
36
I
1.8V CMOS active low input for chip RESET. Internal pull-up.
SCLK
32
I
1.8V CMOS serial interface clock. Internal pull-down.
SDENB
33
I
1.8V CMOS active low serial data enable, always an input to the DAC3282. Internal pull-up.
SDIO
31
I/O
TXENABLE
30
I
1.8V CMOS active high input. TXENABLE must be high for the DATA to the DAC to be enabled.
When TXENABLE is low, the digital logic section is forced to all 0, and any input data is ignored.
Internal pull-down.
VFUSE
41
I
Digital supply voltage. (1.8V) This supply pin is also used for factory fuse programming. Connect to
DACVDD18 pins for normal operation.
GND
4
1.8V CMOS serial interface data. Bi-directional in 3-pin mode (default). In 4-pin interface mode, the
SDIO pin is an input only. Internal pull-down.
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SLAS646 – DECEMBER 2009
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage range
VALUE
UNIT
DACVDD18 (2)
–0.5 to 2.3
V
DIGVDD18 (2)
–0.5 to 2.3
V
CLKVDD18 (2)
–0.5 to 2.3
V
–0.5 to 2.3
V
–0.5 to 4
V
–0.5 to 0.5
V
VFUSE
(2)
AVDD33 (2)
Terminal voltage range
CLKVDD18 to DIGVDD18
DACVDD18 to DIGVDD18
D[7..0]P ,D[7..0]N, DATACLKP,DATACLKN, FRAMEP,
FRAMEN (2)
DACCLKP, DACCLKN, OSTRP, OSTRN (2)
ALARM_SDO, SDIO, SCLK, SDENB, RESETB, TXENABLE
(2)
–0.5 to 0.5
V
–0.5 to DIGVDD18 + 0.5
V
–0.5 to CLKVDD18 + 0.5
V
–0.5 to DIGVDD18 + 0.5
V
IOUTA1/B1, IOUTA2/B2 (2)
–1.0 to AVDD33 + 0.5
V
EXTIO, BIASJ (2)
–0.5 to AVDD33 + 0.5
V
Peak input current (any input)
20
mA
Peak total input current (all inputs)
–30
mA
Operating free-air temperature range, TA: DAC3282
–40 to 85
°C
Storage temperature range
–65 to 150
°C
260
°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds
(1)
(2)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Measured with respect to GND.
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
THERMAL CONDUCTIVITY
TJ
θJA
Maximum Junction Temperature
48ld QFN
UNIT
125
°C
Theta junction-to-ambient (still air)
30
°C/W
Theta junction-to-ambient (150 lfm)
24
°C/W
8
°C/W
1.3
°C/W
θJB
Theta junction-to-board
θJP
Theta junction-to-pad
(1)
(2)
(1) (2)
Air flow or heat sinking reduces θJA and may be required for sustained operation at 85° and maximum operating conditions.
It is strongly recommended to solder the device thermal pad to the board ground plane.
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ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS (1)
over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Resolution
MIN
TYP
MAX
16
UNIT
Bits
DC ACCURACY
DNL
Differential nonlinearity
INL
Integral nonlinearity
1 LSB = IOUTFS/216
±2
LSB
±4
LSB
ANALOG OUTPUT
Coarse gain linearity
Offset error
Gain error
±0.04
LSB
0.01
%FSR
With external reference
±2
%FSR
With internal reference
±2
Mid code offset
Gain mismatch
With internal reference
Minimum full scale output current
Maximum full scale output current
Nominal full-scale current,
IOUTFS = 16 × IBIAS current.
Output compliance range (2)
IOUTFS = 20 mA
–2
%FSR
2
2
mA
20
AVDD
–0.5V
Output resistance
Output capacitance
%FSR
AVDD
+0.5V
V
300
kΩ
5
pF
REFERENCE OUTPUT
VREF
Reference output voltage
1.14
Reference output current (3)
1.2
1.26
100
V
nA
REFERENCE INPUT
VEXTIO
Input voltage range
Input resistance
External Reference Mode
0.1
1.2
1.25
V
1
MΩ
Small signal bandwidth
472
kHz
Input capacitance
100
pF
±1
ppm of
FSR/°C
TEMPERATURE COEFFICIENTS
Offset drift
Gain drift
With external reference
±15
With internal reference
±30
ppm of
FSR/°C
±8
ppm/°C
Reference voltage drift
(1)
(2)
(3)
6
Measured differential across IOUTA1 and IOUTA2 or IOUTB1 and IOUTB2 with 25 Ω each to AVDD.
The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown,
resulting in reduced reliability of the DAC3282 device. The upper limit of the output compliance is determined by the load resistors and
full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.
Use an external buffer amplifier with high impedance input to drive any external load.
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ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS (1) (continued)
over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
AVDD33
3.0
3.3
3.6
DACVDD18, DIGVDD18, CLKVDD18
1.7
1.8
1.9
UNIT
POWER SUPPLY
I(AVDD33)
Analog supply current
I(DIGVDD18)
Digital supply current
I(DACVDD18)
DAC supply current
I(CLKVDD18)
Clock supply current
I(AVDD33)
Power down mode analog supply
current
I(DIGVDD18)
Power down mode digital supply
current
I(DACVDD18)
Power down mode DAC supply
current
I(CLKVDD18)
Power down mode clock supply
current
P
Power Dissipation
PSRR
Power Supply Rejection Ratio
T
Operating Range
Mode 1(below)
V
V
96
mA
268
mA
74
mA
10
mA
2
mA
3
mA
0.5
mA
1
mA
Mode 4 (below)
Mode 1: fDAC = 625MSPS, 2x interpolation, mixer on,
Digital Offset Control on
950
Mode 2: fDAC = 491.52MSPS, 2x interpolation, Zero-IF
Correction Filter on, mixer off, Digital Offset Control on
845
mW
Mode 3: Sleep Mode, fDAC = 625MSPS, 2X interpolation,
mixer on,
DAC in sleep mode:
CONFIG24 sleepa, sleepb set to 1
575
mW
Mode 4: Power-Down mode, No clock, static data pattern,
DAC in power-down mode:
CONFIG23 clkpath_sleep_a, clkpath_sleepb set to 1
CONFIG24 clkrecv_sleep, sleepa, sleepb set to 1
15
mW
DC tested
–0.4
–40
25
1100
mW
0.4
%/FSR/V
85
°C
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ELECTRICAL CHARACTERISTICS – AC SPECIFICATIONS
over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER
ANALOG OUTPUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(1)
1x Interpolation
312.5
2x Interpolation
625
fDAC
Maximum output update rate
ts(DAC)
Output settling time to 0.1%
Transition: Code 0x0000 to 0xFFFF
tpd
Output propagation delay
DAC outputs are updated on the falling edge of DAC clock.
Does not include Digital Latency (see below).
tr(IOUT)
Output rise time 10% to 90%
220
ps
tf(IOUT)
Output fall time 90% to 10%
220
PS
Power-up
time
MSPS
10.4
ns
2
ns
DAC Wake-up Time
IOUT current settling to 1% of IOUTFS. Measured from SDENB
rising edge; Register CONFIG24, toggle sleepa from 1 to 0
90
μs
DAC Sleep Time
IOUT current settling to less than 1% of IOUTFS. Measured from
SDENB rising edge; Register CONFIG24, toggle sleepa from 0
to 1.
90
μs
No interpolation, FIFO off, Offset off, Inverse sinc off
38
2x Interpolation
59
Zero-IF Sinc Correction Filter
16
Digital Latency
FIFO
8
Offset
4
DAC clock
cycles
AC PERFORMANCE (2)
Spurious Free Dynamic Range SFDR
(0 to fDAC/2) Tone at 0 dBFS
SFDR
Third-order two-tone intermodulation
distortion Each tone at –6 dBFS
IMD3
NSD
8
83
fDAC = 625 MSPS, fOUT = 20.1 MHz 2x Interp, DAC A+B on
78
fDAC = 625 MSPS, fOUT = 70.1 MHz 2x Interp, DAC A+B on
64
fDAC = 625 MSPS, fOUT = 30 ± 0.5 MHz 2x Interp, DAC A+B on
82
fDAC = 625 MSPS, fOUT = 50 ± 0.5 MHz 2x Interp, DAC A+B on
80
fDAC = 625 MSPS, fOUT = 150 ± 0.5 MHz 2x Interp, DAC A+B
on,
69
dBc
dBc
Noise Spectral Density Single Tone at
0 dBm
fDAC = 625 MSPS, fOUT = 10.1 MHz 2x Interp, DAC A+B on
161
fDAC = 625 MSPS, fOUT = 150.1 MHz 2x Interp, DAC A+B on
150
Adjacent Channel Leakage Ratio,
Single Carrier
fDAC = 491.52 MSPS, fOUT= 30.72 MHz 2x Interp, DAC A+B on
81
fDAC = 491.52 MSPS, fOUT = 153.6 MHz 2x Interp, DAC A+B on
76
Alternate Channel Leakage Ratio,
Single Carrier
fDAC = 491.52 MSPS, fOUT = 30.72 MHz 2x Interp, DAC A+B on
84
dBc
fDAC = 491.52 MSPS, fOUT = 153.6 MHz 2x Interp, DAC A+B on
77
dBc
Channel Isolation
fDAC = 625 MSPS, fOUT = 10 MHz
84
dBc
WCDMA (3)
(1)
(2)
(3)
fDAC = 625 MSPS, fOUT = 10.1 MHz 2x Interp, DAC A+B on
dBc/Hz
dBc
Measured single ended into 50 Ω load.
4:1 transformer output termination, 50 Ω doubly terminated load.
Single carrier, W-CDMA with 3.84 MHz BW, 5-MHz spacing, centered at IF, PAR = 12dB. TESTMODEL 1, 10 ms
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ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS
over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Byte-wide DDR format
DATACLK frequency = 625 MHz
312.5
MSPS
1x Interpolation
1250
2x Interpolation
1250
LVDS INTERFACE: D[7:0]P/N, DATACLKP/N, FRAMEP/N (1)
fDATA
Input data rate
fBUS
Byte-wide LVDS data transfer rate
VA,B+
Logic high differential input voltage threshold
175
400
VA,B–
Logic low differential input voltage threshold
–175
–400
VCOM
Input Common Mode
1.0
1.2
2.0
V
ZT
Internal termination
85
110
135
Ω
CL
LVDS Input capacitance
MSPS
mV
mV
2
pF
TIMING LVDS INPUTS: DATACLKP/N, double edge latching – See Figure 36
ts(DATA)
Setup time, D[7:0]P/N and FRAMEP/N, valid to
either edge of DATACLKP/N
FRAMEP/N latched on rising edge of
DATACLKP/N only
0
ps
th(DATA)
Hold time, D[7:0]P/N and FRAMEP/N, valid
after either edge of DATACLKP/N
FRAMEP/N latched on rising edge of
DATACLKP/N only
400
ps
t(FRAME)
FRAMEP/N pulse width
fDATACLK is DATACLK frequency in MHz
t_align
Maximum offset between DATACLKP/N and
DACCLKP/N rising edges
FIFO Bypass Mode only
fDACCLK is DACCLK frequency in MHz
1/2fDATACLK
ns
1/2fDACCLK
–0.55
ns
CLOCK INPUT (DACCLKP/N)
Duty cycle
40%
Differential voltage (2)
0.4
60%
1.0
DACCLKP/N Input Frequency
V
625
MHz
fDACCLK /
(8 x interp)
MHz
OUTPUT STROBE (OSTRP/N)
fOSTR
fOSTR = fDACCLK / (n × 8 × Interp) where n
is any positive integer fDACCLK is DACCLK
frequency in MHz
Frequency
Duty cycle
40%
Differential voltage
0.4
60%
1.0
V
TIMING OSTRP/N Input: DACCLKP/N rising edge latching
ts(OSTR)
Setup time, OSTRP/N valid to rising edge of
DACCLKP/N
200
ps
th(OSTR)
Hold time, OSTRP/N valid after rising edge of
DACCLKP/N
200
ps
CMOS INTERFACE: ALARM_SDO, SDIO, SCLK, SDENB, RESETB, TXENABLE
VIH
High-level input voltage
VIL
Low-level input voltage
IIH
High-level input current
–40
IIL
Low-level input current
–40
CI
CMOS Input capacitance
VOH
VOL
1.25
V
0.54
V
40
μA
40
μA
2
pF
SDO, SDIO
Iload = –100 μA
DIGVDD18 –0.2
SDO, SDIO
Iload = –2 mA
0.8 x DIGVDD18
SDO, SDIO
Iload = 100 μA
0.2
V
SDO, SDIO
Iload = 2 mA
0.5
V
V
V
SERIAL PORT TIMING – See Figure 32 and Figure 33
ts(SDENB)
Setup time, SDENB to rising edge of SCLK
20
ns
ts(SDIO)
Setup time, SDIO valid to rising edge of SCLK
10
ns
th(SDIO)
Hold time, SDIO valid to rising edge of SCLK
5
ns
1
μs
100
ns
t(SCLK)
Period of SCLK
Register CONFIG5 read (temperature
sensor read)
All other registers
(1)
(2)
See LVDS INPUTS section for terminology.
Driving the clock input with a differential voltage lower than 1 V will result in degraded performance.
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ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS (continued)
over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER
t(SCLKH)
High time of SCLK
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Register CONFIG5 read (temperature
sensor read)
0.4
μs
All other registers
40
ns
Register CONFIG5 read (temperature
sensor read)
0.4
μs
All other registers
40
t(SCLKL)
Low time of SCLK
td(Data)
Data output delay after falling edge of SCLK
10
ns
tRESET
Minimum RESETB pulsewidth
25
ns
ns
DEFINITION OF SPECIFICATIONS
Adjacent Carrier Leakage Ratio (ACLR): Defined for a 3.84Mcps 3GPP W-CDMA input signal measured in a
3.84MHz bandwidth at a 5MHz offset from the carrier with a 12dB peak-to-average ratio.
Analog and Digital Power Supply Rejection Ratio (APSSR, DPSSR):Defined as the percentage error in the
ratio of the delta IOUT and delta supply voltage normalized with respect to the ideal IOUT current.
Differential Nonlinearity (DNL): Defined as the variation in analog output associated with an ideal 1 LSB
change in the digital input code.
Gain Drift: Defined as the maximum change in gain, in terms of ppm of full-scale range (FSR) per °C, from the
value at ambient (25°C) to values over the full operating temperature range.
Gain Error: Defined as the percentage error (in FSR%) for the ratio between the measured full-scale output
current and the ideal full-scale output current.
Integral Nonlinearity (INL): Defined as the maximum deviation of the actual analog output from the ideal output,
determined by a straight line drawn from zero scale to full scale.
Intermodulation Distortion (IMD3): The two-tone IMD3 is defined as the ratio (in dBc) of the 3rd-order
intermodulation distortion product to either fundamental output tone.
Offset Drift: Defined as the maximum change in DC offset, in terms of ppm of full-scale range (FSR) per °C,
from the value at ambient (25°C) to values over the full operating temperature range.
Offset Error: Defined as the percentage error (in FSR%) for the ratio between the measured mid-scale output
current and the ideal mid-scale output current.
Output Compliance Range: Defined as the minimum and maximum allowable voltage at the output of the
current-output DAC. Exceeding this limit may result reduced reliability of the device or adversely affecting
distortion performance.
Reference Voltage Drift: Defined as the maximum change of the reference voltage in ppm per °C from value at
ambient (25°C) to values over the full operating temperature range.
Spurious Free Dynamic Range (SFDR): Defined as the difference (in dBc) between the peak amplitude of the
output signal and the peak spurious signal.
Signal to Noise Ratio (SNR): Defined as the ratio of the RMS value of the fundamental output signal to the
RMS sum of all other spectral components below the Nyquist frequency, including noise, but excluding the first
six harmonics and dc.
10
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TYPICAL CHARACTERISTICS
5
5
DNL
4
4
3
3
2
2
Error - LSB
Error - LSB
INL
1
0
-1
1
0
-1
-2
-2
-3
-3
-4
-4
-5
0
-5
10000 20000 30000 40000 50000 60000 70000
Code
0
10000 20000 30000 40000 50000 60000 70000
Code
Figure 1. Integral Non-Linearity
Figure 2. Differential Non-Linearity
90
fDAC = 625 MSPS, 2x Interpolation,
IOUTFS = 20 mA
85
SFDR - Spurious Free Dynamic Range - dBc
SFDR - Spurious Free Dynamic Range - dBc
90
80
75
0 dBFS
-6 dBFS
70
65
60
-12 dBFS
55
50
0
50
100
150
200
fOUT - Output Frequency - MHz
250
fDAC = 312.5 MSPS, 0 dBFS,
IOUTFS = 20 mA
85
80
75
1x Interpolation
70
65
60
2x Interpolation
55
50
0
Figure 3. SFDR vs Input Scale
20
40
60
80
100
fOUT - Output Frequency - MHz
120
Figure 4. SFDR vs Interpolation
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TYPICAL CHARACTERISTICS (continued)
90
2x interpolation, 0 dBFS,
IOUTS = 20 mA
SFDR - Spurious Free Dynamic Range - dBc
SFDR - Spurious Free Dynamic Range - dBc
80
75
fDAC = 200 MSPS
70
65
fDAC = 400 MSPS
60
fDAC = 600 MSPS
55
50
fDAC = 625 MSPS, 2x interpolation,
0 dBFS
85
80
75
2 mA
70
10 mA
65
20 mA
60
55
50
0
50
100
150
200
fOUT - Output Frequency - MHz
250
0
50
100
150
200
fOUT - Output Frequency - MHz
Figure 5. SFDR vs fDAC
Figure 6. SFDR vs IOUTFS
10
10
2x Interpolation, 0 dBFS,
fDAC = 625 MSPS,
fOUT = 10 MHz
0
-10
-10
-20
Power - dBm
Power - dBm
2x Interpolation, 0 dBFS,
fDAC = 625 MSPS,
fOUT = 100 MHz
0
-20
-30
-40
-50
-30
-40
-50
-60
-60
-70
-70
-80
-80
-90
0
50
100
150
200
f - Frequency - MHz
250
300
-90
0
Figure 7. Single Tone Spectral Plot
12
250
50
100
150
200
f - Frequency - MHz
250
300
Figure 8. Single Tone Spectral Plot
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TYPICAL CHARACTERISTICS (continued)
95
90
90
fDAC = 625 MSPS, 2x Interpolation,
Tones at fOUT ± 0.5 MHz,
IOUTFS = 20 mA
fDAC = 312.5 MSPS,
Tones at fOUT ± 0.5 MHz,
0 dBFS, IOUTFS = 20 mA
85
85
-6 dBFS
2x Interpolation
IMD3 - dBc
IMD3 - dBc
80
-12 dBFS
75
70
80
75
1x Interpolation
0 dBFS
65
60
70
55
50
0
65
50
100
150
200
fOUT - Output Frequency - MHz
0
250
Figure 9. IMD3 vs Input Scale
20
40
60
80
100
fOUT - Output Frequency - MHz
120
Figure 10. IMD3 vs Interpolation
100
90
95
85
fDAC = 200 MSPS
10 mA
90
80
85
fDAC = 400 MSPS
2 mA
IMD3 - dBc
IMD3 - dBc
75
70
fDAC = 600 MSPS
65
80
75
70
20 mA
65
60
50
60
2x Interpolation,
Tones at fOUT ± 0.5 MHz,
0 dBFS, IOUTS = 20 mA
55
0
50
100
150
200
fOUT - Output Frequency - MHz
55
250
50
0
Figure 11. IMD3 vs fDAC
fDAC = 625 MSPS, 2x Interpolation,
Tones at fOUT ± 0.5 MHz, 0 dBFS
50
100
150
200
fOUT - Output Frequency - MHz
250
Figure 12. IMD3 vs IOUTFS
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TYPICAL CHARACTERISTICS (continued)
170
170
fDAC = 625 MSPS, 2x Interpolation,
IOUTFS = 20 mA
165
fDAC = 312.5 MSPS, 0 dBFS,
IOUTFS = 20 mA
165
160
160
NSD - dBc/Hz
NSD - dBc/Hz
0 dBFS
155
-6 dBFS
150
145
-12 dBFS
2x Interpolation
155
1x Interpolation
150
140
145
135
130
0
50
100
150
200
fOUT - Output Frequency - MHz
250
140
0
20
Figure 13. NSD vs Input Scale
170
2x Interpolation, 0 dBFS,
IOUTS = 20 mA
165
165
160
NSD - dBc/Hz
120
Figure 14. NSD vs Interpolation
170
fDAC = 625 MSPS,
2x Interpolation 0 dBFS
160
155
20 mA
155
fDAC = 600 MSPS
10 mA
150
150
145
145
fDAC = 200 MSPS
2 mA
fDAC = 400 MSPS
140
140
135
135
130
0
50
100
150
200
fOUT - Output Frequency - MHz
250
130
0
Figure 15. NSD vs fDAC
14
40
60
80
100
fOUT - Output Frequency - MHz
50
100
150
200
fOUT - Output Frequency - MHz
250
Figure 16. NSD vs IOUTFS
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TYPICAL CHARACTERISTICS (continued)
90
80
fDAC = 491.52 MSPS, 2x Interpolation
IOUTFS = 20 mA
fDAC = 491.52 MSPS, 2x Interpolation,
IOUTFS = 20 mA
Aternate, 0 dBFS
75
85
ACLR, 0 dBFS
Adjacent 0 dBFS
80
ACLR - dBc
ACLR - dBc
Alternate 0 dBFS
75
Alternate, -6 dBFS
70
ACLR -6 dBFS
65
Adjacent -6 dBFS
Alternate -6 dBFS
70
65
0
60
50
100
150
200
fOUT - Output Frequency - MHz
55
250
0
Figure 17. Single Carrier WCDMA ACLR vs Input Scale
50
100
150
200
fOUT - Output Frequency - MHz
Figure 18. Four Carrier WCDMA ACLR vs Input Scale
* R BW 30 kH z
* RBW 30 kHz
* VBW 300 kHz
* V BW 30 0 k Hz
Re f - 13 d B m
* At t
15 d B
* S WT 10 s
Ref -14.4 dBm
- 20
CL RW R
* Att
10 dB
* SWT 10 s
-20
-30
- 30
1 RM *
250
A
- 40
-40
- 50
-50
- 70
1 RM *
-60
CLRWR
-70
- 80
-80
- 60
- 90
A
-90
N OR
- 10 0
- 11 0
NOR
-100
-110
- 12 0
- 13 0
-120
-130
Ce nt e r 7 0 M Hz
2 MH z/
Tx Channel
Bandwidth
3.84 MHz
Adjacent Channel
Bandwidth
Spacing
3.84 MHz
5 MHz
S pa n 2 0 M Hz
W-CDMA 3GPP FWD
Power
Lower
Upper
Center 153.6 MHz
EXT
-7.62 dBm
-78.89 dB
-78.83 dB
2x Interpolation, 0 dBFS,
fDAC = 491.52 MSPS,
fOUT = 70 MHz
Figure 19. Single Carrier W-CDMA Test Model 1, fOUT = 70 MHz
2 MHz/
Tx Channel
Bandwidth
3.84 MHz
Adjacent Channel
Bandwidth
Spacing
3.84 MHz
5 MHz
2x Interpolation, 0 dBFS,
fDAC = 491.52 MSPS,
fOUT = 153.6 MHz
Span 20 MHz
W-CDMA 3GPP FWD
Power
Lower
Upper
EXT
-8.89 dBm
-76.86 dB
-76.18 dB
Figure 20. Single Carrier W-CDMA Test Model 1,
fOUT = 153.6 MHz
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TYPICAL CHARACTERISTICS (continued)
* RBW 30 kHz
* VBW 300 kHz
* RBW 30 kHz
* VBW 300 kHz
Ref -18 dBm
* Att
10 dB
Ref -19.7 dBm
* SWT 10 s
10 dB
-40
A
-40
-50
-50
1 RM * -60
CLRWR -70
1 RM * -60
CLRWR -70
-80
-80
A
-90
-90
-100
-100
NOR
NOR
-110
-110
-120
-120
-130
-130
Center 70 MHz
3.5 MHz/
Standard: W-CDMA 3GPP FWD
-14.16
-14.20
-14.34
-14.39
-8.25
Span 35 MHz
Adjacent Channel
Lower
Upper
Tx Channels
dBm
dBm
dBm
dBm
dBm
Center 153.6 MHz
EXT
-74.09 dB
-74.14 dB
3.5 MHz/
Ch1(Ref)
Ch2
Ch3
Ch4
2x Interpolation, 0 dBFS,
fDAC = 491.52 MSPS,
fOUT = 70 MHz
Total
-15.80
-15.92
-16.08
-16.21
10 dB
* SWT 10 s
* Att
10 dB
* RBW 30 kHz
* VBW 300 kHz
* SWT 10 s
-30
A
-40
-40
-50
-50
1 RM * -60
CLRWR
-70
1 RM * -60
CLRWR -70
-80
-80
A
-90
-90
-100
NOR
-100
-110
-110
-120
-120
NOR
-130
-130
Center 70 MHz
Adjacent Channel
Bandwidth
Spacing
2x Interpolation, 0 dBFS,
fDAC = 491.52 MSPS,
fOUT = 153.6 MHz
-9.98 dBm
Ref -18.3 dBm
-20
-30
Tx Channel
Bandwidth
EXT
-70.59 dB
-69.18 dB
Figure 22. Four Carrier W-CDMA Test Model 1, fOUT = 153.6 MHz
* VBW 300 kHz
* Att
Lower
Upper
dBm
dBm
dBm
dBm
* RBW 30 kHz
Ref -17.3 dBm
Span 35 MHz
Adjacent Channel
Standard: W-CDMA 3GPP FWD
Tx Channels
Figure 21. Four Carrier W-CDMA Test Model 1, fOUT = 70 MHz
3.5 MHz/
Span 35 MHz
Center 153.6 MHz
EXT
10 MHz
10 MHz
10 MHz
Power
Lower
Upper
-8.39 dBm
-74.18 dB
-70.40 dB
3.5 MHz/
Tx Channel
Bandwidth
10 MHz
Adjacent Channel
Bandwidth
Spacing
10 MHz
10 MHz
Span 35 MHz
EXT
Power
Lower
Upper
-9.49 dBm
-71.66 dB
-69.13 dB
2x Interpolation, 0 dBFS,
fDAC = 491.52 MSPS,
fOUT = 153.6 MHz
2x Interpolation, 0 dBFS,
fDAC = 491.52 MSPS,
fOUT = 70 MHz
Figure 23. 10MHz Single Carrier LTE, fOUT = 70 MHz
16
* SWT 10 s
-30
-30
Ch1(Ref)
Ch2
Ch3
Ch4
Total
* Att
Figure 24. 10MHz Single Carrier LTE, fOUT = 153.6 MHz
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TYPICAL CHARACTERISTICS (continued)
* RBW 30 kHz
* RBW 30 kHz
* VBW 300 kHz
* VBW 300 kHz
Ref -18.8 dBm
* Att
15 dB
Ref -18 dBm
* SWT 10 s
-30
-50
1 RM * -60
-70
1 RM * -60
CLRWR
-70
-80
-80
-90
A
-90
-100
-100
NOR
-110
-110
-120
-120
-130
NOR
-130
Center 70 MHz
6.5 MHz/
Tx Channel
Bandwidth
Span 65 MHz
Center 153.6 MHz
EXT
20 MHz
Adjacent Channel
Bandwidth
Spacing
20 MHz
20 MHz
Power
Lower
Upper
-7.17 dBm
-65.69 dB
-67.79 dB
6.5 MHz/
Tx Channel
Bandwidth
20 MHz
Adjacent Channel
Bandwidth
Spacing
20 MHz
20 MHz
Span 65 MHz
EXT
Power
Lower
Upper
-8.23 dBm
-65.14 dB
-64.96 dB
2x Interpolation, 0 dBFS,
fDAC = 491.52 MSPS,
fOUT = 153.6 MHz
2x Interpolation, 0 dBFS,
fDAC = 491.52 MSPS,
fOUT = 70 MHz
Figure 25. 20MHz Single Carrier LTE, fOUT = 70 MHz
Figure 26. 20MHz Single Carrier LTE, fOUT = 153.6 MHz
300
1000
900
250
2x+coarse_mix
2x+coarse_mix
2x+invsinc
200
DVDD18 - mA
800
Power - mW
* SWT 10 s
-40
A
-50
2x
700
1x+invsinc
600
2x+invsinc
2x
150
1x+invsinc
100
1x
1x
500
400
0
10 dB
-30
-40
CLRWR
* Att
50
50
100
150
200
250
fDATA - MSPS
300
350
0
0
Figure 27. Power vs fDATA
50
100
150
200
250
fDATA - MSPS
300
350
Figure 28. DVDD18 vs fDATA
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TYPICAL CHARACTERISTICS (continued)
100
20
90
18
80
16
CLKVDD18 - mA
DACVDD - mA
14
Coarse_mix on
70
60
50
40
Coarse_mix off
12
10
8
30
6
20
4
10
2
0
0
0
100
200
300
400
fDAC - MSPS
500
600
0
Figure 29. DACVDD18 vs fDAC
100
200
300
400
fDAC - MSPS
500
600
Figure 30. CLKVDD18 vs fDAC
120
100
AVDD33 - mA
80
60
40
20
0
0
100
200
300
400
fDAC - MSPS
500
600
Figure 31. AVDD33 vs fDAC
18
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APPLICATION INFORMATION
SERIAL INTERFACE
The serial port of the DAC3282 is a flexible serial interface which communicates with industry standard
microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the
operating modes of DAC3282. It is compatible with most synchronous transfer formats and can be configured as
a 3 or 4 pin interface by sif4_ena in register CONFIG23. In both configurations, SCLK is the serial interface input
clock and SDENB is serial interface enable. For 3 pin configuration, SDIO is a bidirectional pin for both data in
and data out. For 4 pin configuration, SDIO is data in only and ALARM_SDO is data out only. Data is input into
the device with the rising edge of SCLK. Data is output from the device on the falling edge of SCLK.
Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low for 2 to 5 bytes,
depending on the data length to be transferred (1–4 bytes). The first frame byte is the instruction cycle which
identifies the following data transfer cycle as read or write, how many bytes to transfer, and what address to
transfer the data. Table 1 indicates the function of each bit in the instruction cycle and is followed by a detailed
description of each bit. Frame bytes 2 to 5 comprise the data transfer cycle.
Table 1. Instruction Byte of the Serial Interface
MSB
LSB
Bit
7
6
5
4
3
2
1
0
Description
R/W
N1
N0
A4
A3
A2
A1
A0
R/W
Identifies the following data transfer cycle as a read or write operation. A high indicates a read
operation from DAC3282 and a low indicates a write operation to DAC3282.
[N1 : N0]
Identifies the number of data bytes to be transferred per Table 2. Data is transferred MSB first.
Table 2. Number of Transferred Bytes Within One
Communication Frame
[A4 : A0]
N1
N0
Description
0
0
Transfer 1 Byte
0
1
Transfer 2 Bytes
1
0
Transfer 3 Bytes
1
1
Transfer 4 Bytes
Identifies the address of the register to be accessed during the read or write operation. For
multi-byte transfers, this address is the starting address. Note that the address is written to the
DAC3282 MSB first and counts down for each byte.
Figure 32 shows the serial interface timing diagram for a DAC3282 write operation. SCLK is the serial interface
clock input to DAC3282. Serial data enable SDENB is an active low input to DAC3282. SDIO is serial data in.
Input data to DAC3282 is clocked on the rising edges of SCLK.
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Instruction Cycle
Data Transfer Cycle
SDENB
SCLK
SDIO
rwb
N1
N0
-
A3
A2
tS(SDENB)
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
tSCLK
SDENB
SCLK
SDIO
tSCLKH
tS( SDIO) tH(SDIO)
tSCLKL
Figure 32. Serial Interface Write Timing Diagram
Figure 33 shows the serial interface timing diagram for a DAC3282 read operation. SCLK is the serial interface
clock input to DAC3282. Serial data enable SDENB is an active low input to DAC3282. SDIO is serial data in
during the instruction cycle. In 3 pin configuration, SDIO is data out from DAC3282 during the data transfer
cycle(s), while ALARM_SDO is in a high-impedance state. In 4 pin configuration, ALARM_SDO is data out from
DAC3282 during the data transfer cycle(s). At the end of the data transfer, ALARM_SDO will output low on the
final falling edge of SCLK until the rising edge of SDENB when it will 3-state.
Instruction Cycle
Data Transfer Cycle
SDENB
SCLK
SDIO
rwb
N1
N0
-
A3
A2
A1
ALARM_
SDO
A0
D7
D6
D5
D4
D3
D2
D1
D0
3-pin interface
D7
D6
D5
D4
D3
D2
D1
D0
4-pin interface
SDENB
SCLK
SDIO or
ALARM_SDO
Data n
Data n-1
td (Data)
Figure 33. Serial Interface Read Timing Diagram
20
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Table 3. Register Map
Name
Address
Default
(MSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
CONFIG0
0x00
0x70
qmc_offset_ena
fifo_ena
fifo_reset_ena
multi_sync_ena
alarm_out_ena
alarm_pol
CONFIG1
0x01
0x11
unused
unused
unused
fir_ena
fir4_ena
iotest_ena
CONFIG2
0x02
0x00
unused
unused
unused
unused
CONFIG3
0x03
0x10
64cnt_ena
unused
unused
CONFIG4
0x04
0XFF
CONFIG5
0x05
N/A
CONFIG6
0x06
0x00
0x00
Bit 2
Bit 1
(LSB)
Bit 0
mixer_func(1:0)
unused
twos
output_delay(3:0)
alarm_
2away_ena
fifo_offset(2:0)
coarse_daca(3:0)
alarm_
1away_ena
coarse_dacb(3:0)
tempdata(7:0)
unused
alarm_mask(6:0)
alarm_from_
zerochk
unused
alarm_fifo_
collision
CONFIG7
0x07
reserved
alarm_from_ iotest
CONFIG8
0x08
0x00
iotest_results(7:0)
CONFIG9
0x09
0x7A
iotest_pattern0(7:0)
CONFIG10
0x0A
0xB6
iotest_pattern1(7:0)
CONFIG11
0x0B
0xEA
iotest_pattern2(7:0)
CONFIG12
0x0C
0x45
iotest_pattern3(7:0)
CONFIG13
0x0D
0x1A
iotest_pattern4(7:0)
CONFIG14
0x0E
0x16
iotest_pattern5(7:0)
CONFIG15
0x0F
0xAA
iotest_pattern6(7:0)
CONFIG16
0x10
0xC6
CONFIG17
0x11
0x00
CONFIG18
0x12
0x02
CONFIG19
0x13
0x00
CONFIG20
0x14
0x00
CONFIG21
0x15
0x00
CONFIG22
0x16
0x00
unused
alarm_fifo_
2away
alarm_fifo_
1away
iotest_pattern7(7:0)
reserved
reserved
reserved
bequalsa
aequalsb
reserved
reserved
reserved
reserved
daca_
complement
dacb_
complement
clkdiv_
sync_ena
unused
unused
unused
unused
multi_
sync_sel
rev
qmc_offseta(7:0)
qmc_offsetb(7:0)
qmc_offseta(12:8)
CONFIG23
0x17
0x00
qmc_offsetb(12:8)
CONFIG24
0x18
0x83
CONFIG25
0x19
0x00
CONFIG26
0x1A
0x00
CONFIG27
0x1B
0x00
reserved
CONFIG28
0x1C
0x00
reserved
CONFIG29
0x1D
0x00
reserved
CONFIG30
0x1E
0x00
VERSION31
0x1F
0x41
tsense_ena
clkrecv_sleep
unused
reserved
sleepb
reserved
unused
unused
unused
unused
unused
unused
unused
unused
sif4_ena
clkpath_
sleep_a
clkpath_
sleep_b
sleepa
reserved
reserved
extref_ena
reserved
reserved
reserved
reserved
deviceid(1:0)
version(5:0)
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REGISTER DESCRIPTIONS
Register name: CONFIG0 – Address: 0x00, Default: 0x70
Register
Name
Address
Bit
CONFIG0
0x00
7
Name
Default
Value
Function
qmc_offset_ena
When asserted the DAC offset correction is enabled.
0
6
fifoin_ena
When asserted the FIFO is enabled. When the FIFO is bypassed
DACCCLKP/N and DATACLKP/N must be aligned to within t_align.
1
5
fifo_reset_ena
Allows the FRAME input to act as a FIFO write reset when asserted..
1
4
multi_sync_ena
Allows the FRAME or OSTR signals to be used as a sync signal when
asserted.
This selection is determined by multi_sync_sel in register CONFIG19.
1
3
alarm_out_ena
When asserted the ALARM_SDO pin becomes an output. The
functionality of this pin is controlled by the CONFIG6 alarm_mask
setting.
0
2
alarm_pol
This bit changes the polarity of the ALARM signal. (0=negative logic,
1=positive
0
mixer_func(1:0)
Controls the function of the mixer block.
00
1:0
Mode
mixer_func(1:0)
Normal
00
High Pass(Fs/2)
01
Fs/4
10
–Fs/4
11
Register name: CONFIG1 – Address: 0x01, Default: 0x11
Register
Name
Address
Bit
CONFIG1
0x01
7
Unused
Reserved for factory use.
0
6
Unused
Reserved for factory use.
0
5
Unused
Reserved for factory use.
0
4
fir_ena
When asserted the chip does 2X interpolation of the data.
1
3
fir4_ena
When asserted, the zero-IF sinc correction filter is enabled. This filter
cannot be used unless fir_ena is asserted.
0
2
iotest_ena
When asserted enables the data pattern checker operation.
0
1
Unused
Reserved for factory use.
0
0
twos
When asserted the inputs are expected to be in 2’s complement
format. When de-asserted the input format is expected to be
offset-binary.
1
Name
Default
Value
Function
Register name: CONFIG2 – Address: 0x02, Default: 0x00
Register
Name
Address
Bit
CONFIG2
0x02
7
Unused
Reserved for factory use.
0
6
Unused
Reserved for factory use.
0
5
Unused
Reserved for factory use.
0
4
Unused
Reserved for factory use.
output_delay(3:0)
Delays the output to the DACs from 0 to 15 DAC clock cycles.
3:0
22
Name
Function
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Default
Value
0
0000
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Register name: CONFIG3 – Address: 0x03, Default: 0x10
Register
Name
Address
Bit
CONFIG1
0x00
7
Name
Default
Value
Function
64cnt_ena
This enables resetting the alarms after 64 good samples with the goal
of removing unnecessary errors. For instance, when checking
setup/hold through the pattern checker test, there may initially be
errors. Setting this bit removes the need for a SIF write to clear the
alarm register.
0
6
Unused
Reserved for factory use.
0
5
Unused
Reserved for factory use.
0
fifo_offset(2:0)
When the FIFO is reset, this is the value loaded into the FIFO read
pointer. With this value the initial difference between write and read
pointers can be controlled. This may be helpful in controlling the delay
through the device.
100
1
alarm_2away_ena
When asserted alarms from the FIFO that represent the write and read
pointers being 2 away are enabled.
0
0
alarm_1away_ena
When asserted alarms from the FIFO that represent the write and read
pointers being 1 away are enabled.
0
4:2
Register name: CONFIG4 – Address: 0x04, Default: 0xFF
Register
Name
Address
Bit
CONFIG4
0x04
7:4
Name
coarse_daca(3:0)
Scales the output current in 16 equal steps.
VEXTIO
Rbias
3:0
Default
Value
Function
coarse_dacb(3:0)
´
1111
(coarse_daca/b+1)
Scales the output current in 16 equal steps.
1111
Register name: CONFIG5 – Address: 0x05, READ ONLY
Register
Name
Address
Bit
CONFIG5
0x05
7:0
Name
tempdata(7:0)
Default
Value
Function
This is the output from the chip temperature sensor. The value of this
register in two’s complement format represents the temperature in
degrees Celsius. This register must be read with a minimum SCLK
period of 1μs. (Read Only)
N/A
Register name: CONFIG6 – Address: 0x06, Default: 0x00
Register
Name
Address
CONFIG6
0x06
Bit
7
6:0
Name
Default
Value
Function
Unused
Reserved for factory use.
alarm_mask(6:0)
These bits control the masking of the alarm outputs. This means that the
ALARM_SDO pin will not be asserted if the appropriate bit is set. The
alarm will still show up in the CONFIG7 bits. (0=not masked, 1=
masked).
0
alarm_mask
Masked Alarm
6
alarm_from_zerochk
5
alarm_fifo_collision
4
reserved
3
alarm_from_iotest
2
not used (expansion)
1
alarm_fifo_2away
0
alarm_fifo_1away
0000000
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Register name: CONFIG7 – Address: 0x07, Default: 0x00 (WRITE TO CLEAR)
Register
Name
Address
Bit
CONFIG7
0x07
7
Unused
Reserved for factory use.
0
6
alarm_from_ zerochk
When this bit is asserted the FIFO write pointer has an all zeros
pattern in it. Since this pointer is a shift register, all zeros will
cause the input point to be stuck until the next sync. This alarm
allows checking for this condition.
0
5
alarm_fifo_ collision
Alarm occurs when the FIFO pointers over/under run each other.
0
4
Reserved
Reserved for factory use.
0
3
alarm_from_ iotest
This is asserted when the input data pattern does not match the
pattern in the iotest_pattern registers.
0
2
Unused
Reserved for factory use.
0
1
alarm_fifo_ 2away
Alarm occurs with the read and write pointers of the FIFO are
within 2 addresses of each other.
0
0
alarm_fifo_ 1away
Alarm occurs with the read and write pointers of the FIFO are
within 1 address of each other.
0
Name
Function
Default
Value
Register name: CONFIG8 – Address: 0x08, Default: 0x00 (WRITE TO CLEAR)
Register
Name
Address
Bit
CONFIG8
0x08
7:0
Function
Default
Value
The values of these bits tell which bit in the word failed during the
pattern checker test.
0x00
Name
iotest_results(7:0)
Register name: CONFIG9 – Address: 0x09, Default: 0x7A
Register
Name
Address
Bit
CONFIG9
0x09
7:0
Function
Default
Value
This is dataword0 in the IO test pattern. It is used with the seven
other words to test the input data.
0x7A
Name
iotest_pattern0(7:0)
Register name: CONFIG10 – Address: 0x0A, Default: 0xB6
Register
Name
Address
Bit
CONFIG10
0x0A
7:0
Function
Default
Value
This is dataword1 in the IO test pattern. It is used with the seven
other words to test the input data.
0xB6
Name
iotest_pattern1(7:0)
Register name: CONFIG11 – Address: 0x0B, Default: 0xEA
Register
Name
Address
Bit
CONFIG11
0x0B
7:0
Function
Default
Value
This is dataword2 in the IO test pattern. It is used with the seven
other words to test the input data.
0xEA
Name
iotest_pattern2(7:0)
Register name: CONFIG12 – Address: 0x0C, Default: 0x45
Register
Name
Address
Bit
CONFIG12
0x0C
7:0
24
Function
Default
Value
This is dataword3 in the IO test pattern. It is used with the seven
other words to test the input data.
0x45
Name
iotest_pattern3(7:0)
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Register name: CONFIG13 – Address: 0x0D, Default: 0x1A
Register
Name
Address
Bit
CONFIG13
0x0D
7:0
Function
Default
Value
This is dataword4 in the IO test pattern. It is used with the seven
other words to test the input data.
0x1A
Name
iotest_pattern4(7:0)
Register name: CONFIG14 – Address: 0x0E, Default: 0x16
Register
Name
Address
Bit
CONFIG14
0x0E
7:0
Function
Default
Value
This is dataword5 in the IO test pattern. It is used with the seven
other words to test the input data.
0x16
Name
iotest_pattern5(7:0)
Register name: CONFIG15 – Address: 0x0F, Default: 0xAA
Register
Name
Address
Bit
CONFIG15
0x0F
7:0
Function
Default
Value
This is dataword6 in the IO test pattern. It is used with the seven
other words to test the input data.
0xAA
Name
iotest_pattern6(7:0)
Register name: CONFIG16 – Address: 0x10, Default: 0xC6
Register
Name
Address
Bit
CONFIG16
0x10
7:0
Function
Default
Value
This is dataword7 in the IO test pattern. It is used with the seven
other words to test the input data.
0xC6
Name
iotest_pattern7(7:0)
Register name: CONFIG17 – Address: 0x11, Default: 0x00
Register
Name
Address
Bit
CONFIG17
0x11
7:6
Reserved
Reserved for factory use.
00
5
Reserved
Reserved for factory use.
0
4
Reserved
Reserved for factory use.
0
3:0
Reserved
Reserved for factory use.
0000
Name
Default
Value
Function
Register name: CONFIG18 – Address: 0x12, Default: 0x02
Register
Name
Address
Bit
CONFIG18
0x12
7:5
Reserved
Reserved for factory use.
000
4
Reserved
Reserved for factory use.
0
3
daca_complement
When asserted the output to the DACA is complemented. This
allows to effectively change the + and – designations of the
LVDS data lines.
0
When asserted the output to the DACB is complemented. This
allows to effectively change the + and – designations of the
LVDS data lines.
0
Enables the syncing of the clock divider using the OSTR signal
or the FRAME signal passed through the FIFO. This selection is
determined by multi_sync_sel in register CONFIG19. Syncing of
the clock divider should be done only during device initialization.
1
Reserved for factory use.
0
2
1
0
Name
dacb_complement
clkdiv_sync_ena
Unused
Default
Value
Function
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Register name: CONFIG19 – Address: 0x13, Default: 0x00
Register
Name
Address
Bit
CONFIG
19
0x13
7
bequalsa
When asserted the DACA data is driven onto DACB.
0
6
aequalsb
When asserted the DACB data is driven onto DACA.
0
5
Reserved
Reserved for factory use.
0
4
Unused
Reserved for factory use.
0
3
Unused
Reserved for factory use.
0
2
Unused
Reserved for factory use.
0
1
multi_sync_sel Selects the signal source for multiple device and clock divider synchronization.
Name
multit_sync_sel
0
Default
Value
Function
rev
0
Sync Source
0
OSTR
1
FRAME through FIFO handoff
Reverse the input bits for the data word. MSB becomes LSB.
0
Register name: CONFIG20 – Address: 0x14, Default: 0x00 (CAUSES AUTOSYNC)
Register
Name
Address
Bit
Name
Function
CONFIG20
0x14
7:0
qmc_offseta(7:0)
Lower 8 bits of the DAC A offset correction. The offset is measured in
DAC LSBs. Writing this register causes an autosync to be
generated. This loads the values of all four qmc_offset registers
(CONFIG20-CONFIG23) into the offset block at the same time. When
updating the offset values CONFIG20 should be written last.
Programming any of the other three registers will not affect the
offset setting.
Default
Value
0x00
Register name: CONFIG21 – Address: 0x15, Default: 0x00
Register
Name
Address
Bit
Name
CONFIG21
0x15
7:0
qmc_offsetb(7:0)
Function
Lower 8 bits of the DAC B offset correction. The offset is measured in
DAC LSBs.
Default
Value
0x00
Register name: CONFIG22 – Address: 0x16, Default: 0x00
Register
Name
Address
Bit
Name
CONFIG22
0x16
7:3
qmc_offseta(12:8
)
Upper 5 bits of the DAC A offset correction.
2
Unused
Reserved for factory use.
0
1
Unused
Reserved for factory use.
0
0
Unused
Reserved for factory use.
0
26
Function
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Default
Value
00000
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Register name: CONFIG23 – Address: 0x27, Default: 0x00
Register
Name
Address
Bit
CONFIG23
0x17
7:3
Name
Default
Value
Function
qmc_offsetb(12:8) Upper 5 bits of the DAC B offset correction.
00000
2
sif4_ena
When asserted the SIF interface becomes a 4 pin interface. The
ALARM_SDO pin is turned into a dedicated output for the reading of
data.
0
1
clkpath_sleep_a
When asserted puts the clock path through DAC A to sleep. This is
useful for sleeping individual DACs. Even if the DAC is asleep the clock
needs to pass through it for the logic to work. However, if the chip is
being put into a power down mode, then all parts of the DAC can be
turned off.
0
0
clkpath_sleep_b
When asserted puts the clock path through DAC B to sleep.
0
Register name: CONFIG24 – Address: 0x18, Default: 0x83
Register
Name
Address
Bit
CONFIG24
0x18
7
tsense_ena
Turns on the temperature sensor when asserted.
1
6
clkrecv_sleep
When asserted the clock input receiver gets put into sleep mode.
This also affects the OSTR receiver.
0
5
Unused
Reserved for factory use.
0
4
Reserved
Reserved for factory use.
0
3
sleepb
When asserted DACB is put into sleep mode.
0
2
sleepa
When asserted DACA is put into sleep mode.
0
1
Reserved
Reserved for factory use.
1
0
Reserved
Reserved for factory use.
1
Name
Default
Value
Function
Register name: CONFIG25 – Address: 0x19, Default: 0x00
Register
Name
Address
Bit
CONFIG25
0x19
7:3
Reserved
Reserved for factory use.
2
extref_ena
Allows the device to use an external reference or the internal
reference. (0=internal, 1=external)
0
1
Reserved
Reserved for factory use.
0
0
Reserved
Reserved for factory use.
0
Name
Default
Value
Function
00000
Register name: CONFIG26 – Address: 0x1A, Default: 0x00
Register
Name
Address
Bit
CONFIG26
0x1A
7
Unused
Reserved for factory use.
0
6
Unused
Reserved for factory use.
0
5
Unused
Reserved for factory use.
0
4
Unused
Reserved for factory use.
0
3
Unused
Reserved for factory use.
0
Reserved
Reserved for factory use.
000
2:0
Name
Function
Default
Value
Register name: CONFIG27 – Address: 0x1B, Default: 0x00
Register
Name
Address
Bit
CONFIG27
0x1B
7:0
Name
Reserved
Function
Reserved for factory use.
Default
Value
0x00
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Register name: CONFIG28 – Address: 0x1C, Default: 0x00
Register
Name
Address
Bit
CONFIG28
0x1C
7:0
Name
Reserved
Function
Reserved for factory use.
Default
Value
0x00
Register name: CONFIG29 – Address: 0x1D, Default: 0x00
Register
Name
Address
Bit
CONFIG29
0x1D
7:0
Name
Reserved
Function
Reserved for factory use.
Default
Value
0x00
Register name: CONFIG30 – Address: 0x1E, Default: 0x00
Register
Name
Address
Bit
CONFIG30
0x1E
7:0
Name
Reserved
Default
Value
Function
Reserved for factory use.
0x00
Register name: VERSION31 – Address: 0x1F, Default: 0x41 (READ ONLY)
Register
Name
Address
Bit
VERSION31
0x1F
7:0
deviceid(1:0)
Returns ‘01’ for DAC3282. (Read Only)
5:0
version(5:0)
A hardwired register that contains the version of the chip. (Read Only)
28
Name
Default
Value
Function
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01
000001
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DATA INTERFACE
The DAC3282 has a single 8-bit LVDS bus that accepts dual, 16-bit data input in byte-wide format. Data into the
DAC3282 is formatted according to the diagram shown in Figure 34 where index 0 is the data LSB and index 15
is the data MSB. The data is sampled by DATACLK, a double data rate (DDR) clock.
The FRAME signal is required to indicate the beginning of a frame. The frame signal can be either a pulse or a
periodic signal where the frame period corresponds to 8 samples. The pulse-width (t(FRAME)) needs to be at least
equal to 1/2f the DATACLK period. FRAME is sampled by a rising edge in DATACLK.
The setup and hold requirements listed in the specifications tables must be met to ensure proper sampling.
SAMPLE 0
D[7:0]P/N
FRAMEP/N
I0
[15:8]
I0
[7:0]
Q0
[15:8]
SAMPLE 1
Q0
[7:0]
I1
[15:8]
I1
[7:0]
Q1
[15:8]
Q1
[7:0]
t(FRAME)
DATACLKP /N
(DDR)
Figure 34. Byte-Wide Data Transmission Format
INPUT FIFO
The DAC3282 includes a 2-channel, 16-bits wide and 8-samples deep input FIFO which acts as an elastic buffer.
The purpose of the FIFO is to absorb any timing variations between the input data and the internal DAC data
rate clock such as the ones resulting from clock-to-data variations from the data source.
Figure 35 shows the block diagram of the FIFO.
Clock Handoff
Input Side
Clocked by DATACLK
x2
Two cycles, one for I-data and another
for Q-data
Initial
Position
8-bit
8-bit
Frame Align
Q-data, 16-bit
Data[7:0]
32-bit
0
Sample 0
I0[15:0], Q0[15:0]
0
1
Sample 1
I1[15:0], Q1[15:0]
1
2
Sample 2
I2[15:0], Q2[15:0]
2
3
Sample 3
I3[15:0], Q3[15:0]
3
4
Sample 4
I4[15:0], Q4[15:0]
4
5
Sample 5
I5[15:0], Q5[15:0]
5
6
Sample 6
I6[15:0], Q6[15:0]
6
7
Sample 7
I7[15:0], Q7[15:0]
7
FRAME
Write Pointer Reset
32-bit
0…7
Read Pointer
I-data, 16-bit
0…7
Write Pointer
Data[15:8]
D[7:0]
Output Side
Clocked by FIFO Out Clock
(DACCLK/Interpolation Factor)
FIFO:
2 x 16-bits wide
8-samples deep
16-bit
FIFO I Output
FIFO Q Output
16-bit
Initial
Position
Read Pointer Reset
Figure 35. DAC3282 FIFO Block Diagram
Data is written to the device 8-bits at a time on the rising and falling edges of DATACLK. In order to form a
complete 32-bit wide sample (16-bit I-data and 16-bit Q-data) two DATACLK periods are required as shown in
Figure 36. Each 32-bit wide sample is written into the FIFO at the address indicated by the write pointer.
Similarly, data from the FIFO is read by the FIFO Out Clock 32-bits at a time from the address indicated by the
read pointer. The FIFO Out Clock is generated internally from the DACCLK signal and its rate is equal to
DACCLK/Interpolation. Each time a FIFO write or FIFO read is done the corresponding pointer moves to the next
address.
The reset position for the FIFO read and write pointers is set by default to addresses 0 and 4 as shown in
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Figure 35. This offset gives optimal margin within the FIFO. The default read pointer location can be set to
another value using fifo_offset(2:0) in register CONFIG3. Under normal conditions data is written-to and
read-from the FIFO at the same rate and consequently the write and read pointer gap remains constant. If the
FIFO write and read rates are different, the corresponding pointers will be cycling at different speeds which could
result in pointer collision. Under this condition the FIFO attempts to read and write data from the same address at
the same time which will result in errors and thus must be avoided.
The FRAME signal besides acting as a frame indicator can also used to reset the FIFO pointers to their initial
location. Unlike Data, the FRAME signal is latched only on the rising edges of DATACLK. When a rising edge
occurs on FRAME, the pointers will return to their original position. The write pointer is always set back to
position 0 upon reset. The read pointer reset position is determined by fifo_offset (address 4 by default).
The reset can be done periodically or only once during initialization as the pointer automatically returns to the
initial position when the FIFO has been filled. To enable a single reset, fifo_reset_ena (CONFIG0, bit 5) must be
set to 0 after initialization.
LVDS Pairs (Data Source)
D[7:0]P/N
Q3[15:8]
Q3[7:0]
I4[15:8]
I4[7:0]
Q4[15:8]
Q4[7:0]
I5[15:8]
I5[7:0]
Q5[15:8]
Q5[7:0]
I6[15:8]
I6[7:0]
Q6[15:8]
Q6[7:0]
I7[15:8]
I7[7:0]
Q7[15:8]
Write sample 4 to FIFO (32-bits)
ts(DATA )
Write I4[7:0] (8-bits) to Write Q4[7:0] (8-bits) to
DAC on falling edge
DAC on falling edge
ts(DATA )
DATACLKP /N
(DDR)
th(DATA )
Write I4[15:8] (8-bits) to Write Q4[15:8] (8-bits) to
DAC on rising edge
DAC on rising edge
ts(DATA )
FRAMEP/N
th(DATA )
th(DATA )
Resets write pointer to position 0
Figure 36. FIFO Write Description
FIFO ALARMS
The FIFO only operates correctly when the write and read pointers are positioned properly. If either pointer over
or under runs the other, samples will be duplicated or skipped. To prevent this, register CONFIG7 can be used to
track three FIFO related alarms:
• alarm_fifo_2away. Occurs when the pointers are within two addresses of each other.
• alarm_fifo_1away. Occurs when the pointers are within one address of each other.
• alarm_fifo_collision. Occurs when the pointers are equal to each other.
These three alarm events are generated asynchronously with respect to the clocks and can be accessed either
through CONFIG7 or through the ALARM_SDO pin.
FIFO MODES OF OPERATION
The DAC3282 FIFO can be completely bypassed through register CONFIG0. The register configuration for each
mode is described in Table 4.
Register
Control Bits
CONFIG0
fifo_ena, fifo_reset_ena, multi_sync_ena
Table 4. FIFO Operation Modes
CONFIG0 FIFO Bits
FIFO Mode
30
fifo_ena
fifo_reset_ena
multi_sync_ena
Enabled
1
1
1
Bypass
0
X
X
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Enabled Mode
This is the recommended mode of operation for the DAC3282. In FIFO enabled mode, the FIFO is active and
can be reset continuously or only once during initialization. To reset only once, fifo_reset_ena must be set to 0
after initialization.
Bypass Mode
In FIFO bypass mode, the FIFO block is not used. As a result the input data is handed off from the DATACLK to
the DACCLK domain without any compensation. In this mode the relationship between DATACLK and DACCLK
(t_align) is critical and used as a synchronizing mechanism for the internal logic. Due to the t_align constraint it is
highly recommended that a clock synchronizer device such as Texas Instruments’ CDCM7005 or CDCE62005 is
used to provide both clock inputs. In bypass mode the pointers have no effect on the data path or handoff.
DATA PATTERN CHECKER
The DAC3282 incorporates a simple pattern checker test in order to determine errors in the data interface. The
test mode is enabled by asserting iotest_ena in register CONFIG1. In test mode the analog outputs are
deactivated regardless of the state of TXENABLE.
The data pattern key used for the test is 8 words long and is specified by the contents of iotest_pattern[0:7] in
registers CONFIG9 through CONFIG16. The data pattern key can be modified by changing the contents of these
registers.
The first word in the test frame is determined by a rising edge transition in FRAMEP/N. The test mode
determines if one or more words were received incorrectly by comparing the received data against the data
pattern key. The bits in iotest_results(7:0) in register CONFIG8 indicate which words were received incorrectly.
Furthermore, an error condition will trigger the alarm_from_iotest bit in register CONFIG7. Once set, the
alarm_from_iotest bit must be reset through the serial interface to allow further testing. Alternatively, the
64cnt_ena bit in register CONFIG3 can be enabled to reset the alarms automatically after 64 good samples
without the need for a SIF write to clear the alarm.
FIR FILTERS
The DAC3282 has two FIR filters, a 2x interpolation FIR (FIR0) and a non-interpolating FIR (FIR4) that
compensates for the sinc droop of the DAC on zero-IF applications. The correction filter is placed before the
interpolating filter and can only be used with both FIRs enabled.
Figure 37 shows the magnitude spectrum response for FIR0, a 59-tap interpolating half-band filter. The transition
band is from 0.4 to 0.6 × fIN (the input data rate for the FIR filter) with < 0.002dB of pass-band ripple and > 85 dB
stop-band attenuation. Figure 38 shows the transition band region from 0.36 to 0.46 × fIN. Up to 0.45 × fIN there is
less than 0.5 dB of attenuation.
The DAC sample and hold operation results in the well known sin(x)/x or sinc(x) frequency response shown in
Figure 39 (red line). The DAC3282 has a 5-tap inverse sinc filter (FIR4) placed before the 2x interpolation filter to
compensate for this effect up to 0.2 × fDAC. The inverse sinc filter runs at the input data rate and is operational
only if the 2x interpolation filter is enabled as well, correspondingly the rate of this filter is always half of the DAC
update rate. As a result, the filter cannot completely flatten the frequency response of the sample and hold output
as shown in Figure 39.
Figure 40 shows the magnitude spectrum for FIR4 over the correction range. The inverse sinc filter response
(Figure 40, black line) has approximately the opposite frequency response to sin(x)/x between 0 to 0.2 x fDAC,
resulting in the corrected response in Figure 40 (blue line). Between 0 to 0.2 × fDAC, the inverse sinc filter
compensates for the sample and hold roll-off with less than 0.04-dB error.
The zero-IF sinc filter has a gain > 1 at all frequencies. Therefore, the input data must be reduced from full scale
to prevent saturation in the filter. The amount of back-off required depends on the signal frequency, and is set
such that at the signal frequencies the combination of the input signal and filter response is less than 1 (0 dB).
For example, if the signal input to FIR4 is at 0.1 × fDAC, the response of FIR4 is 0.1 dB, and the signal must be
backed off from full scale by 0.1 dB to avoid saturation.
The filter taps for all digital filters are listed in Table 5.
Note that the loss of signal amplitude may result in lower SNR due to decrease in signal amplitude.
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20
0.1
0
0
-20
Magnitude - dB
Magnitude - dB
-0.1
-40
-60
-80
-100
-0.2
-0.3
-0.4
-120
-0.5
-140
-160
0
0.1
0.2 0.3
0.4 0.5 0.6
f/fin
0.7
0.8 0.9
1
0.36 0.37 0.38 0.39 0.4 0.41 0.42 0.43 0.44 0.45 0.46
f/fin
Figure 37. Magnitude Spectrum for FIR0
Figure 38. FIR0 Transition Band
4
0.5
3
0.4
0.3
FIR4
2
0.2
0
Corrected
-1
-2
Magnitude - dB
Magnitude - dB
FIR4
1
0.1
Corrected
0
-0.1
-0.2
Sin(x)/x
Sin(x)/x
-0.3
-3
-4
0
-0.4
0.05 0.1 0.15 0.2 0.25 0.3 0.35
fOUT/fDAC
0.4 0.45 0.5
Figure 39. Magnitude Spectrum for Zero-IF Sinc
Correction Filter up to 0.5 × fDAC
32
-0.5
0
0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
fOUT/fDAC
Figure 40. Correction Range of Zero-IF Sinc
Correction Filter 0 to 0.2 × fDAC
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Table 5. FIR Filter Coefficients
FIR0
2x Interpolating Half-Band Filter
FIR4
Non-Interpolating Zero-IF
Sinc Correction Filter
59 Taps
5 Taps
4
4
1
0
0
–5
–12
–12
0
0
–5
28
28
1
0
0
–58
–58
0
0
108
108
0
0
–188
–188
0
0
308
308
0
0
–483
–483
0
0
734
734
0
0
–1091
–1091
0
0
1607
1607
0
0
–2392
–2392
0
0
3732
3732
0
0
–6681
–6681
0
0
20768
20768
32768
(1)
264
(1)
(1)
Center taps are highlighted in BOLD.
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COARSE MIXER
The DAC3282 has a coarse mixer block capable of shifting the input signal spectrum by the fixed mixing
frequencies fS/2 or ±fS/4. The coarse mixing function is built into the interpolation filter and thus FIR0 must be
enabled to use it.
Treating channels A and B as a complex vector of the form I(t) + j Q(t), where I(t) = A(t) and Q(t) = B(t), the
outputs of the coarse mixer, AOUT(t) and BOUT(t) are equivalent to:
A OUT (t) = A(t)cos(2p fCMIX t) - B(t)sin(2p fCMIX t)
(1)
BOUT (t) = A(t)sin(2p fCMIX t) + B(t)cos(2p fCMIX t)
(2)
where fCMIX is the fixed mixing frequency selected by mixer_func(1:0). For fS/2, +fS/4 and –fS/4 the above
operations result in the simple mixing sequences shown in Table 6.
Table 6. Coarse Mixer Sequences
Mode
mixer_func(1:0)
Mixing Sequence
Normal
(Low Pass, No Mixing)
00
AOUT = { +A, +A , +A, +A }
BOUT = { +B, +B , +B, +B }
fS/2
01
AOUT = { +A, –A , +A, –A }
BOUT = { +B, –B , +B, –B }
+fS/4
10
AOUT = { +A, –B , –A, +B }
BOUT = { +B, +A , –B, –A }
–fS/4
11
AOUT = { +A, +B , –A, –B }
BOUT = { +B, –A , –B, +A }
(x2 Bypass)
FIR 0
x2
B Data In
A Data Out
Coarse Mixer
x2
A Data In
B Data Out
Block Diagram
A Mix In
0
A Mix Out
1
0 1
1 -1
1
B Mix In
B Mix Out
0
0 1
1 -1
mixer_func(1:0)
Mix Sequencer
Figure 41. Coarse Mixers Block Diagram
The coarse mixer in the DAC3282 treats the A and B inputs as complex input data and for most mixing
frequencies produces a complex output. Only when the mixing frequency is set to fS/2 the A and B channels can
be maintained isolated as shown in Table 6. In this case the two channels are upconverted as independent
signals. By setting the mixer to fS/2 the FIR0 outputs are inverted thus behaving as a high-pass filter.
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Table 7. Dual-Channel Real Upconversion Options
(1)
FIR Mode
Input Frequency (1)
Output Frequency (1)
Signal Bandwidth (1)
Low pass
0.0 to 0.4 x fDATA
0.0 to 0.4 x fDATA
0.4 x fDATA
No
High pass
0.0 to 0.4 x fDATA
0.6 to 1.0 x fDATA
0.4 x fDATA
Yes
Spectrum Inverted?
fDATA is the input data rate of each channel after de-interleaving.
DIGITAL OFFSET CONTROL
The qmc_offseta(12:0) and qmc_offsetb(12:0) values in registers CONFIG20 through CONFIG23 can be used to
independently adjust the A and B path DC offsets. Both offset values are in represented in 2s-complement format
with a range from –4096 to 4095.
Note that a write to register CONFIG20 is required to load the values of all four qmc_offset registers
(CONFIG20-CONFIG23) into the offset block simultaneously. When updating the offset values CONFIG20 should
be written last. Programming any of the other three registers will not affect the offset setting.
The offset value adds a digital offset to the digital data before digital-to-analog conversion. Since the offset is
added directly to the data it may be necessary to back off the signal to prevent saturation. Both data and offset
values are LSB aligned.
qmc_offseta
{-4096 , -4095, … , 4095}
13
16
S
A Data In
16
S
B Data In
13
16
A Data Out
16
B Data Out
qmc_offsetb
{-4096 , -4095, … , 4095}
Figure 42. Digital Offset Block Diagram
TEMPERATURE SENSOR
The DAC3282 incorporates a temperature sensor block which monitors the temperature by measuring the
voltage across 2 transistors. The voltage is converted to an 8-bit digital word using a successive-approximation
(SAR) analog to digital conversion process. The result is scaled, limited and formatted as a twos complement
value representing the temperature in degrees Celsius.
The sampling is controlled by the serial interface signals SDENB and SCLK. If the temperature sensor is enabled
(tsense_ena = 1 in register CONFIG24) a conversion takes place each time the serial port is written or read. The
data is only read and sent out by the digital block when the temperature sensor is read in register CONFIG5. The
conversion uses the first eight clocks of the serial clock as the capture and conversion clock, the data is valid on
the falling eighth SCLK. The data is then clocked out of the chip on the rising edge of the ninth SCLK. No other
clocks to the chip are necessary for the temperature sensor operation. As a result the temperature sensor is
enabled even when the device is in sleep mode.
In order for the process described above to operate properly, the serial port read from CONFIG5 must be done
with an SCLK period of at least 1 µs. If this is not satisfied the temperature sensor accuracy is greatly reduced.
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POWER-UP SEQUENCE
The following startup sequence is recommended to power-up the DAC3282:
1. Set TXENABLE low.
2. Supply 1.8V to DACVDD18, DIGVDD18, CLKVDD18 and VFUSE simultaneously and 3.3V to AVDD33.
Within AVDD33 the multiple AVDD33 pins should be powered up simultaneously. The 1.8V and 3.3V
supplies can be powered up simultaneously or in any order.
There are no specific requirements on the ramp rate for the supplies.
Provide all LVPECL inputs: DACCLKP/N and if used OSTRP/N.
Toggle the RESETB pin for a minimum 25 ns active low pulse width.
Program the SIF registers.
Provide all LVDS inputs (D[7:0]P/N, DATACLKP/N and FRAMEP/N) simultaneously.
Sync the clock dividers and FIFO. After a FRAMEP/N low-to-high transition, clock divider syncing must be
disabled by setting clkdiv_sync_ena (CONFIG18, bit 1) to 0. Optionally, disable FIFO and device syncing by
setting fifo_reset_ena (CONFIG0, bit 5) and multi_sync_ena (CONFIG0, bit 4) to 0. Except when in
Multi-DAC operation it is recommended to sync the DACs and their FIFOs only once during initialization.
8. Enable transmit of data by asserting the TXENABLE pin.
3.
4.
5.
6.
7.
SLEEP MODES
The DAC3282 features independent sleep control of each DAC (sleepa and sleepb), their corresponding clock
path (clkpath_sleep_a and clkpath_sleep_b) as well as the clock input receiver of the device (clkrecv_sleep). The
sleep control of each of these components is done through the SIF interface and is enabled by setting a 1 to the
corresponding sleep register.
Complete power down of the device is set by setting all of these components to sleep. Under this mode the
supply power consumption is reduced to 15mW. Power-up time in this case will be in the milliseconds range.
Alternatively for those applications were power-up and power-down times are critical it is recommended to only
set the DACs to sleep through the sleepa and sleepb registers. In this case both the sleep and wake-up times
are only 90µs.
LVPECL INPUTS
Figure 43 shows an equivalent circuit for the DAC input clock (DACCLKP/N) and the FIFO output strobe clock
(OSTRP/N).
CLKVDD
333 W
DACCLKP
OSTRP
2 kW
Note: Input common mode level is
approximately 2/3*CLKVDD18,
or 1.2V nominal.
2 kW
DACCLKN
OSTRN
666 W
GND
Figure 43. DACCLKP/N and OSTRP/N Equivalent Input Circuit
Figure 44 shows the preferred configuration for driving the CLKIN/CLKINC input clock with a differential
ECL/PECL source.
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0.1 mF
Differential +
ECL
or
(LV)PECL
source
-
CLKIN
CAC
100 W
CLKINC
82.5 W
130 W
RT
130 W
0.1 mF
RT
82.5 W
VTT
Figure 44. Preferred Clock Input Configuration With a Differential ECL/PECL Clock Source
LVDS INPUTS
The D[7:0]P/N, DATACLKP/N and FRAMEP/N LVDS pairs have the input configuration shown in Figure 45.
Figure 46 shows the typical input levels and common-move voltage used to drive these inputs.
To Adjacent
LVDS Input
50
D[7:0]P,
DATACLKP ,
FRAMEP
100pF
Total
D[7:0]N,
DATACLKN ,
FRAMEN
LVDS
Receiver
50
Ref Note (1)
To Adjacent
LVDS Input
Note (1): RCENTER node common
to the D[7:0] P/N, DATACLKP / N and
FRAMEP/N receiver inputs
Figure 45. D[7:0]P/N, DATACLKP/N and FRAMEP/N LVDS Input Configuration
Example
D[7:0]P,
DATACLKP ,
FRAMEP
LVDS
Receiver
100
VA,B
VCOM =
(VA+VB)/2
DAC3282
VA
1.40V
VB
1.00V
400mV
VA,B
0V
VA
VB
D[7:0]N,
DATACLKN ,
FRAMEN
-400mV
GND
1
Logical Bit
Equivalent
0
Figure 46. LVDS Data (D[7:0]P/N, DATACLKP/N, FRAMEP/N Pairs) Input Levels
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Table 8. Example LVDS Data Input Levels
Applied Voltages
Resulting Differential
Voltage
Resulting
Common-Mode
Voltage
VCOM
VA
VB
VA,B
1.4 V
1.0 V
400 mV
1.0 V
1.4 V
–400 mV
1.2 V
0.8 V
400 mV
0.8 V
1.2 V
–400 mV
Logical Bit Binary
Equivalent
1
1.2 V
0
1
1.0 V
0
CMOS DIGITAL INPUTS
Figure 47 shows a schematic of the equivalent CMOS digital inputs of the DAC3282. SDIO, SCLK and
TXENABLE have pull-down resistors while SDENB and RESETB have pull-up resistors internal to the DAC3282.
See the specification table for logic thresholds. The pull-up and pull-down circuitry is approximately equivalent to
100kΩ.
DIGVDD 18
DIGVDD 18
internal
digital in
SDIO
SCLK
TXENABLE
internal
digital in
SDENB
RESETB
GND
GND
Figure 47. CMOS/TTL Digital Equivalent Input
REFERENCE OPERATION
The DAC3282 uses a bandgap reference and control amplifier for biasing the full-scale output current. The
full-scale output current is set by applying an external resistor RBIAS to pin BIASJ. The bias current IBIAS through
resistor RBIAS is defined by the on-chip bandgap reference voltage and control amplifier. The default full-scale
output current equals 16 times this bias current and can thus be expressed as:
IOUTFS = 16 × IBIAS = 16 × VEXTIO / RBIAS
Each DAC has a 4-bit independent coarse gain control via coarse_daca(3:0) and coarse_dacb (3:0) in the
CONFIG4 register. Using gain control, the IOUTFS can be expressed as:
IOUTAFS = (DACA_gain + 1) × IBIAS = (DACA_gain + 1) × VEXTIO / RBIAS
IOUTBFS = (DACB_gain + 1) × IBIAS = (DACB_gain + 1) × VEXTIO / RBIAS
Where VEXTIO is the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage of
1.2V. This reference is active when extref_ena = ‘0’ in CONFIG25. An external decoupling capacitor CEXT of 0.1
μF should be connected externally to terminal EXTIO for compensation. The bandgap reference can additionally
be used for external reference operation. In that case, an external buffer with high impedance input should be
applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference can be
disabled and overridden by an external reference by setting the CONFIG25 extref_ena control bit. Capacitor CEXT
may hence be omitted. Terminal EXTIO thus serves as either input or output node.
The full-scale output current can be adjusted from 20 mA down to 2 mA by varying resistor RBIAS or changing the
externally applied reference voltage. The internal control amplifier has a wide input range, supporting the
full-scale output current range of 20 dB.
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DAC TRANSFER FUNCTION
The CMOS DAC’s consist of a segmented array of NMOS current sinks, capable of sinking a full-scale output
current up to 20 mA. Differential current switches direct the current to either one of the complementary output
nodes IOUT1 or IOUT2. (DACA = IOUTA1 or IOUTA2 and DACB = IOUTB1 or IOUTB2.) Complementary output
currents enable differential operation, thus canceling out common mode noise sources (digital feed-through,
on-chip and PCB noise), dc offsets, even order distortion components, and increasing signal output power by a
factor of two.
The full-scale output current is set using external resistor RBIAS in combination with an on-chip bandgap voltage
reference source (+1.2V) and control amplifier. Current IBIAS through resistor RBIAS is mirrored internally to
provide a maximum full-scale output current equal to 16 times IBIAS.
The relation between IOUT1 and IOUT2 can be expressed as:
IOUT1 = – IOUTFS – IOUT2
We will denote current flowing into a node as – current and current flowing out of a node as + current. Since the
output stage is a current sink the current can only flow from AVDD into the IOUT1 and IOUT2 pins. The output
current flow in each pin driving a resistive load can be expressed as:
IOUT1 = IOUTFS × (65535 – CODE) / 65536
IOUT2 = IOUTFS × CODE / 65536
where CODE is the decimal representation of the DAC data input word.
For the case where IOUT1 and IOUT2 drive resistor loads RL directly, this translates into single ended voltages
at IOUT1 and IOUT2:
VOUT1 = AVDD – | IOUT1 | × RL
VOUT2 = AVDD – | IOUT2 | × RL
Assuming that the data is full scale (65536 in offset binary notation) and the RL is 25 Ω, the differential voltage
between pins IOUT1 and IOUT2 can be expressed as:
VOUT1 = AVDD – | –0mA | × 25 Ω = 3.3 V
VOUT2 = AVDD – | –20mA | × 25 Ω = 2.8 V
VDIFF = VOUT1 – VOUT2 = 0.5V
Note that care should be taken not to exceed the compliance voltages at node IOUT1 and IOUT2, which would
lead to increased signal distortion.
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ANALOG CURRENT OUTPUTS
Figure 48 shows a simplified schematic of the current source array output with corresponding switches.
Differential switches direct the current of each individual NMOS current source to either the positive output node
IOUT1 or its complementary negative output node IOUT2. The output impedance is determined by the stack of
the current sources and differential switches, and is typically >300 kΩ in parallel with an output capacitance of 5
pF.
The external output resistors are referred to an external ground. The minimum output compliance at nodes
IOUT1 and IOUT2 is limited to AVDD – 0.5 V, determined by the CMOS process. Beyond this value, transistor
breakdown may occur resulting in reduced reliability of the DAC3282 device. The maximum output compliance
voltage at nodes IOUT1 and IOUT2 equals AVDD + 0.5 V. Exceeding the minimum output compliance voltage
adversely affects distortion performance and integral non-linearity. The optimum distortion performance for a
single-ended or differential output is achieved when the maximum full-scale signal at IOUT1 and IOUT2 does not
exceed 0.5 V.
AVDD
RLOAD
RLOAD
IOUT1
IOUT2
S(1)
S(N)
S(2)
S(1)C
S(2)C
S(N)C
...
Figure 48. Equivalent Analog Current Output
The DAC3282 can be easily configured to drive a doubly terminated 50 Ω cable using a properly selected RF
transformer. Figure 49 and Figure 50 show the 50 Ω doubly terminated transformer configuration with 1:1 and 4:1
impedance ratio, respectively. Note that the center tap of the primary input of the transformer has to be
connected to AVDD to enable a DC current flow. Applying a 20 mA full-scale output current would lead to a 0.5
Vpp for a 1:1 transformer and a 1 Vpp output for a 4:1 transformer. The low dc-impedance between IOUT1 or
IOUT2 and the transformer center tap sets the center of the ac-signal at AVDD, so the 1 Vpp output for the 4:1
transformer results in an output between AVDD + 0.5 V and AVDD – 0.5 V.
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AVDD
3.3 V
50 W
1:1
IOUT 1
RLOAD
50 W
100 W
IOUT 2
50 W
AVDD 3.3 V
Figure 49. Driving a Doubly Terminated 50 Ω Cable Using a 1:1 Impedance Ratio Transformer
AVDD
3.3 V
100 W
4 :1
IOUT 1
RLOAD
50 W
IOUT 2
100 W
AVDD 3.3 V
Figure 50. Driving a Doubly Terminated 50 Ω Cable Using a 4:1 Impedance Ratio Transformer
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PASSIVE INTERFACE TO ANALOG QUADRATURE MODULATORS
A common application in communication systems is to interface the DAC to an IQ modulator like the TRF3703
family of modulators from Texas Instruments. The input of the modulator is generally of high impedance and
requires a specific common-mode voltage. A simple resistive network can be used to maintain 50Ω load
impedance for the DAC3282 and also provide the necessary common-mode voltages for both the DAC and the
modulator.
Vin ~ Varies
Vout ~ 2.8 to 3.8 V
I1
Signal Conditioning
IOUTA1
IOUTA2
IOUTB1
IOUTB2
I2
S
Q1
RF
Q2
Quadrature modulator
Figure 51. DAC to Analog Quadrature Modulator Interface
The DAC3282 has a maximum 20mA full-scale output and a voltage compliance range of AVDD ± 0.5 V. The
TRF3703 IQ modulator family can be operated at three common-mode voltages: 1.5V, 1.7V, and 3.3V.
Figure 52 shows the recommended passive network to interface the DAC3282 to the TRF3703-17 which has a
common mode voltage of 1.7V. The network generates the 3.3V common mode required by the DAC output and
1.7V at the modulator input, while still maintaining 50Ω load for the DAC.
V1
R1
I
I
R2
R3
DAC3282
TRF3703-17
V2
R3
R2
/I
/I
R1
V1
Figure 52. DAC3282 to TRF3703-17 Interface
If V1 is set to 5V and V2 is set to -5V, the corresponding resistor values are R1 = 57Ω, R2 = 80Ω, and R3 =
336Ω. The loss developed through R2 is about -1.86 dB. In the case where there is no –5V supply available and
V2 is set to 0V, the resistor values are R1 = 66Ω, R2 = 101Ω, and R3 = 107Ω. The loss with these values is
–5.76dB.
Figure 53 shows the recommended network for interfacing with the TRF3703-33 which requires a common mode
of 3.3V. This is the simplest interface as there is no voltage shift. Because there is no voltage shift there isn't any
loss in the network. With V1 = 5V and V2 = 0V, the resistor values are R1 = 66Ω and R3 = 208Ω.
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V1
R1
I
I
R3
DAC3282
TRF3703-33
V2
R3
/I
/I
R1
V1
Figure 53. DAC3282 to TRF3703-33 Interface
In most applications a baseband filter is required between the DAC and the modulator to eliminate the DAC
images. This filter can be placed after the common-mode biasing network. For the DAC to modulator network
shown in Figure 54, R2 and the filter load R4 need to be considered into the DAC impedance. The filter has to be
designed for the source impedance created by the resistor combination of R3 // (R2+R1). The effective
impedance seen by the DAC is affected by the filter termination resistor resulting in R1 // (R2+R3 // (R4/2)).
V1
R1
R2
I
R3
Filter
V2
DAC3282
R4
TRF3703
R3
R2
/I
R1
V1
Figure 54. DAC3282 to Modulator Interface with Filter
Factoring in R4 into the DAC load, a typical interface to the TRF3703-17 with V1 = 5V and V2 = 0V results in the
following values: R1 = 72Ω, R2 = 116Ω, R3 = 124Ω and R4 = 150Ω. This implies that the filter needs to be
designed for 75Ω input and output impedance (single-ended impedance). The common mode levels for the DAC
and modulator are maintained at 3.3V and 1.7V and the DAC load is 50Ω. The added load of the filter
termination causes the signal to be attenuated by –10.8 dB.
A filter can be implemented in a similar manner to interface with the TRF3703-33. In this case it is much simpler
to balance the loads and common mode voltages due to the absence of R2. An added benefit is that there is no
loss in this network. With V1 = 5V and V2 = 0V the network can be designed such that R1 = 115Ω, R3 = 681Ω,
and R4 = 200Ω. This results in a filter impedance of R1 // R2=100Ω, and a DAC load of R1 // R3 // (R4/2) which
is equal to 50Ω. R4 is a differential resistor and does not affect the common mode level created by R1 and R3.
The common-mode voltage is set at 3.3 V for a full-scale current of 20mA.
For more information on how to interface the DAC3282 to an analog quadrature modulator please refer to the
application reports Passive Terminations for Current Output DACs (SLAA399) and Design of Differential Filters
for High-Speed Signal Chains (SLWA053).
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43
DAC3282
SLAS646 – DECEMBER 2009
www.ti.com
APPLICATION EXAMPLE
DIRECT CONVERSION RADIO
Refer to Figure 55 for an example Direct Conversion Radio. The DAC3282 receives an interleaved complex I/Q
baseband input data stream and increases the sample rate through interpolation by a factor of 2. By performing
digital interpolation on the input data, undesired images of the original signal can be push out of the band of
interest and more easily suppressed with analog filters.
For a Zero IF (ZIF) frequency plan, complex mixing of the baseband signal is not required. Alternatively, for a
Complex IF frequency plan the input data can be pre-placed at an IF within the bandwidth limitations of the
interpolation filters. In addition, complex mixing is available using the coarse mixer block to up-convert the signal.
The output of both DAC channels is used to produce a Hilbert transform pair and can be expressed as:
AOUT(t) = A(t)cos(ωct) – B(t)sin(ωct) = m(t)
BOUT(t) = A(t)sin(ωct) + B(t)cos(ωct) = mh(t)
where m(t) and mh(t) connote a Hilbert transform pair and ωc is the mixer frequency. The complex output is input
to an analog quadrature modulator (AQM) such as the Texas Instruments TRF3720 for a single side-band (SSB)
up conversion to RF. A passive (resistor only) interface to the AQM with an optional LC filter network is
recommended. The TRF3720 includes a VCO/PLL to generate the LO frequency. Upper single-sideband
upconversion is achieved at the output of the analog quadrature modulator, whose output is expressed as:
RF(t) = A(t)cos(ωc + ωLO)t – B(t)sin(ωc + ωLO)t
Flexibility is provided to the user by allowing for the selection of negative mixing frequency to produce a
lower-sideband upconversion. Note that the process of complex mixing translates the signal frequency from 0Hz
means that the analog quadrature modulator IQ imbalance produces a sideband that falls outside the signal of
interest. DC offset error in DAC and AQM signal path may produce LO feed-through at the RF output which may
fall in the band of interest. To suppress the LO feed-through, the DAC3282 provides a digital offset correction
capability for both DAC-A and DAC-B paths.
The complex IF architecture has several advantages over the real IF architecture:
• Uncalibrated side-band suppression ~ 35dBc compared to 0dBc for real IF architecture.
• Direct DAC to AQM interface – no amplifiers required
• DAC 2nd Nyquist zone image is offset fDAC compared with fDAC– 2 × IF for a real IF architecture, reducing the
need for filtering at the DAC output.
• Uncalibrated LO feed through for AQM is ~ 35dBc and calibration can reduce or completely remove the LO
feed through.
44
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Product Folder Link(s): DAC3282
DAC3282
www.ti.com
SLAS646 – DECEMBER 2009
5V
Byte-Wide
Data
100
DATACLKP /N
100
Optional
Filter Network
FRAMEP/N
DAC-A
CMIX
100
I-FIR
D0P/N
Q-FIR
100
QISINC
D7P/N
IISINC
DAC3282 DAC
FIFO & Demux
LVDS Data Interface
FPGA
DAC-B
RF OUT
DACCLKP/N
100
0
100
90
PLL/
DLL
Div
2/4/8
VCO
NDivider
VCTRL_IN
Loop
Filter
PFD
RDiv
/1
/2
Div
Clock Divider/
Distribution
CDCE62005
Clock Generator with VCO
PFD/CP
CPOUT
TRF3720
AQM with PLL/VCO
Loop
Filter
Div
10 MHz
OSC
Figure 55. System Diagram of Direct Conversion Radio
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Product Folder Link(s): DAC3282
45
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