LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller; up to 32 kB flash and
8 kB SRAM; USB device
Rev. 01 — 11 December 2009
Product data sheet
1. General description
The LPC1311/13/42/43 are ARM Cortex-M3 based microcontrollers for embedded
applications featuring a high level of integration and low power consumption. The ARM
Cortex-M3 is a next generation core that offers system enhancements such as enhanced
debug features and a higher level of support block integration.
The LPC1311/13/42/43 operate at CPU frequencies of up to 72 MHz. The ARM
Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals. The ARM
Cortex-M3 CPU also includes an internal prefetch unit that supports speculative
branching.
The peripheral complement of the LPC1311/13/42/43 includes up to 32 kB of flash
memory, up to 8 kB of data memory, USB Device (LPC1342/43 only), one Fast-mode Plus
I2C-bus interface, one UART, four general purpose timers, and up to 42 general purpose
I/O pins.
2. Features
n ARM Cortex-M3 processor, running at frequencies of up to 72 MHz.
n ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
n 32 kB (LPC1343/13)/16 kB (LPC1342)/8 kB (LPC1311) on-chip flash programming
memory.
n 8 kB (LPC1343/13)/4 kB (LPC1342/11) SRAM.
n In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
n Selectable boot-up: UART or USB (USB on LPC134x only).
n Serial interfaces:
u USB 2.0 full-speed device controller with on-chip PHY for device (LPC1342/43
only).
u UART with fractional baud rate generation, modem, internal FIFO, and
RS-485/EIA-485 support.
u SSP controller with FIFO and multi-protocol capabilities.
u I2C-bus interface supporting full I2C-bus specification and Fast-mode Plus with a
data rate of 1 Mbit/s with multiple address recognition and monitor mode.
n Other peripherals:
LPC1311/13/42/43
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
n
u Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors.
u Four general purpose timers/counters with a total of four capture inputs and 13
match outputs.
u Programmable WatchDog Timer (WDT).
u System tick timer.
Serial Wire Debug and Serial Wire Trace port.
High-current output driver (20 mA) on one pin.
High-current sink drivers (20 mA) on two I2C-bus pins in Fast-mode Plus.
Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep, Deep-sleep, and Deep power-down modes.
Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.
Single 3.3 V power supply (2.0 V to 3.6 V).
10-bit ADC with input multiplexing among 8 pins.
GPIO pins can be used as edge and level sensitive interrupt sources.
Clock output function with divider that can reflect the system oscillator clock, IRC
clock, CPU clock, or the watchdog clock.
Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 40 of
the functional pins.
Brownout detect with four separate thresholds for interrupt and one threshold for
forced reset.
Power-On Reset (POR).
Crystal oscillator with an operating range of 1 MHz to 25 MHz.
12 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as
a system clock.
PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from the main oscillator, the internal RC oscillator,
or the watchdog oscillator.
Code Read Protection (CRP) with different security levels.
Available as 48-pin LQFP package and 33-pin HVQFN package.
3. Applications
n
n
n
n
n
eMetering
Lighting
Industrial networking
Alarm systems
White goods
LPC1311_13_42_43_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 11 December 2009
2 of 53
LPC1311/13/42/43
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
LPC1311FHN33 HVQFN33
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
33 terminals; body 7 x 7 x 0.85 mm
n/a
LPC1313FBD48 LQFP48
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2
LPC1313FHN33 HVQFN33
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
33 terminals; body 7 x 7 x 0.85 mm
n/a
LPC1342FHN33 HVQFN33
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
33 terminals; body 7 x 7 x 0.85 mm
n/a
LPC1343FBD48 LQFP48
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2
LPC1343FHN33 HVQFN33
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
33 terminals; body 7 x 7 x 0.85 mm
n/a
4.1 Ordering options
Table 2.
Ordering options for LPC1311/13/42/43
Type number
Flash
Total
SRAM
USB
UART
RS-485
I2C/
Fast+
SSP
ADC
channels
Pins
Package
LPC1311FHN33
8 kB
4 kB
-
1
1
1
8
33
HVQFN33
LPC1313FBD48
32 kB
8 kB
-
1
1
1
8
48
LQFP48
LPC1313FHN33
32 kB
8 kB
-
1
1
1
8
33
HVQFN33
LPC1342FHN33
16 kB
4 kB
Device
1
1
1
8
33
HVQFN33
LPC1343FBD48
32 kB
8 kB
Device
1
1
1
8
48
LQFP48
LPC1343FHN33
32 kB
8 kB
Device
1
1
1
8
33
HVQFN33
LPC1311_13_42_43_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 11 December 2009
3 of 53
LPC1311/13/42/43
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
5. Block diagram
XTALIN
XTALOUT
RESET
USB pins
SWD
LPC1311/13/42/43
USB PHY(1)
TEST/DEBUG
INTERFACE
IRC
ARM
CORTEX-M3
I-code
bus
USB DEVICE
CONTROLLER(1)
D-code
bus
system
bus
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
POR
CLKOUT
clocks and
controls
slave
slave
ROM
AHB-LITE BUS
GPIO ports
PIO0/1/2/3
RXD
TXD
DTR, DSR(2), CTS,
DCD(2), RI(2), RTS
CT32B0_MAT[3:0]
CT32B0_CAP0
CT32B1_MAT[3:0]
CT32B1_CAP0
CT16B0_MAT[2:0]
CT16B0_CAP0
CT16B1_MAT[1:0]
CT16B1_CAP0
slave
HIGH-SPEED
GPIO
slave
SRAM
4/8 kB
slave
slave
FLASH
8/16/32 kB
AHB TO
APB
BRIDGE
UART
10-bit ADC
AD[7:0]
SSP
SCK
SSEL
MISO
MOSI
32-bit COUNTER/TIMER 0
SCL
SDA
I2C-BUS
32-bit COUNTER/TIMER 1
16-bit COUNTER/TIMER 0
WDT
16-bit COUNTER/TIMER 1
IOCONFIG
SYSTEM CONTROL
002aae722
(1) LPC1342/43 only.
(2) LQFP48 package only.
Fig 1.
Block diagram
LPC1311_13_42_43_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 11 December 2009
4 of 53
LPC1311/13/42/43
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
6. Pinning information
37 PIO3_1
38 PIO2_3/RI
39 SWDIO/PIO1_3/AD4/CT32B1_MAT2
40 PIO1_4/AD5/CT32B1_MAT3/WAKEUP
41 VSS
42 PIO1_11/AD7
43 PIO3_2
44 VDD(3V3)
45 PIO1_5/RTS/CT32B0_CAP0
46 PIO1_6/RXD/CT32B0_MAT0
47 PIO1_7/TXD/CT32B0_MAT1
48 PIO3_3
6.1 Pinning
PIO2_6
1
36 PIO3_0
PIO2_0/DTR
2
35 TRST/PIO1_2/AD3/CT32B1_MAT1
RESET/PIO0_0
3
34 TDO/PIO1_1/AD2/CT32B1_MAT0
PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE
4
33 TMS/PIO1_0/AD1/CT32B1_CAP0
VSSIO
5
32 TDI/PIO0_11/AD0/CT32B0_MAT3
XTALIN
6
XTALOUT
7
VDD(IO)
8
29 SWCLK/PIO0_10/SCK/CT16B0_MAT2
PIO1_8/CT16B1_CAP0
9
28 PIO0_9/MOSI/CT16B0_MAT1/SWO
31 PIO2_11/SCK
LPC1343FBD48
30 PIO1_10/AD6/CT16B1_MAT1
PIO0_2/SSEL/CT16B0_CAP0 10
27 PIO0_8/MISO/CT16B0_MAT0
Fig 2.
PIO2_9 24
PIO0_7/CTS 23
PIO0_6/USB_CONNECT/SCK 22
PIO2_5 21
USB_DP 20
USB_DM 19
PIO2_4 18
PIO1_9/CT16B1_MAT0 17
PIO0_5/SDA 16
PIO0_4/SCL 15
25 PIO2_10
PIO2_1/DSR 13
26 PIO2_2/DCD
PIO2_8 12
PIO0_3/USB_VBUS 14
PIO2_7 11
002aae505
LPC1343 LQFP48 package
LPC1311_13_42_43_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 11 December 2009
5 of 53
LPC1311/13/42/43
NXP Semiconductors
VDD(3V3)
PIO3_2
PIO1_11/AD7
PIO1_4/AD5/CT32B1_MAT3/WAKEUP
SWDIO/PIO1_3/AD4/CT32B1_MAT2
27
26
25
PIO1_5/RTS/CT32B0_CAP0
28
PIO1_6/RXD/CT32B0_MAT0
30
29
PIO1_7/TXD/CT32B0_MAT1
31
terminal 1
index area
32
32-bit ARM Cortex-M3 microcontroller
PIO2_0/DTR
1
24
TRST/PIO1_2/AD3/CT32B1_MAT1
RESET/PIO0_0
2
23
TDO/PIO1_1/AD2/CT32B1_MAT0
PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE
3
22
TMS/PIO1_0/AD1/CT32B1_CAP0
XTALIN
4
21
TDI/PIO0_11/AD0/CT32B0_MAT3
XTALOUT
5
20
PIO1_10/AD6/CT16B1_MAT1
VDD(IO)
6
PIO1_8/CT16B1_CAP0
7
PIO0_2/SSEL/CT16B0_CAP0
8
LPC1342FHN33
LPC1343FHN33
16
PIO0_7/CTS
USB_DM
15
13
PIO1_9/CT16B1_MAT0
14
12
PIO0_5/SDA
USB_DP
11
PIO0_4/SCL
PIO0_6/USB_CONNECT/SCK
9
10
PIO0_3/USB_VBUS
33 VSS
19
SWCLK/PIO0_10/SCK/CT16B0_MAT2
18
PIO0_9/MOSI/CT16B0_MAT1/SWO
17
PIO0_8/MISO/CT16B0_MAT0
002aae516
Transparent top view
Fig 3.
LPC1342/43 HVQFN33 package
LPC1311_13_42_43_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 11 December 2009
6 of 53
LPC1311/13/42/43
NXP Semiconductors
37 PIO3_1
38 PIO2_3/RI
39 SWDIO/PIO1_3/AD4/CT32B1_MAT2
40 PIO1_4/AD5/CT32B1_MAT3/WAKEUP
41 VSS
42 PIO1_11/AD7
43 PIO3_2
44 VDD(3V3)
45 PIO1_5/RTS/CT32B0_CAP0
46 PIO1_6/RXD/CT32B0_MAT0
47 PIO1_7/TXD/CT32B0_MAT1
48 PIO3_3
32-bit ARM Cortex-M3 microcontroller
PIO2_6
1
36 PIO3_0
PIO2_0/DTR
2
35 TRST/PIO1_2/AD3/CT32B1_MAT1
RESET/PIO0_0
3
34 TDO/PIO1_1/AD2/CT32B1_MAT0
PIO0_1/CLKOUT/CT32B0_MAT2
4
33 TMS/PIO1_0/AD1/CT32B1_CAP0
VSSIO
5
32 TDI/PIO0_11/AD0/CT32B0_MAT3
XTALIN
6
XTALOUT
7
VDD(IO)
8
29 SWCLK/PIO0_10/SCK/CT16B0_MAT2
PIO1_8/CT16B1_CAP0
9
28 PIO0_9/MOSI/CT16B0_MAT1/SWO
31 PIO2_11/SCK
LPC1313FBD48
30 PIO1_10/AD6/CT16B1_MAT1
PIO0_2/SSEL/CT16B0_CAP0 10
27 PIO0_8/MISO/CT16B0_MAT0
Fig 4.
PIO2_9 24
PIO0_7/CTS 23
PIO0_6/SCK 22
PIO3_5 21
PIO2_5 20
PIO2_4 19
PIO3_4 18
PIO1_9/CT16B1_MAT0 17
PIO0_5/SDA 16
PIO0_4/SCL 15
25 PIO2_10
PIO0_3 14
26 PIO2_2/DCD
PIO2_8 12
PIO2_1/DSR 13
PIO2_7 11
002aae513
LPC1313 LQFP48 package
LPC1311_13_42_43_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 11 December 2009
7 of 53
LPC1311/13/42/43
NXP Semiconductors
PIO1_7/TXD/CT32B0_MAT1
PIO1_6/RXD/CT32B0_MAT0
PIO1_5/RTS/CT32B0_CAP0
VDD(3V3)
PIO3_2
PIO1_11/AD7
PIO1_4/AD5/CT32B1_MAT3/WAKEUP
SWDIO/PIO1_3/AD4/CT32B1_MAT2
31
30
29
28
27
26
25
terminal 1
index area
32
32-bit ARM Cortex-M3 microcontroller
PIO2_0/DTR
1
24
TRST/PIO1_2/AD3/CT32B1_MAT1
RESET/PIO0_0
2
23
TDO/PIO1_1/AD2/CT32B1_MAT0
PIO0_1/CLKOUT/CT32B0_MAT2
3
22
TMS/PIO1_0/AD1/CT32B1_CAP0
XTALIN
4
21
TDI/PIO0_11/AD0/CT32B0_MAT3
XTALOUT
5
20
PIO1_10/AD6/CT16B1_MAT1
VDD(IO)
6
PIO1_8/CT16B1_CAP0
7
PIO0_2/SSEL/CT16B0_CAP0
8
LPC1311FHN33
LPC1313FHN33
9
10
11
12
13
14
15
16
PIO0_3
PIO0_4/SCL
PIO0_5/SDA
PIO1_9/CT16B1_MAT0
PIO3_4
PIO3_5
PIO0_6/SCK
PIO0_7/CTS
33 VSS
19
SWCLK/PIO0_10/SCK/CT16B0_MAT2
18
PIO0_9/MOSI/CT16B0_MAT1/SWO
17
PIO0_8/MISO/CT16B0_MAT0
002aae517
Transparent top view
Fig 5.
LPC1311/13 HVQFN33 package
6.2 Pin description
Table 3.
LPC1313/43 LQFP48 pin description table
Symbol
Pin
Type
Description
RESET/PIO0_0
3
I
RESET — External reset input: A LOW on this pin resets the device,
causing I/O ports and peripherals to take on their default states, and
processor execution to begin at address 0.
I/O
PIO0_0 — General purpose digital input/output pin.
PIO0_1/CLKOUT/
CT32B0_MAT2/
USB_FTOGGLE
4[1]
I/O
PIO0_1 — General purpose digital input/output pin. A LOW level on this pin
during reset starts the ISP command handler or the USB device
enumeration (USB on LPC1343 only, see description of PIO0_3).
O
CLKOUT — Clockout pin.
O
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
O
USB_FTOGGLE — USB 1 ms Start-of-Frame signal (LPC1343 only).
I/O
PIO0_2 — General purpose digital input/output pin.
O
SSEL — Slave select for SSP.
I
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
PIO0_2/SSEL/
CT16B0_CAP0
10[1]
LPC1311_13_42_43_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 11 December 2009
8 of 53
LPC1311/13/42/43
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Table 3.
LPC1313/43 LQFP48 pin description table …continued
Symbol
Pin
Type
Description
PIO0_3/USB_VBUS
14[1]
I/O
PIO0_3 — General purpose digital input/output pin. LPC1343 only: A LOW
level on this pin during reset starts the ISP command handler, a HIGH level
starts the USB device enumeration.
I
USB_VBUS — Monitors the presence of USB bus power (LPC1343 only).
PIO0_4/SCL
15[2]
I/O
PIO0_4 — General purpose digital input/output pin.
I/O
SCL — I2C-bus clock input/output. High-current sink only if I2C Fast-mode
Plus is selected in the I/O configuration register.
I/O
PIO0_5 — General purpose digital input/output pin.
I/O
SDA — I2C-bus data input/output. High-current sink only if I2C Fast-mode
Plus is selected in the I/O configuration register.
I/O
PIO0_6 — General purpose digital input/output pin.
O
USB_CONNECT — Signal used to switch an external 1.5 kΩ resistor under
software control. Used with the SoftConnect USB feature (LPC1343 only).
I/O
SCK — Serial clock for SSP.
I/O
PIO0_7 — General purpose digital input/output pin (high-current output
driver).
I
CTS — Clear To Send input for UART.
I/O
PIO0_8 — General purpose digital input/output pin.
I/O
MISO — Master In Slave Out for SSP.
PIO0_5/SDA
16[2]
PIO0_6/USB_CONNECT/ 22[1]
SCK
PIO0_7/CTS
23[1]
PIO0_8/MISO/
CT16B0_MAT0
27[1]
PIO0_9/MOSI/
CT16B0_MAT1/
SWO
28[1]
SWCLK/PIO0_10/
SCK/CT16B0_MAT2
29[1]
TDI/PIO0_11/
AD0/CT32B0_MAT3
TMS/PIO1_0/
AD1/CT32B1_CAP0
TDO/PIO1_1/
AD2/CT32B1_MAT0
32[3]
33[3]
34[3]
O
CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
I/O
PIO0_9 — General purpose digital input/output pin.
I/O
MOSI — Master Out Slave In for SSP.
O
CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
O
SWO — Serial wire trace output.
I
SWCLK — Serial wire clock and test clock TCK for JTAG interface.
I/O
PIO0_10 — General purpose digital input/output pin.
O
SCK — Serial clock for SSP.
O
CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
I
TDI — Test Data In for JTAG interface.
I/O
PIO0_11 — General purpose digital input/output pin.
I
AD0 — A/D converter, input 0.
O
CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
I
TMS — Test Mode Select for JTAG interface.
I/O
PIO1_0 — General purpose digital input/output pin.
I
AD1 — A/D converter, input 1.
I
CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
O
TDO — Test Data Out for JTAG interface.
I/O
PIO1_1 — General purpose digital input/output pin.
I
AD2 — A/D converter, input 2.
O
CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
LPC1311_13_42_43_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 11 December 2009
9 of 53
LPC1311/13/42/43
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Table 3.
LPC1313/43 LQFP48 pin description table …continued
Symbol
Pin
Type
Description
TRST/PIO1_2/
AD3/CT32B1_MAT1
35[3]
I
TRST — Test Reset for JTAG interface.
I/O
PIO1_2 — General purpose digital input/output pin.
I
AD3 — A/D converter, input 3.
SWDIO/PIO1_3/AD4/
CT32B1_MAT2
PIO1_4/AD5/
CT32B1_MAT3/WAKEUP
PIO1_5/RTS/
CT32B0_CAP0
39[3]
40[3]
45[1]
PIO1_6/RXD/
CT32B0_MAT0
46[1]
PIO1_7/TXD/
CT32B0_MAT1
47[1]
PIO1_8/CT16B1_CAP0
9[1]
O
CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
I/O
SWDIO — Serial wire debug input/output.
I/O
PIO1_3 — General purpose digital input/output pin.
I
AD4 — A/D converter, input 4.
O
CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
I/O
PIO1_4 — General purpose digital input/output pin.
I
AD5 — A/D converter, input 5.
O
CT32B1_MAT3 — Match output 3 for 32-bit timer 1.
I
WAKEUP — Deep power-down mode wake-up pin. This pin must be pulled
HIGH externally to enter Deep power-down mode and pulled LOW to exit
Deep power-down mode.
I/O
PIO1_5 — General purpose digital input/output pin.
O
RTS — Request To Send output for UART.
I
CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
I/O
PIO1_6 — General purpose digital input/output pin.
I
RXD — Receiver input for UART.
O
CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
I/O
PIO1_7 — General purpose digital input/output pin.
O
TXD — Transmitter output for UART.
O
CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
I/O
PIO1_8 — General purpose digital input/output pin.
I
CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
I/O
PIO1_9 — General purpose digital input/output pin.
O
CT16B1_MAT0 — Match output 0 for 16-bit timer 1.
I/O
PIO1_10 — General purpose digital input/output pin.
I
AD6 — A/D converter, input 6.
PIO1_9/CT16B1_MAT0
17[1]
PIO1_10/AD6/
CT16B1_MAT1
30[3]
O
CT16B1_MAT1 — Match output 1 for 16-bit timer 1.
PIO1_11/AD7
42[3]
I/O
PIO1_11 — General purpose digital input/output pin.
I
AD7 — A/D converter, input 7.
PIO2_0/DTR
2[1]
I/O
PIO2_0 — General purpose digital input/output pin.
O
DTR — Data Terminal Ready output for UART.
PIO2_1/DSR
13[1]
I/O
PIO2_1 — General purpose digital input/output pin.
I
DSR — Data Set Ready input for UART.
PIO2_2/DCD
26[1]
I/O
PIO2_2 — General purpose digital input/output pin.
I
DCD — Data Carrier Detect input for UART.
PIO2_3/RI
38[1]
I/O
PIO2_3 — General purpose digital input/output pin.
I
RI — Ring Indicator input for UART.
PIO2_4
18[1]
I/O
PIO2_4 — General purpose digital input/output pin (LPC1343 only).
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32-bit ARM Cortex-M3 microcontroller
Table 3.
LPC1313/43 LQFP48 pin description table …continued
Symbol
Pin
Type
Description
PIO2_4
19[1]
I/O
PIO2_4 — General purpose digital input/output pin (LPC1313 only).
PIO2_5
21[1]
I/O
PIO2_5 — General purpose digital input/output pin (LPC1343 only).
PIO2_5
20[1]
I/O
PIO2_5 — General purpose digital input/output pin (LPC1313 only).
PIO2_6
1[1]
I/O
PIO2_6 — General purpose digital input/output pin.
PIO2_7
11[1]
I/O
PIO2_7 — General purpose digital input/output pin.
PIO2_8
12[1]
I/O
PIO2_8 — General purpose digital input/output pin.
PIO2_9
24[1]
I/O
PIO2_9 — General purpose digital input/output pin.
PIO2_10
25[1]
I/O
PIO2_10 — General purpose digital input/output pin.
PIO2_11/SCK
31[1]
I/O
PIO2_11 — General purpose digital input/output pin.
I/O
SCK — Serial clock for SSP.
PIO3_0
36[1]
I/O
PIO3_0 — General purpose digital input/output pin.
PIO3_1
37[1]
I/O
PIO3_1 — General purpose digital input/output pin.
PIO3_2
43[1]
I/O
PIO3_2 — General purpose digital input/output pin.
PIO3_3
48[1]
I/O
PIO3_3 — General purpose digital input/output pin.
PIO3_4
18[1]
I/O
PIO3_4 — General purpose digital input/output pin (LPC1313 only).
PIO3_5
21[1]
I/O
PIO3_5 — General purpose digital input/output pin (LPC1313 only).
USB_DM
19[4]
I/O
USB_DM — USB bidirectional D− line (LPC1343 only).
USB_DP
20[4]
I/O
USB_DP — USB bidirectional D+ line (LPC1343 only).
VDD(IO)
8[5]
I
3.3 V input/output supply voltage.
VDD(3V3)
44[5]
I
3.3 V supply voltage to the internal regulator and the ADC. Also used as the
ADC reference voltage.
VSSIO
5
I
Ground.
XTALIN
6[6]
I
Input to the oscillator circuit and internal clock generator circuits. Input
voltage must not exceed 1.8 V.
XTALOUT
7[6]
O
Output from the oscillator amplifier.
VSS
41
I
Ground.
[1]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
[2]
I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.
[3]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant.
[4]
Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode
only).
[5]
Tie together VDD(3V3) and VDD(IO) externally. If separate supplies are used for VDD(3V3) and VDD(IO), ensure that the voltage difference
between both supplies is smaller than or equal to 0.5 V.
[6]
When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
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32-bit ARM Cortex-M3 microcontroller
Table 4.
LPC1311/13/42/43 HVQFN33 pin description table
Symbol
Pin
Type
Description
RESET/PIO0_0
2
I
RESET — External reset input: A LOW on this pin resets the device,
causing I/O ports and peripherals to take on their default states, and
processor execution to begin at address 0.
I/O
PIO0_0 — General purpose digital input/output pin.
PIO0_1/CLKOUT/
CT32B0_MAT2/
USB_FTOGGLE
3[1]
I/O
PIO0_1 — General purpose digital input/output pin. A LOW level on this pin
during reset starts the ISP command handler or the USB device
enumeration (USB on LPC1342/43 only, see description of PIO0_3).
O
CLKOUT — Clock out pin.
O
CT32B0_MAT2 — Match output 2 for 32-bit timer 0.
PIO0_2/SSEL/
CT16B0_CAP0
8[1]
PIO0_3/USB_VBUS
9[1]
PIO0_4/SCL
PIO0_5/SDA
10[2]
11[2]
PIO0_6/USB_CONNECT/
SCK
15[1]
PIO0_7/CTS
16[1]
PIO0_8/MISO/
CT16B0_MAT0
17[1]
PIO0_9/MOSI/
CT16B0_MAT1/
SWO
SWCLK/PIO0_10/SCK/
CT16B0_MAT2
18[1]
19[1]
O
USB_FTOGGLE — USB 1 ms Start-of-Frame signal (LPC1342/43 only).
I/O
PIO0_2 — General purpose digital input/output pin.
O
SSEL — Slave select for SSP.
I
CT16B0_CAP0 — Capture input 0 for 16-bit timer 0.
I/O
PIO0_3 — General purpose digital input/output pin. LPC1342/43 only: A
LOW level on this pin during reset starts the ISP command handler, a HIGH
level starts the USB device enumeration.
I
USB_VBUS — Monitors the presence of USB bus power (LPC1342/43
only).
I/O
PIO0_4 — General purpose digital input/output pin.
I/O
SCL — I2C-bus clock input/output. High-current sink only if I2C Fast-mode
Plus is selected in the I/O configuration register.
I/O
PIO0_5 — General purpose digital input/output pin.
I/O
SDA — I2C-bus data input/output. High-current sink only if I2C Fast-mode
Plus is selected in the I/O configuration register.
I/O
PIO0_6 — General purpose digital input/output pin.
O
USB_CONNECT — Signal used to switch an external 1.5 kΩ resistor under
software control. Used with the SoftConnect USB feature (LPC1342/43
only).
I/O
SCK — Serial clock for SSP.
I/O
PIO0_7 — General purpose digital input/output pin (high-current output
driver).
I
CTS — Clear To Send input for UART.
I/O
PIO0_8 — General purpose digital input/output pin.
I/O
MISO — Master In Slave Out for SSP.
O
CT16B0_MAT0 — Match output 0 for 16-bit timer 0.
I/O
PIO0_9 — General purpose digital input/output pin.
I/O
MOSI — Master Out Slave In for SSP.
O
CT16B0_MAT1 — Match output 1 for 16-bit timer 0.
O
SWO — Serial wire trace output.
I
SWCLK — Serial wire clock and test clock TCK for JTAG interface.
I/O
PIO0_10 — General purpose digital input/output pin.
O
SCK — Serial clock for SSP.
O
CT16B0_MAT2 — Match output 2 for 16-bit timer 0.
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32-bit ARM Cortex-M3 microcontroller
Table 4.
LPC1311/13/42/43 HVQFN33 pin description table …continued
Symbol
Pin
Type
Description
TDI/PIO0_11/AD0/
CT32B0_MAT3
21[3]
I
TDI — Test Data In for JTAG interface.
I/O
PIO0_11 — General purpose digital input/output pin.
I
AD0 — A/D converter, input 0.
TMS/PIO1_0/AD1/
CT32B1_CAP0
TDO/PIO1_1/AD2/
CT32B1_MAT0
TRST/PIO1_2/AD3/
CT32B1_MAT1
SWDIO/PIO1_3/AD4/
CT32B1_MAT2
PIO1_4/AD5/
CT32B1_MAT3/WAKEUP
PIO1_5/RTS/
CT32B0_CAP0
22[3]
23[3]
24[3]
25[3]
26[3]
30[1]
PIO1_6/RXD/
CT32B0_MAT0
31[1]
PIO1_7/TXD/
CT32B0_MAT1
32[1]
PIO1_8/CT16B1_CAP0
7[1]
PIO1_9/CT16B1_MAT0
12[1]
O
CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
I
TMS — Test Mode Select for JTAG interface.
I/O
PIO1_0 — General purpose digital input/output pin.
I
AD1 — A/D converter, input 1.
I
CT32B1_CAP0 — Capture input 0 for 32-bit timer 1.
O
TDO — Test Data Out for JTAG interface.
I/O
PIO1_1 — General purpose digital input/output pin.
I
AD2 — A/D converter, input 2.
O
CT32B1_MAT0 — Match output 0 for 32-bit timer 1.
I
TRST — Test Reset for JTAG interface.
I/O
PIO1_2 — General purpose digital input/output pin.
I
AD3 — A/D converter, input 3.
O
CT32B1_MAT1 — Match output 1 for 32-bit timer 1.
I/O
SWDIO — Serial wire debug input/output.
I/O
PIO1_3 — General purpose digital input/output pin.
I
AD4 — A/D converter, input 4.
O
CT32B1_MAT2 — Match output 2 for 32-bit timer 1.
I/O
PIO1_4 — General purpose digital input/output pin.
I
AD5 — A/D converter, input 5.
O
CT32B1_MAT3 — Match output 3 for 32-bit timer 1.
I
WAKEUP — Deep power-down mode wake-up pin. This pin must be pulled
HIGH externally to enter Deep power-down mode and pulled LOW to exit
Deep power-down mode.
I/O
PIO1_5 — General purpose digital input/output pin.
O
RTS — Request To Send output for UART.
I
CT32B0_CAP0 — Capture input 0 for 32-bit timer 0.
I/O
PIO1_6 — General purpose digital input/output pin.
I
RXD — Receiver input for UART.
O
CT32B0_MAT0 — Match output 0 for 32-bit timer 0.
I/O
PIO1_7 — General purpose digital input/output pin.
O
TXD — Transmitter output for UART.
O
CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
I/O
PIO1_8 — General purpose digital input/output pin.
I
CT16B1_CAP0 — Capture input 0 for 16-bit timer 1.
I/O
PIO1_9 — General purpose digital input/output pin.
O
CT16B1_MAT0 — Match output 0 for 16-bit timer 1.
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LPC1311/13/42/43
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
Table 4.
LPC1311/13/42/43 HVQFN33 pin description table …continued
Symbol
Pin
Type
Description
PIO1_10/AD6/
CT16B1_MAT1
20[3]
I/O
PIO1_10 — General purpose digital input/output pin.
I
AD6 — A/D converter, input 6.
O
CT16B1_MAT1 — Match output 1 for 16-bit timer 1.
PIO1_11/AD7
27[3]
I/O
PIO1_11 — General purpose digital input/output pin.
I
AD7 — A/D converter, input 7.
I/O
PIO2_0 — General purpose digital input/output pin.
PIO2_0/DTR
1[1]
O
DTR — Data Terminal Ready output for UART.
PIO3_2
28[1]
I/O
PIO3_2 — General purpose digital input/output pin.
PIO3_4
13[1]
I/O
PIO3_4 — General purpose digital input/output pin (LPC1311/13 only).
PIO3_5
14[1]
I/O
PIO3_5 — General purpose digital input/output pin (LPC1311/13 only).
USB_DM
13[4]
I/O
USB_DM — USB bidirectional D− line (LPC1342/43 only).
USB_DP
14[4]
I/O
USB_DP — USB bidirectional D+ line (LPC1342/43 only).
VDD(IO)
6[5]
I
3.3 V input/output supply voltage.
VDD(3V3)
29[5]
I
3.3 V supply voltage to the internal DC-DC converter and the ADC. Also
used as the ADC reference voltage.
XTALIN
4[6]
I
Input to the oscillator circuit and internal clock generator circuits. Input
voltage must not exceed 1.8 V.
XTALOUT
5[6]
O
Output from the oscillator amplifier.
VSS
33
-
Thermal pad. Connect to ground.
[1]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.
[2]
I2C-bus pads compliant with the I2C-bus specification for I2C standard mode and I2C Fast-mode Plus.
[3]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled, and the pin is not 5 V tolerant.
[4]
Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode
only).
[5]
Tie together VDD(3V3) and VDD(IO) externally. If separate supplies are used for VDD(3V3) and VDD(IO), ensure that the voltage difference
between both supplies is smaller than or equal to 0.5 V.
[6]
When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
7. Functional description
7.1 Architectural overview
The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and
the D-code bus (see Figure 1). The I-code and D-code core buses are faster than the
system bus and are used similarly to TCM interfaces: one bus dedicated for instruction
fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for
simultaneous operations if concurrent operations target different devices.
7.2 ARM Cortex-M3 processor
The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM Cortex-M3 offers many new
features, including a Thumb-2 instruction set, low interrupt latency, hardware divide,
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32-bit ARM Cortex-M3 microcontroller
interruptible/continuable multiple load and store instructions, automatic state save and
restore for interrupts, tightly integrated interrupt controller, and multiple core buses
capable of simultaneous accesses.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical
Reference Manual which is available on the official ARM website.
7.3 On-chip flash program memory
The LPC1311/13/42/43 contain 32 kB (LPC1313 and LPC1343), 16 kB (LPC1342), or
8 kB (LPC1311) of on-chip flash memory.
7.4 On-chip SRAM
The LPC1311/13/42/43 contain a total of 8 kB (LPC1343 and LPC1313) or 4 kB
(LPC1342 and LPC1311) on-chip static RAM memory.
7.5 Memory map
The LPC134x incorporates several distinct memory regions, shown in the following
figures. Figure 6 shows the overall map of the entire address space from the user program
viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.
The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.
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32-bit ARM Cortex-M3 microcontroller
4 GB
AHB peripherals
LPC1311/13/42/43
0x5020 0000
0xFFFF FFFF
127- 4 reserved
reserved
0x5004 0000
AHB peripherals
3
GPIO PIO3
0x5020 0000
2
GPIO PIO2
0x5000 0000
1
GPIO PIO1
0
GPIO PIO0
0x5003 0000
0x5002 0000
0x5001 0000
0x5000 0000
reserved
APB peripherals
0x4008 0000
1 GB
APB peripherals
0x4008 0000
31 - 19 reserved
0x4000 0000
0x4004 C000
reserved
0x2400 0000
AHB SRAM bit-band alias addressing
0x2200 0000
reserved
18
system control
17
IOCONFIG
16
15
SSP
reserved
14
PMU
0x4004 8000
0x4004 4000
0x4004 0000
0x4003 C000
0x4003 8000
0x2000 0000
0.5 GB
10 - 13 reserved
reserved
0x4002 8000
0x1FFF 4000
16 kB boot ROM
0x1FFF 0000
reserved
0x1000 2000
8 kB SRAM (LPC1313/1343)
I-code/D-code
memory space
4 kB SRAM (LPC1311/1342)
0x1000 1000
0x1000 0000
reserved
9
reserved
8
USB (LPC1342/43 only)
0x4002 0000
7
ADC
0x4001 C000
6
32-bit counter/timer 1
0x4001 8000
5
32-bit counter/timer 0
0x4001 4000
4
16-bit counter/timer 1
0x4001 0000
3
16-bit counter/timer 0
0x4000 C000
2
UART
0x4000 8000
1
0
WDT
0x4000 4000
I2C-bus
0x4000 0000
0x4002 4000
0x0000 8000
32 kB on-chip flash (LPC1313/43)
16 kB on-chip flash (LPC1342)
0 GB
8 kB on-chip flash (LPC1311)
0x0000 4000
0x0000 2000
+ 512 byte
active interrupt vectors
0x0000 0200
0x0000 0000
0x0000 0000
002aae723
Fig 6.
LPC1311/13/42/43 memory map
7.6 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M3. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
7.6.1 Features
• Controls system exceptions and peripheral interrupts.
• On the LPC1311/13/42/43, the NVIC supports 16 vectored interrupts. In addition, up
to 40 of the individual GPIO inputs are NVIC-vector capable.
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• 8 programmable interrupt priority levels, with hardware priority level masking
• Relocatable vector table.
• Software interrupt generation.
7.6.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source.
Any GPIO pin (total of up to 42 pins) regardless of the selected function, can be
programmed to generate an interrupt on a level, or rising edge or falling edge, or both.
7.7 IOCONFIG block
The IOCONFIG block allows selected pins of the microcontroller to have more than one
function. Configuration registers control the multiplexers to allow connection between the
pin and the on-chip peripherals.
Peripherals should be connected to the appropriate pins prior to being activated and prior
to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is
not mapped to a related pin should be considered undefined.
7.8 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back as well as the current state of the port pins.
LPC1311/13/42/43 use accelerated GPIO functions:
• GPIO registers are a dedicated AHB peripheral and are accessed through the AHB so
that the fastest possible I/O timing can be achieved.
• Entire port value can be written in one instruction.
Additionally, any GPIO pin (total of up to 42 pins) providing a digital function can be
programmed to generate an interrupt on a level, a rising or falling edge, or both.
7.8.1 Features
• Bit level set and clear registers allow a single instruction to set or clear any number of
bits in one port.
• Direction control of individual bits.
• All I/O default to inputs with pull-up resistors enabled after reset.
• Pull-up/pull-down resistor configuration can be programmed through the IOCONFIG
block for each GPIO pin.
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7.9 USB interface (LPC1342/43 only)
The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports
hot-plugging and dynamic configuration of the devices. All transactions are initiated by the
host controller.
The LPC1342/43 USB interface is a device controller with on-chip PHY for device
functions.
7.9.1 Full-speed USB device controller
The device controller enables 12 Mbit/s data exchange with a USB Host controller. It
consists of a register interface, serial interface engine, and endpoint buffer memory. The
serial interface engine decodes the USB data stream and writes data to the appropriate
endpoint buffer. The status of a completed USB transfer or error condition is indicated via
status registers. An interrupt is also generated if enabled.
7.9.1.1
Features
• Fully compliant with USB 2.0 specification (full speed).
• Supports 10 physical (5 logical) endpoints with up to 64 bytes buffer RAM per
endpoint (see Table 5).
• Supports Control, Bulk, Isochronous, and Interrupt endpoints.
• Supports SoftConnect feature.
• Double buffer implementation for Bulk and Isochronous endpoints.
Table 5.
USB device endpoint configuration
Logical
endpoint
Physical
endpoint
Endpoint type
Direction
Packet size
(byte)
Double buffer
0
0
Control
0
1
Control
out
64
no
in
64
no
1
2
Interrupt/Bulk
out
64
no
1
3
Interrupt/Bulk
in
64
no
2
4
Interrupt/Bulk
out
64
no
2
5
Interrupt/Bulk
in
64
no
3
6
Interrupt/Bulk
out
64
yes
3
7
Interrupt/Bulk
in
64
yes
4
8
Isochronous
out
512
yes
4
9
Isochronous
in
512
yes
7.10 UART
The LPC1311/13/42/43 contains one UART.
Support for RS-485/9-bit mode allows both software address detection and automatic
address detection using 9-bit mode.
The UART includes a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
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7.10.1 Features
•
•
•
•
16-byte receive and transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• Fractional divider for baud rate control, auto baud capabilities and FIFO control
mechanism that enables software flow control implementation.
• Support for RS-485/9-bit mode.
• Support for modem control.
7.11 SSP serial I/O controller
The LPC1311/13/42/43 contain one SSP controller. The SSP controller is capable of
operation on a SSP, 4-wire SSI, or Microwire bus. It can interact with multiple masters and
slaves on the bus. Only a single master and a single slave can communicate on the bus
during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits
to 16 bits of data flowing from the master to the slave and from the slave to the master. In
practice, often only one of these data flows carries meaningful data.
7.11.1 Features
• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses
•
•
•
•
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
4-bit to 16-bit frame
7.12 I2C-bus serial I/O controller
The LPC1311/13/42/43 contain one I2C-bus controller.
The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
(SCL) and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be
controlled by more than one bus master connected to it.
7.12.1 Features
• The I2C-bus interface is a standard I2C-bus compliant interface with open-drain pins.
The I2C-bus interface also supports Fast-mode Plus with bit rates up to 1 Mbit/s.
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
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• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.
• The I2C-bus controller supports multiple address recognition and a bus monitor mode.
7.13 10-bit ADC
The LPC1311/13/42/43 contains one ADC. It is a single 10-bit successive approximation
ADC with eight channels.
7.13.1 Features
•
•
•
•
•
•
•
•
10-bit successive approximation ADC.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 V to VDD(3V3).
10-bit conversion time ≥ 2.44 µs.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition of input pin or timer match signal.
Individual result registers for each ADC channel to reduce interrupt overhead.
7.14 General purpose external event counters/timers
The LPC1311/13/42/43 includes two 32-bit counter/timers and two 16-bit counter/timers.
The counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. Each counter/timer also includes one capture input to trap the timer value
when an input signal transitions, optionally generating an interrupt.
7.14.1 Features
• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
• Counter or timer operation.
• One capture channel per timer, that can take a snapshot of the timer value when an
input signal transitions. A capture event may also generate an interrupt.
• Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following
capabilities:
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– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
7.15 System tick timer
The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception, normally set to a 10 ms interval.
7.16 Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a reasonable amount of
time if it enters an erroneous state. When enabled, the watchdog will generate a system
reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined
amount of time.
7.16.1 Features
• Internally resets chip if not periodically reloaded.
• Debug mode.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
•
•
•
•
Incorrect/incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 32-bit timer with internal prescaler.
Selectable time period from (Tcy(WDCLK) × 256 × 4) to (Tcy(WDCLK) × 232 × 4) in
multiples of Tcy(WDCLK) × 4.
• The Watchdog Clock (WDCLK) source can be selected from the Internal RC oscillator
(IRC), the watchdog oscillator, or the main clock. This gives a wide range of potential
timing choices of watchdog operation under different power reduction conditions. It
also provides the ability to run the WDT from an entirely internal source that is not
dependent on an external crystal and its associated components and wiring for
increased reliability.
7.17 Clocking and power control
7.17.1 Crystal oscillators
The LPC1311/13/42/43 include three independent oscillators. These are the system
oscillator, the Internal RC oscillator (IRC), and the watchdog oscillator. Each oscillator can
be used for more than one purpose as required in a particular application.
Following reset, the LPC1311/13/42/43 will operate from the internal RC oscillator until
switched by software. This allows systems to operate without any external crystal and the
bootloader code to operate at a known frequency.
See Figure 7 for an overview of the LPC1311/13/42/43 clock generation.
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SYSTEM CLOCK
DIVIDER
AHB clock 0
(system)
system clock
AHB clock 1
(ROM)
AHBCLKCTRL
(AHB clock enable)
AHB clocks
2 to 15
(memories
and peripherals)
14
AHBCLKCTRL
AHB clock 16
(IOCONFIG)
AHBCLKCTRL
SSP PERIPHERAL
CLOCK DIVIDER
IRC oscillator
SSP
main clock
UART PERIPHERAL
CLOCK DIVIDER
watchdog oscillator
MAINCLKSEL
(main clock select)
IRC oscillator
system oscillator
UART
ARM TRACE
CLOCK DIVIDER
ARM
trace clock
SYSTICK TIMER
CLOCK DIVIDER
SYSTICK
timer
SYSTEM PLL
IRC oscillator
watchdog oscilllator
SYSPLLCLKSEL
(system PLL clock select)
WDT CLOCK
DIVIDER
WDT
USB 48 MHz CLOCK
DIVIDER
USB
CLKOUT PIN CLOCK
DIVIDER
CLKOUT pin
watchdog oscillator
WDTUEN
(WDT clock update enable)
USB PLL
system oscillator
USBPLLCLKSEL
(USB clock select)
USBUEN
(USB clock update enable)
IRC oscillator
system oscillator
watchdog oscillator
CLKOUTUEN
(CLKOUT update enable)
002aae859
The USB clock is available on LPC1342/43 only.
Fig 7.
LPC1311/13/42/43 clocking generation block diagram
7.17.1.1
Internal RC oscillator
The IRC may be used as the clock source for the WDT, and/or as the clock that drives the
system PLL and subsequently the CPU. The nominal IRC frequency is 12 MHz. The IRC
is trimmed to 1 % accuracy over the entire voltage and temperature range.
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Upon power-up, any chip reset, or wake-up from Deep power-down mode, the
LPC1311/13/42/43 use the IRC as the clock source. Software may later switch to one of
the other available clock sources.
7.17.1.2
System oscillator
The system oscillator can be used as the clock source for the CPU, with or without using
the PLL. On the LPC134x, the system oscillator must be used to provide the clock source
to USB.
The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the
system PLL.
7.17.2 System PLL and USB PLL
The LPC134x contain a system PLL and a dedicated PLL for generating the 48 MHz USB
clock. The LPC131x contain the system PLL only. The system and USB PLLs are
identical.
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO).
The multiplier can be an integer value from 1 to 32. The CCO operates in the range of
156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within
its frequency range while the PLL is providing the desired output frequency. The output
divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the
minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle.
The PLL is turned off and bypassed following a chip reset and may be enabled by
software. The program must configure and activate the PLL, wait for the PLL to lock, and
then connect to the PLL as a clock source. The PLL settling time is 100 µs.
7.17.3 Clock output
The LPC1311/13/42/43 features a clock output function that routes the IRC oscillator, the
system oscillator, the watchdog oscillator, or the main clock to an output pin.
7.17.4 Wake-up process
The LPC1311/13/42/43 begin operation at power-up and when awakened from Deep
power-down mode by using the 12 MHz IRC oscillator as the clock source. This allows
chip operation to resume quickly. If the main oscillator or the PLL is needed by the
application, software will need to enable these features and wait for them to stabilize
before they are used as a clock source.
7.17.5 Power control
The LPC1311/13/42/43 support a variety of power control features. There are three
special modes of processor power reduction: Sleep mode, Deep-sleep mode, and Deep
power-down mode. The CPU clock rate may also be controlled as needed by changing
clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This
allows a trade-off of power versus processing speed based on application requirements.
In addition, a register is provided for shutting down the clocks to individual on-chip
peripherals, allowing fine tuning of power consumption by eliminating all dynamic power
use in any peripherals that are not required for the application. Selected peripherals have
their own clock divider which provides even better power control.
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7.17.5.1
Sleep mode
When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, and internal
buses.
7.17.5.2
Deep-sleep mode
In Deep-sleep mode, the chip is in Sleep mode, and in addition analog blocks are shut
down for increased power savings. The user can configure the Deep-sleep mode to a
large extend, selecting any of the oscillators, any of the PLLs, the USB PHY (LPC134x
only), BOD, the ADC, and the flash to be shut down or remain powered during Deep-sleep
mode. The user can also select which of the oscillators and analog blocks will be powered
up after the chip exits from Deep-sleep mode.
The GPIO pins (up to 40 pins total) serve as external wake-up pins to a dedicated start
logic to wake up the chip from Deep-sleep mode.
The timing of the wake-up process from Deep-sleep mode depends on which blocks are
selected to be powered down during deep-sleep.
For lowest power consumption, the clock source should be switched to IRC before
entering Deep-sleep mode, all oscillators and PLLs should be turned off during
deep-sleep, and the IRC should be selected as clock source when the chip wakes up from
deep-sleep. The IRC can be switched on and off glitch-free and provides a clean clock
signal after start-up.
If power consumption is not a concern, any of the oscillators and/or PLLs can be left
running in Deep-sleep mode to obtain short wake-up times when waking up from
deep-sleep.
7.17.5.3
Deep power-down mode
In Deep power-down mode, power is shut off to the entire chip with the exception of the
WAKEUP pin. The LPC1311/13/42/43 can wake up from Deep power-down mode via the
WAKEUP pin.
7.18 System control
7.18.1 Reset
Reset has four sources on the LPC1311/13/42/43: the RESET pin, the Watchdog reset,
power-on reset (POR), and the Brown-Out Detection (BOD) circuit. The RESET pin is a
Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage
attains a usable level, starts the IRC and initializes the flash controller.
When the internal reset is removed, the processor begins executing at address 0, which is
initially the reset vector mapped from the boot block. At that point, all of the processor and
peripheral registers have been initialized to predetermined values.
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7.18.2 Brownout detection
The LPC1311/13/42/43 includes four levels for monitoring the voltage on the VDD(3V3) pin.
If this voltage falls below one of the four selected levels, the BOD asserts an interrupt
signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable
Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the
signal by reading a dedicated status register. An additional threshold level can be selected
to cause a forced reset of the chip.
7.18.3 Code security (Code Read Protection - CRP)
This feature of the LPC1311/13/42/43 allows user to enable different levels of security in
the system so that access to the on-chip flash and use of the JTAG and ISP can be
restricted. When needed, CRP is invoked by programming a specific pattern into a
dedicated flash location. IAP commands are not affected by the CRP.
There are three levels of Code Read Protection:
1. CRP1 disables access to chip via the JTAG and allows partial flash update (excluding
flash sector 0) using a limited set of the ISP commands. This mode is useful when
CRP is required and flash field updates are needed but all sectors can not be erased.
2. CRP2 disables access to chip via the JTAG and only allows full flash erase and
update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected fully disables any access to chip via
the JTAG pins and the ISP. This mode effectively disables ISP override using PIO0_1
pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
UART0.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details see the LPC13xx user manual.
7.18.4 Boot loader
The boot loader controls initial operation after reset and also provides the means to
program the flash memory. This could be initial programming of a blank device, erasure
and re-programming of a previously programmed device, or programming of the flash
memory by the application program in a running system.
The boot loader code is executed every time the part is reset or powered up. The loader
can either execute the ISP command handler or the user application code, or, on the
LPC134x, it can obtain the boot image as an attached MSC device through USB. A LOW
level during reset at the PIO0_1 pin is considered an external hardware request to start
the ISP command handler or the USB device enumeration. The state of PIO0_3
determines whether the UART or USB interface will be used (LPC134x only).
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7.18.5 APB interface
The APB peripherals are located on one APB bus.
7.18.6 AHB-Lite
The AHB-Lite connects the instruction (I-code) and data (D-code) CPU buses of the ARM
Cortex-M3 to the flash memory, the main static RAM, and the boot ROM.
7.18.7 External interrupt inputs
All GPIO pins can be level or edge sensitive interrupt inputs.
7.18.8 Memory mapping control
The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table
to alternate locations in the memory map. This is controlled via the Vector Table Offset
Register contained in the NVIC.
The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address
space. The vector table must be located on a 128 word (512 byte) boundary because the
NVIC on the LPC1311/13/42/43 is configured for 128 total interrupts.
7.19 Emulation and debugging
Debug functions are integrated into the ARM Cortex-M3. Serial wire debug is supported.
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8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
VDD(3V3)
Parameter
supply voltage (3.3 V)
Conditions
core and external rail
Min
Max
Unit
[2]
2.0
3.6
V
[2]
VDD(IO)
input/output supply voltage
2.0
3.6
V
VI
input voltage
5 V tolerant I/O pins; only valid
when the VDD(IO) supply voltage is
present
[3]
−0.5
+5.5
V
IDD
supply current
per supply pin
[4]
-
100
mA
ISS
ground current
per ground pin
[4]
-
100
mA
Ilatch
I/O latch-up current
−(0.5VDD(IO)) < VI < (1.5VDD(IO));
-
100
mA
Tstg
storage temperature
−65
+150
°C
Tj(max)
maximum junction temperature
-
150
°C
Ptot(pack)
total power dissipation (per
package)
based on package heat transfer, not
device power consumption
-
1.5
W
VESD
electrostatic discharge voltage
human body model; all pins
−5000
+5000
V
Tj < 125 °C
[5]
[6]
[1]
The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
[2]
Tie together VDD(3V3) and VDD(IO) externally. If separate supplies are used for VDD(3V3) and VDD(IO), ensure that the voltage difference
between both supplies is smaller than or equal to 0.5 V.
[3]
Including voltage on outputs in 3-state mode.
[4]
The peak current is limited to 25 times the corresponding maximum current.
[5]
Dependent on package type.
[6]
Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
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9. Static characteristics
Table 7.
Static characteristics
Tamb = −40 °C to +85 °C, unless otherwise specified.
Min
Typ[1]
Max
Unit
supply voltage (3.3 V)
[2]
2.0
3.3
3.6
V
VDD(IO)
input/output supply
voltage
[2]
2.0
3.3
3.6
V
IDD
supply current
Symbol
VDD(3V3)
Parameter
Conditions
Active mode; VDD(3V3) = 3.3 V;
Tamb = 25 °C; code
while(1){}
executed from flash;
system clock = 12 MHz
[3][4][5]
-
4
-
mA
system clock = 72 MHz
[4][5][6]
-
17
-
mA
[3][4][5]
-
2
-
mA
Deep-sleep mode; VDD(3V3) = 3.3 V;
Tamb = 25 °C
[7]
-
30
-
µA
Deep power-down mode;
VDD(3V3) = 3.3 V; VDD(IO) = 3.3 V;
Tamb = 25 °C
[8]
-
220
-
nA
Deep power-down mode;
VDD(3V3) = 3.3 V; VDD(IO) = 3.3 V;
Tamb = 25 °C
[8][9]
-
20
-
nA
Sleep mode;
VDD(3V3) = 3.3 V; Tamb = 25 °C;
system clock = 12 MHz
IDD(IO)
I/O supply current
Standard port pins and RESET pin; see Figure 16, Figure 17, Figure 18 and Figure 19
IIL
LOW-level input current VI = 0 V; on-chip pull-up resistor
disabled
-
-
3
µA
IIH
HIGH-level input current VI = VDD(IO); on-chip pull-down
resistor disabled
-
-
3
µA
IOZ
OFF-state output
current
VO = 0 V; VO = VDD(IO); on-chip
pull-up/down resistors disabled
-
-
3
µA
VI
input voltage
pin configured to provide a digital
function
0
-
5.0
V
0
-
VDD(IO)
V
[10][11]
[12]
VO
output voltage
output active
VIH
HIGH-level input
voltage
2.0
-
-
V
VIL
LOW-level input voltage
-
-
0.8
V
Vhys
hysteresis voltage
0.4
-
-
V
VDD(IO) −
0.4
-
-
V
VOH
HIGH-level output
voltage
IOH = −4 mA
[13]
VOL
LOW-level output
voltage
IOL = 4 mA
[13]
-
-
0.4
V
IOH
HIGH-level output
current
VOH = VDD(IO) − 0.4 V
[13]
−4
-
-
mA
IOL
LOW-level output
current
VOL = 0.4 V
[13]
4
-
-
mA
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Table 7.
Static characteristics …continued
Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
-
-
−45
mA
-
-
50
mA
IOHS
HIGH-level short-circuit VOH = 0 V
output current
[14]
IOLS
LOW-level short-circuit
output current
VOL = VDD(IO)
[14]
Ipd
pull-down current
VI = 5 V
10
50
150
µA
Ipu
pull-up current
VI = 0 V
−15
−50
−85
µA
VDD(IO) < VI < 5 V
0
0
0
µA
High-drive output pin (PIO0_7); see Figure 14 and Figure 16
IIL
LOW-level input current VI = 0 V; on-chip pull-up resistor
disabled
-
-
3
µA
IIH
HIGH-level input current VI = VDD(IO); on-chip pull-down
resistor disabled
-
-
3
µA
IOZ
OFF-state output
current
VO = 0 V; VO = VDD(IO); on-chip
pull-up/down resistors disabled
-
-
3
µA
VI
input voltage
pin configured to provide a digital
function
0
-
5.0
V
0
-
VDD(IO)
V
[10][11]
[12]
VO
output voltage
output active
VIH
HIGH-level input
voltage
2.0
-
-
V
VIL
LOW-level input voltage
-
-
0.8
V
Vhys
hysteresis voltage
0.4
-
-
V
VDD(IO) −
0.4
-
-
V
VOH
HIGH-level output
voltage
IOH = −20 mA
[13]
VOL
LOW-level output
voltage
IOL = 4 mA
[13]
-
-
0.4
V
IOH
HIGH-level output
current
VOH = VDD(IO) − 0.4 V; VDD(IO) ≥
2.5 V
[13]
20
-
-
mA
IOL
LOW-level output
current
VOL = 0.4 V
[13]
4
-
-
mA
Ipd
pull-down current
VI = 5 V
10
50
150
µA
Ipu
pull-up current
VI = 0 V
−15
−50
−85
µA
VDD(IO) < VI < 5 V
0
0
0
µA
V
I2C-bus
pins (PIO0_4 and PIO0_5); see Figure 15
VIH
HIGH-level input
voltage
0.7VDD(IO) -
-
VIL
LOW-level input voltage
-
-
0.3VDD(IO) V
Vhys
hysteresis voltage
VOL
LOW-level output
voltage
IOLS = 20 mA
[13]
ILI
input leakage current
VI = VDD(IO)
[15]
VI = 5 V
-
0.5VDD(IO) -
V
-
-
0.4
V
-
2
4
µA
-
10
22
µA
Oscillator pins
Vi(xtal)
crystal input voltage
0
1.8
1.95
V
Vo(xtal)
crystal output voltage
0
1.8
1.95
V
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Table 7.
Static characteristics …continued
Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
0 V < VI < 3.3 V
-
-
±10
µA
-
-
5.25
V
USB pins (LPC1342/43 only)
IOZ
OFF-state output
current
VBUS
bus supply voltage
VDI
differential input
sensitivity voltage
|(D+) − (D−)|
0.2
-
-
V
VCM
differential common
mode voltage range
includes VDI range
0.8
-
2.5
V
Vth(rs)se
single-ended receiver
switching threshold
voltage
0.8
-
2.0
V
VOL
LOW-level output
voltage
for low-/full-speed;
RL of 1.5 kΩ to 3.6 V
-
-
0.18
V
VOH
HIGH-level output
voltage
driven; for low-/full-speed;
RL of 15 kΩ to GND
2.8
-
3.5
V
Ctrans
transceiver capacitance pin to GND
-
-
20
pF
ZDRV
with 33 Ω series resistor; steady
driver output
state drive
impedance for driver
which is not high-speed
capable
36
-
44.1
Ω
[16]
[1]
Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.
[2]
Tie together VDD(3V3) and VDD(IO) externally. If separate supplies are used for VDD(3V3) and VDD(IO), ensure that the voltage difference
between both supplies is smaller than or equal to 0.5 V.
[3]
IRC enabled; system oscillator disabled; system PLL disabled.
[4]
BOD disabled.
[5]
All peripherals disabled in the AHBCLKCTRL register. Peripheral clocks to UART, SSP, trace clock, and SysTick timer disabled in the
syscon block.
[6]
IRC disabled; system oscillator enabled; system PLL enabled.
[7]
All oscillators and analog blocks turned off in the PDSLEEPCFG register; PDSLEEPCFG = 0xFFFF FFFF
[8]
WAKEUP pin pulled HIGH externally.
[9]
For LPC134x: USB_DP and USB_DM pulled LOW externally.
[10] Including voltage on outputs in 3-state mode.
[11] VDD(3V3) and VDD(IO) supply voltages must be present.
[12] 3-state outputs go into 3-state mode when VDD(IO) is grounded.
[13] Accounts for 100 mV voltage drop in all supply lines.
[14] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[15] To VSS.
[16] Includes external resistors of 33 Ω ± 1 % on USB_DP and USB_DM.
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Table 8.
ADC static characteristics
Tamb = −40 °C to +85 °C unless otherwise specified; ADC frequency 4.5 MHz, VDD(3V3) = 2.5 V to 3.6 V.
Symbol
Parameter
VIA
Cia
Conditions
Min
Typ
Max
Unit
analog input voltage
0
-
VDD(3V3)
V
analog input capacitance
-
-
1
pF
[1][2]
-
-
±1
LSB
integral non-linearity
[3]
-
-
± 1.5
LSB
EO
offset error
[4]
-
-
± 3.5
LSB
EG
gain error
[5]
-
-
0.6
%
absolute error
[6]
-
-
±4
LSB
differential linearity error
ED
EL(adj)
ET
[1]
The ADC is monotonic, there are no missing codes.
[2]
The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 8.
[3]
The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 8.
[4]
The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 8.
[5]
The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 8.
[6]
The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC
and the ideal transfer curve. See Figure 8.
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offset
error
EO
gain
error
EG
1023
1022
1021
1020
1019
1018
(2)
7
code
out
(1)
6
5
(5)
4
(4)
3
(3)
2
1 LSB
(ideal)
1
0
1
2
3
4
5
6
7
1018
1019
1020
1021
1022
1023
1024
VIA (LSBideal)
offset error
EO
1 LSB =
VDD(3V3) − VSS
1024
002aae787
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 8.
ADC characteristics
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9.1 BOD static characteristics
Table 9.
BOD static characteristics[1]
Tamb = 25 °C.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vth
threshold voltage
interrupt level 0
assertion
-
1.69
-
V
de-assertion
-
1.84
-
V
assertion
-
2.29
-
V
de-assertion
-
2.44
-
V
assertion
-
2.59
-
V
de-assertion
-
2.74
-
V
assertion
-
2.87
-
V
de-assertion
-
2.98
-
V
assertion
-
1.49
-
V
de-assertion
-
1.64
-
V
interrupt level 1
interrupt level 2
interrupt level 3
reset level 0
[1]
Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC13xx
user manual.
9.2 Power consumption
002aae993
18
IDD
(mA)
72 MHz
15
12
9
48 MHz
36 MHz
24 MHz
6
12 MHz
3
2.0
2.4
2.8
3.2
3.6
VDD(3V3) (V)
Conditions: Tamb = 25 °C; active mode entered executing code while(1){} from flash;
VDD(3V3) = 3.3 V; internal pull-up resistors disabled; system oscillator and system PLL enabled;
IRC, BOD disabled; all peripherals disabled in the AHBCLKCTRL register (AHBCLKCTRL = 0x1F);
all peripheral clocks disabled.
Fig 9.
Typical supply current versus regulator supply voltage VDD(3V3) in active mode
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32-bit ARM Cortex-M3 microcontroller
002aae994
18
IDD
(mA)
72 MHz
15
48 MHz
12
36 MHz
9
24 MHz
6
12 MHz
3
−40
−15
10
35
60
85
temperature (°C)
Conditions: Active mode entered executing code while(1){} from flash; VDD(3V3) = 3.3 V; internal
pull-up resistors disabled; system oscillator and system PLL enabled; IRC, BOD disabled; all
peripherals disabled in the AHBCLKCTRL register (AHBCLKCTRL = 0x1F); all peripheral clocks
disabled.
Fig 10. Typical supply current versus temperature in active mode
002aae995
10
72 MHz
IDD
(mA)
8
48 MHz
6
36 MHz
4
24 MHz
12 MHz
2
0
−40
−15
10
35
60
85
temperature (°C)
Conditions: VDD(3V3) = 3.3 V; Sleep mode entered from flash; internal pull-up resistors disabled;
system oscillator and system PLL enabled; IRC, BOD disabled; all peripherals disabled in the
AHBCLKCTRL register (AHBCLKCTRL = 0x1F); all peripheral clocks disabled.
Fig 11. Typical supply current versus temperature in Sleep mode
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002aae998
80
IDD
(µA)
60
VDD(3V3) = 3.6 V
3.3 V
2.0 V
40
20
0
−40
−15
10
35
60
85
temperature (°C)
Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG
register; PDSLEEPCFG = 0xFFFF FFFF.
Fig 12. Typical supply current versus temperature in Deep-sleep mode (analog blocks
disabled)
002aae996
1000
IDD
(nA)
800
VDD(3V3) = 3.6 V
3.3 V
2.0 V
600
400
200
0
−40
−15
10
35
60
85
temperature (°C)
Fig 13. Typical supply current versus temperature in Deep power-down mode
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32-bit ARM Cortex-M3 microcontroller
Table 10. Power consumption in Deep-sleep mode for individual analog blocks
Tamb = 25 °C; VDD(3V3) = 3.3 V.
Analog block enabled in PDSLEEPCFG register
Conditions
Typical IDD[1]
USB PLL
[2]
39 µA
System PLL
[2]
39 µA
System oscillator
[2]
197 µA
BOD
[2]
74 µA
IRC
[2]
36 µA
IRC output
[2]
27 µA
[1]
Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply
voltages.
[2]
All other blocks disabled in the PDSLEEPCFG register.
9.3 Electrical pin characteristics
002aae990
3.6
VOH
(V)
T = 85 °C
25 °C
−40 °C
3.2
2.8
2.4
2
0
10
20
30
40
50
60
IOH (mA)
Conditions: VDD(3V3) = VDD(IO) = 3.3 V; on pin PIO0_7.
Fig 14. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level
output current IOH.
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002aaf019
60
T = 85 °C
25 °C
−40 °C
IOL
(mA)
40
20
0
0
0.2
0.4
0.6
VOL (V)
Conditions: VDD(3V3) = VDD(IO) = 3.3 V; on pins PIO0_4 and PIO0_5.
Fig 15. I2C-bus pins (high current sink): Typical LOW-level output current IOL versus
LOW-level output voltage VOL
002aae991
15
IOL
(mA)
T = 85 °C
25 °C
−40 °C
10
5
0
0
0.2
0.4
0.6
VOL (V)
Conditions: VDD(3V3) = VDD(IO) = 3.3 V; standard port pins and PIO0_7.
Fig 16. Typical LOW-level output current IOL versus LOW-level output voltage VOL
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002aae992
3.6
VOH
(V)
T = 85 °C
25 °C
−40 °C
3.2
2.8
2.4
2
0
8
16
24
IOH (mA)
Conditions: VDD(3V3) = VDD(IO) = 3.3 V; standard port pins.
Fig 17. Typical HIGH-level output voltage VOH versus HIGH-level output source current
IOH
002aae988
10
Ipu
(µA)
−10
−30
T = 85 °C
25 °C
−40 °C
−50
−70
0
1
2
3
4
5
VI (V)
Conditions: VDD(3V3) = VDD(IO) = 3.3 V; standard port pins.
Fig 18. Typical pull-up current Ipu versus input voltage Vi
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002aae989
80
T = 85 °C
25 °C
−40 °C
Ipd
(µA)
60
40
20
0
0
1
2
3
4
5
VI (V)
Conditions: VDD(3V3) = VDD(IO) = 3.3 V; standard port pins.
Fig 19. Typical pull-down current Ipd versus input voltage Vi
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10. Dynamic characteristics
10.1 Flash memory
Table 11. Flash characteristics
Tamb = −40 °C to +85 °C, unless otherwise specified.
Symbol
Parameter
Nendu
endurance
tret
retention time
[1]
Conditions
Min
[1]
Typ
Max
Unit
10000
-
-
cycles
powered
10
-
-
years
unpowered
20
-
-
years
Number of program/erase cycles.
10.2 External clock
Table 12. Dynamic characteristic: external clock
Tamb = −40 °C to +85 °C; VDD(3V3) over specified ranges.[1]
Min
Typ[2]
Max
Unit
oscillator frequency
1
-
25
MHz
clock cycle time
40
-
1000
ns
tCHCX
clock HIGH time
Tcy(clk) × 0.4
-
-
ns
tCLCX
clock LOW time
Tcy(clk) × 0.4
-
-
ns
tCLCH
clock rise time
-
-
5
ns
tCHCL
clock fall time
-
-
5
ns
Symbol
Parameter
fosc
Tcy(clk)
Conditions
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.
tCHCL
tCHCX
tCLCH
tCLCX
Tcy(clk)
002aaa907
Fig 20. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
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10.3 Internal oscillators
Table 13. Dynamic characteristic: internal oscillators
Tamb = −40 °C to +85 °C; 2.7 V ≤ VDD(3V3) ≤ 3.6 V[1].
Symbol
Parameter
Conditions
Min
Typ[2]
Max
Unit
fosc(RC)
internal RC oscillator frequency
-
11.88
12
12.12
MHz
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages.
002aae987
12.15
VDD(3V3) = 3.6 V
3.3 V
3.0 V
2.7 V
2.4 V
2.0 V
f
(MHz)
12.05
11.95
11.85
−40
−15
10
35
60
85
temperature (°C)
Conditions: Frequency values are typical values. 12 MHz ± 1 % accuracy is guaranteed for
2.7 V ≤ VDD(3V3) ≤ 3.6 V and Tamb = −40 °C to +85 °C. Variations between parts may cause the
IRC to fall outside the 12 MHz ± 1 % accuracy specification for voltages below 2.7 V.
Fig 21. Internal RC oscillator frequency f versus temperature
10.4 I2C-bus
Table 14. Dynamic characteristic: I2C-bus pins (Fast-mode Plus)
Tamb = −40 °C to +85 °C; VDD(3V3) = VDD(IO) = 3.3 V.[1][2][3]
Symbol
Parameter
fSCL
Conditions
Min
Typ
Max
Unit
SCL clock frequency
-
-
1
MHz
tf
fall time
-
-
45
ns
tSU;DAT
data set-up time
50
-
-
ns
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Main clock frequency 10 MHz; system clock divider AHBCLKDIV = 0x1; I2C-bus interface configured in master mode.
[3]
Bus capacitance Cb = 550 pF; external pull-up resistance of 103 Ω.
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SDA
tf
SCL
P
S
tSU;DAT
002aae860
Fig 22. I2C-bus pins clock timing
10.5 SSP interface
Table 15.
Dynamic characteristics of SSP pins in SPI mode
Symbol
Parameter
Tcy(PCLK)
PCLK cycle time
Tcy(clk)
clock cycle time
Conditions
Min
Max
Unit
13.9
-
ns
[1]
27.8
-
ns
in SPI mode
[2]
15
Tcy(clk)
ns
SSP master
data set-up time
tDS
tDH
data hold time
in SPI mode
[2]
-
0
ns
tv(Q)
data output valid time
in SPI mode
[2]
-
10
ns
data output hold time
in SPI mode
[2]
-
0
ns
tDS
data set-up time
in SPI mode
[3][4]
0
-
ns
tDH
data hold time
in SPI mode
[3][4]
3 × Tcy(PCLK) + 4
-
ns
in SPI mode
[3][4]
-
3 × Tcy(PCLK) + 11
ns
in SPI mode
[3][4]
-
2 × Tcy(PCLK) + 5
ns
th(Q)
SSP slave
data output valid time
tv(Q)
data output hold time
th(Q)
[1]
Tcy(clk) = (SSPCLKDIV × (1 + SCR) × CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the
main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0
register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
[2]
Tamb = −40 °C to 85 °C; VDD(3V3) = 2.0 V to 3.6 V; VDD(IO) = 2.0 V to 3.6 V.
[3]
Tcy(clk) = 12 × Tcy(PCLK).
[4]
Tamb = 25 °C; VDD(3V3) = 3.3 V; VDD(IO) = 3.3 V.
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Tcy(clk)
tclk(H)
tclk(L)
SCK (CPOL = 0)
SCK (CPOL = 1)
tv(Q)
th(Q)
DATA VALID
MOSI
DATA VALID
tDS
DATA VALID
MISO
th(Q)
DATA VALID
DATA VALID
tDS
MISO
CPHA = 1
DATA VALID
tv(Q)
MOSI
tDH
DATA VALID
tDH
CPHA = 0
DATA VALID
002aae829
Fig 23. SSP master timing in SPI mode
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Tcy(clk)
tclk(H)
tclk(L)
tDS
tDH
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI
DATA VALID
DATA VALID
tv(Q)
MISO
th(Q)
DATA VALID
DATA VALID
tDS
MOSI
DATA VALID
tDH
DATA VALID
tv(Q)
MISO
DATA VALID
CPHA = 1
th(Q)
CPHA = 0
DATA VALID
002aae830
Fig 24. SSP slave timing in SPI mode
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10.6 USB interface (LPC1342/43 only)
Table 16. Dynamic characteristics: USB pins (full-speed)
CL = 50 pF; Rpu = 1.5 kΩ on D+ to VDD(3V3), unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tr
rise time
10 % to 90 %
8.5
-
13.8
ns
tf
fall time
10 % to 90 %
7.7
-
13.7
ns
tFRFM
differential rise and fall time
matching
tr / tf
-
-
109
%
VCRS
output signal crossover voltage
1.3
-
2.0
V
tFEOPT
source SE0 interval of EOP
see Figure 25
160
-
175
ns
tFDEOP
source jitter for differential transition
to SE0 transition
see Figure 25
−2
-
+5
ns
tJR1
receiver jitter to next transition
−18.5
-
+18.5
ns
tJR2
receiver jitter for paired transitions
10 % to 90 %
−9
-
+9
ns
tEOPR1
EOP width at receiver
must reject as
EOP; see
Figure 25
[1]
40
-
-
ns
tEOPR2
EOP width at receiver
must accept as
EOP; see
Figure 25
[1]
82
-
-
ns
[1]
Characterized but not implemented as production test. Guaranteed by design.
TPERIOD
crossover point
extended
crossover point
differential
data lines
source EOP width: tFEOPT
differential data to
SE0/EOP skew
n × TPERIOD + tFDEOP
receiver EOP width: tEOPR1, tEOPR2
002aab561
Fig 25. Differential data-to-EOP transition skew and EOP width
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11. Application information
11.1 Suggested USB interface solutions (LPC1342/43 only)
VDD(IO)
USB_CONNECT
LPC134x
soft-connect switch
R1
1.5 kΩ
USB_VBUS
USB_DP RS = 33 Ω
USB_DM
USB-B
connector
RS = 33 Ω
VSSIO
002aae608
Fig 26. LPC1342/43 USB interface on a self-powered device
VDD(IO)
LPC134x
R1
1.5 kΩ
USB_VBUS
USB_DP RS = 33 Ω
USB-B
connector
USB_DM RS = 33 Ω
VSSIO
002aae609
Fig 27. LPC1342/43 USB interface on a bus-powered device
11.2 XTAL input
The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a
clock in slave mode, it is recommended that the input be coupled through a capacitor with
Ci = 100 pF. To limit the input voltage to the specified range, choose an additional
capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave
mode, a minimum of 200 mV(RMS) is needed.
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LPC1xxx
XTALIN
Ci
100 pF
Cg
002aae788
Fig 28. Slave mode operation of the on-chip oscillator
11.3 XTAL Printed-Circuit Board (PCB) layout guidelines
The crystal should be connected on the PCB as close as possible to the oscillator input
and output pins of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of
third overtone crystal usage have a common ground plane. The external components
must also be connected to the ground plain. Loops must be made as small as possible in
order to keep the noise coupled in via the PCB as small as possible. Also parasitics
should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller
accordingly to the increase in parasitics of the PCB layout.
11.4 Standard I/O pad configuration
Figure 29 shows the possible pin modes for standard I/O pins. The pull-up and pull-down
resistors (Rpu and Rpd) can be enabled or disabled. The default value for each standard
port pin is input with Rpu enabled. For details on pin modes and hysteresis control, see the
LPC13xx user manual.
VDD(IO)
Rpu
enable
output
PIN
input
Rpd
hysteresis
control
VSS
002aae828
Fig 29. Standard I/O pad configuration
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12. Package outline
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
37
24
ZE
e
E HE
A A2
(A 3)
A1
w M
θ
bp
pin 1 index
Lp
L
13
48
1
detail X
12
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.6
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
7.1
6.9
7.1
6.9
0.5
9.15
8.85
9.15
8.85
1
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
0.95
0.55
7
o
0
0.95
0.55
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT313-2
136E05
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-25
Fig 30. Package outline SOT313-2 (LQFP48)
LPC1311_13_42_43_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 11 December 2009
48 of 53
LPC1311/13/42/43
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
33 terminals; body 7 x 7 x 0.85 mm
B
D
A
terminal 1
index area
A
E
A1
c
detail X
e1
e
9
16
C
C A B
C
v
w
b
y
y1 C
L
8
17
e
e2
Eh
33
1
terminal 1
index area
24
32
X
25
Dh
0
2.5
scale
Dimensions
Unit
mm
5 mm
A(1)
A1
b
max 1.00 0.05 0.35
nom 0.85 0.02 0.28
min 0.80 0.00 0.23
c
D(1)
Dh
E(1)
0.2
7.1
7.0
6.9
4.85
4.70
4.55
7.1
7.0
6.9
Eh
e
e1
e2
L
0.75
4.85
4.70 0.65 4.55 4.55 0.60
0.45
4.55
v
0.1
w
y
0.05 0.08
y1
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
Outline
version
References
IEC
JEDEC
JEITA
---
hvqfn33_po
European
projection
Issue date
09-03-17
09-03-23
Fig 31. Package outline (HVQFN33)
LPC1311_13_42_43_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 11 December 2009
49 of 53
LPC1311/13/42/43
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
13. Abbreviations
Table 17.
Abbreviations
Acronym
Description
A/D
Analog-to-Digital
ADC
Analog-to-Digital Converter
AHB
Advanced High-performance Bus
AMBA
Advanced Microcontroller Bus Architecture
APB
Advanced Peripheral Bus
BOD
BrownOut Detection
EOP
End Of Packet
ETM
Embedded Trace Macrocell
FIFO
First-In, First-Out
GPIO
General Purpose Input/Output
I/O
Input/Output
LSB
Least Significant Bit
MSC
Mass Storage Class
PHY
Physical Layer
PLL
Phase-Locked Loop
SE0
Single Ended Zero
SPI
Serial Peripheral Interface
SSI
Serial Synchronous Interface
SSP
Synchronous Serial Port
SoF
Start-of-Frame
TCM
Tightly-Coupled Memory
TTL
Transistor-Transistor Logic
UART
Universal Asynchronous Receiver/Transmitter
USB
Universal Serial Bus
LPC1311_13_42_43_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 11 December 2009
50 of 53
LPC1311/13/42/43
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
14. Revision history
Table 18.
Revision history
Document ID
Release date
Data sheet status
Change
notice
Supersedes
LPC1311_13_42_43_1
20091211
Product data sheet
-
-
LPC1311_13_42_43_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 11 December 2009
51 of 53
LPC1311/13/42/43
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
LPC1311_13_42_43_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 11 December 2009
52 of 53
LPC1311/13/42/43
NXP Semiconductors
32-bit ARM Cortex-M3 microcontroller
17. Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
7.2
7.3
7.4
7.5
7.6
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional description . . . . . . . . . . . . . . . . . . 14
Architectural overview. . . . . . . . . . . . . . . . . . . 14
ARM Cortex-M3 processor . . . . . . . . . . . . . . . 14
On-chip flash program memory . . . . . . . . . . . 15
On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 15
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Nested Vectored Interrupt Controller
(NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.6.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.6.2
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 17
7.7
IOCONFIG block. . . . . . . . . . . . . . . . . . . . . . . 17
7.8
Fast general purpose parallel I/O . . . . . . . . . . 17
7.8.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.9
USB interface (LPC1342/43 only). . . . . . . . . . 18
7.9.1
Full-speed USB device controller . . . . . . . . . . 18
7.9.1.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.10
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.10.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.11
SSP serial I/O controller . . . . . . . . . . . . . . . . . 19
7.11.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.12
I2C-bus serial I/O controller . . . . . . . . . . . . . . 19
7.12.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.13
10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.13.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.14
General purpose external event
counters/timers . . . . . . . . . . . . . . . . . . . . . . . . 20
7.14.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.15
System tick timer . . . . . . . . . . . . . . . . . . . . . . 21
7.16
Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 21
7.16.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.17
Clocking and power control. . . . . . . . . . . . . . . 21
7.17.1
Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 21
7.17.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 22
7.17.1.2 System oscillator. . . . . . . . . . . . . . . . . . . . . . . 23
7.17.2
System PLL and USB PLL . . . . . . . . . . . . . . . 23
7.17.3
Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.17.4
Wake-up process . . . . . . . . . . . . . . . . . . . . . . 23
7.17.5
Power control . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.17.5.1
7.17.5.2
7.17.5.3
7.18
7.18.1
7.18.2
7.18.3
7.18.4
7.18.5
7.18.6
7.18.7
7.18.8
7.19
8
9
9.1
9.2
9.3
10
10.1
10.2
10.3
10.4
10.5
10.6
11
11.1
11.2
11.3
11.4
12
13
14
15
15.1
15.2
15.3
15.4
16
17
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . .
Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . .
Deep power-down mode . . . . . . . . . . . . . . . .
System control . . . . . . . . . . . . . . . . . . . . . . . .
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Brownout detection . . . . . . . . . . . . . . . . . . . .
Code security
(Code Read Protection - CRP). . . . . . . . . . . .
Boot loader. . . . . . . . . . . . . . . . . . . . . . . . . . .
APB interface . . . . . . . . . . . . . . . . . . . . . . . . .
AHB-Lite . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External interrupt inputs . . . . . . . . . . . . . . . . .
Memory mapping control . . . . . . . . . . . . . . . .
Emulation and debugging. . . . . . . . . . . . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
BOD static characteristics . . . . . . . . . . . . . . .
Power consumption . . . . . . . . . . . . . . . . . . . .
Electrical pin characteristics. . . . . . . . . . . . . .
Dynamic characteristics . . . . . . . . . . . . . . . . .
Flash memory . . . . . . . . . . . . . . . . . . . . . . . .
External clock. . . . . . . . . . . . . . . . . . . . . . . . .
Internal oscillators . . . . . . . . . . . . . . . . . . . . .
I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSP interface . . . . . . . . . . . . . . . . . . . . . . . . .
USB interface (LPC1342/43 only) . . . . . . . . .
Application information . . . . . . . . . . . . . . . . .
Suggested USB interface solutions
(LPC1342/43 only) . . . . . . . . . . . . . . . . . . . . .
XTAL input . . . . . . . . . . . . . . . . . . . . . . . . . . .
XTAL Printed-Circuit Board
(PCB) layout guidelines . . . . . . . . . . . . . . . . .
Standard I/O pad configuration . . . . . . . . . . .
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
24
24
24
24
25
25
25
26
26
26
26
26
27
28
33
33
36
40
40
40
41
41
42
45
46
46
46
47
47
48
50
51
52
52
52
52
52
52
53
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 11 December 2009
Document identifier: LPC1311_13_42_43_1