E2B0039-27-Y2 ¡ Semiconductor MSM6255 ¡ Semiconductor This version: Nov. 1997 MSM6255 Previous version: Mar. 1996 DOT MATRIX LCD CONTROLLER GENERAL DESCRIPTION The MSM6255 is a CMOS si-gate LSI designed to display characters and graphics on a DOT MATRIX LCD panel. FEATURES • Display control capacity – Graphic mode – Character mode : 512,000 dots (216 bytes) Memory address MA0 to MA15 : 65,536 characters (216 bytes) Display address MA0 to MA15 • Direct interface with 8085 or Z80 CPU • Duty : 1/2 to 1/256 selectable • Attributes – Screen clear – Cursor ON/OFF/blink • Scrolling and paging • Display system : AC inversion at each frame • Data output (upper and lower display outputs) 4-bit parallel output, 2-bit parallel output, 1-bit serial output • Crystal oscillation/external clock selectable • Single +5V power supply • Package options: 80-pin plastic QFP (QFP80-P-1420-0.80-K) (Product name: MSM6255GS-K) 80-pin plastic QFP (QFP80-P-1420-0.80-BK) (Product name: MSM6255GS-BK) 1/39 RD VSS VDD RES DB0 - DB7 CS WR DIV XT XT OSC R/W control Instruction register T Output register Input register Q Cursor position (lower) Cursor position (upper) Cursor address Cursor address Dot counter PR Timing generator circuit for CHφ PS and Load CMP Number of HNR characters horizontal direction Number of Hp CMP CMP CMP CMP CMP CMP Number DUR of duty Number DPR of Vp CPR CPR CLR CUP CHφ Timing control CHφ BUSY LIP Shift clock suspension counter Character counter Duty counter Vp counter Cursor generation circuit SLR FRP FRMB RD0 - RD7 LD0 - LD3 CLP CEφ UD0 - UD3 RA0 - RA3 DIEN A0 - A15 ADF MA0 - MA15 8-bit parallel/ serial Raster address Start SUAR address (upper) 3-state output 4-bit parallel output 2-bit parallel output MPX Linear address counter Start address (lower) ¡ Semiconductor MSM6255 BLOCK DIAGRAM 2/39 ¡ Semiconductor MSM6255 65 XT 66 XT 67 VSS 68 TEST1 69 TEST2 70 DIV 71 MA15 72 MA14 73 MA13 74 MA12 75 MA11 76 MA10 77 MA9 2 64 RA3 63 RA2 3 62 RA1 4 61 RA0 5 60 RD7 59 RD6 1 6 7 9 58 RD5 57 RD4 56 RD3 10 55 RD2 11 12 54 RD1 53 RD0 13 52 DB7 14 51 DB6 15 50 DB5 49 DB4 8 16 17 48 DB3 47 DB2 18 19 46 DB1 45 DB0 20 44 RES 43 WR 21 22 42 RD 41 CS 23 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 CEf 25 24 CLP FRMB LD0 LD1 LD2 LD3 VDD UD0 UD1 UD2 UD3 CHf BUSY DIEN ADF MA5 MA4 MA3 MA2 MA1 MA0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 FRP LIP 79 MA7 78 MA8 80 MA6 PIN CONFIGURATION (TOP VIEW) 80-Pin Plastic QFP 3/39 ¡ Semiconductor MSM6255 PIN DESCRIPTIONS Pin Symbol 1-6 MA0 Type O 71 - 80 MA15 7 A0 22 A15 23 FRP Description Address output for displaying RAM. MA0 - MA15 are high impedance when ADF = "L". I Memory address input pins O Frame signal. Synchronization of display 24 LIP O Display data latch signal 25 CEφ O Chip enable clock for LCD segment driver 26 CLP O Display data shift clock 27 FRMB O Alternate signal output pin 28 LD0 O Display data parallel output for lower side 31 LD3 O Supply voltage 32 VDD 33 UD0 O 36 UD3 Display data parallel output, Upper display 4-bit output (OD1, ED1, OD2 and ED2 outputs) 37 CHφ O Character clock 38 Busy O Ready state signal. This signal is used while serial transmission stops. 39 DIEN I Display enable signal. When this signal is "H", display is enabled. 40 ADF I 41 CS I Chip select. CS = "L" 42 RD I Read. Reading data is valid when RD = "L" Address floating input. When this signal is "L", MA0 - MA15, RA0 - RA3 are high impedance, and when it is "H", A0 - A15 or a refresh address is output to MA0 - MA15. 43 WR I Write. Data is written when WR = "H" 44 RES I Reset. Resets each counter. 45 DB0 I/O 52 DB7 53 RD0 60 RD7 61 RA0 I RA3 65 XT ROM/RAM data input. Dot pattern data for the character generator Raster address output. O 64 8-bit data bus. Common pins for 3-state I/O. *This output is not used in the graphic mode. RA0 - RA3 are high impedance when ADF = "L". I X’tal osc. When an external clock is used by setting DIV to "H", feeds it to XT. 66 XT O 67 VSS — 70 DIV I Ground pin. "H" : EXT clock "L" : Self oscillation 4/39 ¡ Semiconductor MSM6255 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition VDD VI TSTG Supply Voltage Input Voltage Storage Temperature Rating Unit Ta = 25°C –0.3 to +6 V Ta = 25°C –0.3 to VDD V — –50 to +150 °C RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Range Unit VDD VSS = 0V 4.5 to 5.5 V Supply Voltage Operating Temperature Top — –20 to +85 °C Operating Frequency fosc VDD = 5V ±10% 0 to 11 MHz ELECTRICAL CHARACTERISTICS Input Characteristics (VDD = 5V ± 5%, Ta = –20 to +85°C) Parameter Symbol Min. Typ. Max. Unit Applicable pin "H" Input Voltage VIH 2.4 — "L" Input Voltage VIL — — — V DB0 - DB7, CS, RD, WR, A0 - A15, 0.7 V DIEN, ADF, RD0 - RD7 "H" Input Voltage VIH 4.5 — — V "L" Input Voltage VIL — — 1.0 V RES, DIV, XT "H" Input Current IIH — — 1 mA DB0 - DB7, CS, RD, WA, A0 - A15, "L" Input Current IIL — — –1 mA DIEN, ADF, RD0 - RD7, RES, DIV "H" Input Current IIH 25 — 100 mA "L" Input Current IIL — — –1 mA TEST1, TEST2 Output Characteristics (VDD = 5V ± 5%, Ta = –20 to +85°C) Parameter Symbol Condition Min. Typ. Max. Unit Applicable pin LD0 - LD3 "H" Output Current IOH VOH = 2.8V –500 — — mA UD0 - UD3 MA0 - MA15 RA0 - RA3 CHφ, CEφ, LIP, FRP "L" Output Current IOL VOL = 0.4V 2.4 — — mA FRMB, BUSY, CLP DB0 - DB7 5/39 ¡ Semiconductor MSM6255 Supply Current (VDD = 5V ± 5%, Ta = –20 to +85°C) Parameter Symbol VDD Condition Min. Typ. Max. Unit Static Current IDDS 5 fosc = 0 Hz, no load — — 50 mA Dynamic Current IDD 5 fosc = 10 MHz, no load — — 15 mA Note: TEST 1 and TEST2 are open, and other inputs are either VDD or GND. Switching Characteristics 0.8 VDD 0.8 VDD 0.2 VDD 0.2 VDD tr tf (VDD = 5V ± 5%, Ta = –20 to +85°C) Symbol Condition Min. Rise Time tr CL = 60 pF — — 100 ns Fall Time tf CL = 60 pF — — 100 ns Symbol Condition Min. Oscillating Frequency fosc DIV = "L" — — Basic Clock Frequency fs DIV = "H" — — Parameter Typ. Max. Unit Applicable pin All output pins Operating Frequency (VDD = 5V ± 5%, Ta = –20 to +85°C) Parameter Typ. Max. Unit Notes 11 MHz Crystal oscillator 5.5 MHz External clock 6/39 ¡ Semiconductor MSM6255 TIMING DIAGRAM LCDC Control Signal Timing Characteristics (CL = 30pF, VDD = 5V ± 5%, Ta = –20 to +85°C) Parameter Symbol Min. Typ. Max. Unit Clock Cycle Time tCP 180 — — ns Clock "H" Level Pulse Width PWH 80 — — ns Clock "L" Level Pulse Width PWL 80 — — ns Clock Rise/Fall Time tcr/tcf — — 20 ns tCH — — 200 ns Memory Address Clock Delay Time tMA — — 100 ns Memory Address Disable Delay Time tAD1 — — 40 ns Memory Address Enable Delay Time tAD2 — — 40 ns CPU Address Delay Time tAD3 — — 100 ns Refresh Address Delay Time tAD4 — — 100 ns Reset "H" Level Pulse Width tRES 1 — — ms CPU Address Delay Time tAD5 — — 100 ns Character Clock Delay Time tCP PWL XT (External clock) PWH tcr tcf CHφ tCH MA0 - MA15 Upper Side Address Lower Side Address tMA tMA ADF MA0 - MA15 RA0 - RA3 Floating VALID tAD1 VALID tAD2 DIEN MA0 - MA15 Refresh Address CPU Address tAD3 Refresh Address tAD4 RES tRES A0 - A15 tAD5 tAD5 MA0 - MA15 7/39 ¡ Semiconductor MSM6255 Bus Timing Characteristics (CL = 50pF, VDD = 5V ± 5%, Ta = –20 to +85°C) Symbol Min. Typ. Max. Unit Ao, CS Setup Time Parameter tCS 30 — — ns RD, WR Pulse Width tCW 200 — — ns Address Hold Time tAH 10 — — ns Data Setup Time tDS 60 — — ns Data Hold Time tDH 20 — — ns Output Disable Time tOH 0 — 40 ns Access Time tACC — — 200 ns tAH A0, CS tcs tcw WR, RD tDS DB0 - DB7 (WRITE) tDH VALID DB0 - DB7 (READ) VALID tACC tOH 8/39 ¡ Semiconductor MSM6255 LCDC Driver Interface Timing Characteristics (CL = 30pF, VDD = 5V ± 5%, Ta = –20 to +85°C) Symbol Min. Typ. Max. Unit Data Delay Time Parameter tDA — — 100 ns 1 Character Cycle Time tCHφ 730 — — ns Latch Signal Delay Time tR — — 200 ns Latch Signal "H" Time tLIP 1.46 — — ms Chip Enable Clock Delay Time tCE — — 200 ns Chip Enable Clock "H" Time tCEφ 730 — — ns tB — — 200 ns Ready Signal Delay Time Ready Signal "H" Time tBUSY 5.11 — — ms Frame Signal Delay Time tFRP 2tCHφ — 2tCHφ +200 ns Alternating Frame Signal Delay Time tFR — — 200 ns CLP UD0 - UD3 LD0 - LD3 tDA tCHφ CHφ LIP tLIP t t CEφ tCEφ tCE tCE BUSY tBUSY tB tB LIP FRP tFRP tFRP FRMB tFR tFR 9/39 ¡ Semiconductor MSM6255 Timing for Fetching Pattern Data (VDD = 5V ± 5%, Ta = –20 to +85°C) Parameter Symbol Min. Typ. Max. Unit Upper Side Data Setup Time tUDS 120 — — ns Upper Side Data Hold Time tUDH 0 — — ns Lower Side Data Setup Time tLDS 120 — — ns Lower Side Data Hold Time tLDH 0 — — ns CHφ q MA0 - MA15 RD0 - RD7 w Upper side Lower side Upper side data of q tUDS Upper side Lower side data of q tLDS tUDH Lower side Upper side data of w Lower side data of w tLDH 10/39 ¡ Semiconductor MSM6255 FUNCTIONAL DESCRIPTION LCDC Internal Registers The internal registers include one instruction register (IR) and nine data registers. (See Table 1.) Table 1 MSM6255 Internal Registers CS A0 Instruction register Register Register name Data bit READ WRITE 3 2 1 0 7 6 5 4 3 2 1 0 H X X X X X – Invalid L H X X X X IR Instruction register L L L L L L MOR L L L L L H PR L L L L H L HNR Horizontal character number register L L L L H H DVR Duty number register L L L H L L CPR Cursor form register L L L H L H SLR Start address (lower) register L L L H H L SUR Start address (upper) register L L L H H H CLR Cursor address (lower) register L L H L L L CUR Cursor address (upper) register Mode control register – – X X X X X X X Character pitch register X X Note: "L" is read if the data of the registers marked X is read. – Instruction register The instruction register is a register for specifying the address of the data register which is accessed. This register is cleared when RES input is "L". 11/39 ¡ Semiconductor MSM6255 – Mode control register The mode control register is specified by writing "00H" in the instruction register. Register D6 D5 D4 D3 D2 D1 D0 L L L L L L L L Mode control register L L D1 L L H L X H X H L L H L X H X H D0 MODE DATA Output mode 1-bit serial L 2-bit parallel Character display 4-bit parallel 1-bit serial H 2-bit parallel Graphics 4-bit parallel Mode H/L D2 4-bit parallel/ 1-bit serial H/L D3 2-bit parallel H/L D4 Display ON/OFF D5 Cursor blink Blink time H/L D7 H Cursor ON/OFF D6 A0 Instruction register H: Display ON L: Display OFF D5 D4 L L Cursor OFF L H Cursor OFF H L Cursor ON H H Cursor blink H: 16 frames L: 32 frames Half of blinking cycle 12/39 ¡ Semiconductor MSM6255 – Character pitch register Register A0 D7 D6 D5 D4 D3 D2 Instruction register H L L L L L L Character pitch register L (Vp – 1) L D1 D0 L H (Hp – 1) Hp represents the number of bits to be displayed among one byte display data sent from RAM. The value of Hp is the following five types. Hp D2 D1 D0 4 L H H 5 H L L 6 H L H 7 H H L 8 H H H – Horizontal character number register Register A0 D7 D6 D5 D4 D3 D2 D1 D0 Instruction register H L L L L L L H L Character number register L L (HN – 1) Assuming that the total horizontal dot number of the display is nH, nH = Hp x HN, where HN = 2 to 128. The maximum value of nH = 8 x 128 = 128 bytes = 1,024 dots. – Duty number register Register A0 D7 D6 D5 D4 D3 D2 D1 D0 Instruction register H L L L L L L H H Time division register L (NX – 1) Nx = 2 to 256 – Cursor form register A0 D7 D6 D5 D4 D3 D2 D1 D0 Instruction register Register H L L L L L H L L Cursor position register L (Cpu – 1) (Cpd – 1) The cursor is displayed on the lines from Cpu to Cpd in the character display mode. The length of the cursor in the horizontal direction is equal to the character pitch in the horizontal direction, Hp. The cursor is not displayed in graphic mode. The relation between the cursor and Vp is as follows. 13/39 ¡ Semiconductor MSM6255 Font configuration of Hp = 7 and Vp = 8 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Cpu = 8, Cpd = 8 0 1 2 3 4 5 6 7 Cpu = 7, Cpd = 8 Cpu = 2, Cpd = 6 Notes: (1) Setting of Cpu, Cpd > Vp is not available. (2) The cursor signal and pattern data are displayed subject to EX-OR. – Start address (lower) register A0 D7 D6 D5 D4 D3 D2 D1 D0 Instruction register H L L L L L H L H Display start address register (lower byte) L Register Start address (lower) – Start address (upper) register A0 D7 D6 D5 D4 D3 D2 D1 D0 Instruction register H L L L L L H H L Display start address register (upper byte) L Register Start address (upper) The display start address shows an address of the RAM which stores data displayed at the left end and the most upper position. The start address is composed of upper and lower 8 bits (16 bits in total). – Cursor address (lower) register A0 D7 D6 D5 D4 D3 D2 D1 D0 Instruction register H L L L L L H H H Cursor address register (lower byte) L Register Cursor address (lower) – Cursor address (upper) register A0 D7 D6 D5 D4 D3 D2 D1 D0 Instruction register Register H L L L L H L L L Cursor address register (upper byte) L Cursor address (upper) By this instruction, the value of the cursor address is written in the cursor address register. The cursor is displayed at the position specified by the cursor address register. 14/39 ¡ Semiconductor MSM6255 HN Hp RD0 Vp RD7 V (Lower) V (Upper) Cpu Cpd Fig. 1 Cursor Address (Upper) Register Table 2 Legend Symbol Name Meaning Value Hp Horizontal pitch Pitch of characters in horizontal direction 4 - 8 dots Vp Vertical pitch Pitch of characters in vertical direction 1 - 16 dots HN Number of characters in one line Number of characters per line or number of words per line V Number of rows Display duty Cpu Cursor start position A position where the cursor starts display Line 1 - 16 Cpd Cursor end position A position where the cursor stops display Line 1 - 16 2 - 128 characters 2 - 256 15/39 ¡ Semiconductor MSM6255 – Built-in Bus Averter The bus averter which switches the address buses A0 - A15 of the CPU with the memory address buses of the refresh. The refresh memory addresses are output to MA0 - MA15 when the DIEN pin is set at high level and A0 - A15 are output to MA0 - MA15 when the DIEN pin is set at low level. – External Clock Operation An external clock enables the MSM6255 to operate when the DIV pin is set at high level. Input the external clock to XT.(Leave XT open.) When the DIV pin is set at low level, the IC enters the crystal oscillation mode. – Address Output Floating MA0 - MA15 and RA0 - RA3 become high impedance when the ADF pin is set at low level. MA0 - MA15 and RA0 - RA3 become normal impedance when the ADF pin is set at high level. – Power Down Function The chip select function becomes enabled for the segment driver by connecting the CEf pin to the ECLK input of the MSM5279. The power down function is valid only in 4-bit parallel output mode. – Refresh Memory Address (MA0 - MA15) Operation In the horizontal direction, MAxx is counted up at the falling edge of CHf. Upper side is addressed while CHf is set at low level and lower side is addressed while CHf is set at high level. MAxx is counted up even if it exceeds the number of horizontal display characters, but this does not affect the display since no data is being transferred at the time. The period in which the data transfer is suspended corresponds to eight characters. When the period passes, one horizontal cycle is completed and the next cycle is commenced. Memory address operation in the graphic mode is shown in Fig. 2 and that in the character mode is shown in Fig. 3. 16/39 ¡ Semiconductor MSM6255 Address configuration of display RAM MSB LSB MA15 MA14 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 HN MA1 MA0 Suspension of data transfer 1 word 0000 0001 004E 004F 0050 0051 009E 009F Upper 1EF0 1EF1 1F3E 1F3F 1F40 1F41 1F8E 1F8F 1F90 1F91 1FDE 1FDF Lower 3E30 3E31 3E7E 3E7F Fig. 2 Memory Address in Graphic Mode (640 x 200) Note: "L" is output for RA0 - RA3. 17/39 ¡ Semiconductor MSM6255 HN (Number of characters in horizontal display line) Raster address Line 1 000 001 010 011 100 101 110 111 000 Suspension of data transfer 1 character 0000 0000 0001 0001 004E 004E 004F 004F 0000 0050 0001 0051 004E 009E 004F 009F Line 2 Upper 111 0050 0051 009E 009F 000 0370 0371 03BE 03BF 111 000 0370 03C0 0371 03C1 03BE 040E 03BF 040F 111 03C0 03C1 040E 040F Line 12 Line 13 Lower 000 0730 0731 077E 077F 111 0730 0731 077E 077F Line 24 Note : Start address is 0000, 80 characters x 24 lines and Vp = 8 Fig. 3 Memory Address in Character Mode (80 characters x 24 lines) 18/39 ¡ Semiconductor MSM6255 – Output Mode Three kinds of modes, 1-bit serial, 2-bit parallel and 4-bit parallel, are available as output modes. Data flows of each mode are shown below. Segment driver Data shift UD0 Upper LCD panel Lower Segment driver UD1 Data shift Fig. 4 1-Bit Serial Data Transfer UD1 UD0 Data shift Upper LCD panel Lower Data shift UD2 UD3 Fig. 5 2-Bit Parallel Data Transfer 19/39 ¡ Semiconductor UD0 - UD3 MSM6255 4 CEφ Upper LCD panel Lower LD0 - LD3 4 Fig. 6 4-bit Parallel Data Transfer Time charts corresponding to data transfers shown in Fig. 4 - Fig. 6 are shown in Fig. 7 - Fig. 9. fs, the dot clock, shown in Figs.7-9, is a signal inside the IC. For more information see "Relation between Reference Clock (fs) and External Clock" on page 601. 20/39 STAN: STAM: ENDN: ENDM: ENDM data STAN STAM STAM+1 STAN+1 data STAM data STAM+1 data D7 6 5 4 3 2 1 D0 D7 6 5 4 3 2 1 D0 STAN data D7 6 5 4 3 2 1 D0 D7 6 5 4 3 2 1 D0 STAN+1 Fig. 7 1-bit Serial Data Transfer First memory address of one horizontal line in the upper side First memory address of one horizontal line in the lower side Last memory address of one horizontal line in the upper side Last memory address of one horizontal line in the lower side D7 6 5 4 3 2 1 D0 ENDN data Suspension of data transfer UD1 ENDM D7 6 5 4 3 2 1 D0 ENDN UD0 CLP MA0 - MA15 CHφ fs ¡ Semiconductor MSM6255 21/39 D5 D7 D6 UD2 UD3 STAN: STAM: ENDN: ENDM: D4 D4 D6 D5 D2 D3 D2 D3 ENDM data ENDN data STAN STAM D6 D7 D6 D7 STAN+1 D2 D3 D2 D3 STAM data D4 D5 STAN data D4 D5 STAM+1 D0 D1 D0 D1 D6 D7 D6 D7 D2 D3 D2 D3 STAM+1 data D4 D5 STAN+1 data D4 D5 Fig. 8 2-bit Parallel Data Transfer First memory address of one horizontal line in the upper side First memory address of one horizontal line in the lower side Last memory address of one horizontal line in the upper side Last memory address of one horizontal line in the lower side D0 D1 D0 D1 Suspension of data transfer UD1 ENDM D7 ENDN UD0 CLP MA0 - MA15 CHφ fs D0 D1 D0 D1 ¡ Semiconductor MSM6255 22/39 D2 D6 D5 D4 UD2 UD1 UD0 D2 D6 D5 D4 UD2 UD1 UD0 ENDM-1 data D0 D1 D3 D7 UD3 ENDN-1 data D0 D1 D3 ENDM D7 ENDN UD3 CLP MA0 - MA15 CHφ fs D4 D5 D6 D7 D0 D1 D2 D3 ENDM data D4 D5 D6 D7 D0 D1 D2 D3 ENDM+1 ENDN data ENDN+1 Fig. 9 4-bit Parallel Data Transfer Suspension of data transfer STAN STAM STAN+1 D0 D1 D2 D3 D0 D1 D2 D3 STAM data D4 D5 D6 D7 STAN data D4 D5 D6 D7 STAM+1 D0 D1 D2 D3 D0 D1 D2 D3 STAM+1 data D4 D5 D6 D7 STAN+1 data D4 D5 D6 D7 ¡ Semiconductor MSM6255 23/39 ¡ Semiconductor MSM6255 – Relation Between Duty and Number of Lines Number of lines is determined by Vr, number of lines in vertical direction(display duty). Number of lines = Vr x 2 Note: In the character display mode, number of lines should not be odd number. – Calculation of Crystal Oscillation Frequency (fosc) Table 3 Calculation Formula of fosc DIV Output mode Calculation formula of fosc q FRP x (HN + 8) x Hp x Vr x 2 9.856 w FRP x (HN + 8) x Vr x 4 2.464 q FRP x (HN + 8) x Hp x Vr 4.928 w FRP x (HN + 8) x Vr x 2 1.232 L H Calculation exmaple (MHz) Note: (1) Table 3 shows a calculation example assuming that FRP = 70 Hz, HN = 80, Hp = 8 and Vr = 100. However, the example of Hp = 4 to 7 in 4-bit parallel is not included. (2) Output mode q : Hp = 4 to 7 in 1-bit serial, 2-bit parallel and 4-bit parallel Output mode w : Hp = 8 in 4-bit parallel – Calculation of Character Clock (CHf) Frequency CHφ = FRP x (HN + 8) x Vr Example: Assuming FRP = 70 Hz, HN = 80 and Vr= 100, CHf = 1.62 (ms) – Calculation of Shift Clock (CLP) Frequency Table 4 Calculation Formula of CLP Output mode Calculation formula of CLP Calculation exmaple (MHz) 1-bit serial RP x (HN + 8) x Hp x Vr 4.928 2-bit parallel FRP x (HN + 8) x Hp x Vr x 1/2 2.464 4-bit parallel FRP x (HN + 8) x Hp x Vr x 1/4 1.232 Note: Table 4 shows a calculation example assuming that FRP = 70 Hz, HN = 80, Hp = 8 and Vr= 100. 24/39 ¡ Semiconductor MSM6255 – Relation Between Reference Clock (fs) and External Clock DIV XT fs Q XT T XT fs (DIV = 1) fs functions as a dot clock in LCDC and the dot counter inside the IC is counted up at the trailing edge of fs. The dot counter operates as a N-ary counter on a basis of HP and generates the character clocks (CHf). (Refer to the time charts Fig. 7 - 9 and Fig. 14.) – Access to the Display RAM In writing/reading the data to/from the display RAM, DIEN should be low level. By setting DIEN signal at low level, the address from the CPU are output from MA0 - MA15, and this enables the access to the display RAM. There are three methods of accessing display RAM from the CPU. (1) Direct access from CPU Display RAM is accessed directly from the CPU, irrespective of the condition of MSM6255 (refresh cycle or not). In this method, the RAM address changes to the CPU address when the display is on the screen. So, frequent access to the RAM causes flickering on the screen. (2) Access while BUSY signal is high BUSY signal indicates the period when the data transfer stops, and BUSY signal is set high when the data transfer stops. The period when BUSY signal is high corresponds to that of seven characters’. If display RAM is accesed during this period (when BUSY is high), the display on the screen does not flicker. Note: This method is effective when the size of screen is small. In the case of big size screen, 640 x 200 dots, 1character needs approx. 1.6ms. So, in this case, the period when BUSY is at high level is 11.2ms, which is impossible to write or read a lot of data. (3) Synchronized access (only for operating the IC by external clock) Refresh cycle and CPU cycle are alternately performed. So, there is not flickering on the screen and there is no need to sense the BUSY signal. When using this method, however, some external circuitry is necessary. The timing chart of this method is described in the Figure 10 below. 25/39 ¡ Semiconductor MSM6255 CHφ TC TL CPU LCDC DIEN CPU LCDC CPU LCDC CPU LCDC fetching the pattern data display RAM OUT N tRAM tUDS M N+1 M+1 tUDH Fig. 10 Basic Timing of Synchronized Access to Display RAM Legend TC TL tRAM tUDS tUDH : : : : : Period when the address bus is occupied by CPU Period when the LCDC fetches the refreshed data Refresh address delay time + memory access time Upper side data set-up time Upper side data hold time When DIEN is high, MA0 - MA15 output address to the upper side when CHf is low and to the lower side when CHf is high. To perform synchronized access method, the timing between DIEN and CHf should be as described in Figure 10. WR VDD M-WR M-RD V-RAM SELECT D PR Q D CL Q PR Q CL Q D PR Q CL Q D PR Q CL Q DIEN READY DATA LATCH Fig. 11 Wait Function Controlling Circuit Display RAM must meet the following condition: TL > tRAM + tUDS In writing data into the display RAM, LCDC should be synchronized so that the write pulse occurs during the period of TC. In reading the pattern data from the CPU, the data of display RAM should be latched first. Figure 11 shows the controlling circuit. 26/39 ¡ Semiconductor MSM6255 – DIEN DIEN has to be generated when the display RAM is accessed by Synchronized access method. (1) When the LCD screen is not split into upper and lower ones If, for example, an LCD panel with a total of 64 dots in vertical direction is displayed at 1/64 duty, either the upper side data or the lower side data becomes unnecessary, and then the CHf signal can be used as a DIEN signal. (2) When the LCD screen is split into upper and lower ones If 4-bit parallel output mode is set and HP=8, the timing diagram of the dot clock and the character clock is as shown below. XT (dot clock) CHφ tCH DIEN signal is generated by XT and CHφ. DIEN signal generating circuit is shown below. DIEN CHφ XT(dot clock) D Q Q When Hp π 8 in the 1-bit serial, 2-bit parallel and 4-bit parallel mode, the relation between XT and CHφ should be referred to Figures 7 and 8. – Scroll◊Paging Scroll◊paging is enabled by setting the display start address to the scroll address register. (1) Memory address of vertical scroll◊paging Figure 2 shows the memory address when the start address is 0000. When the start address is set at 0050, the display will be vertically shifted by +1. By setting the starting address one by one, the screen will scroll vertically. paging will be performed by setting the start address as 3E80. (2) Memory address of horizontal scroll When the starting address is set at 0001 in Figure 2, the display on the screen will be shifted by +1 byte horizontally. The data shown as 004F in Figure 2 corresponds to the memory data in the 2nd line shown as 0050. 27/39 ¡ Semiconductor MSM6255 APPLICATION CIRCUITS Interface With CPU MSM6255 WR RD 8085 WR RD IO/M A1 - A 7 Decoder CS AD0 - AD7 ALE HLDA DB0 - DB7 OC A8 - A15 A0 - A15 MSM6255 WR RD Z80 WR RD IORQ A1 - A 7 Decoder CS D 0 - D7 DB0 - DB7 A0 - A15 A0 - A15 28/39 ¡ Semiconductor MSM6255 MSM6255 8086 WR RD M/IO A1 - A15 Decoder CS DT/R DEN AD0 - AD15 A16 - A19 Transceiver Latch BHE ALE D1 - D7 D0 - D15 A0 - A19 BHE DB0 - DB7 A0 - A15 *Minimum mode MSM6255 6800 φ2 VMA RD/WR RD WR A1 - A15 Decoder CS D0 - D 7 DB0 - DB7 A0 - A15 A0 - A15 29/39 CPU Decoder WR A A0 - A15 Display RAM I/O 40H245 LD0 - LD3 FRP FRMB LIP CEφ CLP UD3 4 bit MSM 6698 Fig. 12 System Configuration in Graphic Mode A0 - A15 MA0 - MA15 MSM6255 RD0 - RD7 DIEN UD0 RD WR ~ B DB0 - DB7 CS MSM 5299C ¡ Semiconductor MSM6255 System Configuration 30/39 CPU Decoder DIEN WR Display RAM Character generator FRMB FRP LIP CEφ CLP UD3 4 bit MSM 6698 Fig. 13 System Configuration in Character Mode A0 - A15 MA0 - MA15 DB0 - DB7 DIEN MSM6255 RA0 - RA3 UD0 RD WR ~ RD0 - DB7 CS MSM 5299C ¡ Semiconductor MSM6255 31/39 fs Memory address N N+1 N+2 STA STA STA STA STA STA STA STA + 1 STA + 2 Start address STA + 3 ¡ Semiconductor Ts LIP TLIP CEφ TCEφ BUSY TBUSY FRP CHφ CH Fig. 14 Timing Chart During Suspension of Shift Clock CH = Ts x Hp 32/39 TLIP = 2CH TCEφ = CH TBUSY = 7CH MSM6255 Condition : 4-bit parallel output mode HP = 5 Memory address • • • • • • • • Suspension of shift clock Line 2 • • • • • • • • • • • • • • •• • • • • • • •• ¡ Semiconductor Line 1 LIP FRP FRMB X driver Line N Line 1 Line 2 Y1 Y driver Y2 – – – 33/39 Fig. 15 Timing Chart of LIP, FRP and FRMB MSM6255 YN ¡ Semiconductor MSM6255 LIP CLP Counter (Inside the IC) 0 1 2 19 0 CEf Carry output of segment driver Valid Fig.16 Timing Chart of CLP and CEf 34/39 RESET SW 6.144 MHz 2.2µF X2 X1 RST-IN 51 kW +5V 50 pF 50 pF 80C85A CLK RSTOUT READY IO/M WR RD ALE 0 1 2 3 4 5 6 D7 8 9 11 12 13 14 A15 READY DIR OE A Q B HCT245 OE D HCT373 Fig. 17-1 HC04 D.BUS-7 D.BUS-6 D.BUS-5 D.BUS-4 D.BUS-3 D.BUS-2 D.BUS-1 D.BUS-0 ADR-7 ADR-6 ADR-5 ADR-4 ADR-3 ADR-2 ADR-1 ADR-0 ADR- 5 ADR-14 ADR-13 ADR-12 ADR-11 ADR-10 ADR- 9 ADR- 8 7 6 5 4 3 2 1 Y0 HC138 G2A G2B G1 A B C PR D Q HC74 CL Q +5V +5V +5V 1Y 2Y 3Y 4Y HC257 RES CLK-OUT CLK G 1A 3B 2A 4B 1B 2B 3A 4A SEL(A) D CL PR +5V Q LCDC-CS M .RD M .WR IO.RD IO.WR VRAMSEL ¡ Semiconductor MSM6255 Figures 17-1, 17-2, and 18 show application circuits. In these examples, the size of LCD module is 640 x 200 dots. 4-bit data transfer is applied and Hp = 8. The synchronized access method is used as a method of access to the display VRAM. 35/39 IO-WR IO-RD LCDC-CS CLK D.BUS-0 D.BUS-1 D..BUS-2 D.BUS-3 D.BUS-4 D BUS-5 D..BUS-6 D BUS-7 CLK-OUT VRAMSEL READY M-RD RES M-WR ADR-15 ADR-14 HC00 HC04 D HC04 HC32 HC32 +5V CL HC74 PR +5V HC08 HC08 Q Q HC32 HC32 HC86 HC08 +5V D HC32 CL HC74 RP Q Q D CL HC74 RP Q Q D HC08 +5V CL HC74 RP OE Q HCT374 G1 G2 A HCT244 Q Q D Y Fig. 17-2 HC04 1 2 3 4 5 6 7 D0 OE OE HC04 WE MSM5165 WE CE1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 CE1 WR RD CS XT DIEN DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 RES A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 ADF DIV CIP CEφ LIP FRMB FRP LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 CHφ ADR-0 ADR-1 ADR-2 ADR-3 ADR-4 ADR-5 ADR-6 ADR-7 ADR-8 ADR-9 ADR-10 ADR-11 ADR-12 ADR-13 ADR-14 ADR-15 +5V LCD ¡ Semiconductor MSM6255 MSM6255 MSM5165 36/39 RES A0 - A15 A0 - A12 5V A0 - A12 LS125 A B A0 - A12 A11 - A15 “H” = RD LS13B 5V 5V A0 - A12 WE MA13 - MA Fig. 18 Y 1G 2G A LS244 CE1 OE CE2 I/O1 - I/O8 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 LS13B G1 G2A G2B A~B CE1 CE2 OE A0 - A12 WE I/O1 - I/O8 CE1 5V A B OE CE2 LS245 DIR I/O1 - I/O8 WE G Y0 Y5 Y7 G1 G2A G2B A~B OE DO0 ~ DO7 CE 2764 for software D Q CK LS74 DB1 5V A0 - A7 OE A0 - A12 WE CE1 OE CE2 I/O1 - I/O8 CE A11 A8 DO0 - DO7 A12 ~ Z80 RD WR MREQ DB0 - DB7 → 5V 4 MA12 - MA15 MA0 - MA12 MAM5165RS (8K x 8 bit) for CGROM RES A0 - A15 ADF MA0 - MA15 MSM6255 RA0 - RA3 RD0 - RD7 DIEN RD WR BUSY DB0 - DB7 CS DIV XT XT 30pF 2.5 MHz ¡ Semiconductor MSM6255 37/39 ¡ Semiconductor MSM6255 PACKAGE DIMENSIONS (Unit : mm) QFP80-P-1420-0.80-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.27 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 38/39 ¡ Semiconductor MSM6255 (Unit : mm) QFP80-P-1420-0.80-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Epoxy resin 42 alloy Solder plating 5 mm or more Package weight (g) 1.27 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 39/39