ON NCV898032D1R2G 2 mhz automotive grade non-synchronous boost controller Datasheet

NCV898032
2 MHz Automotive Grade
Non-Synchronous Boost
Controller
The NCV898032 is an adjustable output non−synchronous boost
controller which drives an external N−channel MOSFET. The device
uses peak current mode control with internal slope compensation. The
IC incorporates an internal regulator that supplies charge to the gate
driver.
Protection features include internally−set soft−start, undervoltage
lockout, cycle−by−cycle current limiting and thermal shutdown.
Additional features include low quiescent current sleep mode and
microprocessor compatible input pin.
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MARKING
DIAGRAM
8
SOIC−8
D SUFFIX
CASE 751
8
1
1
Features
•
•
•
•
•
•
•
•
•
•
•
•
8980xx
ALYW
G
Peak Current Mode Control with Internal Slope Compensation
0.2 V $3% Reference Voltage for Constant Current Loads
2 MHz Fixed Frequency Operation
Wide Input Voltage Range of 3.2 V to 40 V, 45 V Load Dump
Input Undervoltage Lockout (UVLO)
Internal Soft−Start
Low Quiescent Current in Sleep Mode (< 10 mA Typical)
Cycle−by−Cycle Current Limit Protection
Hiccup−Mode Overcurrent Protection (OCP)
Thermal Shutdown (TSD)
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
8980xx = Specific Device Code
xx = 32
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
PIN CONNECTIONS
EN 1
8 VFB
ISNS 2
7 VC
GND 3
6 VIN
GDRV 4
5 VDRV
(Top View)
Typical Applications
• LED Lighting
• Headlamps
• Backlighting
ORDERING INFORMATION
Device
Package
Shipping†
NCV898032D1R2G
SOIC−8
(Pb−Free)
2500 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2017
August, 2017 − Rev. 1
1
Publication Order Number:
NCV89803/D
NCV898032
6
TEMP
VDRV
FAULT
LOGIC
SC
VC
Cg
CDRV
VDRV
CLK
OSC
1
DRIVE
LOGIC
4
PWM
EN
EN
5
Vg
VIN
2
CL
7
CSA
3
+
RC
8
Gm
CC
L
NRVBS260T3G
Vo
Q
GDRV
D2
NVTFS5C680NLWFTAG
Co
ISNS
GND
RSNS
Dn
VFB
RF1
SS
Vref
Figure 1. Simplified Block Diagram and Application Schematic
PACKAGE PIN DESCRIPTIONS
Pin No.
Pin
Symbol
1
EN
Enable input. The part is disabled into sleep mode when this pin is brought low for longer than the enable
time−out period.
2
ISNS
Current sense input. Connect this pin to the source of the external N−MOSFET, through a current−sense
resistor to ground to sense the switching current for regulation and current limiting.
3
GND
Ground reference.
4
GDRV
Gate driver output. Connect to gate of the external N−MOSFET. A series resistance can be added from
GDRV to the gate to tailor EMC performance in addition to the internal.
5
VDRV
Driving voltage. Internally−regulated supply for driving the external N−MOSFET, sourced from VIN. Bypass
with a 1.0 mF ceramic capacitor to ground.
6
VIN
Input voltage. If bootstrapping operation is desired, connect a diode from the input supply to VIN, in addition to a diode from the output voltage to VDRV and/or VIN.
7
VC
Output of the voltage error amplifier. An external compensator network from VC to GND is used to stabilize
the converter.
8
VFB
Output voltage feedback. A resistor from the output voltage to VFB with another resistor from VFB to GND
creates a voltage divider for regulation and programming of the output voltage.
Function
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NCV898032
ABSOLUTE MAXIMUM RATINGS (Voltages are with respect to GND, unless otherwise indicated)
Rating
Value
Unit
−0.3 to 40
V
Peak Transient Voltage (Load Dump on VIN)
45
V
Dc Supply Voltage (VDRV, GDRV)
12
V
−0.3 to 6
V
−0.3 to 3.6
V
Dc Voltage (EN)
−0.3 to 6
V
Dc Voltage Stress (VIN − VDRV)*
−0.7 to 40
V
Operating Junction Temperature
−40 to 150
°C
Storage Temperature Range
−65 to 150
°C
Peak Reflow Soldering Temperature: Pb−Free, 60 to 150 seconds at 217°C
265 peak
°C
Dc Supply Voltage (VIN)
Peak Transient Voltage (VFB)
Dc Voltage (VC, VFB, ISNS)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
*An external diode from the input to the VIN pin is required if bootstrapping VDRV and VIN off of the output voltage.
PACKAGE CAPABILITIES
Characteristic
ESD Capability (All Pins)
Human Body Model
Machine Model
Moisture Sensitivity Level
1. 1
Unit
w2.0
w200
KV
V
1
Package Thermal Resistance
in2,
Value
°C/W
100
Junction−to−Ambient, RqJA (Note 1)
1 oz copper area used for heatsinking.
Ordering Options
The NCV898032 features several variants to better fit a
multitude of applications. The table below shows the typical
values of parameters for the parts that are currently
available.
TYPICAL VALUES
YY
Dmax
SCE
tss
Sa
Vcl
Isrc
Isink
VDRV
NCV898032
88%
No
800 ms
204 mV/ms
200 mV
800 mA
600 mA
6.3 V
DEFINITIONS
Symbol
Dmax
Characteristic
Symbol
Characteristic
Maximum duty cycle
Sa
Slope compensating ramp
Vcl
Isink
Gate drive sinking current
VDRV
Current limit trip voltage
Drive voltage
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3
Symbol
Characteristic
tss
Soft−start time
Isrc
Gate drive sourcing current
SCE
Short Circuit Enable
NCV898032
ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.2 V < VIN < 40 V, unless otherwise specified) Min/Max values are
guaranteed by test, design or statistical correlation.
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
mA
GENERAL
Quiescent Current, Sleep Mode
Iq,sleep
VIN = 13.2 V, EN = 0, TJ = 25°C
−
2.0
−
Quiescent Current, Sleep Mode
Iq,sleep
VIN = 13.2 V, EN = 0, −40°C < TJ < 125°C
−
2.0
6.0
mA
Quiescent Current, No switching
Iq,off
Into VIN pin, EN = 1, No switching
−
1.9
2.9
mA
Quiescent Current, Switching,
normal operation
Iq,on
Into VIN pin, EN = 1, Switching
−
7.5
10
mA
30
65
90
ns
OSCILLATOR
Minimum pulse width
ton,min
Maximum duty cycle
Dmax
YY = 32
85
87.5
91
%
Switching frequency
fs
YY = 32
1.8
2.0
2.2
MHz
Soft−start time
tss
From start of switching with VFB = 0 until
reference voltage = VREF
YY = 32
650
800
950
From EN → 1 until start of switching with
VFB = 0 with floating VC pin
80
100
280
Sa
YY = 32
179
204
240
mV/ms
EN pull−down current
IEN
VEN = 5 V
−
5.0
10
mA
EN input high voltage
Vs,ih
VIN > VUVLO
2.0
−
5.0
V
EN input low voltage
Vs,il
0
−
800
mV
EN time−out ratio
%ten
From EN falling edge, to oscillator control
(EN high) or shutdown (EN low), Percent of
typical switching frequency
−
−
350
%
Acsa
Input−to−output gain at dc, ISNS v 1 V
0.9
1.0
1.1
V/V
2.5
−
−
MHz
−
30
50
Soft−start delay
Slope compensating ramp
tss,dly
ms
ms
ENABLE
CURRENT SENSE AMPLIFIER
Low−frequency gain
Bandwidth
BWcsa
Gain of Acsa − 3 dB
ISNS input bias current
Isns,bias
Out of ISNS pin
Current limit threshold voltage
Vcl
Voltage on ISNS pin
YY = 32
mA
mV
180
200
220
−
80
125
ns
125
150
175
%
−
80
125
ns
0.80
1.20
1.63
mS
2.0
−
−
MW
−
0.5
2.0
mA
Vref
0.194
0.200
0.206
V
VEA maximum output voltage
Vc,max
2.5
−
−
V
VEA minimum output voltage
Vc,min
−
−
0.3
V
VEA sourcing current
Isrc,vea
VEA output current, Vc = 2.0 V
80
100
−
mA
VEA sinking current
Isnk,vea
VEA output current, Vc = 0.7 V
80
100
−
mA
Current limit,
Response time
tcl
Overcurrent protection,
Threshold voltage
%Vocp
Overcurrent protection,
Response Time
tocp
CL tripped until GDRV falling edge,
VISNS = Vcl(typ) + 60 mV
Percent of Vcl
From overcurrent event, Until switching
stops, VISNS = VOCP + 40 mV
VOLTAGE ERROR OPERATIONAL TRANSCONDUCTANCE AMPLIFIER
Transconductance
gm,vea
VEA output resistance
Ro,vea
VFB input bias current
Ivfb,bias
Reference voltage
VFB – Vref = ± 20 mV
Current out of VFB pin
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NCV898032
ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.2 V < VIN < 40 V, unless otherwise specified) Min/Max values are
guaranteed by test, design or statistical correlation.
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
VDRV ≥ 6 V, VDRV − VGDRV = 2 V
YY = 32
600
800
−
VGDRV ≥ 2 V
YY = 32
500
600
−
VIN − VDRV, IvDRV = 25 mA
−
0.3
0.6
V
VIN − VDRV = 1 V
35
45
−
mA
−
−
0.7
V
6.0
6.3
6.6
−
15
−
kW
GATE DRIVER
Sourcing current
Sinking current
Driving voltage dropout
Isrc
Isink
Vdrv,do
mA
Driving voltage source current
Idrv
Backdrive diode voltage drop
Vd,bd
VDRV − VIN, Id,bd = 5 mA
Driving voltage
VDRV
VIN = 12 V, IVDRV = 0.1 − 25 mA
YY = 32
Pull−down resistance
mA
Rpd
V
UVLO
Undervoltage lock−out,
Threshold voltage
Vuvlo
VIN falling
2.95
3.05
3.15
V
Undervoltage lock−out,
Hysteresis
Vuvlo,hys
VIN rising
50
150
250
mV
Thermal shutdown threshold
Tsd
TJ rising
160
170
180
°C
Thermal shutdown hysteresis
Tsd,hys
TJ falling
10
15
20
°C
Thermal shutdown delay
tsd,dly
From TJ > Tsd to stop switching
−
−
100
ns
THERMAL SHUTDOWN
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NCV898032
TYPICAL PERFORMANCE CHARACTERISTICS
6
7
Iq,sleep, SLEEP CURRENT (mA)
Iq,sleep, SLEEP CURRENT (mA)
TJ = 25°C
6
5
4
3
2
1
0
0
10
20
30
VIN, INPUT VOLTAGE (V)
VIN = 13.2 V
5
4
3
2
1
0
−50
40
Figure 2. Sleep Current vs. Input Voltage
64.5
ton,min MINIMUM ON TIME (ns)
Iq,on, QUIESCENTCURRENT (mA)
200
Figure 3. Sleep Current vs. Temperature
7.8
7.7
7.6
7.5
7.4
7.3
7.2
64.0
63.5
63.0
62.5
62.0
VIN = 13.2 V
7.1
−50
0
50
100
150
TJ, JUNCTION TEMPERATURE (°C)
61.5
−50
200
0
50
100
150
200
TJ, JUNCTION TEMPERATURE (°C)
Figure 4. Quiescent Current vs. Temperature
Figure 5. Minimum On Time vs. Temperature
202.2
1.010
Vref, REFERENCE VOLTAGE (V)
NORMALIZED CURRENT LIMIT (25°C)
0
50
100
150
TJ, JUNCTION TEMPERATURE (°C)
1.005
202
201.8
1.000
201.6
0.995
0.990
−40
201.4
10
60
110
TJ, JUNCTION TEMPERATURE (°C)
160
201.2
−40
10
60
110
TJ, JUNCTION TEMPERATURE (°C)
Figure 6. Normalized Current Limit vs.
Temperature
Figure 7. Reference Voltage vs. Temperature
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160
NCV898032
TYPICAL PERFORMANCE CHARACTERISTICS
8.0
TJ = 25°C
6
Ienable, PULLDOWN CURRENT (mA)
Ienable, PULLDOWN CURRENT (mA)
7
5
4
3
2
1
0
0
1
2
3
4
Venable, VOLTAGE (V)
5
7.5
7.0
6.5
6.0
5.5
5.0
−40
6
10
60
110
TJ, JUNCTION TEMPERATURE (°C)
Figure 8. Enable Pulldown Current vs. Voltage
Figure 9. Enable Pulldown Current vs.
Temperature
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160
NCV898032
THEORY OF OPERATION
Current Mode Control
If the voltage across the current sense resistor exceeds the
over current threshold voltage the part enters over current
hiccup mode. The part will remain off for the hiccup time
and then go through the soft−start procedure.
The NCV898032 incorporates a current mode control
scheme, in which the PWM ramp signal is derived from the
power switch current. This ramp signal is compared to the
output of the error amplifier to control the on−time of the
power switch. The oscillator is used as a fixed−frequency
clock to ensure a constant operational frequency. The
resulting control scheme features several advantages over
conventional voltage mode control. First, derived directly
from the inductor, the ramp signal responds immediately to
line voltage changes. This eliminates the delay caused by the
output filter and error amplifier, which is commonly found
in voltage mode controllers. The second benefit comes from
inherent pulse−by−pulse current limiting by merely
clamping the peak switching current. Finally, since current
mode commands an output current rather than voltage, the
filter offers only a single pole to the feedback loop. This
allows for a simpler compensation.
The NCV898032 also includes a slope compensation
scheme in which a fixed ramp generated by the oscillator is
added to the current ramp. A proper slope rate is provided to
improve circuit stability without sacrificing the advantages
of current mode control.
EN
This pin has two modes. When a dc logic high
(CMOS/TTL compatible) voltage is applied to this pin the
NCV898032 operates at the programmed frequency. When
a dc logic low voltage is applied to this pin the NCV898032
enters a low quiescent current sleep mode. If an Enable
command is received during normal operation, the
minimum duration of the Enable low−state must be greater
than 7 clock cycles. The NCV898032 requires 2 clock cycles
after the falling edge of the Enable signal to stop switching.
UVLO
Input Undervoltage Lockout (UVLO) is provided to
ensure that unexpected behavior does not occur when VIN
is too low to support the internal rails and power the
controller. The IC will start up when enabled and VIN
surpasses the UVLO threshold plus the UVLO hysteresis
and will shut down when VIN drops below the UVLO
threshold or the part is disabled.
It is highly recommended to keep EN pin voltage at a
lower amplitude than the VIN pin voltage during a UVLO
event.
Current Limit
The NCV898032 features a peak current−mode current
limit protection. When the current sense amplifier detects a
voltage above the peak current limit between ISNS and
GND after the current limit leading edge blanking time, the
peak current limit causes the power switch to turn off for the
remainder of the cycle. Set the current limit with a resistor
from ISNS to GND, with R = VCL / Ilimit.
Internal Soft−Start
To insure moderate inrush current and reduce output
overshoot, the NCV898032 features a soft start which charges
a capacitor with a fixed current to ramp up the reference
voltage.
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NCV898032
APPLICATION INFORMATION
Vg
L
D1
Oscillator
VO
S
GDRV
Q
D2
Q
Gate
Driver
R
PWM
CO
ISNS
Comparator
RSNS
CSA
Slope
Compensation
Dn
VFB
Gm
RF1
VREF
NCV898032
Compensation
Figure 10. Current Mode Control Schematic
Boost LED Design Methodology
M max +
This section details an overview of the component
selection process for the NCV898032 in discontinuous
conduction mode (DCM) Boost converter operation with a
high brightness LED (100−150 mA typical) string as a load.
LED current is used for the feedback signal. It is intended to
assist with the design process but does not remove all
engineering design work. Many of the equations make use
of the small ripple approximation. This process entails the
following steps:
1. Define Operational Parameters
2. Select Current Sense Resistor
3. Select Output Inductor
4. Select Output Capacitors
5. Select Input Capacitors
6. Select Feedback Resistors
7. Select Compensator Components
8. Select MOSFET(s)
9. Select Diode
R out +
D max +
Ǹ
Ǹ
ƪ
ƫ
2
Lf s
ǒ2M min * 1Ǔ * 1
2R out
Lf s
ƪ(2Mmax * 1)2 * 1ƫ
2R out
2V out 2
*D,
V inR outI L,peak
Where: (D + d) < 1 for DCM operation IL.
Both duty cycles will actually be slightly higher due to
power loss in the conversion. The exact duty cycles depend
on conduction and switching losses. If the maximum input
voltage is higher than the output voltage, the minimum duty
cycle will be a complex value. This is because a Boost
converter cannot have an output voltage lower than the input
voltage. In situations where the input voltage is higher than
the output, the output will follow the input (minus the diode
drop of the Boost diode) and the converter will not attempt
to switch.
If the inductor value is too large, continuous conduction
mode (CCM) operation will occur and a right-half-plane
(RHP) zero appears which can result in operation instability.
If the calculated Dmax is higher than the Dmax of the
NCV898032, the conversion will not be possible. It is
important for a Boost converter to have a restricted Dmax,
because while the ideal conversion ration of a Boost
converter goes up to infinity as D approaches 1, a real
converter’s conversion ratio starts to decrease as losses
1. Define Operational Parameters
Before beginning the design, define the operating
parameters of the application. These include:
VIN(min): minimum input voltage [V]
VIN(max): maximum input voltage [V]
VOUT: output voltage [V]
ILED: LED current [A]
ICL: desired typical cycle-by-cycle current limit [A]
Vref: NCV898032 feedback reference voltage = 0.2 V
IL: inductor current [A]
From this the ideal minimum and maximum duty cycles
can be calculated as follows:
M min +
V out
I LED
D min +
d+
V out
V in(min)
V out
V in(max)
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NCV898032
overtake the increased power transfer. If the converter is in
this range it will not be able to maintain output regulation.
If the following equation is not satisfied, the device will
skip pulses at high VIN:
V OUT(ripple) +
The capacitors must withstand an RMS ripple current as
follows:
D min
w t on(min)
fs
I Cout(RMS) +
Where: fs: switching frequency [Hz]
ton(min): minimum on time [s]
Current sensing for peak current mode control and current
limit relies on the MOSFET current signal, which is
measured with a ground referenced amplifier. The easiest
method of generating this signal is to use a current sense
resistor between the MOSFET source and ground. The sense
resistor should be selected as follows:
I Cin(RMS) +
Ǔ
D(M max) ) d (M max)
I L,pk 2 * I L,avg 2
3
V ref
I LED
Current Mode control method employed by the
NCV898032 allows the use of a simple Type II
compensation to optimize the dynamic response according
to system requirements. A transconductance amplifier is
used, so compensation components must be connected
between the compensation pin and ground.
8. Select MOSFET(s)
In order to ensure the gate drive voltage does not drop out,
the selected MOSFET must not violate the following
inequality:
ǒ Ǔ
Vout
ILED
Q g(total) v
2f sV out 2
I drv
fs
Where: Qg(total): Total Gate Charge of MOSFET(s) [C]
Idrv: Drive voltage current [A]
fs: Switching Frequency [Hz]
The maximum RMS Current can be calculated as follows:
V OUTI OUT(max)
V IN(min)
The peak inductor current can be calculated as follows:
I L,peak +
Ǔ
* I L,pkI LED
7. Select Compensator Components
The maximum average inductor current can be calculated
as follows:
I L,avg +
3
The feedback resistor provides LED current sensing for
the feedback signal. It may be calculated as follows:
The Boost inductor controls the current ripple that occurs
over a switching period. A discontinuous current ripple will
result in superior transient response and lower switching
noise at the expense of higher transistor conduction losses
and operating ripple current requirements. A low current
ripple will result in CCM operation having a slower response
current slew rate in case of load steps (e.g. introducing an
LED series dimming circuit). A good starting point is to
select components for DCM operation at Vin(min), but
operation should be verified empirically. Calculate the
maximum inductor value as follows:
max
Ǹǒ
R F1 +
2
I L,pk 2
6. Select Feedback Resistors
3. Select the Boost Inductor
in(min)
ǒ
The input capacitor reduces voltage ripple on the input to
the module associated with the ac component of the input
current.
Where: RSNS: sense resistor [W]
VCL: current limit threshold voltage [V]
ICL: desired current limit [A]
L max +
I LED 2 ) d(M max)
5. Select Input Capacitors
V CL
I CL
ǒ1 * M1 ǓV
Ǹ
A 1−2.2 mF ceramic capacitor is usually sufficient for high
brightness LED applications for fs = 2 MHz.
2. Select Current Sense Resistor
R SNS +
I LEDǒ1 * d (M max)Ǔ
f sC OUT
I Q(max) + I L,peak
V IN(min)D max
Lf s
ǸD(M3
max)
The maximum voltage across the MOSFET will be the
maximum output voltage, which is the higher of the
maximum input voltage and the regulated output voltage:
Where: IL,peak: Peak inductor current value [A]
4. Select Output Capacitor
V Q(max) + V OUT(max)
The output capacitor smoothes the output voltage and
reduces the overshoot and undershoot associated with line
transients. The steady state output ripple associated with the
output capacitors can be calculated as follows:
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NCV898032
9. Select Diode
Low Voltage Operation
The output diode rectifies the output current. The average
current through diode will be equal to the output current:
If the input voltage drops below the UVLO or MOSFET
threshold voltage, another voltage may be used to power the
device. Simply connect the voltage you would like to boost
to the inductor and connect the stable voltage to the VIN pin
of the device. In Boost configuration, the output of the
converter can be used to power the device. In some cases it
may be desirable to connect 2 sources to VIN pin, which can
be accomplished simply by connecting each of the sources
through a diode to the VIN pin.
I D(avg) + I OUT(max)
Additionally, the diode must block voltage equal to the
higher of the output voltage or the maximum input voltage:
V D(max) + V OUT
The maximum power dissipation in the diode can be
calculated as follows:
P D + V f (max)I OUT(max)
Where: Pd: Power dissipation in the diode [W]
Vf(max): Maximum forward voltage of the diode
[V]
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NCV898032
SEPIC TOPOLOGY APPLICATION INFORMATION
VIN
L1
Oscillator
S Q
PWM Comparator
GDRV
Gate
Drive
R
+
CCPL
L2
Co
ISNS
CSA
RL
VFB
Voltage Error
VEA
NCV898032
Compensation
Figure 11. SEPIC Current Mode Schematic
SEPIC Design Methodology
From this the ideal minimum and maximum duty cycles
can be calculated as follows:
This section details an overview of the component
selection process for the NCV898032 in continuous
conduction mode SEPIC. It is intended to assist with the
design process but does not remove all engineering design
work. Many of the equations make heavy use of the small
ripple approximation. This process entails the following
steps:
1. Define Operational Parameters
2. Select Current Sense Resistor
3. Select SEPIC Inductors
4. Select Coupling Capacitor
5. Select Output Capacitors
6. Select Input Capacitors
7. Select Feedback Resistors
8. Select Compensator Components
9. Select MOSFET(s)
10. Select Diode
D min +
V OUT
V IN(max) ) V OUT
D max +
V OUT
V IN(min) ) V OUT
Both duty cycles will actually be higher due to power loss
in the conversion. The exact duty cycles will depend on
conduction and switching losses.
If the calculated DWC (worst case) is higher than the Dmax
limit of the NCV898032, the conversion will not be
possible. It is important for a SEPIC converter to have a
restricted Dmax, because while the ideal conversion ratio of
a SEPIC converter goes up to infinity as D approaches 1, a
real converter’s conversion ratio starts to decrease as losses
overtake the increased power transfer. If the converter is in
this range it will not be able to regulate properly.
If the following equation is not satisfied, the device will
skip pulses at high VIN:
1. Define Operational Parameters
Before beginning the design, define the operating
parameters of the application. These include:
VIN(min): minimum input voltage [V]
VIN(max): maximum input voltage [V]
VOUT: output voltage [V]
IOUT(max): maximum output current [A]
ICL: desired typical cycle−by−cycle current limit [A]
D min
w t on(min)
fs
Where: fs: switching frequency [Hz]
ton(min): minimum on time [s]
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12
NCV898032
2. Select Current Sense Resistor
Current mode control helps resolve some of the resonant
frequencies that create issues in voltage mode SEPIC
converter designs, but some resonance issues may occur. A
resonant frequency exists at
Current sensing for peak current mode control and current
limit relies on the MOSFET current signal, which is
measured with a ground referenced amplifier. Note that the
ICL equals the sum of the currents from both inductors. The
easiest method of generating this signal is to use a current
sense resistor from the source of the MOSFET to device
ground. The sense resistor should be selected as follows:
RS +
f resonance +
It may become necessary to place an RC damping network
in parallel with the coupling capacitor if the resonance is
within ~1 decade of the closed−loop crossover frequency.
The capacitance of the damping capacitor should be ~5
times that of the coupling capacitor. The optimal damping
resistance (including the ESR of the damping capacitor) is
calculated as
V CL
I CL
Where: RS: sense resistor [W]
VCL: current limit threshold voltage [V]
ICL: desire current limit [A]
R damping +
3. Select SEPIC Inductors
The output inductor controls the current ripple that occurs
over a switching period. A high current ripple will result in
excessive power loss and ripple current requirements. A low
current ripple will result in a poor control signal and a slow
current slew rate in case of load steps. A good starting point
for peak to peak ripple is around 20−40% of the inductor
current at the maximum load at the worst case VIN, but
operation should be verified empirically. The worst case VIN
is the minimum input voltage. After choosing a peak current
ripple value, calculate the inductor value as follows:
L+
V OUT(ripple) +
I OUT(max)D WC
C OUT f s
)
ǒ
I OUT(max)
1 * D WC
)
Ǔ
D WCV IN(min)
2 f sL 2
R esr
The capacitors need to survive an RMS ripple current as
follows:
Ǹ
Where: VIN(WC): VIN value as close as possible to half of
VOUT [V]
DWC: duty cycle at VIN(WC)
DIL,max: maximum peak to peak ripple [A]
The maximum average inductor current can be calculated as
follows:
I Cout(RMS) +
ǒ
I OUT(max) 2 D WC ) I 2a )
Ǔ
I 2r
* I aI r DȀ WC
3
where
I a + I L1_peak ) I L2_peak * I out
I r + DI L1 ) DI L2
V OUT I OUT(max)
V IN(min)h
The use of parallel ceramic bypass capacitors is strongly
encouraged to help with the transient response.
The Peak Inductor current can be calculated as follows:
DI L1
2
I L2,peak + I OUT(max) )
L1 ) L2
C coupling
The output capacitors smooth the output voltage and
reduce the overshoot and undershoot associated with line
transients. The steady state output ripple associated with the
output capacitors can be calculated as follows:
DI L,max f s
I L1,peak + I L1,avg )
Ǹ
5. Select Output Capacitors
V IN(WC) D WC
I L,AVG +
1
2p Ǹ(L1 ) L2)C coupling
6. Select Input Capacitors
The input capacitor reduces voltage ripple on the input to
the module associated with the ac component of the input
current.
DI L2
2
Where (if L1 = L2): DIL1 = DIL2
I Cin(RMS) +
DI L1
Ǹ12
4. Select Coupling Capacitor
Coupling capacitor RMS current is significant. A low
ESR ceramic capacitor is required as a coupling capacitor.
Selecting a capacitor value too low will result in high
capacitor ripple voltage which will distort ripple current and
diminish input line regulation capability. Budgeting 2−5%
coupling capacitor ripple voltage is a reasonable guideline.
DV coupling +
7. Select Feedback Resistors
The feedback resistors form a resistor divider from the
output of the converter to ground, with a tap to the feedback
pin. During regulation, the divided voltage will equal Vref.
The lower feedback resistor can be chosen, and the upper
feedback resistor value is calculated as follows:
I out D WC
C coupling f s
R upper + R lower
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13
ǒV out * V refǓ
V ref
NCV898032
9. Select MOSFET(s)
The total feedback resistance (Rupper + Rlower) should be
in the range of 1 kW – 100 kW.
In order to ensure the gate drive voltage does not drop out
the MOSFET(s) chosen must not violate the following
inequality:
8. Select Compensator Components
Current Mode control method employed by the
NCV898032 allows the use of a simple, Type II
compensation to optimize the dynamic response according
to system requirements.
Q g(total) v
Where: Qg(total): Total Gate Charge of MOSFET(s) [C]
Idrv: Drive voltage current [A]
fs: Switching Frequency [Hz]
The maximum RMS Current can be calculated as follows:
I D(max) +
Ǹ ǒ
D WC
I Q(peak) 2 )
ǒDI L1 ) DI L2Ǔ
3
I drv
fs
2
* I Q(peak)ǒDI L1 ) DI L2Ǔ
Ǔ
10. Select Diode
where
I Q(peak) + I L1_peak ) I L2_peak
The output diode rectifies the output current. The average
current through diode will be equal to the output current:
The maximum voltage across the MOSFET will be the
maximum output voltage, which is the higher of the
maximum input voltage and the regulated output voltaged:
I D(avg) + I OUT(max)
Additionally, the diode must block voltage equal to the
higher of the output voltage and the maximum input voltage:
V Q(max) + V OUT(max) ) V IN(max)
V D(max) + V OUT(max) ) V IN(max)
The maximum power dissipation in the diode can be
calculated as follows:
P D + V f (max) I OUT(max)
Where: Pd: Power dissipation in the diode [W]
Vf(max): Maximum forward voltage of the diode [V]
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14
NCV898032
BOOST TOPOLOGY APPLICATION INFORMATION
VIN
Oscillator
PWM Comparator
GDRV
S Q
L
VOUT
Gate
Drive
R
CO
ISNS
+
RL
CSA
Slope
Compensation
VFB
Voltage Error
VEA
NCV898032
Compensation
Figure 12. Boost Current Mode Schematic
Boost Converter Design Methodology
D min + 1 *
This section details an overview of the component
selection process for the NCV898032 in continuous
conduction mode boost. It is intended to assist with the
design process but does not remove all engineering design
work. Many of the equations make heavy use of the small
ripple approximation. This process entails the following
steps:
1. Define Operational Parameters
2. Select Current Sense Resistor
3. Select Output Inductor
4. Select Output Capacitors
5. Select Input Capacitors
6. Select Feedback Resistors
7. Select Compensator Components
8. Select MOSFET(s)
9. Select Diode
10. Determine Feedback Loop Compensation Network
D WC + 1 *
V IN(max)
V OUT
V IN(WC)
V OUT
Both duty cycles will actually be higher due to power loss
in the conversion. The exact duty cycles will depend on
conduction and switching losses. If the maximum input
voltage is higher than the output voltage, the minimum duty
cycle will be negative. This is because a boost converter
cannot have an output lower than the input. In situations
where the input is higher than the output, the output will
follow the input, minus the diode drop of the output diode
and the converter will not attempt to switch.
If the calculated DWC is higher than the Dmax limit of the
NCV898032, the conversion will not be possible. It is
important for a boost converter to have a restricted Dmax,
because while the ideal conversion ratio of a boost converter
goes up to infinity as D approaches 1, a real converter’s
conversion ratio starts to decrease as losses overtake the
increased power transfer. If the converter is in this range it
will not be able to regulate properly.
If the following equation is not satisfied, the device will
skip pulses at high VIN:
1. Define Operational Parameters
Before beginning the design, define the operating
parameters of the application. These include:
VIN(min): minimum input voltage [V]
VIN(max): maximum input voltage [V]
VOUT: output voltage [V]
IOUT(max): maximum output current [A]
ICL: desired typical cycle−by−cycle current limit [A]
From this the ideal minimum and maximum duty cycles can
be calculated as follows:
D min
w t on(min)
fs
Where: fs: switching frequency [Hz]
ton(min): minimum on time [s]
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15
NCV898032
2. Select Current Sense Resistor
Current sensing for peak current mode control and current
limit relies on the MOSFET current signal, which is
measured with a ground referenced amplifier. The easiest
method of generating this signal is to use a current sense
resistor from the source of the MOSFET to device ground.
The sense resistor should be selected as follows:
RS +
I Cout(RMS) + I OUT
Ǹ
D WC
D
) WC
12
DȀ WC
ǒ
DȀ WC
L
R
OUT
T
SW
Ǔ
2
The use of parallel ceramic bypass capacitors is strongly
encouraged to help with the transient response.
5. Select Input Capacitors
V CL
I CL
The input capacitor reduces voltage ripple on the input to
the module associated with the ac component of the input
current.
Where: RS: sense resistor [W]
VCL: current limit threshold voltage [V]
ICL: desire current limit [A]
I Cin(RMS) +
V IN(WC) 2 D WC
Lf sV OUT2 Ǹ3
3. Select Output Inductor
The output inductor controls the current ripple that occurs
over a switching period. A high current ripple will result in
excessive power loss and ripple current requirements. A low
current ripple will result in a poor control signal and a slow
current slew rate in case of load steps. A good starting point
for peak to peak ripple is around 20−40% of the inductor
current at the maximum load at the worst case VIN, but
operation should be verified empirically. The worst case VIN
is half of VOUT, or whatever VIN is closest to half of VIN.
After choosing a peak current ripple value, calculate the
inductor value as follows:
L+
6. Select Feedback Resistors
The feedback resistors form a resistor divider from the
output of the converter to ground, with a tap to the feedback
pin. During regulation, the divided voltage will equal Vref.
The lower feedback resistor can be chosen, and the upper
feedback resistor value is calculated as follows:
R upper + R lower
V IN(WC) 2 D WC
7. Select Compensator Components
DI L,max f sV OUT
Current Mode control method employed by the
NCV898032 allows the use of a simple, Type II
compensation to optimize the dynamic response according
to system requirements.
I L,avg +
8. Select MOSFET(s)
In order to ensure the gate drive voltage does not drop out
the MOSFET(s) chosen must not violate the following
inequality:
V OUTI OUT(max)
Q g(total) v
V IN(min)
The Peak Inductor current can be calculated as follows:
I L,peak + I L,avg )
V IN(min) D WC
Lf sV OUT
Where: IL,peak: Peak inductor current value [A]
I Q(max) + I out
4. Select Output Capacitors
The output capacitors smooth the output voltage and
reduce the overshoot and undershoot associated with line
transients. The steady state output ripple associated with the
output capacitors can be calculated as follows:
fC OUT
)
ǒ
I OUT(max)
1*D
I drv
fs
Where: Qg(total): Total Gate Charge of MOSFET(s) [C]
Idrv: Drive voltage current [A]
fs: Switching Frequency [Hz]
The maximum RMS Current can be calculated as follows:
2
DI OUT(max)
V ref
The total feedback resistance (Rupper + Rlower) should be
in the range of 1 kW – 100 kW.
Where: VIN(WC): VIN value as close as possible to half of
VOUT [V]
DWC: duty cycle at VIN(WC)
DIL,max: maximum peak to peak ripple [A]
The maximum average inductor current can be calculated as
follows:
V OUT(ripple) +
ǒV out * V refǓ
)
V IN(min)D
2fL
Ǔ
ǸD WC
DȀ WC
The maximum voltage across the MOSFET will be the
maximum output voltage, which is the higher of the
maximum input voltage and the regulated output voltaged:
V Q(max) + V OUT(WC)
9. Select Diode
R ESR
The output diode rectifies the output current. The average
current through diode will be equal to the output current:
The capacitors need to survive an RMS ripple current as
follows:
I D(avg) + I OUT(max)
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NCV898032
Additionally, the diode must block voltage equal to the
higher of the output voltage and the maximum input voltage:
compensation pin (VC). The information from the OTA
PWM feedback control signal (VCTRL) may differ from the
IC-VC signal if R2 is of similar order of magnitude as RESD .
The compensation and gain expressions which follow take
influence from the OTA output impedance elements into
account.
Type-I compensation is not possible due to the presence
of RESD . The Figures 13 and 14 compensation networks
correspond to a Type-II network in series with RESD .
The resulting control-output transfer function is an accurate
mathematical model of the IC in a boost converter topology.
The model does have limitations and a more accurate SPICE
model should be considered for a more detailed analysis:
• The attenuating effect of large value ceramic capacitors
in parallel with output electrolytic capacitor ESR is not
considered in the equations.
• The CCM Boost control-output transfer function
includes operating efficiency as a correction factor to
improve modeling accuracy under low input voltage
and high output current operating conditions where
operating losses becomes significant.
V D(max) + V OUT(max)
The maximum power dissipation in the diode can be
calculated as follows:
P D + V f (max) I OUT(max)
Where: Pd: Power dissipation in the diode [W]
Vf(max): Maximum forward voltage of the diode [V]
10. Determine Feedback Loop Compensation Network
The purpose of a compensation network is to stabilize the
dynamic response of the converter. By optimizing the
compensation network, stable regulation response is
achieved for input line and load transients.
Compensator design involves the placement of poles and
zeros in the closed loop transfer function. Losses from the
boost inductor, MOSFET, current sensing and boost diode
losses also influence the gain and compensation
expressions. The OTA has an ESD protection structure
(RESD ≈ 502 W, data not provided in the datasheet) located
on the die between the OTA output and the IC package
L
rL
VIN
Vd
VOUT
rCf
COUT
Rds(on)
VC
GDRV
R2
RESD
C2
C1
ISNS
VCTRL
OTA
Ri
R0
VFB
GND
R1
Rlow
Figure 13. NCV898032 Boost Converter OTA and Compensation
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17
ROUT
NCV898032
Vd
VIN
VOUT
1:N
rCf
Lp
COUT
Rds(on)
ROUT
VC
GDRV
R2
RESD
C2
ISNS
C1
VCTRL
OTA
R0
Ri
VREF
VFB
GND
R1
Rlow
Figure 14. NCV898032 Flyback Converter OTA and Compensation
Necessary equations for describing the modulator gain
(Vctrl-to-Vout gain) Hctrl_output (f) are described next. Boost
continuous conduction mode (CCM) and discontinuous
conduction mode (DCM) transfer function expressions are
summarized in Table 1. Flyback CCM and DCM transfer
function expressions are summarized in Table 2.
The following equations may be used to select compensation
components R2 , C1 , C2 for Figures 13 & 14 power supply.
Required input design parameters for analysis are:
Vd = Output diode Vf (V)
VIN = Power supply input voltage (V)
N = Ns /Np (Flyback transformer turns ratio)
Ri = Current sense resistor (W)
RDS(on) = MOSFET RDS(on) (W)
(Rsw_eq = RDS(on) + Ri for the boost continuous conduction
mode (CCM) expressions)
COUT = Bulk output capacitor value (F)
rCF = Bulk output capacitor ESR (W)
ROUT = Equivalent resistance of output load (W)
Pout = Output Power (W)
L = Boost inductor value or flyback transformer primary
side inductance (H)
rL = Boost inductor ESR (W)
Ts = 1/fs , where fs = 2 MHz clock frequency
R1 and Rlow = Feedback resistor divider values used to set the
output voltage (W)
VOUT = Device specific output voltage (defined by R1 and
Rlow values) (V)
R0 = OTA output resistance = 3 MW
Sa = IC slope compensation (e.g. 34 mV/ms for NCV898032)
gm = OTA transconductance = 1.2 mS
D = Controller duty ratio
D’ = 1 − D
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NCV898032
Table 1. BOOST CCM AND DCM TRANSFER FUNCTION EXPRESSIONS
CCM
Duty Ratio (D)
ȡ
ȧ
ȧ
ȧ
Ȣ
-V OUT
DCM
ƪ
2R OUTV dV IN* R sw_eq)R OUT
Ǹ ǒ
ǒ
V IN
V OUT
*2
V OUT 2
Ǔ
ǒ
VOUT/VIN DC
Conversion Ratio
(M)
Ǹ2tLM(M * 1)
L
Where: t L +
R OUTT s
Ǔ
1
1
1*D
2
ǒ Ǹ
1)
1)
2D 2
tL
Ǔ
V IN * I Laveǒr L ) R sw_eqǓ
Inductor On-slope
(Sn ), V/s
Ri
L
Where average inductor current:
Compensation
Ramp (mc )
(1 * D)
L
Low Frequency
Modulator Pole
(wp1 )
2
V IN
I Lave +
P out
L
Sa
1)
Sn
Sn
1
1
r CFC OUT
r CFC OUT
ǒ
r CFR OUT
R OUT *
r CF ) R OUT
Ǔ
*
rL
R OUT
L
M 2L
Ts
2
)
mc
R OUT
LM 3
1
R CFC OUT
C OUT
High Frequency
Modulator Pole
(wp2 )
2F SW
p
Sampling Double
Pole (wn )
2M * 1
@
M*1
ǒ Ǔ
−
1
1*M
2
D
−
Ts
Sampling Quality
Coefficient (Qp )
Ri
V INh
Sa
1)
Cout ESR Zero
(wz1 )
1
−
p(m c(1 * D) * 0.5)
Fm
1
ǒ
R OUTT s 1
Sa
2M )
)
2
Sn
LM 2
Hd
Control-Output
Transfer Function
(Hctrl_output (f))
ȣ
ȧ
ȧ
ȧ
Ȥ
R OUTV IN 2)2R sw_eqV INV OUT*4V dR sw_eqV IN
R OUT
)R sw_eq 2V OUT 2
-4R sw_eqV OUT 2*4r LV dV IN*4r LV OUT 2
2R OUT V OUT 2 ) V dV IN
Right-Half-Plane
Zero (wz2 )
Ǔƫ
1
Ǔ
S nm cT s
hR OUT
2V OUT
Ri
D
F mH d
ǒ
2pf
1 )jw
p1
Ǔǒ
z2
1)j
2pf 2
2pf
) ǒj w Ǔ
n
w nQ p
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19
M*1
2M * 1
ǒ1 ) j w2pfǓǒ1 * j w2pfǓ
ǒ1 ) j w2pfǓǒ1 * j w2pfǓ
z1
@
Ǔ
F mH d
z1
ǒ
2pf
1 )jw
p1
Ǔǒ
z2
2pf
1 ) jw
p2
Ǔ
NCV898032
Table 2. FLYBACK CCM AND DCM TRANSFER FUNCTION EXPRESSIONS
CCM
DCM
Duty ratio (D)
V OUT
V OUT
V OUT ) NV IN
VOUT/VIN DC Conversion
Ratio (M)
Compensation Ramp (mc )
1*D
V IN
V IN
Cout ESR Zero (wz1 )
Right-Half-Plane Zero (wz2 )
Ri
Lp
Sa
1)
1
r CFC OUT
(1 * D) R OUT
R OUT
DL pN 2
N 2L
ǒ
@
p
1
M(M ) 1)
Ǔ
2
R OUTC OUT
ǒ Ǔ
wp2
−
1
ǒ
2F SW
2
1
1)M
S nm cT s
R OUT
V IN
R iN
ǒ1 ) j w2pfǓǒ1 * j w2pfǓ
2pf
1 ) jw
p1
F mH d
Ǔ
Once the desired cross-over frequency (fc ) gain
adjustment and necessary phase boost are determined from
the Hctrl_output (f) gain and phase plots, the Table 3 equations
may be used. It should be noted that minor compensation
Ǹ
1
2t L
ǒ1 ) j w2pfǓǒ1 * j w2pfǓ
z2
z1
ǒ
1
D
1
Ǔ
Sa
DȀ 2
t L 1 ) 2 S n ) 2M ) 1
F mH d
Sn
1
Sa
DȀ 3
1 ) 2
)1)D
2t L
Sn
Control-output Transfer
Function (Hctrl_output (f))
Ri
r CFC OUT
2
Hd
T sR OUT
Sa
1)
Sn
R OUTC OUT
Fm
N 2L p
N@D
Ǹ2 @ tL
Lp
Modulator Pole (wp1 )
Where: t L +
N@D
Inductor On-slope (Sn ), V/s
Ǹ2t L
NV IN
z1
ǒ
2pf
1 )jw
p1
Ǔǒ
z2
2pf
1 ) jw
p2
Ǔ
component value adjustments may become necessary when
R2 ≤ ~10·Resd as a result of approximations for determining
components R2 , C1 , C2 .
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20
NCV898032
Table 3. OTA COMPENSATION TRANSFER FUNCTION AND COMPENSATION VALUES
Desired OTA Gain at Cross-over Frequency fc (G)
desired_G fc_gain_db
20
10
ǒq
Desired Phase Boost at Cross-over Frequency fc (boost)
Ǔ 180°
* 90° Ǔ
p
ǒ
( )
margin * arg H ctrl_output fc
p
180°
w p1e
Select OTA Compensation Zero to Coincide
with Modulator Pole at fp1 (fz )
2p
f zf c ) f c 2 tan(boost)
Resulting OTA High Frequency Pole Placement (fp )
f c * f z tan(boost)
Compensation Resistor R2
V OUT
f p * f z 1.2g m
f pG
Ǹ
1)
Ǹ
1)
Compensation Capacitor C1
ǒǓ
2
fc
fp
ǒǓ
fz
fp
1
2pf zR 2
Compensation Capacitor C2
1
2pf pG
OTA DC Gain (G0_OTA )
@
R lowg m
R low ) R 1
R low
R low ) R 1
ȳ
R R C
1*
1*4
ȧ
ȧ
2 R R C
ǒR ) R Ǔ C ȴ
Ȳ
ǒ
Ǔ
ȳ
R R C
1 R )R ȱ
1)
1*4
ȧ
ȧ
2 R R C
ǒR ) R Ǔ C ȴ
Ȳ
ǒ
Ǔȱ
ȳ
R ǒR ) R ǓC
1 R )R )R
1
*
1
*
4
ȧ
ȧ
2 R ǒR ) R ǓC
ǒR ) R ) R Ǔ C ȴ
Ȳ
ǒ
Ǔȱ
ȳ
R ǒR ) R ǓC
1 R )R )R
1)
1*4
ȧ
ȧ
2 R ǒR ) R ǓC
ǒR ) R ) R Ǔ C ȴ
Ȳ
ǒ1 ) j w Ǔ ǒ1 ) j w2pf Ǔ
Low Frequency Zero (wz1e )
1
ǒR2 ) ResdǓȱ
@ gm @ R0
2 esd 2
High Frequency Zero (wz2e )
2
0
2
High Frequency Pole (wp2e )
2
0
0
2
OTA Transfer Function (GOTA (f))
2
0
2
esd
esd
2 esd 2
2
2
1
esd
Ǹ
Ǹ
esd
esd
2 esd 2
2
2
1
esd
Ǹ
esd
2 esd 2
Low Frequency Pole (wp1e )
Ǹ
2
2
0
0
2
2
0
esd
2
2
1
esd
0
esd
2
esd
2
2
1
2pf
z2e
z1e
-G 0_OTA
The open-loop-response in closed-loop form to verify the
gain/phase margins may be obtained from the following
expression.
ǒ
2pf
1 ) jw
p1e
Ǔǒ
2pf
1 )jw
p2e
Ǔ
device. Simply connect the voltage you would like to boost
to the inductor and connect the stable voltage to the VIN pin
of the device. In boost configuration, the output of the
converter can be used to power the device. In some cases it
may be desirable to connect 2 sources to VIN pin, which can
be accomplished simply by connecting each of the sources
through a diode to the VIN pin.
T(f) + G OTA(f) H ctrl_output(f)
Low Voltage Operation
If the input voltage drops below the UVLO or MOSFET
threshold voltage, another voltage may be used to power the
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21
NCV898032
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
S
J
SOLDERING FOOTPRINT*
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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