Samsung K4R441869A-NMCK8 256k x 16/18 bit x 2*16 dependent banks direct rdramtm Datasheet

Direct RDRAM™
K4R271669A/K4R441869A
128/144Mbit RDRAM
256K x 16/18 bit x 2*16 Dependent Banks
Direct RDRAMTM
Revision 1.02
January 2000
Page -1
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Revision History
Version 1.0 (July 1999) - Preliminary
- Based on the Rambus Datasheet 1.0 ver.
Version 1.01 (October 1999)
On page 1
- Delete the part numbers of low power
On page 32
- Add the data of CNFGA Register @ Figure 28
On page 33
- Add the data of CNFGB Register @ Figure 29 and correct the CORG4..0 field of CNFGB register
On page 44
- Add the Tj value from TBD to Max. 100°C @ Table 18
On page 46
- Add the ΘJC value from TBD to 0.2°C/Watt @ Table 20
On page 55
- Add the current values for 356MHz and 300MHz RDRAM device
Version 1.02 (January 2000)
* Change the part number of RDRAM Component according to New Code System since ’00.Jan.1st
On page 45
- Reduce swing of VIH,CMOS & VIL,CMOS from “0.5VCMOS±0.6V“ to “0.5VCMOS±0.4V“
- Relax tS1 from 1.0ns to “1.25ns“ ( But, Keep tH1 as 1.0ns)
Page 0
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Overview
The Rambus Direct RDRAM™ is a general purpose highperformance memory device suitable for use in a broad
range of applications including computer memory, graphics,
video, and any other application where high bandwidth and
low latency are required.
SAMSUNG 001
K4Rxxxx69A-Nxxx
The 128/144Mbit Direct Rambus DRAMs (RDRAM) are
extremely high-speed CMOS DRAMs organized as 8M
words by 16 or 18 bits. The use of Rambus Signaling Level
(RSL) technology permits 600MHz to 800MHz transfer
rates while using conventional system and board design
technologies. Direct RDRAM devices are capable of
sustained data transfers at 1.25 ns per two bytes (10ns per
sixteen bytes).
M
a. Normal Package
The 128/144Mbit Direct RDRAMs are offered in a CSP
horizontal package suitable for desktop as well as lowprofile add-in card and mobile applications.
System oriented features for mobile, graphics and large
memory systems include power management, byte masking,
and x18 organization. The two data bits in the x18 organization are general and can be used for additional storage and
bandwidth or for error correction.
Key Timing Parameters/Part Numbers
Speed
Organization
256Kx16x32sa
♦ Highest sustained bandwidth per DRAM device
- 1.6GB/s sustained data transfer rate
- Separate control and data buses for maximized
efficiency
- Separate row and column control buses for
easy scheduling and highest performance
- 32 banks: four transactions can take place simultaneously at full bandwidth data rates
♦ Low latency features
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
♦ Advanced power management:
b. Mirrored Package
Figure 1: Direct RDRAM CSP Package
The architecture of the Direct RDRAMs allows the highest
sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and
data buses with independent row and column control yield
over 95% bus efficiency. The Direct RDRAM's thirty-two
banks support up to four simultaneous transactions.
Features
SAMSUNG 001
K4Rxxxx69A-Mxxx
256Kx18x32s
I/O
Freq.
MHz
tRAC (Row
Access
Time) ns
Part Number
Bin
-CG6
600
53.3
K4R271669A-Nb(M)CcG6
-CK7
711
45
K4R271669A-N(M)CK7
-CK8
800
45
K4R271669A-N(M)CK8
-CG6
600
53.3
K4R441869A-N(M)CG6
-CK7
711
45
K4R441869A-N(M)CK7
-CK8
800
45
K4R441869A-N(M)CK8
a.The “32s"designation indicates that this RDRAM core is composed of 32
banks which use a "split" bank architecture.
b.The “N“ designator indicates the normal package and the “M“ indicates the
mirrored package.
c.The “C“ designator indicates that this RDRAM core uses Normal Power
Self Refresh.
- Direct RDRAM operates from a 2.5 volt supply
- Multiple low power states allows flexibility in power
consumption versus time to transition to active state
- Power-down self-refresh
♦ Organization: 1Kbyte pages and 32 banks, x 16/18
- x18 organization allows ECC configurations or
increased storage/bandwidth
- x16 organization for low cost applications
♦ Uses Rambus Signaling Level (RSL) for up to 800MHz
operation
Page 1
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Pinouts and Definitions
Normal Package
This table shows the pin assignments of the normal RDRAM package.
Table 1 : a. Center-Bonded Device(Top View For Normal Package)
12
GND
VDD
VDD
b. Top marking example of normal package
GND
11
10
DQA7
DQA4
CFM
CFMN
RQ5
RQ3
DQB0
DQB4
DQB7
9
GND
VDD
GND
GNDa
VDD
GND
VDD
VDD
GND
8
CMD
DQA5
DQA2
VDDa
RQ6
RQ2
DQB1
DQB5
SIO1
5
SCK
DQA6
DQA1
VREF
RQ7
RQ1
DQB2
DQB6
SIO0
4
VCMOS
GND
VDD
GND
GND
VDD
GND
GND
VCMOS
3
DQA8*
DQA3
DQA0
CTMN
CTM
RQ4
RQ0
DQB3
DQB8*
SAMSUNG 001
K4Rxxxx69A-Nxxx
7
6
For normal package, pin #1(ROW 1, COL A) is
located at the A1 position on the top side and
the A1 position is marked by the marker “ “.
2
1
Top View
GND
A
ROW
VDD
B
C
VDD
D
E
F
G
GND
H
J
COL
Chip
Mirrored Package
This table shows the pin assignments of the mirrored RDRAM package.
Table 2: a.Center-Bonded Device(Top View For Mirrored Package)
12
GND
VDD
VDD
* DQA8/DQB8 are just used for
144Mb RDRAM. These two pins are
NC(No Connection) in 128Mb RDRAM.
GND
11
10
DQA8*
9
VCMOS
GND
8
SCK
DQA6
DQA3
DQA0
CTMN
CTM
RQ4
VDD
GND
GND
VDD
DQA1
VREF
RQ7
RQ1
DQB3
DQB8*
GND
GND
VCMOS
DQB2
DQB6
SIO0
RQ0
b. Top marking example of mirrored package
SAMSUNG 001
7
K4Rxxxx69A-Mxxx
6
5
CMD
DQA5
DQA2
VDDa
RQ6
RQ2
DQB1
DQB5
SIO1
4
GND
VDD
GND
GNDa
VDD
GND
VDD
VDD
GND
3
DQA7
DQA4
CFM
CFMN
RQ5
RQ3
DQB0
DQB4
DQB7
M
2
1
GND
A
ROW
VDD
B
C
VDD
D
E
F
G
GND
H
J
For mirrored package, pin #1(ROW 1, COL A)
is located at the A1 postion on the top side and
the A1 position is marked by the alphabet “M“.
COL
Page 2
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Table 3: Pin Description
Signal
I/O
Type
# of Pins
Description
SIO1,SIO0
I/O
CMOSa
2
Serial input/output. Pins for reading from and writing to the control
registers using a serial access protocol. Also used for power management.
CMD
I
CMOSa
1
Command input. Pins used in conjunction with SIO0 and SIO1 for
reading from and writing to the control registers. Also used for
power management.
SCK
I
CMOSa
1
Serial clock input. Clock source used for reading from and writing to
the control registers
VDD
10
Supply voltage for the RDRAM core and interface logic.
VDDa
1
Supply voltage for the RDRAM analog circuitry.
VCMOS
2
Supply voltage for CMOS input/output pins.
GND
13
Ground reference for RDRAM core and interface.
GNDa
1
Ground reference for RDRAM analog circuitry.
9
Data byte A. Nine pins which carry a byte of read or write data
between the Channel and the RDRAM. DQA8 is not used by
RDRAMs with a x16 organization.
DQA8..DQA0
I/O
RSLb
CFM
I
RSLb
1
Clock from master. Interface clock used for receiving RSL signals
from the Channel. Positive polarity.
CFMN
I
RSLb
1
Clock from master. Interface clock used for receiving RSL signals
from the Channel. Negative polarity
1
Logic threshold reference voltage for RSL signals
CTMN
I
RSLb
1
Clock to master. Interface clock used for transmitting RSL signals
to the Channel. Negative polarity.
CTM
I
RSLb
1
Clock to master. Interface clock used for transmitting RSL signals
to the Channel. Positive polarity.
RQ7..RQ5 or
ROW2..ROW0
I
RSLb
3
Row access control. Three pins containing control and address
information for row accesses.
RQ4..RQ0 or
COL4..COL0
I
RSLb
5
Column access control. Five pins containing control and address
information for column accesses.
DQB8..
DQB0
I/O
RSLb
9
Data byte B. Nine pins which carry a byte of read or write data
between the Channel and the RDRAM. DQB8 is not used by
RDRAMs with a x16 organization.
VREF
Total pin count per package
62
a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
Page 3
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
RQ7..RQ5 or
ROW2..ROW0
3
DQB8..DQB0
9
RQ4..RQ0 or
COL4..COL0
5
CTM CTMN SCK,CMD SIO0,SIO1 CFM CFMN
2
2
DQA8..DQA0
9
RCLK
RCLK
1:8 Demux
1:8 Demux
TCLK
RCLK
Control Registers
Packet Decode
ROWR
ROWA
11 5
5
9
ROP DR BR
AV
Match
DM
6
R
REFR
Power Modes
Mux
DEVID
COLX
5
5
Packet Decode
COLC
5
5
5
6
XOP DX BX COP DC BC
M
S
Match
Row Decode
Match
C
COLM
8
MB MA
Write
Buffer
XOP Decode
PRER
ACT
8
PREX
Mux
Mux
Column Decode & Mask
Bank 16
Bank 17
Bank 18
Bank 30
Bank 31
9
•••
9
8:1 Mux
Bank 29
9
9
•••
•••
Bank 15
•••
SAmp SAmp SAmp
15
14/15 13/14
SAmp SAmp SAmp
17/18 16/17
16
•••
Bank 14
72
TCLK
SAmp SAmp SAmp
31
30/31 29/30
Write Buffer
Bank 13
Internal DQA Data Path
1:8 Demux
1:8 Demux
Bank 2
72
Write Buffer
TCLK
Bank 1
SAmp SAmp SAmp
29/30 30/31
31
8:1 Mux
Bank 0
SAmp SAmp SAmp
16
16/17 17/18
9
9
32x72
SAmp SAmp SAmp
13/14 14/15
15
9
9
•••
9
32x72 512x64x144
RD, WR
RCLK
RCLK
72
72
PREC
DRAM Core
SAmp SAmp SAmp
0
0/1
1/2
Internal DQB Data Path
SAmp SAmp SAmp
1/2
0/1
0
Sense Amp
32x72
9
Figure 2: 128/144 Mbit Direct RDRAM Block Diagram
Page 4
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
General Description
24-bit ROWA (row-activate) or ROWR (row-operation)
packet.
Figure 2 is a block diagram of the 128/144 Mbit Direct
RDRAM. It consists of two major blocks: a “core“ block
built from banks and sense amps similar to those found in
other types of DRAM, and a Direct Rambus interface block
which permits an external controller to access this core at up
to 1.6GB/s.
COL Pins: The principle use of these five pins is to
manage the transfer of data between the DQA/DQB pins and
the sense amps of the RDRAM. These pins are de-multiplexed into a 23-bit COLC (column-operation) packet and
either a 17-bit COLM (mask) packet or a 17-bit COLX
(extended-operation) packet.
Control Registers: The CMD, SCK, SIO0, and SIO1
ACT Command: An ACT (activate) command from an
pins appear in the upper center of Figure 2. They are used to
write and read a block of control registers. These registers
supply the RDRAM configuration information to a
controller and they select the operating modes of the device.
The nine bit REFR value is used for tracking the last
refreshed row. Most importantly, the five bit DEVID specifies the device address of the RDRAM on the Channel.
ROWA packet causes one of the 512 rows of the selected
bank to be loaded to its associated sense amps (two 256 byte
sense amps for DQA and two for DQB).
PRER Command: A PRER (precharge) command from
Clocking: The CTM and CTMN pins (Clock-To-Master)
generate TCLK (Transmit Clock), the internal clock used to
transmit read data. The CFM and CFMN pins (Clock-FromMaster) generate RCLK (Receive Clock), the internal clock
signal used to receive write data and to receive the ROW and
COL pins.
DQA,DQB Pins: These 18 pins carry read (Q) and write
(D) data across the Channel. They are multiplexed/de-multiplexed from/to two 72-bit data paths (running at one-eighth
the data frequency) inside the RDRAM.
Banks: The 16Mbyte core of the RDRAM is divided into
32 0.5Mbyte banks, each organized as 512 rows, with each
row containing 64 dualocts, and each dualoct containing 16
bytes. A dualoct is the smallest unit of data that can be
addressed.
Sense Amps: The RDRAM contains 34 sense amps. Each
sense amp consists of 512 bytes of fast storage (256 for
DQA and 256 for DQB) and can hold one-half of one row of
one bank of the RDRAM. The sense amp may hold any of
the 512 half-rows of an associated bank. However, each
sense amp is shared between two adjacent banks of the
RDRAM (except for numbers 0, 15, 30, and 31). This introduces the restriction that adjacent banks may not be simultaneously accessed.
RQ Pins: These pins carry control and address information. They are broken into two groups. RQ7..RQ5 are also
called ROW2..ROW0, and are used primarily for controlling
row accesses. RQ4..RQ0 are also called COL4..COL0, and
are used primarily for controlling column accesses.
an ROWR packet causes the selected bank to release its two
associated sense amps, permitting a different row in that
bank to be activated, or permitting adjacent banks to be activated.
RD Command: The RD (read) command causes one of
the 64 dualocts of one of the sense amps to be transmitted on
the DQA/DQB pins of the Channel.
WR Command: The WR (write) command causes a
dualoct received from the DQA/DQB data pins of the
Channel to be loaded into the write buffer. There is also
space in the write buffer for the BC bank address and C
column address information. The data in the write buffer is
automatically retired (written with optional bytemask) to one
of the 64 dualocts of one of the sense amps during a subsequent COP command. A retire can take place during a RD,
WR, or NOCOP to another device, or during a WR or
NOCOP to the same device. The write buffer will not retire
during a RD to the same device. The write buffer reduces the
delay needed for the internal DQA/DQB data path turnaround.
PREC Precharge: The PREC, RDA and WRA
commands are similar to NOCOP, RD and WR, except that
a precharge operation is performed at the end of the column
operation. These commands provide a second mechanism
for performing precharge.
PREX Precharge: After a RD command, or after a WR
command with no byte masking (M=0), a COLX packet may
be used to specify an extended operation (XOP). The most
important XOP command is PREX. This command provides
a third mechanism for performing precharge.
ROW Pins: The principle use of these three pins is to
manage the transfer of data between the banks and the sense
amps of the RDRAM. These pins are de-multiplexed into a
Page 5
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Packet Format
Figure 3 shows the formats of the ROWA and ROWR
packets on the ROW pins. Table 4 describes the fields which
comprise these packets. DR4T and DR4F bits are encoded to
contain both the DR4 device address bit and a framing bit
which allows the ROWA or ROWR packet to be recognized
by the RDRAM.
The AV (ROWA/ROWR packet selection) bit distinguishes
between the two packet types. Both the ROWA and ROWR
packet provide a five bit device address and a five bit bank
address. An ROWA packet uses the remaining bits to
specify a nine bit row address, and the ROWR packet uses
the remaining bits for an eleven bit opcode field. Note the
use of the “RsvX” notation to reserve bits for future address
field extension.
Table 4: Field Description for ROWA Packet and ROWR Packet
Field
Description
DR4T,DR4F
Bits for framing (recognizing) a ROWA or ROWR packet. Also encodes highest device address bit.
DR3..DR0
Device address for ROWA or ROWR packet.
BR4..BR0
Bank address for ROWA or ROWR packet. RsvB denotes bits ignored by the RDRAM.
AV
Selects between ROWA packet (AV=1) and ROWR packet (AV=0).
R8..R0
Row address for ROWA packet. RsvR denotes bits ignored by the RDRAM.
ROP10..ROP0
Opcode field for ROWR packet. Specifies precharge, refresh, and power management functions.
Figure 3 also shows the formats of the COLC, COLM, and
COLX packets on the COL pins. Table 5 describes the fields
which comprise these packets.
The COLC packet uses the S (Start) bit for framing. A
COLM or COLX packet is aligned with this COLC packet,
and is also framed by the S bit.
The 23 bit COLC packet has a five bit device address, a five
bit bank address, a six bit column address, and a four bit
opcode. The COLC packet specifies a read or write
command, as well as some power management commands.
The remaining 17 bits are interpreted as a COLM (M=1) or
COLX (M=0) packet. A COLM packet is used for a COLC
write command which needs bytemask control. The COLM
packet is associated with the COLC packet from a time tRTR
earlier. An COLX packet may be used to specify an independent precharge command. It contains a five bit device
address, a five bit bank address, and a five bit opcode. The
COLX packet may also be used to specify some housekeeping and power management commands. The COLX
packet is framed within a COLC packet but is not otherwise
associated with any other packet.
Table 5: Field Description for COLC Packet, COLM Packet, and COLX Packet
Field
Description
S
Bit for framing (recognizing) a COLC packet, and indirectly for framing COLM and COLX packets.
DC4..DC0
Device address for COLC packet.
BC4..BC0
Bank address for COLC packet. RsvB denotes bits reserved for future extension (controller drives 0’s).
C5..C0
Column address for COLC packet. RsvC denotes bits ignored by the RDRAM.
COP3..COP0
Opcode field for COLC packet. Specifies read, write, precharge, and power management functions.
M
Selects between COLM packet (M=1) and COLX packet (M=0).
MA7..MA0
Bytemask write control bits. 1=write, 0=no-write. MA0 controls the earliest byte on DQA8..0.
MB7..MB0
Bytemask write control bits. 1=write, 0=no-write. MB0 controls the earliest byte on DQB8..0.
DX4..DX0
Device address for COLX packet.
BX4..BX0
Bank address for COLX packet. RsvB denotes bits reserved for future extension (controller drives 0’s).
XOP4..XOP0
Opcode field for COLX packet. Specifies precharge, IOL control, and power management functions.
Page 6
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
T0
T1
T2
T3
T8
CTM/CFM
T9
T10
T11
CTM/CFM
ROW2 DR4T DR2 BR0 BR3 RsvR R8
R5
R2
ROW2 DR4T DR2 BR0 BR3
ROW1
DR4F DR1 BR1 BR4 RsvR
R7
R4
R1
ROW1
DR4F DR1 BR1 BR4 ROP9 ROP7 ROP4 ROP1
ROW0
DR3 DR0 BR2 RsvB AV=1 R6
R3
R0
ROW0
DR3 DR0 BR2 RsvB AV=0 ROP6 ROP3 ROP0
ROWA Packet
T0
T1
T2
ROP10 ROP8 ROP5 ROP2
ROWR Packet
T3
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15
CTM/CFM
CTM/CFM
S=1
RsvC
C4
C5
C3
COL4
DC4
COL3
DC3
COL2
DC2 COP1
RsvB BC2
C2
COL1
DC1 COP0
BC4 BC1
C1
COL0
DC0 COP2
COP3 BC3 BC0
C0
ROW2
..ROW0
ACT a0
COL4
..COL0
WR b1
PRER c0
tPACKET
MSK (b1)
PREX d0
DQA8..0
DQB8..0
COLC Packet
T8
T9
T10
T11
CTM/CFM
a
T12
T13
T14
T15
CTM/CFM
COL4
S=1a MA7 MA5 MA3 MA1
COL4
S=1b DX4 XOP4 RsvB BX1
COL3
M=1 MA6 MA4 MA2 MA0
COL3
M=0 DX3 XOP3 BX4 BX0
COL2
MB7 MB4 MB1
COL2
DX2 XOP2 BX3
COL1
MB6 MB3 MB0
COL1
DX1 XOP1 BX2
COL0
MB5 MB2
COL0
DX0 XOP0
The COLM is associated with a
previous COLC, and is aligned
with the present COLC, indicated
by the Start bit (S=1) position.
b The
COLM Packet
COLX Packet
COLX is aligned
with the present COLC,
indicated by the Start
bit (S=1) position.
Figure 3: Packet Formats
Page 7
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Field Encoding Summary
broadcast operation is indicated when both bits are set.
Broadcast operation would typically be used for refresh and
power management commands. If the device is selected, the
DM (DeviceMatch) signal is asserted and an ACT or ROP
command is performed.
Table 6 shows how the six device address bits are decoded
for the ROWA and ROWR packets. The DR4T and DR4F
encoding merges a fifth device bit with a framing bit. When
neither bit is asserted, the device is not selected. Note that a
Table 6: Device Field Encodings for ROWA Packet and ROWR Packet
DR4T
DR4F
Device Selection
Device Match signal (DM)
1
1
All devices (broadcast)
DM is set to 1
0
1
One device selected
DM is set to 1 if {DEVID4..DEVID0} == {0,DR3..DR0} else DM is set to 0
1
0
One device selected
DM is set to 1 if {DEVID4..DEVID0} == {1,DR3..DR0} else DM is set to 0
0
0
No packet present
DM is set to 0
row address comes from an internal register REFR, and
REFR is incremented at the largest bank address. The REFP
(refresh-precharge) command is identical to a PRER
command.
Table 7 shows the encodings of the remaining fields of the
ROWA and ROWR packets. An ROWA packet is specified
by asserting the AV bit. This causes the specified row of the
specified bank of this device to be loaded into the associated
sense amps.
An ROWR packet is specified when AV is not asserted. An
11 bit opcode field encodes a command for one of the banks
of this device. The PRER command causes a bank and its
two associated sense amps to precharge, so another row or
an adjacent bank may be activated. The REFA (refresh-activate) command is similar to the ACT command, except the
The NAPR, NAPRC, PDNR, ATTN, and RLXR commands
are used for managing the power dissipation of the RDRAM
and are described in more detail in “ Power state management “ on page 38. The TCEN and TCAL commands are
used to adjust the output driver slew rate and they are
described in more detail in “Current and Temperature
Control“ on page 43.
Table 7: ROWA Packet and ROWR Packet Field Encodings
ROP10..ROP0 Field
DMa
AV
Name
10 9
8
7
6
5
4
3
2:0
-
-
-
-
-
-
---
0
-
-
1
1
Row address
-
Command Description
-
No operation.
ACT
Activate row R8..R0 of bank BR4..BR0 of device and move device to ATTNb.
1
0
1
1
0
0
0
xc
x
x
000
PRER
Precharge bank BR4..BR0 of this device.
1
0
0
0
0
1
1
0
0
x
000
REFA
Refresh (activate) row REFR8..REFR0 of bank BR4..BR0 of device.
Increment REFR if BR4..BR0 = 1111 (see Figure 50).
1
0
1
0
1
0
1
0
0
x
000
REFP
Precharge bank BR4..BR0 of this device after REFA (see Figure 50).
1
0
x
x
0
0
0
0
1
x
000
PDNR
Move this device into the powerdown (PDN) power state (see Figure 47).
1
0
x
x
0
0
0
1
0
x
000
NAPR
Move this device into the nap (NAP) power state (see Figure 47).
1
0
x
x
0
0
0
1
1
x
000
NAPRC
Move this device into the nap (NAP) power state conditionally
1
0
x
x
x
x
x
x
x
0
000
ATTNb
Move this device into the attention (ATTN) power state (see Figure 45).
1
0
x
x
x
x
x
x
x
1
000
RLXR
Move this device into the standby (STBY) power state (see Figure 46).
1
0
0
0
0
0
0
0
0
x
001
TCAL
Temperature calibrate this device (see Figure 52).
1
0
0
0
0
0
0
0
0
x
010
TCEN
Temperature calibrate/enable this device (see Figure 52).
1
0
0
0
0
0
0
0
0
0
000
NOROP
No operation.
a. The DM (Device Match signal) value is determined by the DR4T,DR4F, DR3..DR0 field of the ROWA and ROWR packets. See Table 6.
b. The ATTN command does not cause a RLX-to-ATTN transition for a broadcast operation (DR4T/DR4F=1/1).
c. An “x“ entry indicates which commands may be combined. For instance, the three commands PRER/NAPRC/RLXR may be specified in one ROP value (011000111000).
Page 8
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Table 8 shows the COP field encoding. The device must be
in the ATTN power state in order to receive COLC packets.
The COLC packet is used primarily to specify RD (read) and
WR (write) commands. Retire operations (moving data from
the write buffer to a sense amp) happen automatically. See
Figure 17 for a more detailed description.
The COLC packet can also specify a PREC command,
which precharges a bank and its associated sense amps. The
RDA/WRA commands are equivalent to combining RD/WR
with a PREC. RLXC (relax) performs a power mode transition. See “ Power State Management “ on page 38.
Table 8: COLC Packet Field Encodings
S
DC4.. DC0
(select device)a
COP3..0 Name
Command Description
0
----
-----
-
No operation.
1
/= (DEVID4 ..0)
-----
-
Retire write buffer of this device.
1
== (DEVID4 ..0)
x000b
NOCOP
Retire write buffer of this device.
1
== (DEVID4 ..0)
x001
WR
Retire write buffer of this device, then write column C5..C0 of bank BC4..BC0 to write buffer.
1
== (DEVID4 ..0)
x010
RSRV
Reserved, no operation.
1
== (DEVID4 ..0)
x011
RD
Read column C5..C0 of bank BC4..BC0 of this device.
1
== (DEVID4 ..0)
x100
PREC
Retire write buffer of this device, then precharge bank BC4..BC0 (see Figure 14).
1
== (DEVID4 ..0)
x101
WRA
Same as WR, but precharge bank BC4..BC0 after write buffer (with new data) is retired.
1
== (DEVID4 ..0)
x110
RSRV
Reserved, no operation.
1
== (DEVID4 ..0)
x111
RDA
Same as RD, but precharge bank BC4..BC0 afterward.
1
== (DEVID4 ..0)
1xxx
RLXC
Move this device into the standby (STBY) power state (see Figure 46).
a. “ /= “ means not equal, “ == “ means equal.
b. An “ x“ entry indicates which commands may be combined. For instance, the two commands WR/RLXC may be specified in one COP value(1001).
specified without consuming control bandwidth on the ROW
pins. It is also used for the CAL(calibrate) and SAM
(sample) current control commands (see “Current and
Temperature Control“ on page 43), and for the RLXX power
mode command (see “Power State Management“ on page
38).
Table 9 shows the COLM and COLX field encodings. The
M bit is asserted to specify a COLM packet with two 8 bit
bytemask fields MA and MB. If the M bit is not asserted, an
COLX is specified. It has device and bank address fields,
and an opcode field. The primary use of the COLX packet is
to permit an independent PREX (precharge) command to be
Table 9: COLM Packet and COLX Packet Field Encodings
M
DX4 .. DX0
(selects device)
XOP4..0
Name
Command Description
1
----
-
MSK
MB/MA bytemasks used by WR/WRA.
0
/= (DEVID4 ..0)
-
-
No operation.
0
== (DEVID4 ..0)
00000
NOXOP
No operation.
0
== (DEVID4 ..0)
1xxx0a
PREX
Precharge bank BX4..BX0 of this device (see Figure 14).
0
== (DEVID4 ..0)
x10x0
CAL
Calibrate (drive) IOL current for this device (see Figure 51).
0
== (DEVID4 ..0)
x11x0
CAL/SAM
Calibrate (drive) and Sample ( update) IOL current for this device (see Figure 51).
0
== (DEVID4 ..0)
xxx10
RLXX
Move this device into the standby (STBY) power state (see Figure 46).
0
== (DEVID4 ..0)
xxxx1
RSRV
Reserved, no operation.
a. An “x“ entry indicates which commands may be combined. For instance, the two commands PREX/RLXX may be specified in one XOP value (10010).
Page 9
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
DQ Packet Timing
Figure 4 shows the timing relationship of COLC packets
with D and Q data packets. This document uses a specific
convention for measuring time intervals between packets: all
packets on the ROW and COL pins (ROWA, ROWR,
COLC, COLM, COLX) use the trailing edge of the packet as
a reference point, and all packets on the DQA/DQB pins (D
and Q) use the leading edge of the packet as a reference
point.
An RD or RDA command will transmit a dualoct of read
data Q a time tCAC later. This time includes one to five
cycles of round-trip propagation delay on the Channel. The
tCAC parameter may be programmed to a one of a range of
values ( 8, 9, 10, 11, or 12 tCYCLE). The value chosen
depends upon the number of RDRAM devices on the
Channel and the RDRAM timing bin. See Figure 39 for
more information.
A WR or WRA command will receive a dualoct of write
data D a time tCWD later. This time does not need to include
the round-trip propagation time of the Channel since the
COLC and D packets are traveling in the same direction.
When a Q packet follows a D packet (shown in the left half
of the figure), a gap (tCAC -tCWD) will automatically appear
between them because the tCWD value is always less than the
tCAC value. There will be no gap between the two COLC
packets with the WR and RD commands which schedule the
D and Q packets.
When a D packet follows a Q packet (shown in the right half
of the figure), no gap is needed between them because the
tCWD value is less than the tCAC value. However, , a gap of
tCAC -tCWD or greater must be inserted between the COLC
packets with the RD WR commands by the controller so the
Q and D packets do not overlap.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47
CTM/CFM
This gap on the DQA/DQB pins appears automatically
ROW2
..ROW0
tCAC-tCWD
tCAC -tCWD
WR a1
•••
RD b1
DQA8..0
DQB8..0
RD c1
D (a1)
tCAC
WR d1
WR d1
WR d1
WR d1
WR d1
•••
tCWD
COL4
..COL0
This gap on the COL pins must be inserted by the controller
Q (b1)
Q (b1)
Q (a1)
Q
(a1)
Q (a1)
•••
tCWD
•••
Q (c1)
D (d1)
Q (c1)
D (d1)
Q (c1)
D (d1)
Q (c1)
D (d1)
Q (a1)
D (d1)
•••
tCAC
Figure 4: Read (Q) and Write (D) Data Packet - Timing for tCAC = 8, 9, 10, 11, or 12 tCYCLE
COLM Packet to D Packet Mapping
Figure 5 shows a write operation initiated by a WR
command in a COLC packet. If a subset of the 16 bytes of
write data are to be written, then a COLM packet is transmitted on the COL pins a time tRTR after the COLC packet
containing the WR command. The M bit of the COLM
packet is set to indicate that it contains the MA and MB
mask fields. Note that this COLM packet is aligned with the
COLC packet which causes the write buffer to be retired.
See Figure 17 for more details.
housekeeping command (this case is not shown). The M bit
is not asserted in an COLX packet and causes all 16 bytes of
the previous WR to be written unconditionally. Note that a
RD command will never need a COLM packet, and will
always be able to use the COLX packet option (a read operation has no need for the byte-write-enable control bits).
Figure 5 also shows the mapping between the MA and MB
fields of the COLM packet and bytes of the D packet on the
DQA and DQB pins. Each mask bit controls whether a byte
of data is written (=1) or not written (=0).
If all 16 bytes of the D data packet are to be written, then no
further control information is required. The packet slot that
would have been used by the COLM packet (tRTR after the
COLC packet) is available to be used as an COLX packet.
This could be used for a PREX precharge command or for a
Page 10
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47
CTM/CFM
ROW2
..ROW0
ACT a0
PRER a2
ACT b0
tRTR
COL4
..COL0
WR a1
retire (a1)
MSK (a1)
tCWD
DQA8..0
DQB8..0
D (a1)
Transaction a: WR
a0 = {Da,Ba,Ra}
a1 = {Da,Ba,Ca1}
a3 = {Da,Ba}
COLM Packet
T17
T18
T19
CTM/CFM
D Packet
T20
T19
T20
T21
T22
COL4
MA7 MA5 MA3 MA1
DQB8
DB8
DB17 DB26 DB35 DB45 DB53 DB62 DB71
COL3
M=1 MA6 MA4 MA2 MA0
DQB7
DB7
DB16 DB25 DB34 DB44 DB52 DB61 DB70
COL2
MB7 MB4 MB1
•••
CTM/CFM
COL1
MB6 MB3 MB0
DQB1
DB1
DB10 DB19 DB28 DB37 DB46 DB55 DB64
COL0
MB5 MB2
DQB0
DB0
DB9
DB18 DB27 DB36 DB45 DB54 DB63
MB0
MB1
MB2
DQA8
DA8
DA17 DA26 DA35 DA45 DA53 DA62 DA71
DQA7
DA7
DA16 DA25 DA34 DA44 DA52 DA61 DA70
DQA1
DA1
DA10 DA19 DA28 DA37 DA46 DA55 DA64
DQA0
DA0
DA9
DA18 DA27 DA36 DA45 DA54 DA63
MA0
MA1
MA2
MB3
MB4
MB5
MB6
MB7
Each bit of the MB7..MB0 field
controls writing (=1) or no writing
(=0) of the indicated DB bits when
the M bit of the COLM packet is one.
•••
When M=1, the MA and MB
fields control writing of
individual data bytes.
When M=0, all data bytes are
written unconditionally.
Each bit of the MA7..MA0 field
controls writing (=1) or no writing
(=0) of the indicated DA bits when
the M bit of the COLM packet is one.
MA3
MA4
MA5
MA6
MA7
Figure 5: Mapping Between COLM Packet and D Packet for WR Command
Page 11
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
ROW-to-ROW Packet Interaction
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T
CTM/CFM
tRRDELAY
ROW2
..ROW0
ROPa a0
ROPb b0
Cases RR1 through RR4 show two successive ACT
commands. In case RR1, there is no restriction since the
ACT commands are to different devices. In case RR2, the
tRR restriction applies to the same device with non-adjacent
banks. Cases RR3 and RR4 are illegal (as shown) since bank
Ba needs to be precharged. If a PRER to Ba, Ba+1, or Ba-1
is inserted, tRRDELAY is tRC (tRAS to the PRER command,
and tRP to the next ACT).
Cases RR5 through RR8 show an ACT command followed
by a PRER command. In cases RR5 and RR6, there are no
restrictions since the commands are to different devices or to
non-adjacent banks of the same device. In cases RR7 and
RR8, the tRAS restriction means the activated bank must wait
before it can be precharged.
COL4
..COL0
DQA8..0
DQB8..0
Transaction a: ROPa
Transaction b: ROPb
a0 = {Da,Ba,Ra}
b0= {Db,Bb,Rb}
Figure 6: ROW-to-ROW Packet Interaction- Timing
Figure 6 shows two packets on the ROW pins separated by
an interval tRRDELAY which depends upon the packet
contents. No other ROW packets are sent to banks
{Ba,Ba+1,Ba-1} between packet “a” and packet “b” unless
noted otherwise. Table 10 summarizes the tRRDELAY values
for all possible cases.
Cases RR9 through RR12 show a PRER command followed
by an ACT command. In cases RR9 and RR10, there are
essentially no restrictions since the commands are to
different devices or to non-adjacent banks of the same
device. RR10a and RR10b depend upon whether a bracketed
bank (Ba±1) is precharged or activated. In cases RR11 and
RR12, the same and adjacent banks must all wait tRP for the
sense amp and bank to precharge before being activated.
Table 10: ROW-to-ROW Packet Interaction - Rules
Case #
ROPa
Da
Ba
Ra
ROPb
Db
Bb
Rb
tRRDELAY
Example
RR1
ACT
Da
Ba
Ra
ACT
/= Da
xxxx
x..x
tPACKET
Figure 11
RR2
ACT
Da
Ba
Ra
ACT
== Da
/= {Ba,Ba+1,Ba-1}
x..x
tRR
Figure 11
RR3
ACT
Da
Ba
Ra
ACT
== Da
== {Ba+1,Ba-1}
x..x
tRC - illegal unless PRER to Ba/Ba+1/Ba-1
Figure 10
RR4
ACT
Da
Ba
Ra
ACT
== Da
== {Ba}
x..x
tRC - illegal unless PRER to Ba/Ba+1/Ba-1
Figure 10
RR5
ACT
Da
Ba
Ra
PRER
/= Da
xxxx
x..x
tPACKET
Figure 11
RR6
ACT
Da
Ba
Ra
PRER
== Da
/= {Ba,Ba+1,Ba-1}
x..x
tPACKET
Figure 11
RR7
ACT
Da
Ba
Ra
PRER
== Da
== { Ba+1,Ba-1}
x..x
tRAS
Figure 10
RR8
ACT
Da
Ba
Ra
PRER
== Da
== {Ba}
x..x
tRAS
Figure 15
RR9
PRER
Da
Ba
Ra
ACT
/= Da
xxxx
x..x
tPACKET
Figure 12
RR10
PRER
Da
Ba
Ra
ACT
== Da
/= {Ba,Ba±1,Ba±2}
x..x
tPACKET
Figure 12
RR10a
PRER
Da
Ba
Ra
ACT
== Da
== {Ba+2}
x..x
tPACKET/tRP if Ba+1 is precharged/activated.
RR10b
PRER
Da
Ba
Ra
ACT
== Da
== {Ba-2}
x..x
tPACKET/tRP if Ba-1 is precharged/activated.
RR11
PRER
Da
Ba
Ra
ACT
== Da
== {Ba+1,Ba-1}
x..x
tRP
Figure 10
RR12
PRER
Da
Ba
Ra
ACT
== Da
== {Ba}
x..x
tRP
Figure 10
RR13
PRER
Da
Ba
Ra
PRER
/= Da
xxxx
x..x
tPACKET
Figure 12
RR14
PRER
Da
Ba
Ra
PRER
== Da
/= {Ba,Ba+1,Ba-1}
x..x
tPP
Figure 12
RR15
PRER
Da
Ba
Ra
PRER
== Da
== {Ba+1,Ba-1}
x..x
tPP
Figure 12
RR16
PRER
Da
Ba
Ra
PRER
== Da
== Ba
x..x
tPP
Figure 12
Page 12
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
ROW-to-ROW Interaction - continued
Cases RC1 through RC5 summarize the rules when the
ROW packet has an ACT command. Figure 15 and
Figure 16 show examples of RC5 - an activation followed by
a read or write. RC4 is an illegal situation, since a read or
write of a precharged banks is being attempted (remember
that for a bank to be activated, adjacent banks must be
precharged). In cases RC1, RC2, and RC3, there is no interaction of the ROW and COL packets.
Cases RR13 through RR16 summarize the combinations of
two successive PRER commands. In case RR13 there is no
restriction since two devices are addressed. In RR14, tPP
applies, since the same device is addressed. In RR15 and
RR16, the same bank or an adjacent bank may be given
repeated PRER commands with only the tPP restriction.
Two adjacent banks can’t be activate simultaneously. A
precharge command to one bank will thus affect the state of
the adjacent banks (and sense amps). If bank Ba is activate
and a PRER is directed to Ba, then bank Ba will be
precharged along with sense amps Ba-1/Ba and Ba/Ba+1. If
bank Ba+1 is activate and a PRER is directed to Ba, then
bank Ba+1 will be precharged along with sense amps
Ba/Ba+1 and Ba+1/Ba+2. If bank Ba-1 is activate and a
PRER is directed to Ba, then bank Ba-1 will be precharged
along with sense amps Ba/Ba-1 and Ba-1/Ba-2.
A ROW packet may contain commands other than ACT or
PRER. The REFA and REFP commands are equivalent to
ACT and PRER for interaction analysis purposes. The interaction rules of the NAPR, NAPRC, PDNR, RLXR, ATTN,
TCAL, and TCEN commands are discussed in later sections
(see Table 7 for cross-ref).
ROW-to-COL Packet Interaction
Figure 7 shows two packets on the ROW and COL pins.
They must be separated by an interval tRCDELAY which
depends upon the packet contents. Table 11 summarizes the
tRCDELAY values for all possible cases. Note that if the COL
packet is earlier than the ROW packet, it is considered a
COL-to-ROW packet interaction.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T
CTM/CFM
tRCDELAY
ROW2
..ROW0
ROPa a0
COL4
..COL0
COPb b1
DQA8..0
DQB8..0
Transaction a: ROPa
Transaction b: COPb
a0 = {Da,Ba,Ra}
b1= {Db,Bb,Cb1}
Figure 7: ROW-to-COL Packet Interaction- Timing
Cases RC6 through RC8 summarize the rules when the
ROW packet has a PRER command. There is either no interaction (RC6 through RC9) or an illegal situation with a read
or write of a precharged bank (RC9).
The COL pins can also schedule a precharge operation with
a RDA, WRA, or PREC command in a COLC packet or a
PREX command in a COLX packet. The constraints of these
precharge operations may be converted to equivalent PRER
command constraints using the rules summarized in
Figure 14.
Table 11: ROW-to-COL Packet Interaction - Rules
Case #
ROPa
Da
Ba
Ra
COPb
Db
Bb
Cb1
tRCDELAY
RC1
ACT
Da
Ba
Ra
NOCOP,RD,retire
/= Da
xxxx
x..x
0
RC2
ACT
Da
Ba
Ra
NOCOP
== Da
xxxx
x..x
0
RC3
ACT
Da
Ba
Ra
RD,retire
== Da
/= {Ba,Ba+1,Ba-1}
x..x
0
RC4
ACT
Da
Ba
Ra
RD,retire
== Da
== {Ba+1,Ba-1}
x..x
Illegal
RC5
ACT
Da
Ba
Ra
RD,retire
== Da
== Ba
x..x
tRCD
RC6
PRER
Da
Ba
Ra
NOCOP,RD,retire
/= Da
xxxx
x..x
0
RC7
PRER
Da
Ba
Ra
NOCOP
== Da
xxxx
x..x
0
RC8
PRER
Da
Ba
Ra
RD,retire
== Da
/= {Ba,Ba+1,Ba-1}
x..x
0
RC9
PRER
Da
Ba
Ra
RD,retire
== Da
== {Ba+1,Ba-1}
x..x
Illegal
Page 13
Example
Figure 15
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
COL-to-COL Packet Interaction
CC2, CC4, and CC5, there is no restriction (tCCDELAY is
tCC).
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T
CTM/CFM
ROW2
..ROW0
COL4
..COL0
tCCDELAY
COPa a1
COPb b1
COPc c1
In case CC10, there is a RD-WR-RD sequence directed to
the same device. If a prior write to the same device is unretired when COPa is issued, then a gap will be needed
between the packets with COPb and COPc as in case CC6.
The gap will need a COLC packet with a NOCOP command
directed to any device in order to force an automatic retire to
take place.
DQA8..0
DQB8..0
Transaction a: COPa
Transaction b: COPb
Transaction c: COPc
In cases CC6 through CC10, COPb is a WR command and
COPc is a RD command. The tCCDELAY value needed
between these two packets depends upon the command and
address in the packet with COPa. In particular, in case CC6
when there is WR-WR-RD command sequence directed to
the same device, a gap will be needed between the packets
with COPb and COPc. The gap will need a COLC packet
with a NOCOP command directed to any device in order to
force an automatic retire to take place. Figure 18 (right)
provides a more detailed explanation of this case.
a1 = {Da,Ba,Ca1}
b1 = {Db,Bb,Cb1}
c1 = {Dc,Bc,Cc1}
Figure 8: COL-to-COL Packet Interaction- Timing
Figure 8 shows three arbitrary packets on the COL pins.
Packets “b” and “c” must be separated by an interval
tCCDELAY which depends upon the command and address
values in all three packets. Table 12 summarizes the
tCCDELAY values for all possible cases.
Cases CC7, CC8, and CC9 have no restriction (tCCDELAY is
tCC).
Cases CC1 through CC5 summarize the rules for every situation other than the case when COPb is a WR command and
COPc is a RD command. In CC3, when a RD command is
followed by a WR command, a gap of tCAC -tCWD must be
inserted between the two COL packets. See Figure 4 for
more explanation of why this gap is needed. For cases CC1,
For the purposes of analyzing COL-to-ROW interactions,
the PREC, WRA, and RDA commands of the COLC packet
are equivalent to the NOCOP, WR, and RD commands.
These commands also cause a precharge operation PREC to
take place. This precharge may be converted to an equivalent PRER command on the ROW pins using the rules
summarized in Figure 14.
Table 12: COL-to-COL Packet Interaction - Rules
Case #
COPa
Da
Ba
Ca1
COPb
Db
Bb
Cb1
COPc
Dc
Bc
Cc1
tCCDELAY
CC1
xxxx
xxxxx
x..x
x..x
NOCOP
Db
Bb
Cb1
xxxx
xxxxx
x..x
x..x
tCC
CC2
xxxx
xxxxx
x..x
x..x
RD,WR
Db
Bb
Cb1
NOCOP
xxxxx
x..x
x..x
tCC
CC3
xxxx
xxxxx
x..x
x..x
RD
Db
Bb
Cb1
WR
xxxxx
x..x
x..x
tCC+tCAC -tCWD
Example
Figure 4
CC4
xxxx
xxxxx
x..x
x..x
RD
Db
Bb
Cb1
RD
xxxxx
x..x
x..x
tCC
Figure 15
CC5
xxxx
xxxxx
x..x
x..x
WR
Db
Bb
Cb1
WR
xxxxx
x..x
x..x
tCC
Figure 16
CC6
WR
== Db
x
x..x
WR
Db
Bb
Cb1
RD
== Db
x..x
x..x
tRTR
Figure 18
CC7
WR
== Db
x
x..x
WR
Db
Bb
Cb1
RD
/= Db
x..x
x..x
tCC
CC8
WR
/= Db
x
x..x
WR
Db
Bb
Cb1
RD
== Db
x..x
x..x
tCC
CC9
NOCOP
== Db
x
x..x
WR
Db
Bb
Cb1
RD
== Db
x..x
x..x
tCC
CC10
RD
== Db
x
x..x
WR
Db
Bb
Cb1
RD
== Db
x..x
x..x
tCC
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Direct RDRAM™
K4R271669A/K4R441869A
COL-to-ROW Packet Interaction
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T
In case CR6, the COLC packet contains a RD command, and
the ROW packet contains a PRER command for the same
bank. The tRDP parameter specifies the required spacing.
CTM/CFM
tCRDELAY
ROW2
..ROW0
COL4
..COL0
ROPb b0
Likewise, in case CR7, the COLC packet causes an automatic retire to take place, and the ROW packet contains a
PRER command for the same bank. The tRTP parameter
specifies the required spacing.
COPa a1
Case CR8 is labeled “Hazardous” because a WR command
should always be followed by an automatic retire before a
precharge is scheduled. Figure 19 shows an example of what
can happen when the retire is not able to happen before the
precharge.
DQA8..0
DQB8..0
Transaction a: COPa
Transaction b: ROPb
Case CR4 is illegal because an already-activated bank is to
be re-activated without being precharged Case CR5 is illegal
because an adjacent bank can’t be activated or precharged
until bank Ba is precharged first.
a1= {Da,Ba,Ca1}
b0= {Db,Bb,Rb}
Figure 9: COL-to-ROW Packet Interaction- Timing
Figure 9 shows arbitrary packets on the COL and ROW pins.
They must be separated by an interval tCRDELAY which
depends upon the command and address values in the
packets. Table 13 summarizes the tCRDELAY value for all
possible cases.
Cases CR1, CR2, CR3, and CR9 show no interaction
between the COL and ROW packets, either because one of
the commands is a NOP or because the packets are directed
to different devices or to non-adjacent banks.
For the purposes of analyzing COL-to-ROW interactions,
the PREC, WRA, and RDA commands of the COLC packet
are equivalent to the NOCOP, WR, and RD commands.
These commands also cause a precharge operation to take
place. This precharge may converted to an equivalent PRER
command on the ROW pins using the rules summarized in
Figure 14.
A ROW packet may contain commands other than ACT or
PRER. The REFA and REFP commands are equivalent to
ACT and PRER for interaction analysis purposes. The interaction rules of the NAPR, PDNR, and RLXR commands are
discussed in a later section.
Table 13: COL-to-ROW Packet Interaction - Rules
Case #
COPa
Da
Ba
Ca1
ROPb
Db
Bb
Rb
tCRDELAY
CR1
NOCOP
Da
Ba
Ca1
x..x
xxxxx
xxxx
x..x
0
CR2
RD/WR
Da
Ba
Ca1
x..x
/= Da
xxxx
x..x
0
CR3
RD/WR
Da
Ba
Ca1
x..x
== Da
/= {Ba,Ba+1,Ba-1}
x..x
0
CR4
RD/WR
Da
Ba
Ca1
ACT
== Da
== {Ba}
x..x
Illegal
CR5
RD/WR
Da
Ba
Ca1
ACT
== Da
== {Ba+1,Ba-1}
x..x
Illegal
CR6
RD
Da
Ba
Ca1
PRER
== Da
== {Ba,Ba+1,Ba-1} x..x
CR7
retirea
Da
Ba
Ca1
PRER
== Da
== {Ba,Ba+1,Ba-1} x..x
tRTP
Figure 16
CR8
WRb
Da
Ba
Ca1
PRER
== Da
== {Ba,Ba+1,Ba-1} x..x
0
Figure 19
CR9
xxxx
Da
Ba
Ca1
NOROP
xxxxx
xxxx
0
x..x
Example
tRDP
Figure 15
a. This is any command which permits the write buffer of device Da to retire (see Table 8). “Ba” is the bank address in the write buffer.
b. This situation is hazardous because the write buffer will be left unretired while the targeted bank is precharged. See Figure 19.
Page 15
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Direct RDRAM™
K4R271669A/K4R441869A
ROW-to-ROW Examples
between ACT commands to the same bank must also satisfy
the tRC timing parameter (RR4).
Figure 10 shows examples of some of the ROW-to-ROW
packet spacings from Table 10. A complete sequence of activate and precharge commands is directed to a bank. The
RR8 and RR12 rules apply to this sequence. In addition to
satisfying the tRAS and tRP timing parameters, the separation
When a bank is activated, it is necessary for adjacent banks
to remain precharged. As a result, the adjacent banks will
also satisfy parallel timing constraints; in the example, the
RR11 and RR3 rules are analogous to the RR12 and RR4
rules.
Same Device
Same Device
Same Device
Same Device
Same Device
Adjacent Bank
Adjacent Bank
Same Bank
Adjacent Bank
Same Bank
RR7
RR3
RR4
RR11
RR12
a0 = {Da,Ba,Ra}
a1 = {Da,Ba+1}
b0 = {Da,Ba+1,Rb}
b0 = {Da,Ba,Rb}
b0 = {Da,Ba+1,Rb}
b0 = {Da,Ba,Rb}
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47
CTM/CFM
ROW2
..ROW0
ACT a0
PRER a1
ACT b0
COL4
..COL0
tRAS
tRP
DQA8..0
DQB8..0
tRC
Figure 10: Row Packet Example
Figure 11 shows examples of the ACT-to-ACT (RR1, RR2)
and ACT-to-PRER (RR5, RR6) command spacings from
Table 10. In general, the commands in ROW packets may be
spaced an interval tPACKET apart unless they are directed to
the same or adjacent banks or unless they are a similar
command type (both PRER or both ACT) directed to the
same device.
CTM/CFM
ROW2
..ROW0
COL4
..COL0
DQA8..0
DQB8..0
Figure 11: Row Packet Example
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Direct RDRAM™
K4R271669A/K4R441869A
spaced an interval tPACKET apart unless they are directed to
the same or adjacent banks or unless they are a similar
command type (both PRER or both ACT) directed to the
same device.
Figure 12 shows examples of the PRER-to-PRER (RR13,
RR14) and PRER-to-ACT (RR9, RR10) command spacings
from Table 10. The RR15 and RR16 cases (PRER-to-PRER
to same or adjacent banks) are not shown, but are similar to
RR14. In general, the commands in ROW packets may be
Different Device
Same Device
Same Device
Same Device
Different Device
Same Device
Any Bank
Non-adjacent Bank
Adjacent Bank
Same Bank
Any Bank
Non-adjacent Bank
RR13
RR14
RR15
RR16
RR9
RR10
a0 = {Da,Ba,Ra}
b0 = {Db,Bb,Rb}
c0 = {Da,Bc,Rc}
c0 = {Da,Ba,Rc}
c0 = {Da,Ba+1Rc}
b0 = {Db,Bb,Rb}
c0 = {Da,Bc,Rc}
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47
CTM/CFM
ROW2
..ROW0
PRER a0
tPACKET
PRER b0
PRER a0
PRER c0
PRER a0
tPACKET
tPP
ACT b0
PRER a0
ACT c0
tPACKET
COL4
..COL0
DQA8..0
DQB8..0
Figure 12: Row Packet Examples
Row and Column Cycle Description
Activate: A row cycle begins with the activate (ACT) operation. The activation process is destructive; the act of sensing
the value of a bit in a bank’s storage cell transfers the bit to
the sense amp, but leaves the original bit in the storage cell
with an incorrect value.
Restore: Because the activation process is destructive, a
hidden operation called restore is automatically performed.
The restore operation rewrites the bits in the sense amp back
into the storage cells of the activated row of the bank.
Read/Write: While the restore operation takes place, the
sense amp may be read (RD) and written (WR) using
column operations. If new data is written into the sense amp,
it is automatically forwarded to the storage cells of the bank
so the data in the activated row and the data in the sense amp
remain identical.
Precharge: When both the restore operation and the column
operations are completed, the sense amp and bank are
precharged (PRE). This leaves them in the proper state to
begin another activate operation.
and write operations are also performed during the tRAS,MIN
- tRCD,MIN interval (if more than about four column operations are performed, this interval must be increased). The
precharge operation requires the interval tRP,MIN to
complete.
Adjacent Banks: An RDRAM with an “s” designation
(256Kx32sx16/18) indicates it contains “split banks”. This
means the sense amps are shared between two adjacent
banks. The only exception is that sense amp 0, 15, 30, and
31are not shared. When a row in a bank is activated, the two
adjacent sense amps are connected to (associated with) that
bank and are not available for use by the two adjacent banks.
These two adjacent banks must remain precharged while the
selected bank goes through its activate, restore, read/write,
and precharge operations.
For example (referring to the block diagram of Figure 2), if
bank 5 is accessed, sense amp 4/5 and sense amp 5/6 will
both be loaded with one of the 512 rows (with 512 bytes
loaded into each sense amp from the 1Kbyte row - 256 bytes
to the DQA side and 256 bytes to the DQB side). While this
row from bank 5 is being accessed, no rows may be accessed
in banks 4 or 6 because of the sense amp sharing.
Intervals: The activate operation requires the interval
tRCD,MIN to complete. The hidden restore operation requires
the interval tRAS,MIN - tRCD,MIN to complete. Column read
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Direct RDRAM™
K4R271669A/K4R441869A
Precharge Mechanisms
Figure 13 shows an example of precharge with the ROWR
packet mechanism. The PRER command must occur a time
tRAS after the ACT command, and a time tRP before the next
ACT command. This timing will serve as a baseline against
which the other precharge mechanisms can be compared.
a0 = {Da,Ba,Ra}
a5 = {Da,Ba}
b0 = {Da,Ba,Rb}
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47
CTM/CFM
ROW2
..ROW0
ACT a0
PRER a5
ACT b0
COL4
..COL0
tRAS
tRP
DQA8..0
DQB8..0
tRC
Figure 13: Precharge via PRER Command in ROWR Packet
Figure 14 (top) shows an example of precharge with a RDA
command. A bank is activated with an ROWA packet on the
ROW pins. Then, a series of four dualocts are read with RD
commands in COLC packets on the COL pins. The fourth of
these commands is a RDA, which causes the bank to automatically precharge when the final read has finished. The
timing of this automatic precharge is equivalent to a PRER
command in an ROWR packet on the ROW pins that is
offset a time tOFFP from the COLC packet with the RDA
command. The RDA command should be treated as a RD
command in a COLC packet as well as a simultaneous (but
offset) PRER command in an ROWR packet when analyzing
interactions with other packets.
the WR command unless the second COLC contains a RD
command to the same device. This is described in more
detail in Figure 17.
Figure 14 (bottom) shows an example of precharge with a
PREX command in an COLX packet. A bank is activated
with an ROWA packet on the ROW pins. Then, a series of
four dualocts are read with RD commands in COLC packets
on the COL pins. The fourth of these COLC packets
includes an COLX packet with a PREX command. This
causes the bank to precharge with timing equivalent to a
PRER command in an ROWR packet on the ROW pins that
is offset a time tOFFP from the COLX packet with the PREX
command.
Figure 14 (middle) shows an example of precharge with a
WRA command. As in the RDA example, a bank is activated with an ROWA packet on the ROW pins. Then, two
dualocts are written with WR commands in COLC packets
on the COL pins. The second of these commands is a WRA,
which causes the bank to automatically precharge when the
final write has been retired. The timing of this automatic
precharge is equivalent to a PRER command in an ROWR
packet on the ROW pins that is offset a time tOFFP from the
COLC packet that causes the automatic retire. The WRA
command should be treated as a WR command in a COLC
packet as well as a simultaneous (but offset) PRER
command in an ROWR packet when analyzing interactions
with other packets. Note that the automatic retire is triggered
by a COLC packet a time tRTR after the COLC packet with
Page 18
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Direct RDRAM™
K4R271669A/K4R441869A
COLC Packet: RDA Precharge Offset
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47
CTM/CFM
The RDA precharge is equivalent to a PRER command here
ROW2
..ROW0
ACT a0
ACT b0
PRER a5
tOFFP
COL4
..COL0
RD a1
RD a2
RD a3
DQA8..0
DQB8..0
RDA a4
Q (a1)
Transaction a: RD
a0 = {Da,Ba,Ra}
Q (a2)
a1 = {Da,Ba,Ca1}
a3 = {Da,Ba,Ca3}
Q (a3)
Q (a4)
a2 = {Da,Ba,Ca2}
a4 = {Da,Ba,Ca4}
a5 = {Da,Ba}
COLC Packet: WDA Precharge Offset
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47
CTM/CFM
The WRA precharge (triggered by the automatic retire) is equivalent to a PRER command here
ROW2
..ROW0
ACT a0
PRER a5
tRTR
COL4
..COL0
WR a1
WRA a2
tOFFP
retire (a1) retire (a2)
MSK (a1) MSK (a2)
DQA8..0
DQB8..0
D (a1)
Transaction a: WR
ACT b0
a0 = {Da,Ba,Ra}
D (a2)
a1 = {Da,Ba,Ca1}
a2 = {Da,Ba,Ca2}
a5 = {Da,Ba}
COLX Packet: PREX Precharge Offset
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47
CTM/CFM
The PREX precharge command is equivalent to a PRER command here
ROW2
..ROW0
ACT a0
PRER a5
ACT b0
tOFFP
COL4
..COL0
RD a1
RD a2
RD a3
DQA8..0
DQB8..0
RD a4
PREX a5
Q (a1)
Transaction a: RD
a0 = {Da,Ba,Ra}
Q (a2)
a1 = {Da,Ba,Ca1}
a3 = {Da,Ba,Ca3}
Q (a3)
Q (a4)
a2 = {Da,Ba,Ca2}
a4 = {Da,Ba,Ca4}
a5 = {Da,Ba}
Figure 14: Offsets for Alternate Precharge Mechanisms
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Direct RDRAM™
K4R271669A/K4R441869A
Read Transaction - Example
includes the same device and bank address as the a0, a1, and
a2 addresses. The PRER command must occur a time tRAS
or more after the original ACT command (the activation
operation in any DRAM is destructive, and the contents of
the selected row must be restored from the two associated
sense amps of the bank during the tRAS interval). The PRER
command must also occur a time tRDP or more after the last
RD command. Note that the tRDP value shown is greater
than the tRDP,MIN specification in Table 22. This transaction
example reads two dualocts, but there is actually enough
time to read three dualocts before tRDP becomes the limiting
parameter rather than tRAS. If four dualocts were read, the
packet with PRER would need to shift right (be delayed) by
one tCYCLE (note - this case is not shown).
Figure 15 shows an example of a read transaction. It begins
by activating a bank with an ACT a0 command in an ROWA
packet. A time tRCD later a RD a1 command is issued in a
COLC packet. Note that the ACT command includes the
device, bank, and row address (abbreviated as a0) while the
RD command includes device, bank, and column address
(abbreviated as a1). A time tCAC after the RD command the
read data dualoct Q(a1) is returned by the device. Note that
the packets on the ROW and COL pins use the end of the
packet as a timing reference point, while the packets on the
DQA/DQB pins use the beginning of the packet as a timing
reference point.
A time tCC after the first COLC packet on the COL pins a
second is issued. It contains a RD a2 command. The a2
address has the same device and bank address as the a1
address (and a0 address), but a different column address. A
time tCAC after the second RD command a second read data
dualoct Q(a2) is returned by the device.
Finally, an ACT b0 command is issued in an ROWR packet
on the ROW pins. The second ACT command must occur a
time tRC or more after the first ACT command and a time tRP
or more after the PRER command. This ensures that the
bank and its associated sense amps are precharged. This
example assumes that the second transaction has the same
device and bank address as the first transaction, but a
different row address. Transaction b may not be started until
transaction a has finished. However, transactions to other
banks or other devices may be issued during transaction a.
Next, a PRER a3 command is issued in an ROWR packet on
the ROW pins. This causes the bank to precharge so that a
different row may be activated in a subsequent transaction or
so that an adjacent bank may be activated. The a3 address
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47
CTM/CFM
tRC
ROW2
..ROW0
ACT a0
PRER a3
tRAS
COL4
..COL0
RD a1
tRCD
tRP
RD a2
tCC
DQA8..0
DQB8..0
tRDP
Q (a1)
tCAC
Transaction a: RD
Transaction b: xx
ACT b0
a0 = {Da,Ba,Ra}
b0 = {Da,Ba,Rb}
Q (a2)
tCAC
a1 = {Da,Ba,Ca1}
a2 = {Da,Ba,Ca2}
a3 = {Da,Ba}
Figure 15: Read Transaction Example
Page 20
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Direct RDRAM™
K4R271669A/K4R441869A
Write Transaction - Example
the write buffer to retire is delayed, then the COLM packet
(if used) must also be delayed.
Figure 16 shows an example of a write transaction. It begins
by activating a bank with an ACT a0 command in an ROWA
packet. A time tRCD-tRTR later a WR a1 command is issued
in a COLC packet (note that the tRCD interval is measured to
the end of the COLC packet with the first retire command).
Note that the ACT command includes the device, bank, and
row address (abbreviated as a0) while the WR command
includes device, bank, and column address (abbreviated as
a1). A time tCWD after the WR command the write data
dualoct D(a1) is issued. Note that the packets on the ROW
and COL pins use the end of the packet as a timing reference
point, while the packets on the DQA/DQB pins use the
beginning of the packet as a timing reference point.
Next, a PRER a3 command is issued in an ROWR packet on
the ROW pins. This causes the bank to precharge so that a
different row may be activated in a subsequent transaction or
so that an adjacent bank may be activated. The a3 address
includes the same device and bank address as the a0, a1, and
a2 addresses. The PRER command must occur a time tRAS
or more after the original ACT command (the activation
operation in any DRAM is destructive, and the contents of
the selected row must be restored from the two associated
sense amps of the bank during the tRAS interval).
A PRER a3 command is issued in an ROWR packet on the
ROW pins. The PRER command must occur a time tRTP or
more after the last COLC which causes an automatic retire.
A time tCC after the first COLC packet on the COL pins a
second COLC packet is issued. It contains a WR a2
command. The a2 address has the same device and bank
address as the a1 address (and a0 address), but a different
column address. A time tCWD after the second WR
command a second write data dualoct D(a2) is issued.
Finally, an ACT b0 command is issued in an ROWR packet
on the ROW pins. The second ACT command must occur a
time tRC or more after the first ACT command and a time tRP
or more after the PRER command. This ensures that the
bank and its associated sense amps are precharged. This
example assumes that the second transaction has the same
device and bank address as the first transaction, but a
different row address. Transaction b may not be started until
transaction a has finished. However, transactions to other
banks or other devices may be issued during transaction a.
A time tRTR after each WR command an optional COLM
packet MSK (a1) is issued, and at the same time a COLC
packet is issued causing the write buffer to automatically
retire. See Figure 17 for more detail on the write/retire
mechanism. If a COLM packet is not used, all data bytes are
unconditionally written. If the COLC packet which causes
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47
CTM/CFM
tRC
ROW2
..ROW0
ACT a0
PRER a3
tRCD
ACT b0
tRAS
COL4
..COL0
WR a1
WR a2
tRP
retire (a1) retire (a2)
MSK (a1) MSK (a2)
tRTR
DQA8..0
DQB8..0
tRTR
D (a1)
tCC
tRTP
D (a2)
tCWD
tCWD
Transaction a: WR
Transaction b: xx
a0 = {Da,Ba,Ra}
b0 = {Da,Ba,Rb}
a1 = {Da,Ba,Ca1}
a2 = {Da,Ba,Ca2}
a3 = {Da,Ba}
Figure 16: Write Transaction Example
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Direct RDRAM™
K4R271669A/K4R441869A
Write/Retire - Examples
The process of writing a dualoct into a sense amp of an
RDRAM bank occurs in two steps. The first step consists of
transporting the write command, write address, and write
data into the write buffer. The second step happens when the
RDRAM automatically retires the write buffer (with an
optional bytemask) into the sense amp. This two-step write
process reduces the natural turn-around delay due to the
internal bidirectional data pins.
Figure 17 (left) shows an example of this two step process.
The first COLC packet contains the WR command and an
address specifying device, bank and column. The write data
dualoct follows a time tCWD later. This information is loaded
into the write buffer of the specified device. The COLC
packet which follows a time tRTR later will retire the write
buffer. The retire will happen automatically unless (1) a
COLC packet is not framed (no COLC packet is present and
the S bit is zero), or (2) the COLC packet contains a RD
command to the same device. If the retire does not take place
at time tRTR after the original WR command, then the device
continues to frame COLC packets, looking for the first that
is not a RD directed to itself. A bytemask MSK(a1) may be
supplied in a COLM packet aligned with the COLC that
retires the write buffer at time tRTR after the WR command.
The memory controller must be aware of this two-step
write/retire process. Controller performance can be
improved, but only if the controller design accounts for
several side effects.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16T17 T18 T19 T20 T21 T22 T23
CTM/CFM
ROW2
..ROW0
CTM/CFM
Retire is automatic here unless:
(1) No COLC packet (S=0) or
(2) COLC packet is RD to device Da
This RD gets the old data
This RD gets the new data
ROW2
..ROW0
tCAC
tCAC
COL4
..COL0
WR a1
retire (a1)
MSK (a1)
COL4
..COL0
WR a1
tRTR
DQA8..0
DQB8..0
retire (a1)
MSK (a1)
RD c1
tRTR
D (a1)
DQA8..0
DQB8..0
D (a1)
tCWD
Transaction a: WR
RD b1
tCWD
Transaction a: WR
Transaction b: RD
Transaction c: RD
a1= {Da,Ba,Ca1}
Q (b1)
Q (c1)
a1= {Da,Ba,Ca1}
b1= {Da,Ba,Ca1}
c1= {Da,Ba,Ca1}
Figure 17: Normal Retire (left) and Retire/Read Ordering (right)
Figure 17 (right) shows the first of these side effects. The
first COLC packet has a WR command which loads the
address and data into the write buffer. The third COLC
causes an automatic retire of the write buffer to the sense
amp. The second and fourth COLC packets (which bracket
the retire packet) contain RD commands with the same
device, bank and column address as the original WR
command. In other words, the same dualoct address that is
written is read both before and after it is actually retired. The
first RD returns the old dualoct value from the sense amp
before it is overwritten. The second RD returns the new
dualoct value that was just written.
retire operation and MSK(a1) will be delayed by a time
tPACKET as a result. If the RD command used the same bank
and column address as the WR command, the old data from
the sense amp would be returned. If many RD commands to
the same device were issued instead of the single one that is
shown, then the retire operation would be held off an arbitrarily long time. However, once a RD to another device or a
WR or NOCOP to any device is issued, the retire will take
place. Figure 18 (right) illustrates a situation in which the
controller wants to issue a WR-WR-RD COLC packet
sequence, with all commands addressed to the same device,
but addressed to any combination of banks and columns.
Figure 18 (left) shows the result of performing a RD
command to the same device in the same COLC packet slot
that would normally be used for the retire operation. The
read may be to any bank and column address; all that matters
is that it is to the same device as the WR command. The
Page 22
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Write/Retire Examples - continued
Therefore, it is required in this situation that the controller
issue a NOCOP command in the third COLC packet,
delaying the RD command by a time of tPACKET. This situation is explicitly shown in Table 12 for the cases in which
tCCDELAY is equal to tRTR.
The RD will prevent a retire of the first WR from automatically happening. But the first dualoct D(a1) in the write
buffer will be overwritten by the second WR dualoct D(b1)
if the RD command is issued in the third COLC packet.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CTM/CFM
ROW2
..ROW0
CTM/CFM
The retire operation for a write can be
held off by a read to the same device
ROW2
..ROW0
The controller must insert a NOCOP to retire (a1)
to make room for the data (b1) in the write buffer
tCAC
COL4
..COL0
WR a1
RD b1
tCAC
COL4
..COL0
retire (a1)
MSK (a1)
WR a1
WR b1
tRTR + tPACKET
DQA8..0
DQB8..0
retire (a1)
MSK (a1)
RD c1
tRTR
Q (b1)
DQA8..0
D (a1)
D (b1)
D (a1)
DQB8..0
tCWD
Transaction a: WR
Transaction b: RD
tCWD
Transaction a: WR
Transaction b: WR
Transaction c: RD
a1= {Da,Ba,Ca1}
b1= {Da,Bb,Cb1}
a1= {Da,Ba,Ca1}
b1= {Da,Bb,Cb1}
c1= {Da,Bc,Cc1}
Figure 18: Retire Held Off by Read (left) and Controller Forces WWR Gap (right)
buffer only contains the bank and column address, not the
row address. The controller can insure that this doesn’t
happen by never precharging a bank with an unretired write
buffer. Note that in a system with more than one RDRAM,
there will never be more than two RDRAMs with unretired
write buffers. This is because a WR command issued to one
device automatically retires the write buffers of all other
devices written a time tRTR before or earlier.
Figure 19 shows a possible result when a retire is held off for
a long time (an extended version of Figure 18-left). After a
WR command, a series of six RD commands are issued to
the same device (but to any combination of bank and column
addresses). In the meantime, the bank Ba to which the WR
command was originally directed is precharged, and a
different row Rc is activated. When the retire is automatically performed, it is made to this new row, since the write
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47
CTM/CFM
The retire operation puts the
write data in the new row
tRC
ROW2
..ROW0
ACT a0
PRER a2
ACT c0
tRAS
COL4
..COL0
WR a1
tRP
RD b1
tRCD
RD b2
D (a1)
tCWD
Transaction c: WR
RD b4
RD b5
RD b6
retire (a1)
MSK (a1)
tRTR
DQA8..0
DQB8..0
Transaction a: WR
Transaction b: RD
RD b3
a0 = {Da,Ba,Ra}
b1 = {Da,Bb,Cb1}
b4 = {Da,Bb,Cb4}
c0 = {Da,Ba,Rc}
Q (b1)
Q (b2)
Q (b3)
Q (b4)
Q (b5)
tCAC
a1 = {Da,Ba,Ca1}
b2 = {Da,Bb,Cb2}
b5 = {Da,Bb,Cb5}
a2 = {Da,Ba}
b3= {Da,Bb,Cb3}
b6 = {Da,Bb,Cb6}
WARNING
This sequence is hazardous
and must be used with caution
Figure 19: Retire Held Off by Reads to Same Device, Write Buffer Retired to New Row
Page 23
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Interleaved Write - Example
using the WRA autoprecharge option rather than the PRER
command in an ROWR packet on the ROW pins.
Figure 20 shows an example of an interleaved write transaction. Transactions similar to the one presented in Figure 16
are directed to non-adjacent banks of a single RDRAM. This
allows a new transaction to be issued once every tRR interval
rather than once every tRC interval (four times more often).
The DQ data pin efficiency is 100% with this sequence.
In this example, the first transaction is directed to device Da
and bank Ba. The next three transactions are directed to the
same device Da, but need to use different, non-adjacent
banks Bb, Bc, Bd so there is no bank conflict. The fifth
transaction could be redirected back to bank Ba without
interference, since the first transaction would have
completed by then (tRC has elapsed). Each transaction may
use any value of row address (Ra, Rb, ..) and column address
(Ca1, Ca2, Cb1, Cb2, ...).
With two dualocts of data written per transaction, the COL,
DQA, and DQB pins are fully utilized. Banks are precharged
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47
CTM/CFM
Transaction e can use the
same bank as transaction a
tRC
ROW2
..ROW0
ACT a0
ACT b0
ACT c0
ACT d0
tRCD
COL4
..COL0
WR z1
WRA z2
MSK (y1) MSK (y2)
ACT e0
ACT f0
tRR
WR a1
MSK (z1)
WRA a2
WR b1
WRA b2
WR c1
WRA c2
WR d1
MSK (z2) MSK (a1) MSK (a2) MSK (b1) MSK (b2) MSK (c1)
WR d2
WR e1
WR e2
MSK (c2) MSK (d1) MSK (d2)
tCWD
DQA8..0
DQB8..0
D (x2)
D (y1)
D (y2)
Transaction y: WR
Transaction z: WR
Transaction a: WR
Transaction b: WR
Transaction c: WR
Transaction d: WR
Transaction e: WR
Transaction f: WR
D (z1)
D (z2)
D (a1)
y0 = {Da,Ba+4,Ry}
z0 = {Da,Ba+6,Rz}
a0 = {Da,Ba,Ra}
b0 = {Da,Ba+2,Rb}
c0 = {Da,Ba+4,Rc}
d0 = {Da,Ba+6,Rd}
e0 = {Da,Ba,Re}
f0 = {Da,Ba+2,Rf}
D (a2)
D (b1)
y1 = {Da,Ba+4,Cy1}
z1 = {Da,Ba+6,Cz1}
a1 = {Da,Ba,Ca1}
b1 = {Da,Ba+2,Cb1}
c1 = {Da,Ba+4,Cc1}
d1 = {Da,Ba+6,Cd1}
e1 = {Da,Ba,Ce1}
f1 = {Da,Ba+2,Cf1}
D (b2)
D(c1)
y2= {Da,Ba+4,Cy2}
z2= {Da,Ba+6,Cz2}
a2= {Da,Ba,Ca2}
b2= {Da,Ba+2,Cb2}
c2= {Da,Ba+4,Cc2}
d2= {Da,Ba+6,Cd2}
e2= {Da,Ba,Ce2}
f2= {Da,Ba+2,Cf2}
D (c2)
D (d1)
Q (d1)
y3 = {Da,Ba+4}
z3 = {Da,Ba+6}
a3 = {Da,Ba}
b3 = {Da,Ba+2}
c3 = {Da,Ba+4}
d3 = {Da,Ba+6}
e3 = {Da,Ba}
f3 = {Da,Ba+2}
Figure 20: Interleaved Write Transaction with Two Dualoct Data Length
Interleaved Read - Example
Figure 21 shows an example of interleaved read transactions. Transactions similar to the one presented in Figure 15
are directed to non-adjacent banks of a single RDRAM. The
address sequence is identical to the one used in the previous
write example. The DQ data pins efficiency is also 100%.
The only difference with the write example (aside from the
use of the RD command rather than the WR command) is
the use of the PREX command in a COLX packet to
precharge the banks rather than the RDA command. This is
done because the PREX is available for a readtransaction but
is not available for a masked write transaction.
that bubble cycles need to be inserted by the controller at
read/write boundaries. The DQ data pin efficiency for the
example in Figure 22 is 32/42 or 76%. If there were more
RDRAMs on the Channel, the DQ pin efficiency would
approach 32/34 or 94% for the two-dualoct RRWW
sequence (this case is not shown).
In Figure 22, the first bubble type tCBUB1 is inserted by the
controller between a RD and WR command on the COL
pins. This bubble accounts for the round-trip propagation
delay that is seen by read data, and is explained in detail in
Figure 4. This bubble appears on the DQA and DQB pins as
tDBUB1 between a write data dualoct D and read data dualoct
Q. This bubble also appears on the ROW pins as tRBUB1.
Interleaved RRWW - Example
Figure 22 shows a steady-state sequence of 2-dualoct
RD/RD/WR/WR.. transactions directed to non-adjacent
banks of a single RDRAM. This is similar to the interleaved
write and read examples in Figure 20 and Figure 21 except
Page 24
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47
CTM/CFM
Transaction e can use the
same bank as transaction a
tRC
ROW2
..ROW0
ACT a0
ACT b0
ACT c0
ACT d0
ACT e0
tRCD
ACT f0
tRR
COL4
..COL0
RD z1
RD z2
PREX y3
RD a1
RD a2
PREX z3
DQA8..0
DQB8..0
Q (x2)
Q (y1)
Q (y2)
Q (z1)
RD b1
RD b2
PREX a3
RD c1
RD c2
PREX b3
RD d1
RDd2
PREX c3
RD e1
RD e2
PREX d3
Q (a1)
Q (a2)
Q (b1)
Q (b2)
Q (c1)
Q (c2)
Q (d1)
tCAC
Transaction y: RD
Transaction z: RD
Transaction a: RD
Transaction b: RD
Transaction c: RD
Transaction d: RD
Transaction e: RD
Transaction f: RD
Q (z2)
y0 = {Da,Ba+4,Ry}
z0 = {Da,Ba+6,Rz}
a0 = {Da,Ba,Ra}
b0 = {Da,Ba+2,Rb}
c0 = {Da,Ba+4,Rc}
d0 = {Da,Ba+6,Rd}
e0 = {Da,Ba,Re}
f0 = {Da,Ba+2,Rf}
y1 = {Da,Ba+4,Cy1}
z1 = {Da,Ba+6,Cz1}
a1 = {Da,Ba,Ca1}
b1 = {Da,Ba+2,Cb1}
c1 = {Da,Ba+4,Cc1}
d1 = {Da,Ba+6,Cd1}
e1 = {Da,Ba,Ce1}
f1 = {Da,Ba+2,Cf1}
y2= {Da,Ba+4,Cy2}
z2= {Da,Ba+6,Cz2}
a2= {Da,Ba,Ca2}
b2= {Da,Ba+2,Cb2}
c2= {Da,Ba+4,Cc2}
d2= {Da,Ba+6,Cd2}
e2= {Da,Ba,Ce2}
f2= {Da,Ba+2,Cf2}
y3 = {Da,Ba+4}
z3 = {Da,Ba+6}
a3 = {Da,Ba}
b3 = {Da,Ba+2}
c3 = {Da,Ba+4}
d3 = {Da,Ba+6}
e3 = {Da,Ba}
f3 = {Da,Ba+2}
Figure 21: Interleaved Read Transaction with Two Dualoct Data Length
The second bubble type tCBUB2 is inserted (as a NOCOP
command) by the controller between a WR and RD
command on the COL pins when there is a WR-WR-RD
sequence to the same device. This bubble enables write data
to be retired from the write buffer without being lost, and is
explained in detail in Figure 18. There would be no bubble if
address c0 and address d0 were directed to different devices.
This bubble appears on the DQA and DQB pins as tDBUB2
between a write data dualoct D and read data dualoct Q. This
bubble also appears on the ROW pins as tRBUB2.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47
CTM/CFM
ACT a0
ACT b0
tCBUB2
COL4
..COL0
RD z1
tDBUB1
DQA8..0
DQB8..0
Transaction e can use the
same bank as transaction a
tRBUB2
tRBUB1
ROW2
..ROW0
ACT c0
ACT d0
tCBUB2
tCBUB1
RD z2
RD a1
RD a2
PREX z3
WR b1
MSK (y2)
ACT e0
WRA b2
PREX a3
WR c1
WRA c2
NOCOP
MSK (b1) MSK (b2) MSK (c1)
NOCOP
MSK (c2)
tDBUB2
D (y2)
RDf1
tDBUB1
Q (z1)
Transaction y: WR
Transaction z: RD
Transaction a: RD
Transaction b: WR
Transaction c: WR
Transaction d: RD
Transaction e: RD
Transaction f: WR
RDd0
Q (z2)
y0 = {Da,Ba+4,Ry}
z0 = {Da,Ba+6,Rz}
a0 = {Da,Ba,Ra}
b0 = {Da,Ba+2,Rb}
c0 = {Da,Ba+4,Rc}
d0 = {Da,Ba+6,Rd}
e0 = {Da,Ba,Re}
f0 = {Da,Ba+2,Rf}
Q (a1)
Q (a2)
y1 = {Da,Ba+4,Cy1}
z1 = {Da,Ba+6,Cz1}
a1 = {Da,Ba,Ca1}
b1 = {Da,Ba+2,Cb1}
c1 = {Da,Ba+4,Cc1}
d1 = {Da,Ba+6,Cd1}
e1 = {Da,Ba,Ce1}
f1 = {Da,Ba+2,Cf1}
D (b1)
D (b2)
D (c1)
y2= {Da,Ba+4,Cy2}
z2= {Da,Ba+6,Cz2}
a2= {Da,Ba,Ca2}
b2= {Da,Ba+2,Cb2}
c2= {Da,Ba+4,Cc2}
d2= {Da,Ba+6,Cd2}
e2= {Da,Ba,Ce2}
f2= {Da,Ba+2,Cf2}
D (c2)
y3 = {Da,Ba+4}
z3 = {Da,Ba+6}
a3 = {Da,Ba}
b3 = {Da,Ba+2}
c3 = {Da,Ba+4}
d3 = {Da,Ba+6}
e3 = {Da,Ba}
f3 = {Da,Ba+2}
Figure 22: Interleaved RRWW Sequence with Two Dualoct Data Length
Page 25
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Control Register Transactions
SCK (serial clock) and CMD (command) are driven by the
controller to all RDRAMs in parallel. SIO0 and SIO1 are
connected (in a daisy chain fashion) from one RDRAM to
the next. In normal operation, the data on SIO0 is repeated
on SIO1, which connects to SIO0 of the next RDRAM (the
data is repeated from SIO1 to SIO0 for a read data packet).
The controller connects to SIO0 of the first RDRAM.
The RDRAM has two CMOS input pins SCK and CMD and
two CMOS input/output pins SIO0 and SIO1. These provide
serial access to a set of control registers in the RDRAM.
These control registers provide configuration information to
the controller during the initialization process. They also
allow an application to select the appropriate operating mode
of the RDRAM.
SCK
T20
T4
T36
T52
T68
1
0
next transaction
CMD
1
00000000...00000000
1111 0000
00000000...00000000
00000000...00000000
00000000...00000000
1111
0
SIO0
1
SRQ - SWR command
SA
SD
SINT
0
Each packet is repeated
from SIO0 to SIO1
SIO1
SRQ - SWR command
1
SA
SD
SINT
0
Figure 23: Serial Write (SWR) Transaction to Control Register
packet contains a 12 bit address for selecting a control
register.
Write and read transactions are each composed of four
packets, as shown in Figure 23 and Figure 24. Each packet
consists of 16 bits, as summarized in Table 14 and Table 15.
The packet bits are sampled on the falling edge of SCK. A
transaction begins with a SRQ (Serial Request) packet. This
packet is framed with a 11110000 pattern on the CMD input
(note that the CMD bits are sampled on both the falling edge
and the rising edge of SCK). The SRQ packet contains the
SOP3..SOP0 (Serial Opcode) field, which selects the transaction type. The SDEV5..SDEV0 (Serial Device address)
selects one of the 32 RDRAMs. If SBC (Serial Broadcast) is
set, then all RDRAMs are selected. The SA (Serial Address)
SCK
T20
T4
A write transaction has a SD (Serial Data) packet next. This
contains 16 bits of data that is written into the selected
control register. A SINT (Serial Interval) packet is last,
providing some delay for any side-effects to take place. A
read transaction has a SINT packet, then a SD packet. This
provides delay for the selected RDRAM to access the
control register. The SD read data packet travels in the opposite direction (towards the controller) from the other packet
types. The SCK cycle time will accomodate the total delay.
T36
T52
T68
1
0
next transaction
CMD
1
1111 0000
00000000...00000000
00000000...00000000
00000000...00000000
addressed RDRAM drives
0/SD15..SD0/0 on SIO0
SIO0
SRQ - SRD command
SIO1
00000000...00000000
SA
SINT
0
controller drives
0 on SIO0
0
First 3 packets are repeated
from SIO0 to SIO1
SRQ - SRD command
1111
SD
1
0
0
non-addressed RDRAMs pass
0/SD15..SD0/0 from SIO1 to SIO0
SA
SINT
0
SD
1
0
0
Figure 24: Serial Read (SRD) Transaction Control Register
Page 26
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Control Register Packets
T20
T4
1
Table 14 summarizes the formats of the four packet types for
control register transactions. Table 15 summarizes the fields
that are used within the packets.
SCK
0
1
CMD
Figure 25 shows the transaction format for the SETR,
CLRR, and SETF commands. These transactions consist of a
single SRQ packet, rather than four packets like the SWR
and SRD commands. The same framing sequence on the
CMD input is used, however. These commands are used
during initialization prior to any control register read or
write transactions.
00000000...00000000
1111 0000
0
1
SIO0
SRQ packet - SETR/CLRR/SETF
0
The packet is repeated
from SIO0 to SIO1
SIO1
1
SRQ packet - SETR/CLRR/SETF
0
Figure 25: SETR, CLRR,SETF Transaction
Table 14: Control Register Packet Formats
SCK
Cycle
SIO0 or
SIO1
for SRQ
SIO0 or
SIO1
for SA
SIO0 or
SIO1
for SINT
SIO0 or
SIO1
for SD
SCK
Cycle
SIO0 or
SIO1
for SRQ
SIO0 or
SIO1
for SA
SIO0 or
SIO1
for SINT
SIO0 or
SIO1
for SD
0
rsrv
rsrv
0
SD15
8
SOP1
SA7
0
SD7
1
rsrv
rsrv
0
SD14
9
SOP0
SA6
0
SD6
2
rsrv
rsrv
0
SD13
10
SBC
SA5
0
SD5
3
rsrv
rsrv
0
SD12
11
SDEV4
SA4
0
SD4
4
rsrv
SA11
0
SD11
12
SDEV3
SA3
0
SD3
5
SDEV5
SA10
0
SD10
13
SDEV2
SA2
0
SD2
6
SOP3
SA9
0
SD9
14
SDEV1
SA1
0
SD1
7
SOP2
SA8
0
SD8
15
SDEV0
SA0
0
SD0
Table 15: Field Description for Control Register Packets
Field
Description
rsrv
Reserved. Should be driven as “0” by controller.
SOP3..SOP0
0000 - SRD. Serial read of control register {SA11..SA0} of RDRAM {SDEV5..SDEV0}.
0001 - SWR. Serial write of control register {SA11..SA0} of RDRAM {SDEV5..SDEV0}.
0010 - SETR. Set Reset bit, all control registers assume their reset values.a 16 tSCYCLE delay until CLRR command.
0100 - SETF. Set fast (normal) clock mode. 4 tSCYCLE delay until next command.
1011 - CLRR. Clear Reset bit, all control registers retain their reset values.a 4 tSCYCLE delay until next command.
1111 - NOP. No serial operation.
0011, 0101-1010, 1100-1110 - RSRV. Reserved encodings.
SDEV5..SDEV0
Serial device. Compared to SDEVID5..SDEVID0 field of INIT control register field to select the RDRAM to which the transaction is directed.
SBC
Serial broadcast. When set, RDRAMs ignore {SDEV5..SDEV0} for RDRAM selection.
SA11..SA0
Serial address. Selects which control register of the selected RDRAM is read or written.
SD15..SD0
Serial data. The 16 bits of data written to or read from the selected control register of the selected RDRAM.
a. The SETR and CLRR commands must always be applied in two successive transactions to RDRAMs; i.e. they may not be used in isolation. This is called “SETR/CLRR Reset”.
Page 27
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Initialization
(for Channel and RDRAMs) in units of 64ps. The
tCYCLE value is determined in stage 1.0.
ο 3.5 Write SDEVID Register - The SDEVID (serial
T16
T0
device identification) register of each RDRAM is written
with a unique address value so that directed SIO read and
write transactions can be performed. This address value
increases from 0 to 31 according to the distance an
RDRAM is from the ASIC component on the SIO bus (
the closest RDRAM is address 0).
1
SCK
0
1
CMD
00001100
00000000...00000000
0
1
SIO0
The packet is repeated
from SIO0 to SIO1
SIO1
ο 3.6 Write DEVID Register - The DEVID (device iden-
0000000000000000
0
1
0000000000000000
0
Figure 26: SIO Reset Sequence
Initialization refers to the process that a controller must go
through after power is applied to the system or the system is
reset. The controller prepares the RDRAM sub-system for
normal Channel operation by using a sequence of control
register transactions on the serial CMOS pins.The following
steps outline the sequence seen by the various memory
subsystem components (including the RDRAM components) during initialization. This sequence is available in the
form of reference code.
1.0 Start Clocks - This step calculates the proper clock
frequencies for PClk (controller logic), SynClk (RAC
block), RefClk (DRCG component), CTM (RDRAM
component), and SCK ( SIO block).
tification) register of each RDRAM is written with a
unique address value so that directed memory read and
write transactions can be performed. This address value
increases from 0 to 31. The DEVID value is not necessarily the same as the SDEVID value. RDRAMs are
sorted into regions of the same core configuration
(number of bank, row, and column address bits and core
type).
ο 3.7 Write PDNX, PDNXA Registers - The PDNX and
PDNXA registers are written with values that are used to
measure the timing intervals connected with an exit from
the PDN (powerdown) power state.
ο 3.8 Write NAPX Register - The NAPX register is
written with values that are used to measure the timing
intervals connected with an exit from the NAP power
state.
ο 3.9 Write TPARM Register - The TPARM register is
2.0 RAC Initialization - This step causes the INIT block to
generate a sequence of pulses which resets the RAC,
performs RAC maintainance operations, and measures
timing intervals in order to ensure clock stability.
3.0 RDRAM Initialization - This stage performs most of
the steps needed to initialize the RDRAMs. The rest are
performed in stages 5.0, 6.0, and 7.0. All of the Steps in 3.0
are carried out through the SIO block interface.
ο 3.1/3.2 SIO Reset - This reset operation is performed
before any SIO control register read or write transactions.
It clears six registers (TEST34, CCA, CCB, SKIP,
TEST78, and TEST79) and places the INIT register into a
special state (all bits cleared except SRP and SDEVID
fields are set to ones).
ο 3.3 Write TEST77 Register - The TEST77 register
must be explicitly written with zeros before any other
registers are read or written.
written with values which determine the time interval
between a COL packet with a memory read command and
the Q packet with the read data on the Channel. The values
written set each RDRAM to the minimum value permitted
for the system. This will be adjusted later in stage 6.0.
ο 3.10 Write TCDLY1 Register - The TCDLY1 register
is written with values which determine the time interval
between a COL packet with a memory read command and
the Q packet with the read data on the Channel. The values
written set each RDRAM to the minimum value permitted
for the system. This will be adjusted later in stage 6.0.
ο 3.11 Write TFRM Register - The TFRM register is
written with a value that is related to the tRCD parameter
for the system. The tRCD parameter is the time interval
between a ROW packet with an activate command and the
COL packet with a read or write command.
ο 3.12 SETR/CLRR - Each RDRAM is given a SETR
command and a CLRR command through the SIO block.
This sequence performs a second reset operation on the
RDRAMs.
ο 3.4 Write TCYCLE Register - The TCYCLE register
is written with the cycle time tCYCLE of the CTM clock
Page 28
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
ο 3.13 Write CCA and CCB Register - These registers
ο 4.6 Set Bank/Row/Col Address Bits - This step deter-
are written with a value halfway between their minimum
and maximum values. This shortens the time needed for
the RDRAMs to reach their steady-state current control
values in stage 5.0.
mines the number of RDRAM bank, row, and column
address bits that are present in the system. It also determines the RDRAM core types (independent, doubled, or
split) that are present. The ConfigRMC bus is written with
a value that will be compatible with all RDRAM devices
that are present.
ο 3.14 Powerdown Exit - The RDRAMs are in the PDN
power state at this point. A broadcast PDNExit command
is performed by the SIO block to place the RDRAMs in
the RLX (relax) power state in which they are ready to
receive ROW packets.
ο 3.15 SETF - Each RDRAM is given a SETF command
through the SIO block. One of the operations performed
by this step is to generate a value for the AS (autoskip) bit
in the SKIP register and fix the RDRAM to a particular
read domain.
5.0 RDRAM Current Control - This step causes the INIT
block to generate a sequence of pulses which performs
RDRAM maintenance operations.
6.0 RDRAM Core, Read Domain Initialization - This
stage completes the RDRAM initialization
ο 6.1 RDRAM Core Initialization - A sequence of 192
memory refresh transactions is performed in order to place
the cores of all RDRAMs into the proper operating state.
4.0 Controller Configuration - This stage initializes the
controller block. Each step of this stage will set a field of the
ConfigRMC[63:0] bus to the appropriate value. Other
controller implementations will have similar initialization
requirements, and this stage may be used as a guide.
ο 6.2 RDRAM Read Domain Initialization - A memory
write and memory read transaction is performed to each
RDRAM to determine which read domain each RDRAM
occupies. The programmed delay of each RDRAM is then
adjusted so the total RDRAM read delay (propagation
delay plus programmed delay) is constant. The TPARM
and TCDLYI registers of each RDRAM are rewritten with
the appropriate read delay values. The ConfigRMC bus is
also rewritten with an updated value.
ο 4.1 Initial Read Data Offsets - The configRMC bus is
written with a value which determines the time interval
between a COL packet with a memory read command and
the Q packet with the read data on the Channel. The value
written sets RMC.d1 to the minimum value permitted for
the system. This will be adjusted later in stage 6.0.
ο 4.2 Configure Row/Column Timing - This step deter-
mines the values of the tRAS,MIN, tRP,MIN, tRC,MIN,
tRCD,MIN, tRR,MIN, and tPP,MIN RDRAM timing parameters that are present in the system. The ConfigRMC bus is
written with values that will be compatible with all
RDRAM devices that are present.
ο 4.3 Set Refresh Interval - This step determines the
values of the tREF,MAX RDRAM timing parameter that are
present in the system. The ConfigRMC bus is written with
a value that will be compatible with all RDRAM devices
that are present.
ο 4.4 Set Current Control Interval - This step deter-
mines the values of the tCCTRL,MAX RDRAM timing
parameter that are present in the system. The ConfigRMC
bus is written with value that will be compatible with all
RDRAM devices that are present.
ο 4.5 Set Slew Rate Control Interval - This step deter-
mines the values of the tTEMP,MAX RDRAM timing
parameter that are present in the system. The ConfigRMC
bus is written with a value that will be compatible with all
RDRAM devices that are present.
7.0 Other RDRAM Register Fields - This stage rewrites
the INIT register with the final values of the LSR,NSR, and
PSR fields.
In essence, the controller must read all the read-only configuration registers of all RDRAMs (or it must read the SPD
device present on each RIMM), it must process this information, and then it must write all the read-write registers to
place the RDRAMs into the proper operating mode.
Initialization Note [1]: During the initialization process, it is
necessary for the controller to perform 128 current control
operations (3xCAL, 1xCAL/SAM) and one temperature
calibrate operation (TCEN/TCAL) after reset or after powerdown (PDN)exit.
Initialization Note [2]: There is a class of 72Mbit RDRAM .
They are distinguished by the “S28IECO” bit in the SPD.
The behavior of the RDRAM at initialization is slightly
different for the two types:
S28IECO=0: Upon powerup the device enters ATTN state.
The serial operations SETR, CLRR and SETF are performed
without requiring a SDEVID match of the SBC bit (broadcast) to be set.
Page 29
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
S28IECO=1: Upon powerup the device enters PDN state.
The serial operations SETR, CLRR, and SETF require a
SDEVID match.
Initialization Note [5]: The CLRR command (in the serial
SRQ packet) leaves some of the contents of the memory
core in an indeterminate state.
See the document detailing the reference initialization procedure for more information on how to handle this in a system.
Control Register Summary
Initialization Note [3]: After the step of equalizing the total
read delay of each RDRAM has been completed (i.e.after the
TCDLY0 and TCDLY1 fields have been written for the final
time), a single final memory read transaction should be
made to each RDRAM in order to ensure that the output
pipeline stages have been cleared.
Initialization Note [4]: The SETF command (in the serial
SRQ packet) should only be issued once during the Initialization process, as should the SETR and CLRR commands.
Table 16 summarizes the RDRAM control registers. Detail
is provided for each control register in Figure 27 through
Figure 43. Read-only bits which are shaded gray are unused
and return zero. Read-write bits which are shaded gray are
reserved and should always be written with zero. The RIMM
SPD Application Note describes additional read-only
configuration registers which are present on Direct RIMMs.
The state of the register fields are potentially affected by the
IO Reset operation or the SETR/CLRR operation. This is
indicated in the text accompanying each register diagram.
Table 16: Control Register Summary
SA11..SA0
Register
Field
read-write/ read-only
Description
02116
INIT
SDEVID
read-write, 6 bits
Serial device ID. Device address for control register read/write.
PSX
read-write, 1 bit
Power select exit. PDN/NAP exit with device addr on DQA5..0.
SRP
read-write, 1 bit
SIO repeater. Used to initialize RDRAM.
NSR
read-write, 1 bit
NAP self-refresh. Enables self-refresh in NAP mode.
PSR
read-write, 1 bit
PDN self-refresh. Enables self-refresh in PDN mode.
LSR
read-write, 1 bit
Low power self-refresh. Enables low power self-refresh.
TEN
read-write, 1 bit
Temperature sensing enable.
TSQ
read-write, 1 bit
Temperature sensing output.
DIS
read-write, 1 bit
RDRAM disable.
02216
TEST34
TEST34
read-write, 16 bits
Test register. Do not read or write after SIO reset.
02316
CNFGA
REFBIT
read-only, 3 bit
Refresh bank bits. Used for multi-bank refresh.
DBL
read-only, 1 bit
Double. Specifies doubled-bank architecture
MVER
read-only, 6 bit
Manufacturer version. Manufacturer identification number.
PVER
read-only, 6 bit
Protocol version. Specifies version of Direct protocol supported.
BYT
read-only, 1 bit
Byte. Specifies an 8-bit or 9-bit byte size.
DEVTYP
read-only, 3 bit
Device type. Device can be RDRAM or some other device category.
SPT
read-only, 1 bit
Split-core. Each core half is an individual dependent core.
CORG
read-only, 6 bit
Core organization. Bank, row, column address field sizes.
SVER
read-only, 6 bit
Stepping version. Mask version number.
02416
CNFGB
04016
DEVID
DEVID
read-write, 5 bits
Device ID. Device address for memory read/write.
04116
REFB
REFB
read-write, 4 bits
Refresh bank. Next bank to be refreshed by self-refresh.
04216
REFR
REFR
read-write, 9 bits
Refresh row. Next row to be refreshed by REFA, self-refresh.
04316
CCA
CCA
read-write, 7 bits
Current control A. Controls IOL output current for DQA.
ASYMA
read-write, 2 bits
Asymmetry control. Controls asymmetry of VOL/VOH swing for DQA.
CCB
read-write, 7 bits
Current control B. Controls IOL output current for DQB.
ASYMB
read-write, 2 bits
Asymmetry control. Controls asymmetry of VOL/VOH swing for DQB.
04416
CCB
Page 30
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Table 16: Control Register Summary
SA11..SA0
Register
Field
read-write/ read-only
Description
04516
NAPX
NAPXA
read-write, 5 bits
NAP exit. Specifies length of NAP exit phase A.
NAPX
read-write, 5 bits
NAP exit. Specifies length of NAP exit phase A + phase B.
DQS
read-write, 1 bits
DQ select. Selects CMD framing for NAP/PDN exit.
04616
PDNXA
PDNXA
read-write, 13 bits
PDN exit. Specifies length of PDN exit phase A.
04716
PDNX
PDNX
read-write, 13 bits
PDN exit. Specifies length of PDN exit phase A + phase B.
04816
TPARM
TCAS
read-write, 2 bits
tCAS-C core parameter. Determines tOFFP datasheet parameter.
TCLS
read-write, 2 bits
tCLS-C core parameter. Determines tCAC and tOFFP parameters.
TCDLY0
read-write, 3 bits
tCDLY0-C core parameter. Programmable delay for read data.
04916
TFRM
TFRM
read-write, 4 bits
tFRM-C core parameter. Determines ROW-COL packet framing interval.
04a16
TCDLY1
TCDLY1
read-write, 3 bits
tCDLY1-C core parameter. Programmable delay for read data.
04b16
SKIP
AS
read, 1 bit
Auto Skip value established by the SETF command.
MSE
read-write, 1 bit
Manual Skip Enable. Allows the MS value to override the AS value.
MS
read-write, 1 bit
Manual Skip value.
04c16
TCYCLE
TCYCLE
read-write, 14 bits
tCYCLE datasheet parameter. Specifies cycle time in 64ps units.
04d16
TEST77
TEST77
read-write, 16 bits
Test register. Write with zero after SIO reset.
04e16
TEST78
TEST78
read-write, 16 bits
Test register. Do not read or write after SIO reset.
04f16
TEST79
TEST79
read-write, 16 bits
Test register. Do not read or write after SIO reset.
08016 - 0ff16
reserved
reserved
vendor-specific
Vendor-specific test registers. Do not read or write after SIO reset.
. .
Page 31
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Control Register: INIT
15 14 13 12 11 10 9
0
8
7
Address: 02116
6
SDE
VID DIS TSQ TEN LSR PSR NSR SRP PSX
5
5
4
3
2
1
0
0
SDEVID4..SDEVID0
Read/write register.
Reset values are undefined except as affected by SIO Reset as noted
below. SETR/CLRR Reset does not affect this register.
SDEVID5..0 - Serial Device Identification. Compared to SDEV5..0
serial address field of serial request packet for register read/write transactions. This determines which RDRAM is selected for the register read or
write operation. SDEVID resets to 3f16.
PSX - Power Exit Select. PDN and NAP are exited with (=0) or without (=1) a device address on the
DQA5..0 pins. PDEV5 (on DQA5) selectes broadcast (1) or directed (0) exit. For a directed exit,
PDEV4..0 (on DQA4..0) is compared to DEVID4..0 to select a device.
SRP - SIO Repeater. Controls value on SIO1; SIO1=SIO0 if SRP=1, SIO1=1 if SRP=0. SRP resets
to 1.
NAP Self-Refresh. NSR=1 enables self-refresh in NAP mode. NSR can’t be set while in NAP
mode. NSR resets to 0.
PDN Self-Refresh. PSR=1 enables self-refresh in PDN mode. PSR can’t be set while in PDN mode.
PSR resets to 0.
Low Power Self-Refresh. LSR=1 enables longer self-refresh interval. The self-refresh supply
current is reduced. LSR resets to 0.
Temperature Sensing Enable. TEN=1 enables temperature sensing circuitry, permitting the TSQ bit
to be read to determine if a thermal trip point has been exceeded. TEN resets to 0.
Temperature Sensing Output. TSQ=1 when a temperature trip point has been exceeded, TSQ=0
when it has not. TSQ is available during a current control operation (see Figure 51).
RDRAM Disable. DIS=1 causes RDRAM to ignore NAP/PDN exit sequence, DIS=0 permits
Figure 27: INIT Register
Control Register: CNFGA
15 14 13 12 11 10 9
PVER5..0
= 000001
8
7
6
MVER5..0
= 010000
5
Address: 02316
Read-only register.
4
REFBIT2..0 - Refresh Bank Bits. Specifies the number of
bank address bits used by REFA and REFP commands.
Permits multi-bank refresh in future RDRAMs.
3
2
1
0
DBL REFBIT2..0
1
= 101
DBL - Doubled-Bank. DBL=1 means the device uses a
doubled-bank architecture with adjacent-bank dependency.
DBL=0 means no dependency.
MVER5..0 - Manufacturer Version. Specifies the manufacturer identification number.
PVER5..0 - Protocol Version. Specifies the Direct Protocol
version used by this device:
0 - Compliant with version 0.62.
1 - Compliant with version 0.7 through this version.
2 to 63 - Reserved.
Note: In RDRAMs with protocol version 1 PVER[5:0] = 000001, the
range of the PDNX field (PDNX[2:0] in the PDNX register) may not
be large enough to specify the location of the restricted interval in
Figure 47. In this case, the effective tS4 parameter must increase and
no row or column packets may overlap the restricted interval. See
Figure 47 and Table 19.
Figure 28: CNFGA Register
Page 32
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Control Register: CNFGB
15 14 13 12 11 10 9
SVER5..0
= 00000
8
7
Address: 02416
6
5
CORG4..0
= 00100
4
3
2
1
0
SPT DEVTYP2..0 BYT
1
= 000
B
..
Read-only register.
BYT - Byte width. B=1 means the device reads and
writes 9-bit memory bytes. B=0 means 8 bits.
DEVTYP2..0 - Device type. DEVTYP = 000 means
that this device is an RDRAM.
SPT - Split-core. SPT=1 means the core is split, SPT=0 means it is not.
CORG4..0 - Core organization. This field specifies the number of bank
(5 bits), row (9 bits), and column (6 bits) address bits.
SVER5..0 - Stepping version. Specifies the mask version number of this
device.
Figure 29: CNFGB Register
Control Register: TEST34
Control Register: DEVID
Address: 02216
Address: 04016
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10 9
8
7
6
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
3
2
1
0
DEVID4..DEVID0
Read/write register.
Reset value of TEST34 is zero (from SIO Reset)
This register are used for testing purposes. It must not
be read or written after SIO Reset.
Read/write register.
Reset value is undefined.
Device Identification register.
DEVID4..DEVID0 is compared to DR4..DR0,
DC4..DC0, and DX4..DX0 fields for all memory read
or write transactions. This determines which RDRAM
is selected for the memory read or write transaction.
Figure 30: TEST Register
Figure 31: DEVID Register
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Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Control Register: REFB
15 14 13 12 11 10 9
8
7
6
5
0
0
0
0
0
0
0
0
0
0
0
Control Register: REFR
Address: 04116
4
3
2
1
0
15 14 13 12 11 10 9
0
REFB4..REFB0
0
0
0
0
0
8
7
Address: 04216
6
0
5
4
3
2
1
0
REFR8..REFR0
Read/write register.
Reset value is zero (from SETR/CLRR).
Refresh Bank register.
REFB4..REFB0 is the bank that will be refreshed next
during self-refresh. REFB4..0 is incremented after each
self-refresh activate and precharge operation pair.
Read/write register.
Reset value is zero (from SETR/CLRR).
Refresh Row register.
REFR8..REFR0 is the row that will be refreshed next
by the REFA command or by self-refresh. REFR8..0 is
incremented when BR4..0=11111 for the REFA
command. REFR8..0 is incremented when
REFB4..0=11111 for self-refresh.
Figure 32: REFB Register
Figure 34: REFR Register
Control Register: CCA
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
ASYMA
0 0
Control Register: CCB
Address: 04316
6
5
4
3
2
1
0
15 14 13 12 11 10 9
0
CCA6..CCA0
0
0
0
0
0
0
8
7
ASYMB
0 0
Address: 04416
6
5
4
3
2
1
0
CCB6.CCB0
Read/write register.
Reset value is zero (SETR/CLRR or SIO Reset).
CCA6..CCA0 - Current Control A. Controls the IOL
output current for the DQA8..DQA0 pins.
Read/write register.
Reset value is zero (SETR/CLRR or SIO Reset).
CCB6..CCB0 - Current Control B. Controls the IOL
output current for the DQB8..DQB0 pins.
ASYMA0 control the asymmetry of the VOL/VOH
voltage swing about the VREF reference voltage for the
DQA8..0 pins.
ASYMB0 control the asymmetry of the VOL/VOH
voltage swing about the VREF reference voltage for the
DQB8..0 pins.
Figure 33: CCA Register
Figure 35: CCB Register
Page 34
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Control Register: NAPX
15 14 13 12 11 10 9
0
0
0
0
0
DQS
8
7
Address: 04516
6
5
4
NAPX4..0
3
2
1
0
NAPXA4..0
.
Read/write register.
Reset value is undefined
Note - tSCYCLE is tCYCLE1 (SCK cycle time).
NAPXA4..0 - Nap Exit Phase A. This field specifies
the number of SCK cycles during the first phase for
exiting NAP mode. It must satisfy:
NAPXA•t SCYCLE ≥ tNAPXA,MAX
Do not set this field to zero.
NAPX4..0 - Nap Exit Phase A plus B. This field specifies the number of SCK
cycles during the first plus second phases for exiting NAP mode. It must satisfy:
NAPX•t SCYCLE ≥ NAPXA•t SCYCLE+tNAPXB,MAX
Do not set this field to zero.
DQS - DQ Select. This field specifies the number of SCK cycles (0 => 0.5
cycles, 1 => 1.5 cycles) between the CMD pin framing sequence and the device
selection on DQ5..0. See Figure 48 - This field must be written with a ″1″ for
this RDRAM.
Figure 36: NAPX Register
Control Register: PDNXA
15 14 13 12 11 10 9
0
0
0
8
7
Control Register: PDNX
Address: 04616
6
5
4
3
2
1
0
15 14 13 12 11 10 9
0
PDNXA12..0
Read/write register.
Reset value is undefined
PDNXA4..0 - PDN Exit Phase A. This field specifies
the number of (64•SCK cycle) units during the first
phase for exiting PDN mode. It must satisfy:
PDNXA•64•t SCYCLE ≥ tPDNXA,MAX
Do not set this field to zero.
Note - only PDNXA5..0 are implemented.
Note - tSCYCLE is tCYCLE1 (SCK cycle time).
0
0
8
7
Address: 04716
6
5
4
3
2
1
0
PDNX12..0
Read/write register.
Reset value is undefined
PDNX4..0 - PDN Exit Phase A plus B. This field specifies the number of (256•SCK cycle) units during the
first plus second phases for exiting PDN mode. It must
satisfy:
PDNX•256•t SCYCLE ≥ PDNXA•64•t SCYCLE+
tPDNXB,MAX
If this equation can’t be satisfied, then the maximum
PDNX value should be written, and the tS4/tH4 timing
window will be modified (see Figure 49)
Do not set this field to zero.
Note - only PDNX2..0 are implemented.
Note - tSCYCLE is tCYCLE1 (SCK cycle time).
Figure 37: PDNXA Register
Figure 38: PDNX Register
Page 35
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Control Register: TPARM
15 14 13 12 11 10 9
8
7
0
0
0
0
0
0
0
0
0
Address: 04816
6
5
4
TCDLY0
3
2
TCLS
1
0
TCAS
Read/write register.
Reset value is undefined.
TCAS1..0 - Specifies the tCAS-C core parameter in
tCYCLE units. This should be “10” (2•tCYCLE).
.
The equations relating the core parameters to the
datasheet parameters follow:
tCAS-C = 2•tCYCLE
tCLS-C = 2•tCYCLE
tCPS-C = 1•tCYCLE
Not programmable
tOFFP = tCPS-C + tCAS-C + tCLS-C - 1•tCYCLE
= 4•tCYCLE
tRCD = tRCD-C + 1•tCYCLE - tCLS-C
= tRCD-C - 1•tCYCLE
TCLS1..0 - Specifies the tCLS-C core parameter in
tCYCLE units. Should be “10” (2•tCYCLE).
TCDLY0 - Specifies the tCDLY0-C core parameter in
tCYCLE units. This adds a programmable delay to Q
(read data) packets, permitting round trip read delay to
all devices to be equalized. This field may be written
with the values “011” (3•tCYCLE) through “101”
(5•tCYCLE).
tCAC = 3•tCYCLE + tCLS-C + tCDLY0-C + tCDLY1-C
(see table below for programming ranges)
TCDLY0
tCDLY0-C
011
3•t CYCLE
TCDLY1 tCDLY1-C
000
0•tCYCLE
011
3•t CYCLE
001
1•tCYCLE
9•tCYCLE
011
3•t CYCLE
010
2•tCYCLE
10•tCYCLE
100
4•t CYCLE
010
2•tCYCLE
11•tCYCLE
101
5•t CYCLE
010
2•tCYCLE
12•tCYCLE
tCAC
8•tCYCLE
Figure 39: TPARM Register
Control Register: TFRM
15 14 13 12 11 10 9
8
7
6
5
4
0
0
0
0
0
0
0
0
0
0
0
0
Control Register: TCDLY1
Address: 04916
3
2
1
0
TFRM3..0
Address: 04a16
15 14 13 12 11 10 9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
0
0
0
2
1
0
TCDLY1
Read/write register.
Reset value is undefined.
TFRM3..0 - Specifies the position of the framing point
in tCYCLE units. This value must be greater than or
equal to the tFRM,MIN parameter. This is the minimum
offset between a ROW packet (which places a device
at ATTN) and the first COL packet (directed to that
device) which must be framed. This field may be
written with the values “0111” (7•tCYCLE) through
“1010” (10•tCYCLE). TFRM is usually set to the value
which matches the largest tRCD,MIN parameter (modulo
4•tCYCLE) that is present in an RDRAM in the memory
system. Thus, if an RDRAM with tRCD,MIN =
9•tCYCLE were present, then TFRM would be
programmed to 5•tCYCLE.
Read/write register.
Reset value is undefined.
TCDLY1 - Specifies the value of the tCDLY1-C core
parameter in tCYCLE units. This adds a programmable
delay to Q (read data) packets, permitting round trip
read delay to all devices to be equalized. This field may
be written with the values “000” (0•tCYCLE) through
“010” (2•tCYCLE). Refer to Figure 39 for more details.
Figure 40: TFRM Register
Figure 41: TRDLY Register
Page 36
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Control Register: SKIP
Address: 04b16
Control Register: TCYCLE
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10 9
0
0
0
0
0
0
0
0
0
0
0
0
0
AS MSE MS
0
Read/write register (except AS field).
Reset value is zero (SIO Reset).
AS - Autoskip. Read-only value determined by
autoskip circuit and stored when SETF serial command
is received by RDRAM during initialization. In figure
58, AS=1 corresponds to the early Q(a1) packet and
AS=0 to the Q(a1) packet one tCYCLE later for the four
uncertain cases.
MSE - Manual skip enable (0=auto, 1=manual).
MS - Manual skip (MS must be 1 when MSE=1).>
During initialization, the RDRAMs at the furthest point
in the fifth read domain may have selected the AS=0
value, placing them at the closest point in a sixth read
domain. Setting the MSE/MS fields to 1/1 overrides
the autoskip value and returns them to the furthest
point of the fifth read domain.
Address: 04d16
Control Register: TEST78
Address: 04e16
Control Register: TEST79
Address: 04f16
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
Figure 44: TCYCLE Register
Control Register: TEST77
0
8
TCYCLE13..TCYCLE0
Read/write register.
Reset value is undefined
TCYCLE13..0 - Specifies the value of the tCYCLE
datasheet parameter in 64ps units. For the tCYCLE,MIN
of 2.5ns (2500ps), this field should be written with the
value “0002716” (39•64ps).
Figure 42: SKIP Register
0
0
Address: 04c16
Read/write registers.
Reset value of TEST78,79 is zero ( SIO Reset).
Do not read or write TEST78,79 after SIO reset.
TEST77 must be written with zero after SIO reset.
These registers must only be used for testing purposes.
Figure 43: TEST Registers
Page 37
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Power State Management
TCLK/RCLK block must resynchronize itself to the external
clock signal.
Table 17 summarizes the power states available to a Direct
RDRAM. In general, the lowest power states have the
longest operational latencies. For example, the relative
power levels of PDN state and STBY state have a ratio of
about 1:110, and the relative access latencies to get read data
have a ratio of about 250:1.
PDN state is the lowest power state available. The information in the RDRAM core is usually maintained with selfrefresh; an internal timer automatically refreshes all rows of
all banks. PDN has a relatively long exit latency because the
NAP state is another low-power state in which either selfrefresh or REFA-refresh are used to maintain the core. See
“Refresh” on page 42 for a description of the two refresh
mechanisms. NAP has a shorter exit latency than PDN
because the TCLK/RCLK block maintains its synchronization state relative to the external clock signal at the time of
NAP entry. This imposes a limit (tNLIMIT) on how long an
RDRAM may remain in NAP state before briefly returning
to STBY or ATTN to update this synchronization state.
Table 17: Power State Summary
Power
State
Description
Power
State
Blocks consuming power
Description
Blocks consuming power
PDN
Powerdown state.
Self-refresh
NAP
Nap state. Similar to PDN
except lower wake-up
latency.
Self-refresh or
REFA-refresh
TCLK/RCLK-Nap
STBY
Standby state.
Ready for ROW
packets.
REFA-refresh
TCLK/RCLK
ROW demux receiver
ATTN
Attention state.
Ready for ROW and COL
packets.
REFA-refresh
TCLK/RCLK
ROW demux receiver
COL demux receiver
ATTNR
Attention read state.
Ready for ROW and COL
packets.
Sending Q (read data)
packets.
REFA-refresh
TCLK/RCLK
ROW demux receiver
COL demux receiver
DQ mux transmitter
Core power
ATTNW
Attention write state.
Ready for ROW and COL
packets.
Ready for D (write data)
packets.
REFA-refresh
TCLK/RCLK
ROW demux receiver
COL demux receiver
DQ demux receiver
Core power
Figure 45 summarizes the transition conditions needed for
moving between the various power states. Note that NAP
and PDN have been divided into two substates (NAPA/NAP-S and PDN-A/PDN-S) to account for the fact that a
NAP or PDN exit may be made to either ATTN or STBY
states.
At initialization, the SETR/CLRR Reset sequence will put
the RDRAM into PDN-S state. The PDN exit sequence
involves an optional PDEV specification and bits on the
CMD and SIOIN pins.
Once the RDRAM is in STBY, it will move to the
ATTN/ATTNR/ATTNW states when it receives a nonbroadcast ROWA packet or non-broadcast ROWR packet
with the ATTN command. The RDRAM returns to STBY
from these three states when it receives a RLX command.
Alternatively, it may enter NAP or PDN state from ATTN or
STBY states with a NAPR or PDNR command in an ROWR
packet. The PDN or NAP exit sequence involves an optional
PDEV specification and bits on the CMD and SIO0 pins.
The RDRAM returns to the ATTN or STBY state it was
originally in when it first entered NAP or PDN.
An RDRAM may only remain in NAP state for a time
tNLIMIT. It must periodically return to ATTN or STBY.
The NAPRC command causes a napdown operation if the
RDRAM’s NCBIT is set. The NCBIT is not directly visible.
It is undefined on reset. It is set by a NAPR command to the
RDRAM, and it is cleared by an ACT command to the
RDRAM. It permits a controller to manage a set of
RDRAMs in a mixture of power states.
STBY state is the normal idle state of the RDRAM. In this
state all banks and sense amps have usually been left
precharged and ROWA and ROWR packets on the ROW
pins are being monitored. When a non-broadcast ROWA
packet or non-broadcast ROWR packet (with the ATTN
command) packet addressed to the RDRAM is seen, the
RDRAM enters ATTN state (see the right side of Figure 46).
This requires a time tSA during which the RDRAM activates
the specified row of the specified bank. A time
TFRM•tCYCLE after the ROW packet, the RDRAM will be
Page 38
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
able to frame COL packets (TFRM is a control register field
- see Figure 40). Once in ATTN state, the RDRAM will
automatically transition to the ATTNW and ATTNR states
as it receives WR and RD commands.
automatic
ATTNR
ATTNW
automatic
automatic
automatic
automatic
automatic
RLX
tNLIMIT
NAPR • RLXR
NAP-A
PDEV.CMD•SIO0
NAP
The RDRAM may be in ATTN or STBY state when the
PDNR command is issued. When PDN state is exited, the
RDRAM will return to the original starting state (ATTN or
STBY). If it is in ATTN state and a RLXR command is
specified with PDNR, then the RDRAM will return to STBY
state when PDN is exited. The current- and slew-rate-control
levels are re-established.
NAP-S
PDEV.CMD•SIO0
PDNR • RLXR
PDN-A
PDEV.CMD•SIO0
PDNR • RLXR
PDN
NAPR
PDNR
PDN-S
ATTN
The RDRAM may be in ATTN or STBY state when the
NAPR command is issued. When NAP state is exited, the
RDRAM will return to the original starting state (ATTN or
STBY). If it is in ATTN state and a RLXR command is
specified with NAPR, then the RDRAM will return to STBY
state when NAP is exited.
Figure 47 also shows the PDN entry sequence (right). PDN
state is entered by sending a PDNR command in a ROW
packet. A time tASP is required to enter PDN state (this specification is provided for power calculation purposes). The
clock on CTM/CFM must remain stable for a time tCD after
the PDNR command.
ATTN
NAPR • RLXR
provided for power calculation purposes). The clock on
CTM/CFM must remain stable for a time tCD after the
NAPR command.
PDEV.CMD•SIO0
The RDRAM’s write buffer must be retired with the appropriate COP command before NAP or PDN are entered. Also,
all the RDRAM’s banks must be precharged before NAP or
PDN are entered. The exception to this is if NAP is entered
with the NSR bit of the INIT register cleared (disabling selfrefresh in NAP). The commands for relaxing, retiring, and
precharging may be given to the RDRAM as late as the
ROPa0, COPa0, and XOPa0 packets in Figure 47. No broadcast packets nor packets directed to the RDRAM entering
Nap or PDN may overlay the quiet window. This window
extends for a time tNPQ after the packet with the NAPR or
PDNR command.
SETR/CLRR
STBY
Notation:
SETR/CLRR - SETR/CLRR Reset sequence in SRQ packets
PDNR - PDNR command in ROWR packet
NAPR - NAPR command in ROWR packet
RLXR - RLX command in ROWR packet
RLX - RLX command in ROWR,COLC,COLX packets
SIO0 - SIO0 input value
PDEV.CMD - (PDEV=DEVID)•(CMD=01)
ATTN - ROWA packet (non-broadcast) or ROWR packet
(non-broadcast) with ATTN command
Figure 45: Power State Transition Diagram
Once the RDRAM is in ATTN, ATTNW, or ATTNR states,
it will remain there until it is explicitly returned to the STBY
state with a RLX command. A RLX command may be given
in an ROWR, COLC , or COLX packet (see the left side of
Figure 46). It is usually given after all banks of the RDRAM
have been precharged; if other banks are still activated, then
the RLX command would probably not be given.
If a broadcast ROWA packet or ROWR packet (with the
ATTN command) is received, the RDRAM’s power state
doesn’t change. If a broadcast ROWR packet with RLXR
command is received, the RDRAM goes to STBY.
Figure 47 shows the NAP entry sequence (left). NAP state is
entered by sending a NAPR command in a ROW packet. A
time tASN is required to enter NAP state (this specification is
Figure 48 shows the NAP and PDN exit sequences. These
sequences are virtually identical; the minor differences will
be highlighted in the following description.
Before NAP or PDN exit, the CTM/CFM clock must be
stable for a time tCE. Then, on a falling and rising edge of
SCK, if there is a “01” on the CMD input, NAP or PDN state
will be exited. Also, on the falling SCK edge the SIO0 input
must be at a 0 for NAP exit and 1 for PDN exit.
If the PSX bit of the INIT register is 0, then a device
PDEV5..0 is specified for NAP or PDN exit on the DQA5..0
pins. This value is driven on the rising SCK edge 0.5 or 1.5
SCK cycles after the original falling edge, depending upon
the value of the DQS bit of the NAPX register. If the PSX bit
of the INIT register is 1, then the RDRAM ignores the
Page 39
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
PDEV5..0 address packet and exits NAP or PDN when the
wake-up sequence is presented on the CMD wire. The ROW
and COL pins must be quiet at a time tS4/tH4 around the indicated falling SCK edge (timed with the PDNX or NAPX
register fields). After that, ROW and COL packets may be
directed to the RDRAM which is now in ATTN or STBY
state.
Figure 49 shows the constraints for entering and exiting
NAP and PDN states. On the left side, an RDRAM exits
NAP state at the end of cycle T3. This RDRAM may not reenter NAP or PDN state for an interval of tNU0. The
RDRAM enters NAP state at the end of cycle T13. This
RDRAM may not re-exit NAP state for an interval of tNU1.
The equations for these two parameters depend upon a
number of factors, and are shown at the bottom of the figure.
NAPX is the value in the NAPX field in the NAPX register.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16T17 T18 T19 T20 T21 T22 T23
CTM/CFM
ROW2
..ROW0
CTM/CFM
ROW2
..ROW0
RLXR
COL4
..COL0
ROP = non-broadcast ROWA
or ROWR/ATTN
a0 = {d0,b0,r0}
a1 = {d1,b1,c1}
ROP a0
COP a1
COP a1
XOP a1
COP a1
XOP a1
COP a1
COP a0
XOP a1
XOP a1
XOP a0
COL4
..COL0
RLXC
RLXX
TFRM•t CYCLE
DQA8..0
DQB8..0
DQA8..0
DQB8..0
tAS
Power
State
tSA
ATTN
STBY
Power
State
STBY
ATTN
No COL packets may be
placed in the three
indicated positions; i.e. at
(TFRM - {1,2,3})•t CYCLE.
A COL packet to device d0
(or any other device) is okay
at
(TFRM)•t CYCLE
or later.
A COL packet to another
device (d1!= d0) is okay at
(TFRM - 4)•t CYCLE
or earlier.
Figure 46: STBY Entry (left) and STBY Exit (right)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16T17 T18 T19 T20 T21 T22 T23
CTM/CFM
CTM/CFM
a0 = {d0,b0,r0,c0}
a1 = {d1,b1,r1,c1}
tCD
ROW2
..ROW0
ROP a0
(NAPR)
restricted
COL4
..COL0
COP a0
XOP a0
restricted
quiet
tCD
ROP a1
ROW2
..ROW0
ROP a0
(PDNR)
restricted
COP a1
XOP a1
COL4
..COL0
COP a0
XOP a0
restricted
tNPQ
quiet
No ROW or COL packets
directed to device d0 may
overlap the restricted
interval. No broadcast ROW
packets may overlap the quiet
interval.
ROP a1
tNPQ
quiet
DQA8..0
DQB8..0
quiet
COP a1
XOP a1
ROW or COL packets to a
device other than d0 may
overlap the restricted
interval.
DQA8..0
DQB8..0
tASN
Power
State
ATTN/STBYa
a
tASP
NAP
Power
State
ATTN/STBYa
PDN
ROW or COL packets
directed to device d0 after the
restricted interval will be
ignored.
The (eventual) NAP/PDN exit will be to the same ATTN/STBY state the RDRAM was in prior to NAP/PDN entry
Figure 47: NAP Entry (left) and PDN Entry (right)
On the right side of Figure 49, an RDRAM exits PDN state
at the end of cycle T3. This RDRAM may not re-enter PDN
or NAP state for an interval of tPU0. The RDRAM enters
PDN state at the end of cycle T13. This RDRAM may not re-
exit PDN state for an interval of tPU1. The equations for
these two parameters depend upon a number of factors, and
are shown at the bottom of the figure. PDNX is the value in
the PDNX field in the PDNX register.
Page 40
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47
CTM/CFM
ROW2
..ROW0
If PSX=1 in Init register, then
NAP/PDN exit is broadcast
(no PDEV field).
COL4
..COL0
DQA8..0
DQB8..0
No ROW packets may
overlap the restricted interval
tCE
ROP
restricted
tS4 tH4
No COL packets may
overlap the restricted interval
if device PDEV is exiting the
NAP-A or PDN-A states
tS3 tH3 tS3 tH3
PDEV5..0b
ROP
COP
XOP
COP
XOP
restricted
tS4 tH4
PDEV5..0b
DQS=0 b,c
DQS=1 b
SCK
CMD
0
SIO0
0/1a
1
Effective hold becomes
tH4’=t H4+[PDNXA • 64 • t SCYCLE+tPDNXB,MAX]-[PDNX • 256 • t SCYCLE]
if [PDNX • 256 • t SCYCLE] < [PDNXA • 64 • t SCYCLE+tPDNXB,MAX].
The packet is repeated
from SIO0 to SIO1
SIO1
0/1a
(NAPX)•t SCYCLE)/(256•PDNX•t SCYCLE)
Power
State
STBY/ATTNd
NAP/PDN
DQS=0
b
c
DQS=1b
a
The DQS field must be written with “1” for this RDRAM.
to STBY or ATTN depends upon whether RLXR was
asserted at NAP or PDN entry time
d Exit
Use 0 for NAP exit, 1 for PDN exit
b
Device selection timing slot is selected by DQS field of NAPX register
Figure 48: NAP and PDN Exit
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23
CTM/CFM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
CTM/CFM
NAP entry
ROW2
..ROW0
PDN entry
ROW2
..ROW0
NAPR
SCK
SCK
NAP exit
CMD
PDNR
0
PDN exit
1
tNU0
no entry to NAP or PDN
tNU0 = 5•t CYCLE + (2+NAPX)•t SCYCLE
tNU1 = 8•t CYCLE - (0.5•t SCYCLE)
if NSR=0
= 23•t CYCLE
if NSR=1
0
1
CMD
0
1
0
tPU0
tNU1
no exit
1
tPU1
no exit
no entry to NAP or PDN
tPU0 = 5 • t CYCLE + (2+256 • PDNX) • t SCYCLE
tPU1 = 8 • t CYCLE - (0.5 • t SCYCLE)
if PSR=0
= 23 • t CYCLE
if PSR=1
Figure 49: NAP Entry/Exit Windows (left) and PDN Entry/Exit Windows (right)
Page 41
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Refresh
RDRAMs, like any other DRAM technology, use volatile
storage cells which must be periodically refreshed. This is
accomplished with the REFA command. Figure 50 shows an
example of this.
The REFA command in the transaction is typically a broadcast command (DR4T and DR4F are both set in the ROWR
packet), so that in all devices bank number Ba is activated
with row number REFR, where REFR is a control register in
the RDRAM. When the command is broadcast and ATTN is
set, the power state of the RDRAMs (ATTN or STBY) will
remain unchanged. The controller increments the bank
address Ba for the next REFA command. When Ba is equal
to its maximum value, the RDRAM automatically increments REFR for the next REFA command.
On average, these REFA commands are sent once every
tREF/2BBIT+RBIT (where BBIT are the number of bank
address bits and RBIT are the number of row address bits) so
that each row of each bank is refreshed once every tREF
interval.
The REFA command is equivalent to an ACT command, in
terms of the way that it interacts with other packets (see
Table 10). In the example, an ACT command is sent after
tRR to address b0, a different (non-adjacent) bank than the
REFA command.
A second ACT command can be sent after a time tRC to
address c0, the same bank (or an adjacent bank) as the REFA
command.
Note that a broadcast REFP command is issued a time tRAS
after the initial REFA command in order to precharge the
refreshed bank in all RDRAMs. After a bank is given a
REFA command, no other core operations (activate or
precharge) should be issued to it until it receives a REFP.
It is also possible to interleave refresh transactions (not
shown). In the figure, the ACT b0 command would be
replaced by a REFA b0 command. The b0 address would be
broadcast to all devices, and would be {Broadcast, Ba+2,
REFR}. Note that the bank address should skip by two to
avoid adjacent bank interference. A possible bank incrementing pattern would be: {13, 11, 9, 7, 5, 3, 1, 8, 10, 12, 14,
0, 2, 4, 6, 15, 29, 27, 25, 23, 21, 19, 17, 24, 26, 28, 30, 16,
18, 20, 22, 31}. Every time bank 31 is reached, the REFA
command would automatically increment the REFR register.
A second refresh mechanism is available for use in PDN and
NAP power states. This mechanism is called self-refresh
mode. When the PDN power state is entered, or when NAP
power state is entered with the NSR control register bit set,
then self-refresh is automatically started for the RDRAM.
Self-refresh uses an internal time base reference in the
RDRAM. This causes an activate and precharge to be
carried out once in every tREF/2BBIT+RBIT interval. The
REFB and REFR control registers are used to keep track of
the bank and row being refreshed.
Before a controller places an RDRAM into self-refresh
mode, it should perform REFA/REFP refreshes until the
bank address is equal to the maximum value. This ensures
that no rows are skipped. Likewise, when a controller returns
an RDRAM to REFA/REFP refresh, it should start with the
minimum bank address value (zero).
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47
CTM/CFM
tRC
ROW2
..ROW0
REFA a0
ACT b0
REFP a1
tRAS
COL4
..COL0
ACT c0
REFA d0
tRP
tRR
tREF/2BBIT+RBIT
DQA8..0
DQB8..0
Transaction a: REFA
a0 = {Broadcast,Ba,REFR}
Transaction b: xx
b0 = {Db, /={Ba,Ba+1,Ba-1}, Rb}
Transaction c: xx
c0 = {Dc, ==Ba, Rc}
Transaction d: REFA d0 = {Broadcast,Ba+1,REFR}
a1 = {Broadcast,Ba}
BBIT = # bank address bits
RBIT = # row address bits
REFB = REFB3..REFB0
REFR = REFR8..REFR0
Figure 50: REFA/REFP Refresh Transaction Example
Page 42
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Current and Temperature Control
samples the last calibration packet and adjusts its IOL current
value.
Figure 51 shows an example of a transaction which performs
current control calibration. It is necessary to perform this
operation once to every RDRAM in every tCCTRL interval in
order to keep the IOL output current in its proper range.
Unlike REF commands, CAL and SAM commands cannot
be broadcast. This is because the calibration packets from
different devices would interfere. Therefore, a current
control transaction must be sent every tCCTRL/N, where N is
the number of RDRAMs on the Channel. The device field
Da of the address a0 in the CAL/SAM command should be
incremented after each transaction.
This example uses four COLX packets with a CAL
command. These cause the RDRAM to drive four calibration packets Q(a0) a time tCAC later. An offset of tRDTOCC
must be placed between the Q(a0) packet and read data
Q(a1)from the same device. These calibration packets are
driven on the DQA4..3 and DQB4..3 wires. The TSQ bit of
the INIT register is driven on the DQA5 wire during same
interval as the calibration packets. The remaining DQA and
DQB wires are not used during these calibration packets.
The last COLX packet also contains a SAM command
(concatenated with the CAL command). The RDRAM
Figure 52 shows an example of a temperature calibration
sequence to the RDRAM. This sequence is broadcast once
every tTEMP interval to all the RDRAMs on the Channel.
The TCEN and TCAL are ROP commands, and cause the
slew rate of the output drivers to adjust for temperature drift.
During the quiet interval tTCQUIET the devices being calibrated can’t be read, but they can be written.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47
CTM/CFM
Read data from the same
device from an earlier RD
command must be at this
packet position or earlier.
ROW2
..ROW0
Read data from a different
device from a later RD
command can be anywhere
after to the Q(a0) packet.
Read data from a different
device from an earlier RD
command can be anywhere
prior to the Q(a0) packet. .
Read data from the same device
from a later RD command must
be at this packet position or
later.
tCCTRL
COL4
..COL0
CAL a0
CAL a0
CAL a0
CAL/SAM a0
CAL a2
tCAC
DQA8..0
DQB8..0
CAL b0
tCCSAMTOREAD
Q (a1)
Q (a0)
tREADTOCC
Transaction a0: CAL/SAM
Transaction a1: RD
Transaction a2: CAL/SAM
a0 = {Da, Bx}
a1 = {Da, Bx}
a2 = {Da, Bx}
Q (a1)
DQA5 of the first calibrate packet has the inverted TSQ bit of INIT
control register; i.e. logic 0 or high voltage means hot temperature.
When used for monitoring, it should be enabled with the DQA3
bit (current control one value) in case there is no RDRAM present:
HotTemp = DQA5•DQA3
Note that DQB3 could be used instead of DQA3.
Figure 51: Current Control CAL/SAM Transaction Example
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47
CTM/CFM
tTEMP
ROW2
..ROW0
TCEN
TCAL
tTCEN
COL4
..COL0
DQA8..0
DQB8..0
TCEN
tTCAL
tTCQUIET
Any ROW packet may be placed
in the gap between the ROW
packets with the TCEN and
TCAL commands.
No read data from devices
being calibrated
Figure 52: Temperature Calibration (TCEN-TCAL) Transactions to RDRAM
Page 43
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Electrical Conditions
Table 18: Electrical Conditions
Symbol
Parameter and Conditions
Min
Max
Unit
TJ
Junction temperature under bias
-
100
°C
VDD, VDDA
Supply voltage
2.50 - 0.13
2.50 + 0.13
V
VDD,N, VDDA,N
Supply voltage droop (DC) during NAP interval (tNLIMIT)
-
2.0
%
vDD,N, vDDA,N
Supply voltage ripple (AC) during NAP interval (tNLIMIT)
-2.0
2.0
%
VCMOS
Supply voltage for CMOS pins (2.5V controllers)
2.50 - 0.13
2.50 + 0.25
V
Supply voltage for CMOS pins (1.8V controllers)
1.80 - 0.1
1.80 + 0.2
V
VTERM
Termination voltage
1.80 - 0.1
1.80 + 0.1
V
VREF
Reference voltage
1.40 - 0.2
1.40 + 0.2
V
VDIL
RSL data input - low voltage
VREF - 0.5
VREF - 0.2
V
VDIH
RSL data input - high voltage
VREF + 0.2
VREF + 0.5
V
VDIS
RSL data input swing: VDIS = VDIH - VDIL
0.4
1.0
V
ADI
RSL data asymmetry: ADI = [(VDIH - VREF) + (VDIL - VREF)]/VDIS
0
-20
%
VX
RSL clock input - crossing point of true and complement signals
1.3
1.8
V
VCM
RSL clock input - common mode VCM = (VCIH+VCIL)/2
1.4
1.7
V
VCIS,CTM
RSL clock input swing: VCIS = VCIH - VCIL (CTM,CTMN pins).
0.35
0.70
V
VCIS,CFM
RSL clock input swing: VCIS = VCIH - VCIL (CFM,CFMN pins).
0.125
0.70
V
VIL,CMOS
CMOS input low voltage
- 0.3
VCMOS/2 - 0.25
V
VIH,CMOS
CMOS input high voltage
VCMOS/2 + 0.25
VCMOS+0.3
V
Timing Conditions
Table 19: Timing Conditions
Symbol
Parameter
Min
Max
Unit
Figure(s)
tCYCLE
CTM and CFM cycle times (-600)
3.33
3.83
ns
Figure 53
CTM and CFM cycle times (-711)
2.80
3.83
ns
Figure 53
CTM and CFM cycle times (-800)
2.50
3.83
ns
Figure 53
tCR, tCF
CTM and CFM input rise and fall times
0.2
0.5
ns
Figure 53
tCH, tCL
CTM and CFM high and low times
40%
60%
tCYCLE
Figure 53
tTR
CTM-CFM differential (MSE/MS=0/0)
CTM-CFM differential (MSE/MS=1/1)a
0.0
0.9
1.0
1.0
tCYCLE
Figure 42
Figure 53
tDCW
Domain crossing window
-0.1
0.1
tCYCLE
Figure 59
tDR, tDF
DQA/DQB/ROW/COL input rise/fall times
0.2
0.65
ns
Figure 54
-
ns
Figure 54
tS, tH
DQA/DQB/ROW/COL-to-CFM setup/hold @ tCYCLE=3.33ns
@ tCYCLE=2.81ns
@tCYCLE=2.50ns
Page 44
b,d
0.275
0.240c,d
0.200d
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Table 19: Timing Conditions
Symbol
Parameter
Min
Max
Unit
Figure(s)
tDR1, tDF1
SIO0, SIO1 input rise and fall times
-
5.0
ns
Figure 56
tDR2, tDF2
CMD, SCK input rise and fall times
-
2.0
ns
Figure 56
tCYCLE1
SCK cycle time - Serial control register transactions
1000
-
ns
Figure 56
10
-
ns
Figure 56
4.25
-
ns
Figure 56
1.25
-
ns
Figure 56
SCK cycle time - Power transitions
tCH1, tCL1
SCK high and low times
edgee
tS1
CMD setup time to SCK rising or falling
tH1
CMD hold time to SCK rising or falling edgee
1
-
ns
Figure 56
tS2
SIO0 setup time to SCK falling edge
40
-
ns
Figure 56
tH2
SIO0 hold time to SCK falling edge
40
-
ns
Figure 56
tS3
PDEV setup time on DQA5..0 to SCK rising edge.
0
-
ns
Figure 48,
Figure 57
tH3
PDEV hold time on DQA5..0 to SCK rising edge.
5.5
-
ns
tS4
ROW2..0, COL4..0 setup time for quiet window
-1
-
tCYCLE
Figure 48
tH4
ROW2..0, COL4..0 hold time for quiet windowf
5
-
tCYCLE
Figure 48
vIL,CMOS
CMOS input low voltage - over/undershoot voltage duration is less
than or equal to 5ns
- 0.7
VCMOS/2
- 0.4
V
vIH,CMOS
CMOS input high voltage - over/undershoot voltage duration is less
than or equal to 5ns
VCMOS/2
+ 0.4
VCMOS +
0.7
V
tNPQ
Quiet on ROW/COL bits during NAP/PDN entry
4
-
tCYCLE
Figure 47
tREADTOCC
Offset between read data and CC packets (same device)
12
-
tCYCLE
Figure 51
tCCSAMTOREAD
Offset between CC packet and read data (same device)
8
-
tCYCLE
Figure 51
tCE
CTM/CFM stable before NAP/PDN exit
2
-
tCYCLE
Figure 48
tCD
CTM/CFM stable after NAP/PDN entry
100
-
tCYCLE
Figure 47
tFRM
ROW packet to COL packet ATTN framing delay
7
-
tCYCLE
Figure 46
tNLIMIT
Maximum time in NAP mode
10.0
µs
Figure 45
tREF
Refresh interval
32
ms
Figure 50
tCCTRL
Current control interval
100ms
ms/tCYCLE
Figure 51
tTEMP
Temperature control interval
100
ms
Figure 52
tTCEN
TCE command to TCAL command
150
-
tCYCLE
Figure 52
tTCAL
TCAL command to quiet window
2
2
tCYCLE
Figure 52
tTCQUIET
Quiet window (no read data)
140
-
tCYCLE
Figure 52
tPAUSE
RDRAM delay (no RSL operations allowed)
200.0
µs
page 28
34 tCYCLE
a. MSE/MS are fields of the SKIP register. For this combination (skip override) the tDCW parameter range is effectively 0.0 to 0.0.
b. This parameter also applies to a -800 or -711 part when operated with tCYCLE=3.33ns.
c. This parameter also applies to a -800 part when operated with tCYCLE=2.81ns.
d. tS,MIN and tH,MIN for other tCYCLE values can be interpolated between or extrapolated from the timings at the 3 specified tCYCLE values.
e. With VIL,CMOS=0.5VCMOS-0.4V and VIH,CMOS=0.5VCMOS+0.4V
f. Effective hold becomes tH4’= tH4+[PDNXA•64•tSCYCLE+tPDNXB,MAX]-[PDNX•256•tSCYCLE]
if [PDNX•256•tSCYCLE] < [PDNXA•64•tSCYCLE+tPDNXB,MAX]. See Figure 48.
Page 45
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Electrical Characteristics
Table 20: Electrical Characteristics
Symbol
Parameter and Conditions
ΘJC
Junction-to-Case thermal resistance
IREF
VREF current @ VREF,MAX
IOH
RSL output high current @ (0≤VOUT≤VDD)
Min
Max
Unit
-
0.2
°C/Watt
-10
10
µA
-10
10
µA
30.0
90.0
mA
-
2.0
mA
150
-
Ω
-10.0
10.0
µA
-
0.3
V
VCMOS-0.3
-
V
VDD,MIN , TJ,MAXa
IALL
RSL IOL current @ VOL = 0.9V,
∆IOL
RSL IOL current resolution step
rOUT
Dynamic output impedance
II,CMOS
CMOS input leakage current @ (0≤VI,CMOS≤VCMOS)
VOL,CMOS
CMOS output voltage @ IOL,CMOS= 1.0mA
VOH,CMOS
CMOS output high voltage @ IOH,CMOS= -0.25mA
a. This measurement is made in manual current control mode; i.e. with all output device legs sinking current.
Timing Characteristics
Table 21: Timing Characteristics
Symbol
Parameter
Min
Max
Unit
Figure(s)
tQ
CTM-to-DQA/DQB output time
-0.350a,c
-0.300b,c
-0.260c
+0.350a,c
+0.300b,c
+0.260c
ns
Figure 55
tQR, tQF
DQA/DQB output rise and fall times
0.2
0.45
ns
Figure 55
tQ1
SCK(neg)-to-SIO0 delay @ CLOAD,MAX = 20pF (SD read data valid).
-
10
ns
Figure 58
tHR
SCK(pos)-to-SIO0 delay @ CLOAD,MAX = 20pF (SD read data hold).
2
-
ns
Figure 58
tQR1, tQF1
SIOOUT rise/fall @ CLOAD,MAX = 20pF
-
5
ns
Figure 58
tPROP1
SIO0-to-SIO1 or SIO1-to-SIO0 delay @ CLOAD,MAX = 20pF
-
10
ns
Figure 58
tNAPXA
NAP exit delay - phase A
-
50
ns
Figure 48
tNAPXB
NAP exit delay - phase B
-
40
ns
Figure 48
tPDNXA
PDN exit delay - phase A
-
4
µs
Figure 48
tPDNXB
PDN exit delay - phase B
-
9000
tCYCLE
Figure 48
tAS
ATTN-to-STBY power state delay
-
1
tCYCLE
Figure 46
tSA
STBY-to-ATTN power state delay
-
0
tCYCLE
Figure 46
tASN
ATTN/STBY-to-NAP power state delay
-
8
tCYCLE
Figure 47
tASP
ATTN/STBY-to-PDN power state delay
-
8
tCYCLE
Figure 47
@ tCYCLE=3.33ns
@ tCYCLE=2.81ns
@ tCYCLE=2.50ns
a. This parameter also applies to a -800 or -711 part when operated with tCYCLE=3.33ns.
b. This parameter also applies to a -800 part when operated with tCYCLE=2.81ns.
c. tQ,MIN and tQ,MAX for other tCYCLE values can be interpolated between or extrapolated from the timings at the 3 specified tCYCLE values.
Page 46
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
RSL - Clocking
Most timing is measured relative to the points where they
cross. The tCYCLE parameter is measured from the falling
CTM edge to the falling CTM edge. The tCL and tCH parameters are measured from falling to rising and rising to falling
edges of CTM. The tCR and tCF rise- and fall-time parameters are measured at the 20% and 80% points.
Figure 53 is a timing diagram which shows the detailed
requirements for the RSL clock signals on the Channel.
The CTM and CTMN are differential clock inputs used for
transmitting information on the DQA and DQB, outputs.
tCYCLE
tCL
tCH
tCR
tCR
CTM
VCIH
80%
VXVCM
50%
VX+
20%
VCIL
CTMN
tCF
tTR
tCF
tCR
tCR
CFM
VCIH
80%
VXVCM
50%
VX+
20%
VCIL
CFMN
tCF
tCL
tCYCLE
tCF
tCH
Figure 53: RSL Timing - Clock Signals
The CFM and CFMN are differential clock outputs used for
receiving information on the DQA, DQB, ROW and COL
outputs. Most timing is measured relative to the points
where they cross. The tCYCLE parameter is measured from
the falling CFM edge to the falling CFM edge. The tCL and
tCH parameters are measured from falling to rising and rising
to falling edges of CFM. The tCR and tCF rise- and fall-time
parameters are measured at the 20% and 80% points.
The tTR parameter specifies the phase difference that may be
tolerated with respect to the CTM and CFM differential
clock inputs (the CTM pair is always earlier).
Page 47
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
RSL - Receive Timing
Figure 54 is a timing diagram which shows the detailed
requirements for the RSL input signals on the Channel.
The DQA, DQB, ROW, and COL signals are inputs which
receive information transmitted by a Direct RAC on the
Channel. Each signal is sampled twice per tCYCLE interval.
The set/hold window of the sample points is tS/tH. The
sample points are centered at the 0% and 50% points of a
cycle, measured relative to the crossing points of the falling
CFM clock edge. The set and hold parameters are measured
at the VREF voltage point of the input transition.
The tDR and tDF rise- and fall-time parameters are measured
at the 20% and 80% points of the input transition.
CFM
VCIH
80%
VXVCM
50%
VX+
20%
VCIL
CFMN
DQA
0.5•t CYCLE
tDR
tS
DQB
tH
tS
tH
VDIH
ROW
80%
COL
even
odd
VREF
20%
VDIL
tDF
Figure 54: RSL Timing - Data Signals for Receive
Page 48
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
RSL - Transmit Timing
Figure 55 is a timing diagram which shows the detailed
requirements for the RSL output signals on the Channel.
The DQA and DQB signals are outputs to transmit information that is received by a Direct RAC on the Channel. Each
signal is driven twice per tCYCLE interval. The beginning
and end of the even transmit window is at the 75% point of
the previous cycle and at the 25% point of the current cycle.
The beginning and end of the odd transmit window is at the
25% point and at the 75% point of the current cycle. These
transmit points are measured relative to the crossing points
of the falling CTM clock edge. The size of the actual
transmit window is less than the ideal tCYCLE/2, as indicated
by the non-zero values of tQ,MIN and tQ,MAX. The tQ parameters are measured at the 50% voltage point of the output
transition.
The tQR and tQF rise- and fall-time parameters are measured
at the 20% and 80% points of the output transition.
CTM
VCIH
80%
VXVCM
50%
VX+
20%
CTMN
VCIL
0.75•t CYCLE
0.75•t CYCLE
0.25•t CYCLE
DQA
tQ,MAX
tQR
tQ,MAX
tQ,MIN
DQB
tQ,MIN
VQH
80%
even
odd
50%
20%
VQL
tQF
Figure 55: RSL Timing - Data Signals for Transmit
Page 49
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
CMOS - Receive Timing
50% level. The rise and fall times of SCK, CMD, and SIO0
are tDR1 and tDF1, measured at the 20% and 80% levels.
Figure 56 is a timing diagram which shows the detailed
requirements for the CMOS input signals.
The CMD signal is sampled twice per tCYCLE1 interval, on
the rising edge (odd data) and the falling edge (even data).
The set/hold window of the sample points is tS1/tH1. The
SCK and CMD timing points are measured at the 50% level.
The CMD and SIO0 signals are inputs which receive information transmitted by a controller or by another RDRAM’s
SIO1 output. SCK is the CMOS clock signal driven by the
controller. All signals are high true.
The SIO0 signal is sampled once per tCYCLE1 interval on the
falling edge. The set/hold window of the sample points is
tS2/tH2. The SCK and SIO0 timing points are measured at the
50% level.
The cycle time, high phase time, and low phase time of the
SCK clock are tCYCLE1, tCH1 and tCL1, all measured at the
tDR2
VIH,CMOS
SCK
80%
50%
20%
tCYCLE1
tCH1
tDF2
tDR2
VIL,CMOS
tCL1
tS1
tH1
tS1
tH1
VIH,CMOS
CMD
80%
even
odd
50%
20%
VIL,CMOS
tDF2
tDR1
tS2
tH2
VIH,CMOS
SIO0
80%
50%
20%
VIL,CMOS
tDF1
Figure 56: CMOS Timing - Data Signals for Receive
Page 50
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
The SCK clock is also used for sampling data on RSL inputs
in one situation. Figure 48 shows the PDN and NAP exit
sequences. If the PSX field of the INIT register is one (see
Figure 27), then the PDN and NAP exit sequences are broadcast; i.e. all RDRAMs that are in PDN or NAP will perform
the exit sequence. If the PSX field of the INIT register is
zero, then the PDN and NAP exit sequences are directed; i.e.
only one RDRAM that is in PDN or NAP will perform the
exit sequence.
The address of that RDRAM is specified on the DQA[5:0]
bus in the set/hold window tS3/tH3 around the rising edge of
SCK. This is shown in Figure 57. The SCK timing point is
measured at the 50% level, and the DQA[5:0] bus signals are
measured at the VREF level.
VIH,CMOS
SCK
80%
50%
20%
VIL,CMOS
tS3
tH3
VDIH
DQA[5:0]
80%
PDEV
VREF
20%
VDIL
Figure 57: CMOS Timing - Device Address for NAP or PDN Exit
Page 51
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
CMOS - Transmit Timing
Figure 58 is a timing diagram which shows the detailed
requirements for the CMOS output signals. The SIO0 signal
is driven once per tCYCLE1 interval on the falling edge. The
clock-to-output window is tQ1,MIN/tQ1,MAX. The SCK and
SIO0 timing points are measured at the 50% level. The rise
and fall times of SIO0 are tQR1 and tQF1, measured at the
20% and 80% levels.
VIH,CMOS
SCK
80%
50%
20%
tQ1,MAX
VIL,CMOS
tHR,MIN
tQR1
VOH,CMOS
SIO0
80%
50%
20%
VOL,CMOS
tQF1
tDR1
VIH,CMOS
SIO0
or
SIO1
80%
50%
20%
tPROP1,MAX
tDF1
tPROP1,MIN
VIL,CMOS
tQR1
VOH,CMOS
SIO1
or
SIO0
80%
50%
20%
VOL,CMOS
tQF1
Figure 58: CMOS Timing - Data Signals for Transmit
Page 52
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Figure 58 also shows the combinational path connecting
SIO0 to SIO1 and the path connecting SIO1 to SIO0 (read
data only). The tPROP1 parameter specified this propagation
delay. The rise and fall times of SIO0 and SIO1 inputs must
be tDR1 and tDF1, measured at the 20% and 80% levels. The
rise and fall times of SIO0 and SIO1 outputs are tQR1 and
tQF1, measured at the 20% and 80% levels.
RSL - Domain Crossing Window
When read data is returned by the RDRAM, information
must cross from the receive clock domain (CFM) to the
transmit clock domain (CTM). The tTR parameter permits
the CFM to CTM phase to vary through an entire cycle; i.e.
there is no restriction on the alignment of these two clocks.
A second parameter tDCW is needed in order to describe how
COL
•••
tTR
DQA/B
Case A
tTR=0
tCAC-tTR
Case A’
tTR=0
tCAC -tTR-tCYCLE
tTR
DQA/B
Case B
tTR=tDCW,MAX
tCAC-tTR
Case B’
tTR=tDCW,MAX
tCAC-tTR-tCYCLE
tTR
Case C
tTR=0.5•t CYCLE
tTR
tCAC-tTR
Case D
tTR=tCYCLE+tDCW,MIN
tCAC-tTR
Case D’ tTR=tCYCLE+tDCW,MIN
DQA/B
Q(a1)
Q(a1)
Q(a1)
tCAC-tTR+tCYCLE
Q(a1)
•••
CTM
DQA/B
Q(a1)
•••
CTM
DQA/B
Q(a1)
•••
CTM
DQA/B
Q(a1)
•••
CTM
DQA/B
tCYCLE
RD a1
CTM
DQA/B
Figure 59 shows this timing for five distinct values of tTR.
Case A (tTR=0) is what has been used throughout this document. The delay between the RD command and read data is
tCAC. As tTR varies from zero to tCYCLE (cases A through
E), the command to data delay is (tCAC-tTR). When the tTR
value is in the range 0 to tDCW,MAX, the command to data
delay can also be (tCAC-tTR-tCYCLE). This is shown as cases
A’ and B’ (the gray packets). Similarly, when the t TR value
is in the range (tCYCLE+tDCW,MIN) to tCYCLE, the command
to data delay can also be (tCAC-tTR+tCYCLE). This is shown
as cases D’ and E’ (the gray packets). The RDRAM will
work reliably with either the white or gray packet timing.
The delay value is selected at initialization, and remains
fixed thereafter.
•••
CFM
DQA/B
the delay between a RD command packet and read data
packet varies as a function of the tTR value.
tTR
Case E
tTR=tCYCLE
tCAC-tTR
Case E’
tTR=tCYCLE
tCAC-tTR+tCYCLE
Q(a1)
Q(a1)
Figure 59: RSL Transmit - Crossing Read Domains
Page 53
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Timing Parameters
Table 22: Timing Parameter Summary
Min
-45
-800
Min
-45
-711
Min
-53.3
-600
Max
Units
Figure(s)
Row Cycle time of RDRAM banks -the interval between ROWA packets with
ACT commands to the same bank.
28
28
28
-
tCYCLE
Figure 15
Figure 16
tRAS
RAS-asserted time of RDRAM bank - the interval between ROWA packet
with ACT command and next ROWR packet with PRERa command to the
same bank.
20
20
20
64µsb
tCYCLE
Figure 15
Figure 16
tRP
Row Precharge time of RDRAM banks - the interval between ROWR packet
with PRERa command and next ROWA packet with ACT command to the
same bank.
8
8
8
-
tCYCLE
Figure 15
Figure 16
tPP
Precharge-to-precharge time of RDRAM device - the interval between successive ROWR packets with PRERa commands to any banks of the same device.
8
8
8
-
tCYCLE
Figure 12
tRR
RAS-to-RAS time of RDRAM device - the interval between successive
ROWA packets with ACT commands to any banks of the same device.
8
8
8
-
tCYCLE
Figure 13
tRCD
RAS-to-CAS Delay - the interval from ROWA packet with ACT command to
COLC packet with RD or WR command). Note - the RAS-to-CAS delay seen
by the RDRAM core (tRCD-C) is equal to tRCD-C = 1 + tRCD because of differences in the row and column paths through the RDRAM interface.
9
7
7
-
tCYCLE
Figure 15
Figure 16
tCAC
CAS Access delay - the interval from RD command to Q read data. The equation for tCAC is given in the TPARM register in Figure 39.
8
8
8
12
tCYCLE
Figure 4
Figure 39
tCWD
CAS Write Delay (interval from WR command to D write data.
6
6
6
6
tCYCLE
Figure 4
tCC
CAS-to-CAS time of RDRAM bank - the interval between successive COLC
commands).
4
4
4
-
tCYCLE
Figure 15
Figure 16
tPACKET
Length of ROWA, ROWR, COLC, COLM or COLX packet.
4
4
4
4
tCYCLE
Figure 3
tRTR
Interval from COLC packet with WR command to COLC packet which causes
retire, and to COLM packet with bytemask.
8
8
8
-
tCYCLE
Figure 17
tOFFP
The interval (offset) from COLC packet with RDA command, or from COLC
packet with retire command (after WRA automatic precharge), or from COLC
packet with PREC command, or from COLX packet with PREX command to
the equivalent ROWR packet with PRER. The equation for tOFFP is given in
the TPARM register in Figure 39.
4
4
4
4
tCYCLE
Figure 14
Figure 39
tRDP
Interval from last COLC packet with RD command to ROWR packet with
PRER.
4
4
4
-
tCYCLE
Figure 15
tRTP
Interval from last COLC packet with automatic retire command to ROWR
packet with PRER.
4
4
4
-
tCYCLE
Figure 16
Parameter
Description
tRC
a. Or equivalent PREC or PREX command. See Figure 14.
b. This is a constraint imposed by the core, and is therefore in units of µs rather than tCYCLE.
Page 54
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Absolute Maximum Ratings
Table 23: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
VI,ABS
Voltage applied to any RSL or CMOS pin with respect to Gnd
- 0.3
VDD+0.3
V
VDD,ABS, VDDA,ABS
Voltage on VDD and VDDA with respect to Gnd
- 0.5
VDD+1.0
V
TSTORE
Storage temperature
- 50
100
°C
IDD - Supply Current Profile
Table 24: Supply Current Profile
IDD value
RDRAM blocks consuming powera
Max
-45
-800
Max
-45
-711
Max
-53.3
-600
Unit
IDD,PDN
Self-refresh only for INIT.LSR=0
3000
3000
3000
µA
IDD,NAP
T/RCLK-Nap
4
4
4
mA
IDD,STBY
T/RCLK, ROW-demux
105
100
90
mA
IDD,ATTN
T/RCLK, ROW-demux, COL-demux
165
155
140
mA
IDD,ATTN-W
T/RCLK, ROW-demux,COL-demux,DQ-demux,1•WR-SenseAmp,
4•ACT-Bank
575/625b
525/580
455/500
mA
IDD,ATTN-R
T/RCLK, ROW-demux,COL-demux,DQ-mux,1•RD-SenseAmp,
4•ACT-Bank c
490/520
450/480
400/420
mA
a. The CMOS interface consumes power in all power states.
b. x16/x18 RDRAM data width
c. This does not include the IOL sink current. The RDRAM dissipates IOL•VOL in each output driver when a logic one is driven.
Page 55
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Capacitance and Inductance
Figure 60 shows the equivalent load circuit of the RSL and
CMOS pins. The circuit models the load that the device
presents to the Channel.
Pad
LI
DQA,DQB,RQ Pin
CI
RI
Gnd Pin
Pad
LI
CTM,CTMN,
CFM,CFMN Pin
CI
RI
Gnd Pin
Pad
LI,CMOS
SCK,CMD Pin
CI,CMOS
Gnd Pin
Pad
LI,CMOS
SIO0,SIO1 Pin
CI,CMOS,SIO
Gnd Pin
Figure 60: Equivalent Load Circuit for RSL Pins
Page 56
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
This circuit does not include pin coupling effects that are
often present in the packaged device. Because coupling
effects make the effective single-pin inductance LI, and
capacitance CI, a function of neighboring pins, these parameters are intrinsically data-dependent. For purposes of specifying the device electrical loading on the Channel, the
effective LI and CI are defined as the worst-case values over
all specified operating conditions.
each RSL signal adjacent to an AC ground (a Gnd or Vdd
pin), the effective inductance must be defined based on this
configuration. Therefore, LI assumes a loop with the RSL
pin adjacent to an AC ground.
CI is defined as the effective pin capacitance based on the
device pin assignment. It is the sum of the effective package
pin capacitance and the IO pad capacitance.
LI is defined as the effective pin inductance based on the
device pin assignment. Because the pad assignment places
Table 25: RSL Pin Parasitics
Symbol
Parameter and Conditions - RSL pins
IO freq.
Min
Max
Unit
LI
RSL effective input inductance
4.0
nH
L12
Mutual inductance between any DQA or DQB RSL signals.
0.2
nH
Mutual inductance between any ROW or COL RSL signals.
0.6
nH
-
1.8
nH
-800
2.0
2.4
pF
-711
2.0
2.4
-600
2.0
2.6
∆LI
Difference in LI value between any RSL pins of a single device.
CI
RSL effective input
capacitancea
C12
Mutual capacitance between any RSL signals.
-
0.1
pF
∆CI
Difference in CI value between average of CTM/CFM and any RSL
pins of a single device.
-
0.06
pF
RI
RSL effective input resistance
4
15
Ω
Min
Max
Unit
8.0
nH
1.7
2.1
pF
-
7.0
pF
a. This value is a combination of the device IO circuitry and package capacitances.
Table 26: CMOS Pin Parasitics
Symbol
LI ,CMOS
Parameter and Conditions - CMOS pins
CMOS effective input inductance
(SCK,CMD)a
CI ,CMOS
CMOS effective input capacitance
CI ,CMOS,SIO
CMOS effective input capacitance (SIO1, SIO0)a
a. This value is a combination of the device IO circuitry and package capacitances.
Page 57
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Center-Bonded uBGA Package
Figure 61 shows the form and dimensions of the recommended package for the center-bonded CSP device class.
D
A
B
C
D
E
F
G
H
Bottom
J
Top
12
Bottom
11
10
9
8
7
A
6
5
4
e2
3
2
1
E1
d
e1
E
Bottom
Figure 61: Center-Bonded uBGA Package
Table 27 lists the numerical values corresponding to dimensions shown in Figure 61.
Table 27: Center-Bonded uBGA Package Dimensions
Symbol
Parameter
Min(128Mb/144Mb)
Max(128Mb/144Mb)
Unit
e1
Ball pitch (x-axis)
1.00
1.00
mm
e2
Ball pitch (y-axis)
0.80
0.80
mm
A
Package body length
11.90
12.10
mm
D
Package body width
10.10
10.30
mm
-
1.00a
mm
E
Package total thickness
E1
Ball height
0.20
0.30
mm
d
Ball diameter
0.30
0.40
mm
a. The E,MAX parameter for SO-RIMM applications is 0.94mm.
Page 58
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Glossary of Terms
controller
A logic-device which drives the
ROW/COL /DQ wires for a Channel of
RDRAMs.
ACT
Activate command from AV field.
activate
To access a row and place in sense amp.
COP
Column opcode field in COLC packet.
adjacent
Two RDRAM banks which share sense
amps (also called doubled banks).
core
The banks and sense amps of an RDRAM.
CTM,CTMN
Clock pins for transmitting packets.
ASYM
CCA register field for RSL VOL/VOH.
current control Periodic operations to update the proper
ATTN
Power state - ready for ROW/COL
packets.
D
Write data packet on DQ pins.
ATTNR
Power state - transmitting Q packets.
DBL
CNFGB register field - doubled-bank.
ATTNW
Power state - receiving D packets.
DC
Device address field in COLC packet.
AV
Opcode field in ROW packets.
device
An RDRAM on a Channel.
DEVID
Control register with device address that is
matched against DR, DC, and DX fields.
Device match for ROW packet decode.
2RBIT•2 CBITstorage
IOL value of RSL output drivers.
bank
A block of
core of the RDRAM.
BC
Bank address field in COLC packet.
DM
BBIT
CNFGA register field - # bank address
bits.
doubled-bank RDRAM with shared sense amp.
broadcast
An operation executed by all RDRAMs.
BR
Bank address field in ROW packets.
bubble
Idle cycle(s) on RDRAM pins needed
because of a resource constraint.
BYT
CNFGB register field - 8/9 bits per byte.
BX
Bank address field in COLX packet.
C
Column address field in COLC packet.
CAL
Calibrate (IOL) command in XOP field.
CNFGB register field - # column address
bits.
CBIT
cells in the
DQ
DQA and DQB pins.
DQA
Pins for data byte A.
DQB
Pins for data byte B.
DQS
NAPX register field - PDN/NAP exit.
DR,DR4T,DR4F Device address field and packet framing
fields in ROWA and ROWR packets.
dualoct
16 bytes - the smallest addressable datum.
DX
Device address field in COLX packet.
field
A collection of bits in a packet.
INIT
Control register with initialization fields.
initialization
Configuring a Channel of RDRAMs so
they are ready to respond to transactions.
LSR
CNFGA register field - low-power selfrefresh.
CCA
Control register - current control A.
CCB
Control register - current control B.
CFM,CFMN
Clock pins for receiving packets.
Channel
ROW/COL/DQ pins and external wires.
M
Mask opcode field (COLM/COLX packet).
CLRR
Clear reset command from SOP field.
MA
Field in COLM packet for masking byte A.
CMD
CMOS pin for initialization/power control.
MB
Field in COLM packet for masking byte B.
CNFGA
Control register with configuration fields.
MSK
Mask command in M field.
CNFGB
Control register with configuration fields.
MVER
Control register - manufacturer ID.
COL
Pins for column-access control.
NAP
Power state - needs SCK/CMD wakeup.
COL
COLC,COLM,COLX packet on COL pins.
NAPR
Nap command in ROP field.
COLC
Column operation packet on COL pins.
NAPRC
Conditional nap command in ROP field.
COLM
Write mask packet on COL pins.
NAPXA
NAPX register field - NAP exit delay A.
column
Rows in a bank or activated row in sense
amps have 2CBIT dualocts column storage.
NAPXB
NAPX register field - NAP exit delay B.
NOCOP
No-operation command in COP field.
NOROP
No-operation command in ROP field.
command
A decoded bit-combination from a field.
COLX
Extended operation packet on COL pins.
Page 59
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
NOXOP
No-operation command in XOP field.
ROWR
Row operation packet on ROW pins.
NSR
INIT register field- NAP self-refresh.
RQ
Alternate name for ROW/COL pins.
packet
A collection of bits carried on the Channel.
RSL
Rambus Signaling Levels.
PDN
Power state - needs SCK/CMD wakeup.
SAM
PDNR
Powerdown command in ROP field.
SA
PDNXA
Control register - PDN exit delay A.
Sample (IOL) command in XOP field.
Serial address packet for control register
transactions w/ SA address field.
PDNXB
Control register - PDN exit delay B.
SBC
Serial broadcast field in SRQ.
SCK
CMOS clock pin.
SD
Serial data packet for control register
transactions w/ SD data field.
pin efficiency The fraction of non-idle cycles on a pin.
PRE
PREC,PRER,PREX precharge commands.
PREC
Precharge command in COP field.
SDEV
Serial device address in SRQ packet.
precharge
Prepares sense amp and bank for activate.
SDEVID
INIT register field - Serial device ID.
PRER
Precharge command in ROP field.
self-refresh
Refresh mode for PDN and NAP.
PREX
Precharge command in XOP field.
sense amp
Fast storage that holds copy of bank’s row.
PSX
INIT register field - PDN/NAP exit.
SETF
Set fast clock command from SOP field.
PSR
INIT register field - PDN self-refresh.
SETR
Set reset command from SOP field.
PVER
CNFGB register field - protocol version.
SINT
Q
Read data packet on DQ pins.
Serial interval packet for control register
read/write transactions.
R
Row address field of ROWA packet.
SIO0,SIO1
CMOS serial pins for control registers.
RBIT
CNFGB register field - # row address bits.
SOP
Serial opcode field in SRQ.
RD/RDA
Read (/precharge) command in COP field.
SRD
Serial read opcode command from SOP.
read
Operation of accesssing sense amp data.
SRP
INIT register field - Serial repeat bit.
receive
Moving information from the Channel into
the RDRAM (a serial stream is demuxed).
SRQ
Serial request packet for control register
read/write transactions.
REFA
Refresh-activate command in ROP field.
STBY
Power state - ready for ROW packets.
REFB
Control register - next bank (self-refresh).
SVER
Control register - stepping version.
REFBIT
CNFGA register field - ignore bank bits
(for REFA and self-refresh).
SWR
Serial write opcode command from SOP.
TCAS
TCLSCAS register field - tCAS core delay.
REFP
Refresh-precharge command in ROP field.
TCLS
REFR
Control register - next row for REFA.
TCLSCAS
TCLSCAS register field - tCLS core delay.
Control register - tCAS and tCLS delays.
refresh
Periodic operations to restore storage cells.
TCYCLE
Control register - tCYCLE delay.
retire
The automatic operation that stores write
buffer into sense amp after WR command.
TDAC
RLX
RLXC,RLXR,RLXX relax commands.
TEST77
Control register - tDAC delay.
Control register - for test purposes.
RLXC
Relax command in COP field.
TEST78
Control register - for test purposes.
TRDLY
Control register - tRDLY delay.
ROW,COL,DQ packets for memory
access.
RLXR
Relax command in ROP field.
RLXX
Relax command in XOP field.
ROP
Row-opcode field in ROWR packet.
row
2CBIT dualocts of cells (bank/sense amp).
ROW
ROW
ROWA
transaction
transmit
Moving information from the RDRAM
onto the Channel (parallel word is muxed).
Pins for row-access control
WR/WRA
Write (/precharge) command in COP field.
ROWA or ROWR packets on ROW pins.
write
Operation of modifying sense amp data.
Activate packet on ROW pins.
XOP
Extended opcode field in COLX packet
Page 60
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Table Of Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Key Timing Parameters/Part Numbers . . . . . . . . . . . 1
Pinouts and Definitions . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7
Field Encoding Summary . . . . . . . . . . . . . . . . . . . . .8-9
DQ Packet Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 10
COLM Packet to D Packet Mapping . . . . . . . . . .10-11
ROW-to-ROW Packet Interaction . . . . . . . . . . . .12-13
ROW-to-COL Packet Interaction . . . . . . . . . . . . . . . 13
COL-to-COL Packet Interaction . . . . . . . . . . . . . . . . 14
COL-to-ROW Packet Interaction . . . . . . . . . . . . . . . 15
ROW-to-ROW Examples . . . . . . . . . . . . . . . . . . .16-17
Row and Column Cycle Description . . . . . . . . . . . . 17
Precharge Mechanisms . . . . . . . . . . . . . . . . . . . .18-19
Read Transaction - Example . . . . . . . . . . . . . . . . . . 20
Write Transaction - Example . . . . . . . . . . . . . . . . . . 21
Write/Retire - Examples . . . . . . . . . . . . . . . . . . . 22-23
Interleaved Write - Example. . . . . . . . . . . . . . . . . . . 24
Interleaved Read - Example . . . . . . . . . . . . . . . .24-25
Interleaved RRWW . . . . . . . . . . . . . . . . . . . . . . .24-25
Control Register Transactions . . . . . . . . . . . . . . . . . 26
Control Register Packets . . . . . . . . . . . . . . . . . . . . . 27
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28-30
Control Register Summary. . . . . . . . . . . . . . . . . 30-37
Power State Management . . . . . . . . . . . . . . . . . 38-41
Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Current and Temperature Control . . . . . . . . . . . . . . 43
Electrical Conditions . . . . . . . . . . . . . . . . . . . . . . . . 44
Timing Conditions . . . . . . . . . . . . . . . . . . . . . . . .44-45
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 46
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . 46
RSL Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
RSL - Receive Timing . . . . . . . . . . . . . . . . . . . . . . . 48
RSL - Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . 49
CMOS - Receive Timing . . . . . . . . . . . . . . . . . . .50-51
CMOS - Transmit Timing . . . . . . . . . . . . . . . . . . .52-53
RSL - Domain Crossing Window . . . . . . . . . . . . . . . 53
Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . 54
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . 55
IDD - Supply Current Profile . . . . . . . . . . . . . . . . . . 55
Capacitance and Inductance . . . . . . . . . . . . . . . .56-57
Center-Bonded uBGA Package . . . . . . . . . . . . . . . . 58
Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . .59-60
© Copyright January 2000 Samsung Electronics.
All rights reserved.
Direct Rambus and Direct RDRAM are trademarks of
Rambus Inc. Rambus, RDRAM, and the Rambus Logo are
registered trademarks of Rambus Inc.
This document contains advanced information that is subject
to change by Samsung without notice.
Document Version 1.02
Samsung Electronics Co., Ltd.
San #24 Nongseo-Ri, Kiheung-Eup Yongin-City
Kyunggi-Do, KOREA
Telephone: 82-331-209-4519
Fax: 82-2-760-7990
http://www.samsungsemi.com
Page 61
Rev. 1.02 Jan. 2000
Direct RDRAM™
K4R271669A/K4R441869A
Page 62
Rev. 1.02 Jan. 2000