IRF IRFR1N60A Power mosfet(vdss=600v, rds(on)max=7.0ohm, id=1.4a) Datasheet

PD - 91846B
SMPS MOSFET
Applications
l Switch Mode Power Supply (SMPS)
l Uninterruptable Power Supply
l Power Factor Correction
Benefits
l Low Gate Charge Qg results in Simple
Drive Requirement
l Improved Gate, Avalanche and dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current
IRFR1N60A
IRFU1N60A
HEXFET® Power MOSFET
VDSS
Rds(on) max
ID
600V
7.0Ω
1.4A
D-Pak
IRFR1N60A
I-Pak
IRFU1N60A
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current 
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery dv/dt ƒ
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
1.4
0.89
5.6
36
0.28
± 30
3.8
-55 to + 150
Units
A
W
W/°C
V
V/ns
°C
300 (1.6mm from case )
Applicable Off Line SMPS Topologies:
l
Low Power Single Transistor Flyback
Notes 
through
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are on page 9
1
3/7/03
IRFR/U1N60A
Static @ TJ = 25°C (unless otherwise specified)
V(BR)DSS
RDS(on)
VGS(th)
Parameter
Drain-to-Source Breakdown Voltage
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
IDSS
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Min.
600
–––
2.0
–––
–––
–––
–––
Typ.
–––
–––
–––
–––
–––
–––
–––
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
7.0
Ω
VGS = 10V, ID = 0.84A „
4.0
V
VDS = VGS, ID = 250µA
25
VDS = 600V, VGS = 0V
µA
250
VDS = 480V, VGS = 0V, TJ = 150°C
100
VGS = 30V
nA
-100
VGS = -30V
Dynamic @ TJ = 25°C (unless otherwise specified)
gfs
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
Min.
0.88
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
–––
–––
–––
9.8
14
18
20
229
32.6
2.4
320
11.5
130
Max. Units
Conditions
–––
S
VDS = 50V, ID = 0.84A
14
ID = 1.4A
2.7
nC VDS = 400V
8.1
VGS = 10V, See Fig. 6 and 13 „
–––
VDD = 250V
–––
ID = 1.4A
ns
–––
RG = 2.15Ω
–––
RD = 178Ω,See Fig. 10 „
–––
VGS = 0V
–––
VDS = 25V
–––
pF
ƒ = 1.0MHz, See Fig. 5
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 480V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 0V to 480V
Avalanche Characteristics
Parameter
EAS
IAR
EAR
Single Pulse Avalanche Energy‚
Avalanche Current
Repetitive Avalanche Energy
Typ.
Max.
Units
–––
–––
–––
93
1.4
3.6
mJ
A
mJ
Typ.
Max.
Units
–––
–––
–––
3.5
50
110
°C/W
Thermal Resistance
Parameter
RθJC
RθJA
RθJA
Junction-to-Case
Junction-to-Ambient (PCB mount)ˆ
Junction-to-Ambient
Diode Characteristics
IS
ISM
VSD
trr
Qrr
ton
2
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) 
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 1.4
showing the
A
G
integral reverse
5.6
––– –––
S
p-n junction diode.
––– ––– 1.6
V
TJ = 25°C, IS = 1.4A, VGS = 0V „
––– 290 440
ns
TJ = 25°C, IF = 1.4A
––– 510 760
nC di/dt = 100A/µs „
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRFR/U1N60A
10
10
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
1
0.1
4.5V
20µs PULSE WIDTH
TJ = 25 °C
0.01
0.1
1
10
4.5V
20µs PULSE WIDTH
TJ = 150 °C
0.1
1
100
10
100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
10
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
1
TJ = 150 ° C
1
TJ = 25 ° C
0.1
4.0
V DS = 100V
20µs PULSE WIDTH
5.0
6.0
7.0
8.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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9.0
ID = 1.4A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFR/U1N60A
10000
20
VGS , Gate-to-Source Voltage (V)
V GS = 0V,
f = 1MHz
C iss = C gs + C gd, C dsSHORTED
C rss = C gd
C oss = C ds + C gd
C, Capacitance (pF)
1000
Ciss
100
C oss
10
ID = 1.4A
VDS = 480V
VDS = 300V
VDS = 120V
16
12
8
4
FOR TEST CIRCUIT
SEE FIGURE 13
Crss
1
A
1
10
100
0
1000
0
2
8
10
12
14
100
10
OPERATION IN THIS AREA LIMITED
BY RDS(on)
ID , Drain Current (A)
ISD , Reverse Drain Current (A)
6
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
TJ = 150 ° C
1
TJ = 25 ° C
10
10us
100us
1
1ms
0.1
0.4
V GS = 0 V
0.6
0.8
1.0
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
4
QG , Total Gate Charge (nC)
V DS , Drain-to-Source Voltage (V)
1.2
0.1
TC = 25 ° C
TJ = 150 ° C
Single Pulse
10
10ms
100
1000
10000
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFR/U1N60A
1.6
RD
VDS
ID , Drain Current (A)
VGS
D.U.T.
RG
1.2
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
0.8
Fig 10a. Switching Time Test Circuit
0.4
VDS
90%
0.0
25
50
75
100
125
150
TC , Case Temperature ( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
D = 0.50
1
0.20
0.10
0.05
0.02
0.01
0.1
PDM
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
0.01
0.00001
Notes:
1. Duty factor D = t 1 / t 2
2. Peak TJ = P DM x Z thJC + TC
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
15V
DRIVER
L
VDS
D.U.T
RG
+
V
- DD
IAS
20V
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
A
EAS , Single Pulse Avalanche Energy (mJ)
IRFR/U1N60A
200
ID
0.65A
0.9A
BOTTOM 1.4A
TOP
160
120
80
40
0
25
50
75
100
125
150
Starting TJ , Junction Temperature( °C)
I AS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
10 V
770
QGD
VG
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
V DSav , Avalanche Voltage (V)
QGS
750
730
710
690
.3µF
D.U.T.
+
V
- DS
670
0.0
VGS
0.8
1.2
1.6
I av , Avalanche Current (A)
3mA
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
A
0.4
Fig 12d. Typical Drain-to-Source Voltage
Vs. Avalanche Current
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IRFR/U1N60A
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
ƒ
+
‚
-
-
„
+

RG
•
•
•
•
Driver Gate Drive
P.W.
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Period
D=
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
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7
IRFR/U1N60A
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
2.38 (.094)
2.19 (.086)
6.73 (.265)
6.35 (.250)
1.14 (.045)
0.89 (.035)
-A1.27 (.050)
0.88 (.035)
5.46 (.215)
5.21 (.205)
0.58 (.023)
0.46 (.018)
4
6.45 (.245)
5.68 (.224)
6.22 (.245)
5.97 (.235)
1.02 (.040)
1.64 (.025)
1
2
10.42 (.410)
9.40 (.370)
LEAD ASSIGNMENTS
1 - GATE
3
0.51 (.020)
MIN.
-B1.52 (.060)
1.15 (.045)
3X
1.14 (.045)
2X
0.76 (.030)
0.89 (.035)
0.64 (.025)
0.25 (.010)
2 - DRAIN
3 - SOURCE
4 - DRAIN
0.58 (.023)
0.46 (.018)
M A M B
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2.28 (.090)
4.57 (.180)
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
D-Pak (TO-252AA) Part Marking Information
Notes : T his part marking information applies to devices produced before 02/26/2001
EXAMPLE: T HIS IS AN IRFR120
WIT H AS S EMBLY
LOT CODE 9U1P
INT ERNAT IONAL
RECT IFIER
LOGO
IRFU120
9U
016
1P
DAT E CODE
YEAR = 0
WEEK = 16
AS S EMBLY
LOT CODE
Notes : T his part marking information applies to devices produced after 02/26/2001
EXAMPLE: T HIS IS AN IRFR120
WIT H AS S EMBLY
LOT CODE 1234
AS S EMBLED ON WW 16, 1999
IN T HE AS S EMBLY LINE "A"
INT ERNAT IONAL
RECT IFIER
LOGO
IRFU120
12
AS S EMBLY
LOT CODE
8
PART NUMBER
916A
34
DAT E CODE
YEAR 9 = 1999
WEEK 16
LINE A
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IRFR/U1N60A
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
6.73 (.265)
6.35 (.250)
2.38 (.094)
2.19 (.086)
-A-
0.58 (.023)
0.46 (.018)
1.27 (.050)
0.88 (.035)
5.46 (.215)
5.21 (.205)
LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
4
6.45 (.245)
5.68 (.224)
6.22 (.245)
5.97 (.235)
1.52 (.060)
1.15 (.045)
1
2
3
-B-
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2.28 (.090)
1.91 (.075)
9.65 (.380)
8.89 (.350)
2 CONTROLLING DIMENSION : INCH.
3 CONFORMS TO JEDEC OUTLINE TO-252AA.
4 DIMENSIONS SHOWN ARE BEFORE SOLDER DIP,
SOLDER DIP MAX. +0.16 (.006).
3X
1.14 (.045)
0.76 (.030)
3X
0.25 (.010)
2.28 (.090)
1.14 (.045)
0.89 (.035)
0.89 (.035)
0.64 (.025)
M A M B
2X
0.58 (.023)
0.46 (.018)
I-Pak (TO-251AA) Part Marking Information
Notes : T his part marking information applies to devices produced before 02/26/2001
EXAMPLE: T HIS IS AN IRFR120
WIT H AS S EMBLY
LOT CODE 9U1P
INT ERNAT IONAL
RECT IFIER
LOGO
IRFU120
016
9U
1P
DAT E CODE
YEAR = 0
WEEK = 16
AS S EMBLY
LOT CODE
Notes : T his part marking information applies to devices produced after 02/26/2001
EXAMPLE: T HIS IS AN IRFR120
WIT H AS S EMBLY
LOT CODE 5678
AS S EMBLED ON WW 19, 1999
IN T HE AS S EMBLY LINE "A"
INT ERNAT IONAL
RECT IFIER
LOGO
IRFU120
919A
56
AS S EMBLY
LOT CODE
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PART NUMBER
78
DAT E CODE
YEAR 9 = 1999
WEEK 19
LINE A
9
IRFR/U1N60A
Tape & Reel Information
TR
TO-252AA
TRR
TRL
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
‚ Starting TJ = 25°C, L = 95mH
RG = 25Ω, IAS = 1.4A. (See Figure 12)
ƒ ISD ≤ 1.4A, di/dt ≤ 180A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C
„ Pulse width ≤ 300µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
† When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to
application note #AN-994.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.3/03
10
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