MOTOROLA MCF5274VM166 Mcf5275 integrated microprocessor family hardware specification Datasheet

Freescale Semiconductor
Hardware Specification
MCF5275EC/D
Rev. 1.1, 9/2004
MCF5275 Integrated
Microprocessor Family Hardware
Specification
32-Bit Embedded Controller Division
The MCF5275 family is a highly integrated
implementation of the ColdFire® family of reduced
instruction set computing (RISC) microprocessors. This
document describes pertinent features and functions
characteristics of the MCF5275 family. The MCF5275
family includes the MCF5275, MCF5275L, MCF5274
and MCF5274L microprocessors. The differences
between these parts are summarized in Table 1. This
document is written from the perspective of the
MCF5275 and unless otherwise noted, the information
applies also to the MCF5275L, MCF5274 and
MCF5274L.
The MCF5275 family delivers a new level of
performance and integration on the popular version 2
ColdFire core with up to 159 (Dhrystone 2.1) MIPS @
166MHz. These highly integrated microprocessors build
upon the widely used peripheral mix on the popular
MCF5272 ColdFire microprocessor (10/100 Mbps
Ethernet MAC and USB device) by adding a second
10/100 Mbps Ethernet MAC (MCF5274 and MCF5275)
and hardware encryption (MCF5275L and MCF5275).
In addition, the MCF5275 family features an Enhanced
Multiply Accumulate Unit (EMAC), large on-chip
Technical Data
© Freescale Semiconductor, Inc., 2004. All rights reserved.
• Preliminary
Table of Contents
1
2
3
4
5
6
7
8
9
10
11
12
MCF5275 Family Configurations ..................... 2
Block Diagram ................................................. 3
Features .......................................................... 5
Signal Descriptions........................................ 17
Chip Configuration......................................... 32
Design Recommendations ............................ 34
Pinout ............................................................ 42
Mechanicals .................................................. 45
Ordering Information ..................................... 47
Preliminary Electrical Characteristics ............ 47
Device/Family Documentation List ................ 74
Document Revision History ........................... 74
MCF5275 Family Configurations
memory (64 Kbytes SRAM, 16 Kbytes configurable cache), and a 16-bit DDR SDRAM memory
controller.
These devices are ideal for cost-sensitive applications requiring significant control processing for file
management, connectivity, data buffering, and user interface, as well as signal processing in a variety of
key markets such as security, imaging, networking, gaming, and medical. This leading package of
integration and high performance allows fast time to market through easy code reuse and extensive third
party tool support.
To locate any published errata or updates for this document, refer to the ColdFire products website at
http://www.freescale.com.
1
MCF5275 Family Configurations
Table 1. MCF5275 Family Configurations
Module
5274L
5275L
5274
5275
x
x
x
x
ColdFire Version 2 Core with EMAC (Enhanced
Multiply-Accumulate Unit)
System Clock
up to 166 MHz
Performance (Dhrystone 2.1 MIPS)
up to 159
Instruction/Data Cache
16 Kbytes (configurable)
Static RAM (SRAM)
64 Kbytes
Interrupt Controllers (INTC)
2
2
2
2
Edge Port Module (EPORT)
x
x
x
x
External Interface Module (EIM)
x
x
x
x
4-channel Direct-Memory Access (DMA)
x
x
x
x
DDR SDRAM Controller
x
x
x
x
Fast Ethernet Controller (FEC)
1
1
2
2
Watchdog Timer Module (WDT)
x
x
x
x
4-channel Programmable Interval Timer Module (PIT)
x
x
x
x
32-bit DMA Timers
4
4
4
4
USB
x
x
x
x
QSPI
x
x
x
x
UART(s)
3
3
3
3
I2
C
x
x
x
x
PWM
4
4
4
4
General Purpose I/O Module (GPIO)
x
x
x
x
CIM = Chip Configuration Module + Reset Controller Module
x
x
x
x
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Block Diagram
Table 1. MCF5275 Family Configurations
Module
5274L
5275L
5274
5275
Debug BDM
x
x
x
x
JTAG - IEEE 1149.1 Test Access Port
x
x
x
x
Hardware Encryption
—
x
—
x
196
MAPBGA
196
MAPBGA
256
MAPBGA
256
MAPBGA
Package
2
Block Diagram
The superset device in the MCF5275 family comes in a 256 Mold Array Plastic Ball Grid Array
(MAPBGA) package.
Figure 1 shows a top-level block diagram of the MCF5275, the superset device.
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Block Diagram
DDR
EIM
QSPI
I2C_SDA
CHIP
SELECTS
(To/From SRAM backdoor)
I2C_SCL
TXDx
RXDx
EBI
INTC0
Arbiter
RTSx
INTC1
CTSx
DTOUTx
DTINx
FAST ETHERNET
CONTROLLER
(FEC0)
FEC0
UART
0
FAST ETHERNET
CONTROLLER
(FEC1)
(To/From PADI)
UART
1
DTIM
0
(To/From
PADI)
UART
2
DTIM
1
I2 C
QSPI
PADI – Pin Muxing
(To/From PADI)
SDRAMC
DTIM
3
DTIM
2
FEC1
USB
PWMx
D[31:16]
A[23:0]
R/W
CS[3:0]
4 CH DMA
TA
JTAG_EN
TRST
DACK[3:0]
BDM
DREQ[1:0]
JTAG
TAP
V2 ColdFire CPU
TCLK
TMS
EMAC
DIV
TDI
MUX
TDO
TSIZ[1:0]
JTAG_EN
TEA
BS[3:2]
64 Kbytes
SRAM
(8Kx16)x4
(To/From
PADI)
(To/From PADI)
16 Kbytes
CACHE
(1Kx32)x4
4 CH PWM
PORTS
(GPIO)
CIM
(To/From Arbiter backdoor)
Watchdog
Timer
SKHA
PLL
CLKGEN
RNGA
USB 2.0
Full Speed
MDHA
(To/From PADI)
PIT0
PIT1
PIT2
PIT3
(To/From INTC)
Edge
Port
Cryptography
Modules
Figure 1. MCF5275 Block Diagram
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Features
3
Features
This document contains information on a new product. Specifications and information herein are subject
to change without notice.
3.1
•
•
•
•
•
•
Feature Overview
ColdFire version 2 variable-length RISC processor
— Static operation
— 32-bit address and data path on-chip
— 166/133 MHz processor core and 83/66.5 MHz bus frequency
— Sixteen general-purpose 32-bit data and address registers
— Enhanced multiply accumulate unit (eMAC) for DSP and fast multiply operations
System debug support
— Real time trace for determining dynamic execution path while in emulator mode
— Background debug mode (BDM) for debug features while halted
— Real time debug support, with two user visible hardware breakpoint registers (PC and address
with optional data) that can be configured into a 1- or 2-level trigger
On chip memories
— 16 Kbyte cache, configurable as I-cache or I-cache and D-cache
— 64 Kbyte dual-ported SRAM on CPU internal bus with standby power supply support
Power management
— Fully static operation with processor sleep and whole chip stop modes
— Very rapid response to interrupts from the low-power sleep mode (wake-up feature)
Two Fast Ethernet Media Access Controllers (FEC MAC)
— 10 base T capability, half or full duplex
— 100 base T capability, half or full duplex throughput
— On chip transmit and receive FIFOs
— Built-in DMA controller
— Memory-based flexible descriptor rings
— Media independent interface (MII)
USB Device Module
— Supports full-speed 12-Mbps and low-speed 1.5-Mbps USB devices
— Full compliance with the Universal Serial Bus Specification, Revision 2.0
— Automatic hardware processing of USB standard device requests
— Supports external USB transceiver
— Protocol control and administration for up to four endpoints (programmable types)
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Features
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•
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•
•
•
•
— One FIFO RAM per endpoint (2-Kbyte total)
— Dedicated 1-Kbyte descriptor RAM, accessible from the Slave bus
— Remote wake-up
Hardware cryptography accelerator (optional)
— Random number generator
— DES/3DES/AES block cipher engine
— MD5/SHA-1/HMAC accelerator
Three Universal Asynchronous/synchronous Receiver Transmitters (UARTs)
— Serial communication channel
— 16-bit divider for clock generation
— Internal channel control logic
— Interrupt control logic
— Maskable interrupts
— DMA support
— Programmable clock-rate generator
— Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity
— Up to 2 stop bits in 1/16 increments
— Error-detection capabilities
— Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines
— Transmit and receive FIFO buffers
I2C Module
— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads
— Fully compatible with industry-standard I2C bus
— Master or slave modes support multiple masters
— Automatic interrupt generation with programmable level
Queued Serial Peripheral Interface (QSPI)
— Full-duplex, three-wire synchronous transfer
— Up to four chip selects available
— Master operation
— Programmable master bit rates
— Up to 16 preprogrammed transfers
Four 32-bit Timers with DMA request capability
Pulse width modulation (PWM) unit
— Four identical channels
Software Watchdog Timer
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Features
•
•
•
•
•
•
— 16-bit counter
— Low power mode support
Phase Locked Loop (PLL)
— Reference crystal 8 to 25 MHz
— Low power modes supported
— Separate CLKOUT and DDR_CLKOUT signals
Four Programmable Interrupt Timers (PITs)
Interrupt Controllers (x2)
— Support for 58 independent interrupt sources, organized as follows:
– 51 fully-programmable interrupt sources
– 7 fixed-level external interrupt sources
— Unique vector number for each interrupt source
— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)
— Support for hardware and software interrupt acknowledge (IACK) cycles
— Combinatorial path to provide wake-up from low power modes
DMA Controller
— Four fully programmable channels
— Dual-address and single-address transfer support with 8-, 16-, and 32-bit data capability
— Source/destination address pointers that can increment or remain constant
— 24-bit transfer counter per channel
— Auto-alignment transfers supported for efficient block movement
— Bursting and cycle steal support
— Two-bus-clock internal access
— External request pins for each channel
External Memory Interface
— External glueless connections to 8-, 16-, and 32-bit external memory devices (e.g., SRAM,
flash, ROM, etc.)
— Glueless interface to SRAM devices with or without byte strobe inputs
— Programmable wait state generator
— 16-bit external bidirectional data bus
— 24-bit address bus
— Eight chip selects
— Byte/write enables
— Ability to boot from external memories that are 8 or 16 bits wide
DDR SDRAM controller
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Features
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•
•
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3.2
— Supports 16-bit wide memory devices
— Supports Dual Data Rate (DDR) SDRAM.
— Page mode support
— Programmable refresh interval timer.
— Sleep mode and self-refresh.
— Supports 16-byte (4-beat, 4-byte) critical-word-first burst transfer.
— Memory sizes from 8 Mbyte to 128 MByte (per chip select)
— 166 MHz data transfer rate (DDR)
— Two independent chip selects
Reset
— Separate Reset In and Reset Out signals
— Six sources of reset (POR, External, Software, Watchdog, Loss of clock/lock)
— Status flag indication of source of last reset
Chip Configurations
— System configuration during reset
— Bus Monitor, Abort Monitor
— Configurable output pad drive strength
— Unique Part Identification and Part Revision Numbers
General Purpose I/O interface
— Up to 69 bits of general purpose I/O
— Coherent 32-bit control
— Bit manipulation supported via set/clear functions
— Unused peripheral pins may be used as extra GPIO
JTAG support for system level board testing
— Unique JTAG Part Identification and Part Revision Numbers
V2 Core Overview
The ColdFire V2 core is comprised of two separate pipelines that are decoupled by an instruction buffer.
The two-stage Instruction Fetch Pipeline (IFP) is responsible for instruction-address generation and
instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched
instructions awaiting execution in the Operand Execution Pipeline (OEP). The OEP includes two pipeline
stages. The first stage decodes instructions and selects operands (DSOC); the second stage (AGEX)
performs instruction execution and calculates operand effective addresses, if needed.
The V2 core implements the ColdFire Instruction Set Architecture Revision A with added support for a
separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the
V2 core includes the enhanced multiply-accumulate unit (EMAC) for improved signal processing
capabilities. The EMAC implements a 4-stage execution pipeline, optimized for 32 x 32 bit operations,
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with support for four 48-bit accumulators. Supported operands include 16- and 32-bit signed and unsigned
integers as well as signed fractional operands as well as a complete set of instructions to process these data
types. The EMAC provides superb support for execution of DSP operations within the context of a single
processor at a minimal hardware cost.
3.3
Debug Module
The ColdFire processor core debug interface is provided to support system debugging in conjunction with
low-cost debug and emulator development tools. Through a standard debug interface, users can access
real-time trace and debug information. This allows the processor and system to be debugged at full speed
without the need for costly in-circuit emulators. The debug interface is a superset of the BDM interface
provided on Motorola’s 683xx family of parts.
The on-chip breakpoint resources include a total of 6 programmable registers—a set of address registers
(with two 32-bit registers), a set of data registers (with a 32-bit data register plus a 32-bit data mask
register), and one 32-bit PC register plus a 32-bit PC mask register. These registers can be accessed through
the dedicated debug serial communication channel or from the processor’s supervisor mode programming
model. The breakpoint registers can be configured to generate triggers by combining the address, data, and
PC conditions in a variety of single or dual-level definitions. The trigger event can be programmed to
generate a processor halt or initiate a debug interrupt exception.
To support program trace, the Version 2 debug module provides processor status (PST[3:0]) and debug
data (DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand
data, and branch target addresses defining processor activity at the CPU’s clock rate.
3.4
JTAG
The MCF5275 microprocessors support circuit board test strategies based on the Test Technology
Committee of IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port
(TAP) consisting of a 16-state controller, an instruction register, and three test registers (a 1-bit bypass
register, a 326-bit boundary-scan register, and a 32-bit ID register). The boundary scan register links the
device’s pins into one shift register. Test logic, implemented using static logic design, is independent of
the device system logic.
The MCF5275 implementation can do the following:
• Perform boundary-scan operations to test circuit board electrical continuity
• Sample MCF5275 system pins during operation and transparently shift out the result in the
boundary scan register
• Bypass the MCF5275 for a given circuit board test by effectively reducing the boundary-scan
register to a single bit
• Disable the output drive to pins during circuit-board testing
• Drive output pins to stable levels
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Features
3.5
On-chip Memories
The 64 Kbyte data RAM and the 16 Kbyte cache RAM for the processors are built using a RAM compiler.
Both RAM blocks connect directly to the RAM controller via a standard single-port synchronous SRAM
interface.
3.5.1
Cache
The 16-Kbyte cache can be configured into one of three possible organizations: a 16-Kbyte instruction
cache, a 16-Kbyte data cache or a split 8-Kbyte instruction/8-Kbyte data cache. The configuration is
software-programmable by control bits within the privileged Cache Configuration Register (CACR). In all
configurations, the cache is a direct-mapped single-cycle memory.
3.5.2
SRAM
The SRAM module provides a general-purpose 64-Kbyte memory implemented as four 16-Kbyte blocks
that the ColdFire core can access in a single cycle. The location of the memory block can be set to any
64-Kbyte boundary within the 4-Gbyte address space. The memory is ideal for storing critical code or data
structures, for use as the system stack, or for storing FEC data buffers. Because the SRAM module is
physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses
or memory-referencing commands from the debug module.
The SRAM module is also accessible by non-core bus masters, for example the DMA and/or the FECs.
The dual-ported nature of the SRAM makes it ideal for implementing applications with double-buffer
schemes, where the processor and a DMA device operate in alternate regions of the SRAM to maximize
system performance. As an example, system performance can be increased significantly if Ethernet
packets are moved from the FEC into the SRAM (rather than external memory) prior to any processing.
3.6
Power Management
The MCF5275 family incorporates several low power modes of operation which are entered under
program control and exited by several external trigger events. An integrated Power-On Reset (POR) circuit
monitors the input supply and forces an MCU reset as the supply voltage rises.
3.7
Fast Ethernet Controller (FEC)
The MCF5275 family contains up to two 10/100 BaseT fast Ethernet Controllers (FECs). Refer to Table 1
for device configurations.
Each FEC includes these distinctive features:
• IEEE 802.3 MAC (compliant with IEEE 802.3 1998 edition)
• Built-in FIFO and DMA controller
• Support for different Ethernet physical interfaces:
— 100Mbps IEEE 802.3 MII
— 10Mbps IEEE 802.3 MII
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•
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3.8
Support for full-duplex operation (200Mbps throughput) with a minimum system clock of
50MHz
Support for half-duplex operation (100Mbps throughput) with a minimum system clock rate of
25MHz
IEEE 802.3 full duplex flow control
Programmable max frame length supports IEEE 802.1 VLAN tags and priority
Retransmission from transmit FIFO following a collision (no system bus utilization)
Automatic internal flushing of the receive FIFO for runts (collision fragments) and address
recognition rejects (no system bus utilization)
Address recognition
— Frames with broadcast address may be always accepted or always rejected
— Exact match for single 48-bit individual (unicast) address
— Hash (64-bit hash) check of individual (unicast) addresses
— Hash (64-bit hash) check of group (multicast) addresses
— Promiscuous mode
RMON and IEEE statistics
Interrupts for network activity and error conditions
Universal Serial Bus (USB)
The USB controller supports device mode data communications with a USB host (typically a PC).
The programmable USB registers allow the user to enable or disable the module, control characteristics of
individual endpoints, and monitor traffic flow through the module without ever seeing the low-level details
of the USB protocol.
The USB module provides the following features to the user:
• Supports full-speed 12-Mbps USB devices and low-speed 1.5-Mbps devices
• Full compliance with the Universal Serial Bus Specification, Revision 2.0
• Automatic hardware processing of USB standard device requests
• USB device controller with protocol control and administration for up to eight endpoints, 16
interfaces, and 16 configurations. Endpoint types are programmable with support for up to eight
control, interrupt, bulk, or isochronous endpoints
• Independent interrupts for each endpoint
• Supports remote wakeup via a register bit
• Detects start-of-frame and missed start-of-frame for isochronous endpoint synchronization
• Notification of start-of-frame, reset, suspend, and resume events
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Features
3.9
Cryptography
Some of the MCF5275 family devices incorporate small, fast, and dedicated hardware accelerators for
random number generation, message digest and hashing, and the DES, 3DES, and AES block cipher
functions. This allows for the implementation of common Internet security protocol cryptography
operations with performance well in excess of software-only algorithms. Refer to Table 1 for device
configurations.
3.10 UARTs
The MCF5275 family of microprocessors each contain three (3) UARTs that function independently. Any
of the three UARTs can be clocked by the system bus clock, eliminating the need for an external crystal.
Each UART module contains the following major functional features:
• Serial communication channel
• 16-bit divider for clock generation
• Internal channel control logic
• Interrupt control logic
• Maskable interrupts
• DMA support
• Programmable clock-rate generator
• Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity
• Up to 2 stop bits in 1/16 increments
• Error-detection capabilities
• Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines
• Transmit and receive FIFO buffers
• UART Modes of Operation:
— Full-duplex
— Auto-echo loopback
— Local loopback
— Remote loopback
3.11 I2C Bus
The I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange,
minimizing the interconnection between devices. This bus is suitable for applications requiring occasional
communications over a short distance between many devices. The flexible I2C allows additional devices
to be connected to the bus for expansion and system development.
The I2C includes these distinctive features:
•
Compatibility with I2C bus standard
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•
Multiple-master operation
Software programmable for one of 64 different serial clock frequencies
Software selectable acknowledge bit
Interrupt driven, byte-by-byte data transfer
Arbitration lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
Start and stop signal generation/detection
Repeated START signal generation
Acknowledge bit generation/detection
Bus-busy detection
DMA support
3.12 QSPI
The queued serial peripheral interface module provides a serial peripheral interface with queued transfer
capability. It allows users to enqueue up to 16 transfers at once, eliminating CPU intervention between
transfers. Transfer RAMs in the QSPI are indirectly accessible using address and data registers.
The QSPI contains the following features:
• Programmable queue to support up to 16 transfers without user intervention
• Supports transfer sizes of 8 to 16 bits in 1-bit increments
• Four peripheral chip-select lines
• Baud rates from 162.1 Kbps to 20.75 Mbps at 83 MHz
• Programmable delays before and after transfers
• Programmable clock phase and polarity
• Supports wraparound mode for continuous transfers
3.13 DMA Timers (DTIM0-DTIM3)
There are four independent, general purpose 32-bit platform timers (DTIM0, DTIM1, DTIM2, DTIM3)
on the MCF5275 family of microprocessors. The output of an 8-bit prescaler clocks each timer.
Each of the platform timer modules has these distinctive features:
• Programmable sources for the clock input, including external clock
• Input capture capability with programmable trigger edge on input pin
• Output compare with programmable mode for the output pin
•
•
•
Free run and restart modes
Maskable interrupts on input capture or reference compare
DMA support
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Features
Each of the four timer modules has four operating modes:
• Capture mode
• Output mode
• Reference compare mode
3.14 Pulse Width Modulation (PWM) Module
The Pulse Width Modulation (PWM) module generates a synchronous series of pulses having
programmable duty cycle. With a suitable low-pass filter, the PWM can be used as a digital-to-analog
converter.
The PWM module has six channels with independent control of left and center aligned outputs on each
channel. The MCF5275 family uses four of these channels namely 0, 1, 2 and 3. The emergency shutdown
functionality (channel 5 only) is not used for the MCF5275 family.
Each of the PWM channels has a programmable period and duty cycle as well as a dedicated counter. A
flexible clock select scheme allows a total of four different clock sources to be used with the counters. Each
of the modulators can create independent continuous waveforms with software-selectable duty rates from
0% to 100%. The PWM outputs can be programmed as left aligned outputs or center aligned outputs
Summary of the main features include:
• Independent PWM channels with programmable period and duty cycle
• Dedicated counter for each PWM channel
• Programmable PWM enable/disable for each channel
• Software selection of PWM duty pulse polarity for each channel
• Period and duty cycle are double buffered. Change takes effect when the end of the effective
period is reached (PWM counter reaches zero) or when the channel is disabled.
• Programmable center or left aligned outputs on individual channels
• 16-bit PWM resolution available by concatenating 8-bit channels
• Four clock sources (A, B, SA and SB) provide for a wide range of frequencies.
• Programmable Clock Select Logic
3.15 Software Watchdog Timer (WDT)
The watchdog timer is a 16-bit timer for helping software recover from runaway code. The watchdog
counter is a free-running down-counter that generates a reset on underflow. To prevent a reset, software
must periodically restart the countdown.
3.16 Phase Locked Loop (PLL)
The clock module contains a crystal oscillator (OSC), frequency modulated phase-locked loop (PLL),
reduced frequency divider (RFD), status/control registers, and control logic. To improve noise immunity,
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the PLL and OSC have their own power supply inputs, VDDPLL and VSSPLL. All other circuits are
powered by the normal supply pins, VDD and VSS.
3.17 Interrupt Controllers (INTC0/INTC1)
There are two interrupt controllers which support 58 interrupt sources on the MCF5275. Each interrupt
controller is organized as 7 levels with 9 interrupt sources per level. Each interrupt source has a unique
interrupt vector, and 51 of the 58 sources of a given controller provide a programmable level [1-7] and
priority within the level.
3.18 Direct Memory Access Controller (DMAC)
The Direct Memory Access Controller (DMA) Module provides an efficient way to move blocks of data
with minimal processor interaction. The DMA module provides four channels that allow byte, word, or
longword operand transfers. These transfers can be single or dual address to off-chip devices or dual
address to on-chip devices.
The DMA contains the following features:
• Four fully independent, programmable DMA controller channels/bus modules
• Auto-alignment feature for source or destination accesses
• Single- and dual-address transfers
• Up to four external request pins (DREQ[3:0])
• Channel arbitration on transfer boundaries
• Data transfers in 8-, 16-, 32- or 128-bit blocks via a 16-byte buffer
• Supports continuous-mode and cycle-steal transfers
• Independent transfer widths for source and destination
• Independent source and destination address registers
• Provide two clock data transfers
3.19 External Interface Module (EIM)
The external interface module on MCF5275 devices handles the transfer of information between the
internal core and memory, peripherals, or other processing elements in the external address space.
Programmable chip select outputs provide signals to enable external memory and peripheral circuits,
providing all handshaking and timing signals for automatic wait-state insertion and data bus sizing.
Base memory address and block size are programmable, with some restrictions. For example, the starting
address must be on a boundary that is a multiple of the block size. Each chip select is general purpose;
however, any one of the chip selects can be programmed to provide read and write enable signals suitable
for use with most popular static RAMs and peripherals. Data bus width (8-bit, 16-bit, or 32-bit) is
programmable on all chip selects, and further decoding is available for protection from user mode access
or read-only access.
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Features
The key features of the EIM are summarized below:
• Eight independent, user-programmable chip-select signals (CS[7:0]) that interface with various
memory types and peripherals
• Address masking for 64 Kbyte to 4 gigabyte memory block sizes
• Programmable wait states and port sizes
•
External master access to chip selects
3.20 Double Data Rate (DDR) Synchronous DRAM
(SDRAM) Controller
The SDRAMC provides a 16-bit glueless external interface to double-data-rate (DDR) SDRAM memory
devices. It is responsible for providing address, data and control signals for up to two independent
chip-selects.
The SDRAMC includes the following features:
• Supports a glueless interface to DDR SDRAMs
• 16-bit fixed memory port width
• 32-bit data bus interface to Coldfire core
• 16 bytes (8 beat x 16-bit) critical word first burst transfer
• Up to 14 row address lines, up to 12 column address lines, maximum of two chip selects. The
maximum row bits plus column bits is 24.
• Supported SDRAM devices include: 8, 16, 32, 64, and 128Mbyte per chip select
• Minimum memory configuration of 8 Mbyte—12 bit row address (RA), 8 bit column address
(CA), 2 bit bank address (BA) and one chip select
• Supports page mode to maximize the data rate
• Supports sleep mode and self-refresh mode
• Error detect and parity check are not supported
3.21 Resets
The Reset Controller is provided to determine the cause of reset, assert the appropriate reset signals to the
system, and then to keep a history of what caused the reset.
The MCF5275 family has six (6) sources of reset:
• External
• Power On Reset (POR)
• Watchdog timer
•
•
•
PLL Loss of Lock
PLL Loss of Clock
Software
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
16
Preliminary
Freescale Semiconductor
Signal Descriptions
External reset on the RSTOUT pin is software-assertable independent of chip reset state. There are also
software-readable status flags indicating the cause of the last reset.
3.22 General Purpose I/O
Most peripheral I/O pins on MCF5275 devices are muxed with GPIO, adding flexibility and usability to
all signals on the chip.
4
Signal Descriptions
Table 2 lists the signals for the MCF5275 in functional group order.
NOTE
In this table and throughout this document a single signal within a group is
designated without square brackets (i.e., A24), while designations for
multiple signals within a group use brackets (i.e., A[23:21]) and is meant to
include all signals within the two bracketed numbers when these numbers
are separated by a colon.
NOTE
The primary functionality of a pin is not necessarily its default functionality.
Pins that are muxed with GPIO will default to their GPIO functionality.
Bonded on
MCF5274/75
256 MAPBGA
Bonded on
MCF5274L/5L
196 MAPBGA
Table 2. Signal Information and Muxing
RESET
—
—
—
I
1
1
RSTOUT
—
—
—
O
1
1
Name
GPIO
Port
Alternate1
Alternate2 Dir.1
Reset
Clock
EXTAL
—
—
—
I
1
1
XTAL
—
—
—
O
1
1
CLKOUT
—
—
—
O
1
1
Mode Selection
CLKMOD[1:0]
—
—
—
I
2
2
RCON
—
—
—
I
1
1
O
3
3
External Memory Interface and Ports
A[23:21]
PADDR[7:5]
CS[6:4]
—
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
Preliminary
17
Signal Descriptions
Name
GPIO
Port
Alternate1
Bonded on
MCF5274/75
256 MAPBGA
Bonded on
MCF5274L/5L
196 MAPBGA
Table 2. Signal Information and Muxing (continued)
A[20:0]
—
—
—
O
21
21
D[31:16]
—
—
—
O
16
16
BS[3:2]
PBS[3:2]
CAS[3:2]
—
O
2
2
OE
PBUSCTL[7]
—
—
O
1
1
TA
PBUSCTL[6]
—
—
I
1
1
TEA
PBUSCTL[5]
DREQ1
—
I
1
0
R/W
PBUSCTL[4]
—
—
O
1
1
TSIZ1
PBUSCTL[3]
DACK1
—
O
1
1
TSIZ0
PBUSCTL[2]
DACK0
—
O
1
1
TS
PBUSCTL[1]
DACK2
—
O
1
1
TIP
PBUSCTL[0]
DREQ0
—
O
1
0
Alternate2 Dir.1
Chip Selects
CS[7:1]
PCS[7:1]
—
—
O
7
7
CS0
—
—
—
O
1
1
DDR SDRAM Controller
DDR_CLKOUT
—
—
—
O
1
1
DDR_CLKOUT
—
—
—
O
1
1
SD_CS[1:0]
PSDRAM[7:6]
CS[3:2]
—
O
2
2
SD_SRAS
PSDRAM[5]
—
—
O
1
1
SD_SCAS
PSDRAM[4]
—
—
O
1
1
SD_WE
PSDRAM[3]
—
—
O
1
1
SD_A10
—
—
—
O
1
1
SD_DQS[1:0]
PSDRAM[1:0]
—
—
I/O
2
2
SD_CKE
PSDRAM[2]
—
—
O
1
1
SD_VREF
—
—
—
I
2
2
External Interrupts Port
IRQ[7:5]
PIRQ[7:5]
—
—
I
3
3
IRQ[4]
PIRQ[4]
DREQ2
—
I
1
1
IRQ[3:2]
PIRQ[3:2]
DREQ[3:2]
—
I
2
2
IRQ1
PIRQ[1]
—
—
I
1
1
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
18
Preliminary
Freescale Semiconductor
Signal Descriptions
Bonded on
MCF5274/75
256 MAPBGA
Bonded on
MCF5274L/5L
196 MAPBGA
Table 2. Signal Information and Muxing (continued)
FEC0_MDIO
PFECI2C[5]
I2C_SDA
U2RXD
I/O
1
1
FEC0_MDC
PFECI2C[4]
I2C_SCL
U2TXD
O
1
1
FEC0_TXCLK
PFEC0H[7]
—
—
I
1
1
FEC0_TXEN
PFEC0H[6]
—
—
I
1
1
FEC0_TXD[0]
PFEC0H[5]
—
—
O
1
1
FEC0_COL
PFEC0H[4]
—
—
I
1
1
FEC0_RXCLK
PFEC0H[3]
—
—
I
1
1
FEC0_RXDV
PFEC0H[2]
—
—
I
1
1
FEC0_RXD[0]
PFEC0H[1]
—
—
I
1
1
FEC0_CRS
PFEC0H[0]
—
—
I
1
1
FEC0_TXD[3:1]
PFEC0L[7:5]
—
—
O
3
3
FEC0_TXER
PFEC0L[4]
—
—
O
1
1
FEC0_RXD[3:1]
PFEC0L[3:1]
—
—
I
3
3
FEC0_RXER
PFEC0L[0]
—
—
O
1
1
Name
GPIO
Port
Alternate1
Alternate2 Dir.1
FEC0
FEC1
FEC1_MDIO
PFECI2C[3]
—
—
I/O
1
0
FEC1_MDC
PFECI2C[2]
—
—
O
1
0
FEC1_TXCLK
PFEC1H[7]
—
—
I
1
0
FEC1_TXEN
PFEC1H[6]
—
—
I
1
0
FEC1_TXD[0]
PFEC1H[5]
—
—
O
1
0
FEC1_COL
PFEC1H[4]
—
—
I
1
0
FEC1_RXCLK
PFEC1H[3]
—
—
I
1
0
FEC1_RXDV
PFEC1H[2]
—
—
I
1
0
FEC1_RXD[0]
PFEC1H[1]
—
—
I
1
0
FEC1_CRS
PFEC1H[0]
—
—
I
1
0
FEC1_TXD[3:1]
PFEC1L[7:5]
—
—
O
3
0
FEC1_TXER
PFEC1L[4]
—
—
O
1
0
FEC1_RXD[3:1]
PFEC1L[3:1]
—
—
I
3
0
FEC1_RXER
PFEC1L[0]
—
—
O
1
0
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
Preliminary
19
Signal Descriptions
Bonded on
MCF5274/75
256 MAPBGA
Bonded on
MCF5274L/5L
196 MAPBGA
Table 2. Signal Information and Muxing (continued)
I2C_SDA
PFECI2C[1]
U2RXD
—
I/O
1
1
I2C_SCL
PFECI2C[0]
U2TXD
—
I/O
1
1
—
—
Name
GPIO
Port
Alternate1
Alternate2 Dir.1
I2C
DMA
DACK[3:0] and DREQ[3:0] do not have a dedicated bond pads.
Please refer to the following pins for muxing:
PCS3/PWM3 for DACK3, PCS2/PWM2 for DACK2, TSIZ1 for
DACK1, TSIZ0 for DACK0, IRQ3 for DREQ3, IRQ2 and TA for
DREQ2, TEA for DREQ1, and TIP for DREQ0.
QSPI
QSPI_CS[3:2]
PQSPI[6:5]
PWM[3:2]
DACK[3:2]
O
2
2
QSPI_CS1
PQSPI[4]
SD_CKE
—
O
1
1
QSPI_CS0
PQSPI[3]
—
—
O
1
1
QSPI_CLK
PQSPI[2]
I2C_SCL
—
O
1
1
QSPI_DIN
PQSPI[1]
I2C_SDA
—
I
1
1
QSPI_DOUT
PQSPI[0]
—
—
O
1
1
UARTs
U0CTS
PUARTL[0]
—
—
I
1
1
U0RTS
PUARTL[1]
—
—
O
1
1
U0RXD
PUARTL[3]
—
—
I
1
1
U0TXD
PUARTL[2]
—
—
O
1
1
U1CTS
PUARTL[4]
—
—
I
1
1
U1RTS
PUARTL[5]
—
—
O
1
1
U1RXD
PUARTL[7]
—
—
I
1
1
U1TXD
PUARTL[6]
—
—
O
1
1
U2CTS
PUARTH[1]
PWM1
—
I
1
0
U2RTS
PUARTH[0]
PWM0
—
O
1
0
U2RXD
PUARTH[3]
—
—
I
1
0
U2TXD
PUARTH[2]
—
—
O
1
0
—
I/O
1
1
USB
USB_SPEED
PUSBH[0]
—
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
20
Preliminary
Freescale Semiconductor
Signal Descriptions
Name
GPIO
Port
Alternate1
Bonded on
MCF5274/75
256 MAPBGA
Bonded on
MCF5274L/5L
196 MAPBGA
Table 2. Signal Information and Muxing (continued)
USB_CLK
PUSBL[7]
—
—
I
1
1
USB_RN
PUSBL[6]
—
—
I
1
1
USB_RP
PUSBL[5]
—
—
I
1
1
USB_RXD
PUSBL[4]
—
—
I
1
1
USB_SUSP
PUSBL[3]
—
—
O
1
1
USB_TN
PUSBL[2]
—
—
O
1
1
USB_TP
PUSBL[1]
—
—
O
1
1
USB_TXEN
PUSBL[0]
—
—
O
1
1
Alternate2 Dir.1
Timers (and PWMs)
DT3IN
PTIMER[7]
DT3OUT
U2RTS
I
1
1
DT3OUT
PTIMER[6]
PWM3
U2CTS
O
1
1
DT2IN
PTIMER[5]
DT2OUT
—
I
1
1
DT2OUT
PTIMER[4]
PWM2
—
O
1
1
DT1IN
PTIMER[3]
DT1OUT
—
I
1
1
DT1OUT
PTIMER[2]
PWM1
—
O
1
1
DT0IN
PTIMER[1]
DT0OUT
—
I
1
1
DT0OUT
PTIMER[0]
PWM0
—
O
1
1
BDM/JTAG2
DSCLK
—
TRST
—
I
1
1
PSTCLK
—
TCLK
—
O
1
1
BKPT
—
TMS
—
I
1
1
DSI
—
TDI
—
I
1
1
DSO
—
TDO
—
O
1
1
JTAG_EN
—
—
—
I
1
1
DDATA[3:0]
—
—
—
O
4
4
PST[3:0]
—
—
—
O
4
4
Test
TEST
—
—
—
I
1
1
PLL_TEST
—
—
—
I
1
1
Power Supplies
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
Preliminary
21
Signal Descriptions
Name
GPIO
Port
Alternate1
Bonded on
MCF5274/75
256 MAPBGA
Bonded on
MCF5274L/5L
196 MAPBGA
Table 2. Signal Information and Muxing (continued)
VDDPLL
—
—
—
I
1
1
VSSPLL
—
—
—
I
1
1
VDD
—
—
—
I
VSS
—
—
—
I
OVDD
—
—
—
I
OVSS
—
—
—
I
SD_VDD
—
—
—
I
Alternate2 Dir.1
NOTES:
1 Refers to pin’s primary function. All pins which are configurable for GPIO have a pullup
enabled in GPIO mode with the exception of PBUSCTL[7], PBUSCTL[4:0], PADDR,
PBS, PSDRAM.
2 If JTAG_EN is asserted, these pins default to Alternate 1 (JTAG) functionality. The GPIO
module is not responsible for assigning these pins.
4.1
Reset Signals
Table 3 describes signals that are used to either reset the chip or as a reset indication.
Table 3. Reset Signals
Signal Name
Abbreviation
Function
I/O
Reset In
RESET
Primary reset input to the device. Asserting RESET immediately
resets the CPU and peripherals.
I
Reset Out
RSTOUT
Driven low for 128 CPU clocks when the soft reset bit of the system
configuration register (SCR[SOFTRST]) is set. It is driven low for 32K
CPU clocks when the software watchdog timer times out or when a
low input level is applied to RESET.
O
4.2
PLL and Clock Signals
Table 4 describes signals that are used to support the on-chip clock generation circuitry.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
22
Preliminary
Freescale Semiconductor
Signal Descriptions
Table 4. PLL and Clock Signals
Signal Name
Abbreviation
Function
I/O
External Clock In
EXTAL
Always driven by an external clock input except when used as a
connection to the external crystal when the internal oscillator circuit is
used. The clock source is configured during reset by CLKMOD[1:0].
I
Crystal
XTAL
Used as a connection to the external crystal when the internal
oscillator circuit is used to drive the crystal.
O
Clock Out
CLKOUT
This output signal reflects the internal system clock.
O
4.3
Mode Selection
Table 5 describes signals used in mode selection.
Table 5. Mode Selection Signals
Signal Name
Abbreviation
Function
I/O
Clock Mode Selection
CLKMOD[1:0] Configure the clock mode after reset.
I
Reset Configuration
RCON
I
4.4
Indicates whether the external D[31:16] pin states affect chip
configuration at reset.
External Memory Interface Signals
These signals are used for doing transactions on the external bus.
Table 6 describes signals that are used for doing transactions on the external bus.
Table 6. External Memory Interface Signals
Signal Name
Abbreviation
Function
I/O
Address Bus
A[23:0]
The 24 dedicated address signals define the address of external byte,
word, and longword accesses. These three-state outputs are the 24
lsbs of the internal 32-bit address bus and multiplexed with the
SDRAM controller row and column addresses.
O
Data Bus
D[31:16]
These three-state bidirectional signals provide the general purpose
data path between the processor and all other devices.
I/O
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
Preliminary
23
Signal Descriptions
Table 6. External Memory Interface Signals (continued)
Signal Name
Byte Strobes
Abbreviation
BS[3:2]
Function
I/O
Define the flow of data on the data bus. During SRAM and peripheral
accesses, these output signals indicate that data is to be latched or
driven onto a byte of the data when driven low. The BS[3:2] signals are
asserted only to the memory bytes used during a read or write access.
BS3 controls access to the most significant byte lane of data, and BS2
controls access to the least significant byte lane of data.
The BS[3:2] signals are asserted during accesses to on-chip
peripherals but not to on-chip SRAM, or cache. During SDRAM
accesses, these signals act as the CAS[3:2] signals, which indicate a
byte transfers between SDRAM and the chip when driven high.
O
For SRAM or Flash devices, the BS[3:2] outputs should be connected
to individual byte strobe signals.
For SDRAM devices, the BS[3:2] should be connected to individual
SDRAM DQM signals. Note that most SDRAMs associate DQM1 with
the MSB, in which case BS3 should be connected to the SDRAM's
DQM1 input.
Output Enable
OE
Indicates when an external device can drive data during external read
cycles.
O
Transfer Acknowledge
TA
Indicates that the external data transfer is complete. During a read
cycle, when the processor recognizes TA, it latches the data and then
terminates the bus cycle. During a write cycle, when the processor
recognizes TA, the bus cycle is terminated.
I
Transfer Error
Acknowledge
TEA
Indicates an error condition exists for the bus transfer. The bus cycle
is terminated and the CPU begins execution of the access error
exception.
I
Read/Write
R/W
Indicates the direction of the data transfer on the bus for SRAM (R/W)
and SDRAM (SD_WE) accesses. A logic 1 indicates a read from a
slave device and a logic 0 indicates a write to a slave device
O
Transfer Size
TSIZ[1:0]
When the device is in normal mode, dynamic bus sizing lets the
programmer change data bus width between 8, 16, and 32 bits for
each chip select. The initial width for the bootstrap program chip
select, CS0, is determined by the state of TSIZ[1:0]. The program
should select bus widths for the other chip selects before accessing
the associated memory space. These pins our output pins.
O
Transfer Start
TS
Bus control output signal indicating the start of a transfer.
O
Transfer in Progress
TIP
Bus control output signal indicating bus transfer in progress.
O
Chip Selects
CS[7:0]
These output signals select external devices for external bus
transactions. The CS[3:2] can also be configured to function as
SDRAM chip selects SD_CS[1:0].
O
4.5
DDR SDRAM Controller Signals
Table 7 describes signals that are used for DDR SDRAM accesses.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
24
Preliminary
Freescale Semiconductor
Signal Descriptions
Table 7. SDRAM Controller Signals
Signal Name
Abbreviation
Function
I/O
SDRAM Clock Out
DDR_CLKOUT This output signal reflects the internal system clock.
O
SDRAM Inverted
Clock Out
DDR_CLKOUT This output signal reflects the inverted internal system clock.
O
SDRAM Synchronous
Row Address Strobe
SD_SRAS
SDRAM synchronous row address strobe.
O
SDRAM Synchronous SD_SCAS
Column Address Strobe
SDRAM synchronous column address strobe.
O
SDRAM Write Enable
SD_WE
SDRAM write enable.
O
SDRAM A10
SD_A10
SDRAM address bit 10 or command.
O
SDRAM Chip Selects
SD_CS[1:0]
SDRAM chip select signals.
O
SDRAM Clock Enable
SD_CKE
SDRAM clock enable.
O
SDRAM Data Strobes
SD_DQS[3:2]
SDRAM byte-lane read/write data strobe signals.
O
4.6
External Interrupt Signals
Table 8 describes the external interrupt signals.
Table 8. External Interrupt Signals
Signal Name
External Interrupts
4.7
Abbreviation
IRQ[7:1]
Function
I/O
External interrupt sources.
IRQ[3:2] can also be configured as DMA request signals DREQ[3:2].
IRQ4 can also be configured as DMA request signals DREQ2.
I
Fast Ethernet Controller Signals
The following signals are used by the Ethernet modules for data and clock signals.
Table 9. Ethernet Module (FEC) Signals
Signal Name
Abbreviation
Function
I/O
Management Data
FECn_MDIO
Transfers control information between the external PHY and the
media-access controller. Data is synchronous to FECn_MDC. Applies
to MII mode operation. This signal is an input after reset. When the
FEC is operated in 10Mbps 7-wire interface mode, this signal should
be connected to VSS.
I/O
Management Data
Clock
FECn_MDC
In Ethernet mode, FECn_MDC is an output clock which provides a
timing reference to the PHY for data transfers on the FECn_MDIO
signal. Applies to MII mode operation.
O
Transmit Clock
FECn_TXCLK
Input clock which provides a timing reference for FECn_TXEN,
FECn_TXD[3:0] and FECn_TXER
I
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
Preliminary
25
Signal Descriptions
Table 9. Ethernet Module (FEC) Signals (continued)
Signal Name
Abbreviation
Function
I/O
Transmit Enable
FECn_TXEN
Indicates when valid nibbles are present on the MII. This signal is
asserted with the first nibble of a preamble and is negated before the
first FECn_TXCLK following the final nibble of the frame.
O
Transmit Data 0
FECn_TXD0
FECn_TXD0 is the serial output Ethernet data and is only valid during
the assertion of FECn_TXEN. This signal is used for 10-Mbps
Ethernet data. It is also used for MII mode data in conjunction with
FECn_TXD[3:1].
O
Collision
FECn_COL
Asserted upon detection of a collision and remains asserted while the
collision persists. This signal is not defined for full-duplex mode.
I
Receive Clock
FECn_RXCLK
Provides a timing reference for FECn_RXDV, FECn_RXD[3:0], and
FECn_RXER.
I
Receive Data Valid
FECn_RXDV
Asserting the receive data valid (FECn_RXDV) input indicates that the
PHY has valid nibbles present on the MII. FECn_RXDV should remain
asserted from the first recovered nibble of the frame through to the last
nibble. Assertion of FECn_RXDV must start no later than the SFD and
exclude any EOF.
I
Receive Data 0
FECn_RXD0
FECn_RXD0 is the Ethernet input data transferred from the PHY to
the media-access controller when FECn_RxDV is asserted. This
signal is used for 10-Mbps Ethernet data. This signal is also used for
MII mode Ethernet data in conjunction with FECn_RXD[3:1].
I
When asserted, indicates that transmit or receive medium is not idle.
Applies to MII mode operation.
I
Transmit Data 1–3
FECn_TXD[3:1] In Ethernet mode, these pins contain the serial output Ethernet data
and are valid only during assertion of FECn_TXEN in MII mode.
O
Transmit Error
FECn_TXER
O
Receive Data 1–3
FECn_RXD[3:1] In Ethernet mode, these pins contain the Ethernet input data
transferred from the PHY to the Media Access Controller when
FECn_RXDV is asserted in MII mode operation.
I
Receive Error
FECn_RXER
O
Carrier Receive Sense FECn_CRS
4.8
In Ethernet mode, when FECn_TXER is asserted for one or more
clock cycles while FECn_TXEN is also asserted, the PHY sends one
or more illegal symbols. FECn_TXER has no effect at 10 Mbps or
when FECn_TXEN is negated. Applies to MII mode operation.
In Ethernet mode, FECn_RXER—when asserted with
FECn_RXDV—indicates that the PHY has detected an error in the
current frame. When FECn_RXDV is not asserted FECn_RXER has
no effect. Applies to MII mode operation.
Queued Serial Peripheral Interface (QSPI)
Table 10 describes QSPI signals.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
26
Preliminary
Freescale Semiconductor
Signal Descriptions
Table 10. Queued Serial Peripheral Interface (QSPI) Signals
Signal Name
Abbreviation
Function
I/O
QSPI Syncrhonous
Serial Output
QSPI_DOUT
Provides the serial data from the QSPI and can be programmed to be
driven on the rising or falling edge of QSPI_CLK. Each byte is sent
msb first.
O
QSPI Synchronous
Serial Data Input
QSPI_DIN
Provides the serial data to the QSPI and can be programmed to be
sampled on the rising or falling edge of QSPI_CLK. Each byte is
written to RAM lsb first.
I
QSPI Serial Clock
QSPI_CLK
Provides the serial clock from the QSPI. The polarity and phase of
QSPI_CLK are programmable. The output frequency is programmed
according to the following formula, in which n can be any value
between 1 and 255:
SPI_CLK = fsys/2 ÷ n
O
Synchronous Peripheral QSPI_CS[1:0] Provide QSPI peripheral chip selects that can be programmed to be
Chip Selects
active high or low. QSPI_CS1 can also be configured as SDRAM clock
enable signal SD_CKE.
O
4.9
I2C I/O SIGNALS
Table 11 describes the I2C serial interface module signals.
Table 11. I2C I/O Signals
Signal Name
Abbreviation
Function
I/O
Serial Clock
I2C_SCL
Open-drain clock signal for the for the I2C interface. Either it is driven
by the I2C module when the bus is in the master mode or it becomes
the clock input when the I2C is in the slave mode.
I/O
Serial Data
I2C_SDA
Open-drain signal that serves as the data input/output for the I2C
interface.
I/O
4.10 UART Module Signals
The UART modules use the signals in this section for data. The baud rate clock inputs are not supported.
Table 12. UART Module Signals
Signal Name
Abbreviation
Function
I/O
Transmit Serial Data
Output
UnTXD
Transmitter serial data outputs for the UART modules. The output is
held high (mark condition) when the transmitter is disabled, idle, or in
the local loopback mode. Data is shifted out, lsb first, on this pin at the
falling edge of the serial clock source.
O
Receive Serial Data
Input
UnRXD
Receiver serial data inputs for the UART modules. Data received on
this pin is sampled on the rising edge of the serial clock source lsb
first. When the UART clock is stopped for power-down mode, any
transition on this pin restarts it.
I
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
Preliminary
27
Signal Descriptions
Table 12. UART Module Signals (continued)
Signal Name
Abbreviation
Function
I/O
Clear-to-Send
UnCTS
Indicate to the UART modules that they can begin data transmission.
I
Request-to-Send
UnRTS
Automatic request-to-send outputs from the UART modules. UnRTS
can also be configured to be asserted and negated as a function of
the RxFIFO level.
O
4.11 USB Signals
Table 13 describes the USB serial interface module signals.
Table 13. USB Module Signals
Signal Name
Abbreviation
Function
I/O
USB Clock
USB_CLK
This 48MHz (or 6MHz) clock is used by the USB module for both
clock recovery and generation of a 12Mhz (or 1.5MHz) internal bit
clock.
I
USB Speed
USB_SPEED Applications which make use of low speed USB signalling must be
able to switch the USB transceiver between low speed and full speed
operations. Software has control of this function by driving the state
of the USB_SPD bit in the USB_CTRL register onto the
USB_SPEED pin.
USB Received D-
USB_RN
This signal is one half of the differential USB signal, and is extracted
from the USB cable via a single ended input buffer on the analog
front end. This signal is used by the module for detecting the single
ended 0 (SE0) USB bus state.
I
USB Received D+
USB_RP
This signal is one half of the differential USB signal, and is extracted
from the USB cable via a single ended input buffer on the analog
front end. This signal is used by the module for detecting the single
ended 0 (SE0) USB bus state.
I
USB Receive Data
USB_RXD
Input data from the differential input receiver. USB_RXD is the
single-ended data extracted from the USB_RP and USB_RN signals
via a differential input buffer.
I
USB Suspended
USB_SUSP
After a long period of inactivity (3.0ms minimum), the USB will enter
suspend mode, indicated on the interface by an active state on
USB_SUSP. During this mode, the device is supposed to enter a low
power state while waiting for a wake-up from the USB Host. When
the device enters suspend mode, it asserts the suspend signal which
forces the analog front end into a low power state. When the device
leaves suspend mode, USB_SUSP is deasserted, enabling the
analog front end for normal USB operations.
O
USB Transmitted D-
USB_TN
This signal is one half of the differential NRZI formatted output from
the USB module. It is fed to the transmitted D- input of the analog
front end.
O
I/O
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
28
Preliminary
Freescale Semiconductor
Signal Descriptions
Table 13. USB Module Signals (continued)
Signal Name
Abbreviation
Function
I/O
USB Transmitted D+
USB_TP
This signal is one half of the differential NRZI formatted output from
the module. It is fed to the transmitted D+ input of the analog front
end.
O
USB Transmit Enable
USB_TXEN
This signal is an active low output enable for the differential drivers on
the analog front end. When this signal is active, the differential drivers
will drive the USB. When this signal is inactive, the differential drivers
will tristate their outputs.
O
4.12 DMA Timer Signals
Table 14 describes the signals of the four DMA timer modules.
Table 14. DMA Timer Signals
Signal Name
Abbreviation
Function
I/O
DMA Timer 0 Input
DT0IN
Can be programmed to cause events to occur in first platform timer. It
can either clock the event counter or provide a trigger to the timer
value capture logic.
I
DMA Timer 0 Output
DT0OUT
The output from first platform timer.
O
DMA Timer 1 Input
DT1IN
Can be programmed to cause events to occur in the second platform
timer. This can either clock the event counter or provide a trigger to the
timer value capture logic.
I
DMA Timer 1 Output
DT1OUT
The output from the second platform timer.
O
DMA Timer 2 Input
DT2IN
Can be programmed to cause events to occur in the third platform
timer. It can either clock the event counter or provide a trigger to the
timer value capture logic.
I
DMA Timer 2 Output
DT2OUT
The output from the third platform timer.
I
DMA Timer 3 Input
DT3IN
Can be programmed as an input that causes events to occur in the
fourth platform timer. This can either clock the event counter or
provide a trigger to the timer value capture logic.
I
DMA Timer 3 Output
DT3OUT
The output from the fourth platform timer.
O
4.13 Pulse Width Modulator Signals
Table 15 describes the PWM signals. Note that the primary functions of these pins are DMA Timer outputs
(DTnOUT).
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
Preliminary
29
Signal Descriptions
Table 15. PWM Signals
Signal Name
Abbreviation
Function
I/O
PWM Output Channel 0 PWM0
Pulse width modulated output for PWM channel 0.
O
PWM Output Channel 1 PWM1
Pulse width modulated output for PWM channel 1.
O
PWM Output Channel 2 PWM2
Pulse width modulated output for PWM channel 2.
O
PWM Output Channel 3 PWM3
Pulse width modulated output for PWM channel 3.
O
4.14 Debug Support Signals
These signals are used as the interface to the on-chip JTAG controller and also to interface to the BDM
logic.
Table 16. Debug Support Signals
Signal Name
Abbreviation
Function
I/O
Test Reset
TRST
This active-low signal is used to initialize the JTAG logic
asynchronously.
I
Test Clock
TCLK
Used to synchronize the JTAG logic.
I
Test Mode Select
TMS
Used to sequence the JTAG state machine. TMS is sampled on the
rising edge of TCLK.
I
Test Data Input
TDI
Serial input for test instructions and data. TDI is sampled on the rising
edge of TCLK.
I
Test Data Output
TDO
Serial output for test instructions and data. TDO is three-stateable and
is actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCLK.
O
Development Serial
Clock
DSCLK
Clocks the serial communication port to the BDM module during
packet transfers.
I
Breakpoint
BKPT
Used to request a manual breakpoint.
I
Development Serial
Input
DSI
This internally-synchronized signal provides data input for the serial
communication port to the BDM module.
I
Development Serial
Output
DSO
This internally-registered signal provides serial output communication
for BDM module responses.
O
Debug Data
DDATA[3:0]
Display captured processor data and breakpoint status. The CLKOUT
signal can be used by the development system to know when to
sample DDATA[3:0].
O
Processor Status
Outputs
PST[3:0]
Indicate core status, as shown in Table 17. Debug mode timing is
synchronous with the processor clock; status is unrelated to the
current bus transfer. The CLKOUT signal can be used by the
development system to know when to sample PST[3:0].
O
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
30
Preliminary
Freescale Semiconductor
Signal Descriptions
Table 17. Processor Status
PST[3:0]
Processor Status
0000
Continue execution
0001
Begin execution of one instruction
0010
Reserved
0011
Entry into user mode
0100
Begin execution of PULSE and WDDATA instructions
0101
Begin execution of taken branch
0110
Reserved
0111
Begin execution of RTE instruction
1000
Begin one-byte transfer on DDATA
1001
Begin two-byte transfer on DDATA
1010
Begin three-byte transfer on DDATA
1011
Begin four-byte transfer on DDATA
1100
Exception processing
1101
Reserved
1110
Processor is stopped
1111
Processor is halted
4.15 Test Signals
Table 18 describes test signals.
Table 18. Test Signals
Signal Name
Abbreviation
Function
I/O
Test
TEST
Reserved for factory testing only and in normal modes of operation
should be connected to VSS to prevent unintentional activation of test
functions.
I
PLL Test
PLL_TEST
Reserved for factory testing only and should be treated as a
no-connect (NC).
I
4.16 Power and Ground Pins
The pins described in Table 19 provide system power and ground to the chip. Multiple pins are provided
for adequate current capability. All power supply pins must have adequate bypass capacitance for
high-frequency noise suppression.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
Preliminary
31
Chip Configuration
Table 19. Power and Ground Pins
Signal Name
Abbreviation
Function
I/O
PLL Analog Supply
VDDPLL,
VSSPLL
Dedicated power supply signals to isolate the sensitive PLL analog
circuitry from the normal levels of noise present on the digital power
supply.
I
Positive Supply
VDDO
These pins supply positive power to the I/O pads.
I
Positive Supply
VDD
These pins supply positive power to the core logic.
I
Ground
VSS
This pin is the negative supply (ground) to the chip.
5
Chip Configuration
5.1
Device Operating Options
•
•
•
•
•
Chip operating mode:
— Master mode
Boot device/size:
— External device boot
– 32-bit
– 16-bit (Default)
– 8-bit
Output pad strength:
— Partial drive strength (Default)
— Full drive strength
Clock mode:
— Normal PLL with external crystal
— Normal PLL with external clock
— 1:1 PLL Mode
— External oscillator mode (no PLL)
Chip Select Configuration:
— PADDR[7:5] configured as chip select(s) and/or address line(s)
– PADDR[7:5] configured as A23-A21 (default)
– PADDR configured as CS6, PADDR[6:5] as A22-A21
– PADDR[7:6] configured as CS[6:5], PADDR5 as A21
– PADDR[7:5] configured as CS[6:4]
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
32
Preliminary
Freescale Semiconductor
Chip Configuration
5.2
Chip Configuration Pins
Table 20. Configuration Pin Descriptions
Chip Configuration
Function
Pin
5.3
Pin State/Meaning
Comments
RCON
Chip configuration
enable
1 disabled
0 enabled
Active low: if asserted, then all
configuration pins must be driven
appropriately for desired operation
D26, D17, D16
Select chip
operating mode
111
110
101
100
0xx
D19, D18
Select external boot
device data port size
00,11 external (32-bit)
10 external (8-bit)
01 external (16-bit)
D21
Select output pad
drive strength
1 Full
0 Partial
CLKMOD1,
CLKMOD0
Select clock mode
00 External clock mode (no VDDPLL must be supplied if a PLL
PLL)
mode is selected
01 1:1 PLL mode
10 Normal PLL with
external clock reference
11 Normal PLL with crystal
clock reference
D25, D24
Select chip select /
address line
00 PADDR[7:5] configured
as A23-A21 (default)
10 PADDR7 configured as
CS6,
PADDR[6:5] as A22-A21
01 PADDR[7:6] configured
as CS[6:5],
PADDR5 as A21
11 PADDR[7:5] configured
as CS[6:4]
JTAG_EN
Selects BDM or
JTAG mode
0 BDM mode
1 JTAG mode
master
reserved
reserved
reserved
reserved
Value read defaults to 32-bit
Chip Configuration Circuit
Figure 2 shows a block diagram of the recommended circuit used to drive the reset configuration values
for the MCF5275.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
Preliminary
33
Design Recommendations
74HC244
MCF5275
D16
Inputs
driven
high or
low as
needed
D17
D18
D19
D21
D24
D25
D26
OE
RSTOUT
RCON
VDD/VSS
CLKMOD0
CLKMOD1
JTAG_EN
Figure 2. MCF5275 Recommended Reset Configuration Circuit
6
Design Recommendations
6.1
Layout
•
•
•
6.2
•
Use a 4-layer printed circuit board with the VDD and GND pins connected directly to the power
and ground planes for the MCF5275.
See application note AN1259 System Design and Layout Techniques for Noise Reduction in
MCU-Based Systems.
Match the PC layout trace width and routing to match trace length to operating frequency and
board impedance. Add termination (series or therein) to the traces to dampen reflections.
Increase the PCB impedance (if possible) keeping the trace lengths balanced and short. Then do
cross-talk analysis to separate traces with significant parallelism or are otherwise "noisy". Use 6
mils trace and separation. Clocks get extra separation and more precise balancing.
Power Supply
33uF, 0.1uF and 0.01uF across each power supply
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
34
Preliminary
Freescale Semiconductor
Design Recommendations
6.3
•
•
Decoupling
Place the decoupling capacitors as close to the pins as possible, but they can be outside the
footprint of the package.
0.1uF and 0.01uF at each supply input
6.4
•
Buffering
Use bus buffers on all data/address lines for all off-board accesses and for all on-board accesses
when excessive loading is expected. See electricals.
6.5
•
Pull-up Recommendations
Use external pull-up resistors on unused inputs. See pin table.
6.6
•
•
•
•
•
•
•
•
Clocking Recommendations
Use a multi-layer board with a separate ground plane.
Place the crystal and all other associated components as close to the EXTAL and XTAL
(oscillator pins) as possible.
Do not run a high frequency trace around crystal circuit.
Ensure that the ground for the bypass capacitors is connected to a solid ground trace.
Tie the ground trace to the ground pin nearest EXTAL and XTAL. This prevents large loop
currents in the vicinity of the crystal.
Tie the ground pin to the most solid ground in the system.
Do not connect the trace that connects the oscillator and the ground plane to any other circuit
element. This tends to make the oscillator unstable.
Tie XTAL to ground when an external oscillator is clocking the device.
6.7
6.7.1
6.7.1.1
Interface Recommendations
DDR SDRAM Controller
SDRAM Controller Signals in Synchronous Mode
Table 21 shows the behavior of SDRAM signals in synchronous mode.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
Preliminary
35
Design Recommendations
Table 21. Synchronous DRAM Signal Connections
Signal
Description
SD_SRAS
Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be
latched by the SDRAM. SD_SRAS should be connected to the corresponding SDRAM
SD_SRAS. Do not confuse SD_SRAS with the DRAM controller’s SDRAM_CS[1:0], which
should not be interfaced to the SDRAM SD_SRAS signals.
SD_SCAS
Synchronous column address strobe. Indicates a valid column address is present and can be
latched by the SDRAM. SD_SCAS should be connected to the corresponding signal labeled
SD_SCAS on the SDRAM.
SD_WE
DRAM read/write. Asserted for write operations and negated for read operations.
SD_CS[1:0]
Row address strobe. Select each memory block of SDRAMs connected to the MCF5275. One
SDRAM_CS signal selects one SDRAM block and connects to the corresponding CS signals.
SD_CKE
Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of
SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is low, memory can
enter a power-down mode where operations are suspended or they can enter self-refresh
mode. SD_CKE functionality is controlled by DCR[COC]. For designs using external
multiplexing, setting COC allows SD_CKE to provide command-bit functionality.
BS[3:2]
Column address strobe. For synchronous operation, BS[3:2] function as byte enables to the
SDRAMs. They connect to the DQM signals (or mask qualifiers) of the SDRAMs.
DDR_CLKOUT
Bus clock output. Connects to the CLK input of SDRAMs.
6.7.1.2
Address Multiplexing
Table 22 shows the generic address multiplexing scheme for SDRAM configurations. All possible address
connection configurations can be derived from this table.
Table 22. Generic Address Multiplexing Scheme
Address Pin Row Address Column Address
17
17
Notes Related to Port Sizes
0
8-bit port only
8- and 16-bit ports only
16
16
1
15
15
2
14
14
3
13
13
4
12
12
5
11
11
6
10
10
7
9
9
8
17
17
16
32-bit port only
18
18
17
16-bit port only or 32-bit port with only 8
column address lines
19
19
18
16-bit port only when at least 9 column
address lines are used
20
20
19
21
21
20
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
36
Preliminary
Freescale Semiconductor
Design Recommendations
Table 22. Generic Address Multiplexing Scheme (continued)
Address Pin Row Address Column Address
22
22
21
23
23
22
24
24
23
25
25
24
Notes Related to Port Sizes
The following tables provide a more comprehensive, step-by-step way to determine the correct address
line connections for interfacing the MCF5275 to SDRAM. To use the tables, find the one that corresponds
to the number of column address lines on the SDRAM and to the port size as seen by the MCF5275, which
is not necessarily the SDRAM port size. For example, if two 8M x 8-bit SDRAMs together form a
8M x 16-bit memory, the port size is 16 bits. Most SDRAMs likely have fewer address lines than are
shown in the tables, so follow only the connections shown until all SDRAM address lines are connected.
Table 23. MCF5275 to SDRAM Interface (8-Bit Port, 9-Column Address Lines)
MCF5275 A17 A16 A15 A14 A13 A12 A11 A10 A9 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
17
16
15
14
13
12
11
10
9
Column
0
1
2
3
4
5
6
7
8
SDRAM
Pins
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22
Table 24. MCF5275 to SDRAM Interface (8-Bit Port,10-Column Address Lines)
MCF5275 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
17
16
15
14
13
12
11
10
9
19
Column
0
1
2
3
4
5
6
7
8
18
SDRAM
Pins
20
21
22
23
24
25
26
27
28
29
30
31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
Table 25. MCF5275 to SDRAM Interface (8-Bit Port,11-Column Address Lines)
MCF5275 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
17
16
15
14
13
12
11
10
9
19
21
Column
0
1
2
3
4
5
6
7
8
18
20
SDRAM
Pins
22
23
24
25
26
27
28
29
30
31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
Preliminary
37
Design Recommendations
Table 26. MCF5275 to SDRAM Interface (8-Bit Port,12-Column Address Lines)
MCF5275 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
17
16
15
14
13
12
11
10
9
19
21
23
Column
0
1
2
3
4
5
6
7
8
18
20
22
SDRAM
Pins
24
25
26
27
28
29
30
31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
Table 27. MCF5275 to SDRAM Interface (8-Bit Port,13-Column Address Lines)
MCF5275 A17 A16 A15 A14 A13 A12 A11 A10 A9 A19 A21 A23 A25 A26 A27 A28 A29 A30 A31
Pins
Row
17
16
15
14
13
12
11
10
9
19
21
23
25
Column
0
1
2
3
4
5
6
7
8
18
20
22
24
SDRAM
Pins
26
27
28
29
30
31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18
Table 28. MCF5275 to SDRAM Interface (16-Bit Port, 8-Column Address Lines)
MCF5275 A16 A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
16
15
14
13
12
11
10
9
Column
1
2
3
4
5
6
7
8
SDRAM
Pins
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22
Table 29. MCF5275 to SDRAM Interface (16-Bit Port, 9-Column Address Lines)
MCF5275 A16 A15 A14 A13 A12 A11 A10 A9 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
16
15
14
13
12
11
10
9
18
Column
1
2
3
4
5
6
7
8
17
SDRAM
Pins
19
20
21
22
23
24
25
26
27
28
29
30
31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
Table 30. MCF5275 to SDRAM Interface (16-Bit Port, 10-Column Address Lines)
MCF5275 A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
16
15
14
13
12
11
10
9
18
20
21
22
23
24
25
26
27
28
29
30
31
Column
1
2
3
4
5
6
7
8
17
19
SDRAM
Pins
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
38
Preliminary
Freescale Semiconductor
Design Recommendations
Table 31. MCF5275 to SDRAM Interface (16-Bit Port, 11-Column Address Lines)
MCF5275 A16 A15 A14 A13 A12 A11 A10 A9 A18 A20 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
16
15
14
13
12
11
10
9
18
20
22
23
24
25
26
27
28
29
30
31
Column
1
2
3
4
5
6
7
8
17
19
21
SDRAM
Pins
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
Table 32. MCF5275 to SDRAM Interface (16-Bit Port, 12-Column Address Lines)
MCF5275 A16 A15 A14 A13 A12 A11 A10
Pins
A9
A18 A20 A22 A24 A25 A26 A27 A28 A29 A30 A31
Row
16
15
14
13
12
11
10
9
18
20
22
24
Column
1
2
3
4
5
6
7
8
17
19
21
23
SDRAM
Pins
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
25
26
27
28
29
30
31
A10 A11 A12 A13 A14 A15 A16 A17 A18
Table 33. MCF5275 to SDRAM Interface (16-Bit Port, 13-Column-Address Lines)
MCF5275 A16 A15 A14 A13 A12 A11 A10
Pins
A9
A18 A20 A22 A24 A26 A27 A28 A29 A30 A31
Row
16
15
14
13
12
11
10
9
18
20
22
24
26
Column
1
2
3
4
5
6
7
8
17
19
21
23
25
SDRAM
Pins
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
27
28
29
30
31
A10 A11 A12 A13 A14 A15 A16 A17
Table 34. MCF5275 to SDRAM Interface (32-Bit Port, 8-Column Address Lines)
MCF5275 A15 A14 A13 A12 A11 A10 A9 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
15
14
13
12
11
10
9
17
Column
2
3
4
5
6
7
8
16
SDRAM
Pins
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
Table 35. MCF5275 to SDRAM Interface (32-Bit Port, 9-Column Address Lines)
MCF5275 A15 A14 A13 A12 A11 A10 A9 A17 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
15
14
13
12
11
10
9
17
19
Column
2
3
4
5
6
7
8
16
18
SDRAM
Pins
A0
A1
A2
A3
A4
A5
A6
A7
A8
20
21
22
23
24
25
26
27
28
29
30
31
A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
Preliminary
39
Design Recommendations
Table 36. MCF5275 to SDRAM Interface (32-Bit Port, 10-Column Address Lines)
MCF5275 A15 A14 A13 A12 A11 A10 A9 A17 A19 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31
Pins
Row
15
14
13
12
11
10
9
17
19
21
22
23
24
25
26
27
28
29
30
31
Column
2
3
4
5
6
7
8
16
18
20
SDRAM
Pins
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
Table 37. MCF5275 to SDRAM Interface (32-Bit Port, 11-Column Address Lines)
MCF5275 A15 A14 A13 A12 A11 A10
Pins
A9
A17 A19 A21 A23 A24 A25 A26 A27 A28 A29 A30 A31
Row
15
14
13
12
11
10
9
17
19
21
23
Column
2
3
4
5
6
7
8
16
18
20
22
SDRAM
Pins
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
24
25
26
27
28
29
30
31
A10 A11 A12 A13 A14 A15 A16 A17 A18
Table 38. MCF5275 to SDRAM Interface (32-Bit Port, 12-Column Address Lines)
MCF5275 A15 A14 A13 A12 A11 A10
Pins
A9
A17 A19 A21 A23 A25 A26 A27 A28 A29 A30 A31
Row
15
14
13
12
11
10
9
17
19
21
23
25
Column
2
3
4
5
6
7
8
16
18
20
22
24
SDRAM
Pins
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
6.7.1.2.1
26
27
28
29
30
31
A10 A11 A12 A13 A14 A15 A16 A17
SDRAM Interfacing Example
The tables in the previous section can be used to configure the interface in the following example. To
interface one 2M x 32-bit x 4 bank SDRAM component (8 columns) to the MCF5275, the connections
would be as shown in Table 39.
Table 39. SDRAM Hardware Connections
SDRAM
Pins
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10 = CMD
BA0
BA1
MCF5275
Pins
A15
A14
A13
A12
A11
A10
A9
A17
A18
A19
A20
A21
A22
6.7.2
Ethernet PHY Transceiver Connection
The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial interface for 10
Mbps Ethernet. The interface mode is selected by R_CNTRL[MII_MODE]. In MII mode, the 802.3
standard defines and the FEC module supports 18 signals. These are shown in Table 40.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
40
Preliminary
Freescale Semiconductor
Design Recommendations
Table 40. MII Mode
Signal Description
MCF5275 Pin
Transmit clock
FECn_TXCLK
Transmit enable
FECn_TXEN
Transmit data
FECn_TXD[3:0]
Transmit error
FECn_TXER
Collision
FECn_COL
Carrier sense
FECn_CRS
Receive clock
FECn_RXCLK
Receive enable
FECn_RXDV
Receive data
FECn_RXD[3:0]
Receive error
FECn_RXER
Management channel clock
FECn_MDC
Management channel serial data
FECn_MDIO
The serial mode interface operates in what is generally referred to as AMD mode. The MCF5275
configuration for seven-wire serial mode connections to the external transceiver are shown in Table 41.
Table 41. Seven-Wire Mode Configuration
Signal Description
MCF5275 Pin
Transmit clock
FECn_TXCLK
Transmit enable
FECn_TXEN
Transmit data
FECn_TXD[0]
Collision
FECn_COL
Receive clock
FECn_RXCLK
Receive enable
FECn_RXDV
Receive data
FECn_RXD[0]
Unused, configure as PB14
FECn_RXER
Unused input, tie to ground
FECn_CRS
Unused, configure as PB[13:11]
FECn_RXD[3:1]
Unused output, ignore
FECn_TXER
Unused, configure as PB[10:8]
FECn_TXD[3:1]
Unused, configure as PB15
FECn_MDC
Input after reset, connect to ground
FECn_MDIO
Refer to the M5275EVBevaluation board user’s manual for an example of how to connect an external
PHY. Schematics for this board are accessible at the MCF5275 site by navigating from:
http://e-www.motorola.com/ following the 32-bit Embedded Processors, 68K/ColdFire, MCF5xxx,
MCF5275 and M5275EVB links.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
Preliminary
41
Pinout
6.7.3
BDM
Use the BDM interface as shown in the M5275EVB evaluation board user’s manual. The schematics for
this board are accessible at the MCF5275 site by navigating from: http://e-www.motorola.com/ following
the 32-bit Embedded Processors, 68K/ColdFire, MCF5xxx, MCF5275 and M5275EVB links.
7
Pinout
7.1
256 MAPBGA Pinout
Figure 3 is a consolidated MCF5274/75 pinout for the 256 MAPBGA package. Table 2 lists the signals by
group and shows which signals are muxed and bonded on each of the device packages.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
42
Preliminary
Freescale Semiconductor
Pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
VSS
FEC1_
RXD1
FEC1_
RXDV
FEC1_
CRS
FEC1_
COL
FEC0_
COL
FEC0_
MDIO
U0RXD
U1RXD
VSS
A23
A20
A17
A14
SD_
VREF
VSS
A
B
FEC1_
RXD3
FEC1_
RXD2
FEC1_
RXD0
FEC1_
RXCLK
FEC0_
RXDV
FEC0_
RXCLK
FEC0_
MDC
U0TXD
U1TXD
I2C_
SDA
A22
A19
A16
A13
A11
A9
B
C
FEC1_
TXCLK
FEC1_
RXER
FEC0_
TXCLK
FEC0_
RXER
FEC0_
RXD2
FEC0_
RXD0
FEC0_
CRS
U0CTS
U1CTS
I2C_
SCL
A21
A18
A15
A12
A10
A8
C
D
FEC1_
TXER
FEC1_
TXEN
FEC0_
TXER
FEC0_
TXEN
FEC0_
RXD3
FEC0_
RXD1
U0RTS
VDD
U1RTS
CS7
CS6
CS5
CS4
A7
A6
TSIZ1
D
E
FEC1_
TXD3
FEC1_
TXD2
FEC0_
TXD3
NC
VSS
OVDD
OVDD
OVDD SD_VDD SD_VDD SD_VDD
VSS
CS3
A5
A4
A3
E
F
FEC1_
TXD0
FEC1_
TXD1
FEC0_
TXD2
FEC0_
TXD1
OVDD
VSS
OVDD
OVDD SD_VDD SD_VDD
SD_VDD
CS2
A2
A1
A0
F
G
FEC1_
MDIO
FEC1_
MDC
DT0OUT
FEC0_
TXD0
OVDD
OVDD
VSS
VSS
VSS
VSS
SD_VDD SD_VDD
IRQ7
USB_
SPEED
USB_
CLK
TSIZ0
G
H
DT1IN
DT1OUT
DT0IN
NC
OVDD
OVDD
VSS
VSS
VSS
VSS
SD_VDD SD_VDD
VDD
IRQ4
IRQ5
IRQ6
H
J
VSS
DT2IN
DT2OUT
DT3IN
SD_VDD
SD_VDD
VSS
VSS
VSS
VSS
OVDD
OVDD
IRQ2
IRQ3
K
OE
SD_WE
DT3OUT
VDD
SD_VDD
SD_VDD
VSS
VSS
VSS
VSS
OVDD
OVDD
IRQ1
L
SD_
SCAS
SD_
SRAS
SD_CKE
TS
SD_VDD
VSS
SD_VDD SD_VDD OVDD
OVDD
VSS
OVDD
TA
USB_
TXEN
USB_
RXD
EXTAL
L
M
D31
SD_CS1
BS3
SD_DQS3
VSS
SD_VDD
SD_VDD SD_VDD OVDD
OVDD
OVDD
NC
USB_
SUSP
PLL_
TEST
VDDPLL
XTAL
M
N
D30
D29
D28
D20
D16
SD_A10
CS1
VDD
DDATA2 DDATA0
QSPI_
CS2
CLK
MOD1
RSTOUT RESET
VSS
N
P
D27
D26
D23
D19
SD_DQS2
TIP
R/W
RCON
U2CTS DDATA3 DDATA1
QSPI_
CS0
CLK
MOD0
TRST/
DSCLK
TDO/
DSO
TCLK/
P
PSTCLK
R
D25
D24
D22
D18
BS2
CS0
VSS
U2RTS
U2TXD
PST2
PST0
QSPI_
DOUT
QSPI_
CS3
JTAG_
EN
TMS/
BKPT
TDI/DSI R
T
VSS
SD_
VREF
D21
D17
SD_CS0
TEA
U2RXD
PST3
PST1
CLKOUT
QSPI_
DIN
QSPI_
CS1
QSPI_
CLK
VSS
1
2
3
4
5
8
9
10
11
12
13
14
15
16
DDR_CLK DDR_CLK
OUT
OUT
6
7
TEST
VSS
USB_RP USB_RN J
USB_TN USB_TP VSSPLL K
Figure 3. MCF5274 and MCF5275 Pinout (256 MAPBGA)
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
Preliminary
43
T
Pinout
7.2
196 MAPBGA Pinout
Figure 4 is a consolidated MCF5274L/75L pinout for the 196 MAPBGA package. Table 2 lists the signals
by group and shows which signals are muxed and bonded on each of the device packages.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
NC
FEC0_
CRS
FEC0_
MDIO
U0RXD
U0TXD
U1RXD
I2C_SCL
A23
CS6
CS5
A15
A12
SD_
VREF
NC
A
B
FEC0_
RXD2
FEC0_
RXD1
FEC0_
RXCLK
FEC0_
COL
U0RTS
U1RTS
I2C_SDA
A22
A20
A16
A13
CS3
A9
TSIZ1
B
C
FEC0_
TXCLK
FEC0_
TXER
FEC0_
TXEN
FEC0_
RXDV
FEC0_
MDC
U0CTS
U1CTS
A21
A18
A17
A14
A10
A8
CS2
C
D
FEC0_
TXD3
FEC0_
TXD0
FEC0_
TXD1
FEC0_
RXD3
FEC0_
RXD0
VDD
U1TXD
CS7
A19
CS4
A11
A7
A5
A2
D
E
DT0IN
DT0OUT
FEC0_
TXD2
FEC0_
RXER
OVDD
OVDD
OVDD
A6
A4
A1
TSIZ0
E
F
DT1IN
DT1OUT
DT2IN
DT2OUT
OVDD
OVDD
VSS
VSS
A3
USB_CLK
A0
IRQ7
F
G
DT3OUT
DT3IN
SD_CAS
SD_WE
VDD
VSS
VSS
VSS
VSS
SD_VDD2
USB_
SPEED
VDD
IRQ6
IRQ5
G
TS
SD_CS1
OE
SD_VDD1
VSS
VSS
VSS
VSS
OVDD
IRQ4
IRQ2
USB_RN
IRQ3
H
VSS
VSS
OVDD
OVDD
USB_RP
USB_TP
IRQ1
USB_TN
J
OVDD
OVDD
OVDD
TDO/DSO
RESET
USB_
TXEN
TA
K
QSPI_
DOUT
QSPI_CLK
RSTOUT
VSSPLL
QSPI_DIN CLKMOD1
TDI/DSI
VDDPLL
EXTAL
M
USB_
SUSP
XTAL
N
NC
P
H SD_SRAS
SD_VDD2 SD_VDD2 SD_VDD2
SD_VDD2 SD_VDD2
J
SD_CKE
SD_DQS3
D31
D22
SD_VDD1 SD_VDD1
K
BS3
D29
D28
D23
SD_VDD1 SD_VDD1 SD_VDD1
L
D30
D26
D25
D24
BS2
R/W
VDD
PST2
DDATA0
M
D27
D21
D18
D17
SD_CS0
RCON
DDATA3
PST1
QSPI_
CS0
N
D20
D19
D16
SD_A10
CS0
TEST
DDATA2
PST0
QSPI_
CS2
QSPI_
CS1
CLKMOD0 TMS/BKPT
P
NC
SD_
VREF
SD_DQS2
CS1
PST3
DDATA1
CLKOUT
QSPI_
CS3
JTAG_EN
1
2
3
4
7
8
9
10
11
DDR_CLK DDR_CLK
OUT
OUT
5
6
TCLK/PST TRST/DSC
CLK
LK
12
13
USB_RXD L
14
Figure 4. MCF5274L and MCF5275L Pinout (196 MAPBGA)
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
44
Preliminary
Freescale Semiconductor
Mechanicals
8
Mechanicals
8.1
Package Dimensions - 256 MAPBGA
Figure 6 shows MCF5275 256 MAPBGA package dimensions.
X
D
M
LASER MARK FOR PIN A1
IDENTIFICATION IN
THIS AREA
Y
5
K
A
0.30 Z
A2
A1
256X
Z
E
4
0.15 Z
DETAIL K
ROTATED 90 °CLOCKWISE
M
0.20
15X
e
S
16151413121110
15X
e
METALIZED MARK FOR
PIN A1 IDENTIFICATION
IN THIS AREA
7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
S
256X
3
b
0.25
M
0.10
M
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSION b IS MEASURED AT THE
MAXIMUM SOLDER BALL DIAMETER,
PARALLEL TO DATUM PLANE Z.
4. DATUM Z (SEATING PLANE) IS DEFINED BY
THE SPHERICAL CROWNS OF THE SOLDER
BALLS.
5. PARALLELISM MEASUREMENT SHALL
EXCLUDE ANY EFFECT OF MARK ON TOP
SURFACE OF PACKAGE.
Z X Y
Z
VIEW M-M
DIM
A
A1
A2
b
D
E
e
S
MILLIMETERS
MIN
MAX
1.25
1.60
0.27
0.47
1.16 REF
0.40
0.60
17.00 BSC
17.00 BSC
1.00 BSC
0.50 BSC
Figure 5. 256 MAPBGA Package Dimensions
8.2
Package Dimensions - 196 MAPBGA
Figure 6 shows MCF5275 196 MAPBGA package dimensions.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
Preliminary
45
Mechanicals
X
D
Y
Laser mark for pin 1
identification in
this area
NOTES:
1. Dimensions are in millimeters.
2. Interpret dimensions and tolerances per
ASME Y14.5M, 1994.
3. Dimension B is measured at the
maximum solder ball diameter, parallel
to datum plane Z.
4. Datum Z (seating plane) is defined by
the spherical crowns of the solder balls.
5. Parallelism measurement shall exclude
any effect of mark on top surface of
package.
M
K
E
DIM
A
A1
A2
b
D
E
e
S
M
Millimeters
Min Max
1.32 1.75
0.27 0.47
1.18 REF
0.35 0.65
15.00 BSC
15.00 BSC
1.00 BSC
0.50 BSC
0.20
13X
e
S
14 13 12 11 10
9
6
5
4
3
2
Metalized mark for
pin 1 identification
in this area
1
A
B
C
13X
5
D
S
E
e
F
A
0.30 Z
A2
G
H
J
A1
Z
K
L
M
0.15 Z
4
Detail K
Rotated 90° Clockwise
N
P
3
196X
b
0.30 Z X Y
View M-m
0.10 Z
Figure 6. 196 MAPBGA Package Dimensions
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
46
Preliminary
Freescale Semiconductor
Ordering Information
9
Ordering Information
Table 42. Orderable Part Numbers
Motorola Part
Number
Description
Speed
Temperature
MCF5274LVM133
MCF5274L RISC Microprocessor, 196 MAPBGA
133MHz
0° to +70° C
MCF5274LVM166
MCF5274L RISC Microprocessor, 196 MAPBGA
166MHz
0° to +70° C
MCF5274VM133
MCF5274 RISC Microprocessor, 256 MAPBGA
133MHz
0° to +70° C
MCF5274VM166
MCF5274 RISC Microprocessor, 256 MAPBGA
166MHz
0° to +70° C
MCF5275LCVM133
MCF5275L RISC Microprocessor, 196 MAPBGA
133MHz
-40° to +85° C
MCF5275LCVM166
MCF5275L RISC Microprocessor, 196 MAPBGA
166MHz
-40° to +85° C
MCF5275CVM133
MCF5275 RISC Microprocessor, 256 MAPBGA
133MHz
-40° to +85° C
MCF5275CVM166
MCF5275 RISC Microprocessor, 256 MAPBGA
166MHz
-40° to +85° C
10
Preliminary Electrical Characteristics
This appendix contains electrical specification tables and reference timing diagrams for the MCF5275
microcontroller unit. This section contains detailed information on power considerations, DC/AC
electrical characteristics, and AC timing specifications of MCF5275.
The electrical specifications are preliminary and are from previous designs or design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle, however
for production silicon these specifications will be met. Finalized specifications will be published after
complete characterization and device qualifications have been completed.
NOTE
The parameters specified in this appendix supersede any values found in the
module specifications.
10.1 Maximum Ratings
Table 43. Absolute Maximum Ratings1, 2
Rating
Symbol
Value
Unit
VDD
– 0.5 to +2.0
V
I/O Pad Supply Voltage (3.3V)
O VDD
– 0.3 to +4.0
V
Memory Interface SSTL 2.5V Pad Supply Voltage
SD VDD
– 0.3 to + 2.8
V
Memory Interface SSTL 3.3V Pad Supply Voltage
SD VDD
– 0.3 to +4.0
V
Clock Synthesizer Supply Voltage
VDDPLL
– 0.3 to +4.0
V
VIN
– 0.3 to + 4.0
V
EXTAL pin voltage
VEXTAL
0 to 3.3
V
XTAL pin voltage
VXTAL
0 to 3.3
V
Core Supply Voltage
Digital Input Voltage 3
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
Preliminary
47
Preliminary Electrical Characteristics
Table 43. Absolute Maximum Ratings1, 2
Instantaneous Maximum Current
Single pin limit (applies to all pins) 4, 5
Operating Temperature Range (Packaged)
ID
25
mA
TA
(TL - TH)
– 40 to 85
°C
Tstg
– 65 to 150
°C
Storage Temperature Range
NOTES:
1
Functional operating conditions are given in DC Electrical Specifications. Absolute Maximum Ratings
are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond those
listed may affect device reliability or cause permanent damage to the device.
2
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either VSS or O VDD).
3 Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use
the larger of the two values.
4 All functional non-supply pins are internally clamped to V
SS and O VDD.
5 Power supply must maintain regulation within operating O V
DD range during instantaneous and
operating maximum current conditions. If positive injection current (Vin > O VDD) is greater than IDD, the
injection current may flow out of O VDD and could result in external power supply going out of
regulation. Insure external O VDD load will shunt current greater than maximum injection current. This
will be the greatest risk when the MCU is not consuming power (ex; no clock).Power supply must
maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions.
10.2 Thermal Characteristics
Table 44 lists thermal resistance values
Table 44. Thermal characteristics
Characteristic
Symbol
Value
Unit
Junction to ambient, natural convection
256 MBGA
Four layer board (2s2p)
θJMA
261,2
°C/W
Junction to ambient (@200 ft/min)
256 MBGA
Four layer board (2s2p)
θJMA
23
°C/W
Junction to board
256 MBGA
θJB
153
°C/W
Junction to case
256 MBGA
θJC
104
°C/W
Junction to top of package
Natural convection
Ψjt
25
°C/W
Maximum operating junction temperature
256 MBGA
Tj
105
oC
NOTES:
1
θJMA and Ψjt parameters are simulated in conformance with EIA/JESD Standard 51-2 for natural convection.
Motorola recommends the use of θJmA and power dissipation specifications in the system design to prevent device
junction temperatures from exceeding the rated specification. System designers should be aware that device
junction temperatures can be significantly influenced by board layout and surrounding devices. Conformance to the
device junction temperature specification can be verified by physical measurement in the customer’s system using
the Ψjt parameter, the device power dissipation, and the method described in EIA/JESD Standard 51-2.
2 Per JEDEC JESD51-6 with the board horizontal.
3
Thermal resistance between the die and the printed circuit board in conformance with JEDEC JESD51-8. Board
temperature is measured on the top surface of the board near the package.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
48
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
4
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL
SPEC-883 Method 1012.1).
5
Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter
is written in conformance with Psi-JT.
The average chip-junction temperature (TJ) in °C can be obtained from:
T J = T A + ( P D × Θ JMA ) (1)
Where:
TA
= Ambient Temperature, °C
ΘJMA
= Package Thermal Resistance, Junction-to-Ambient, °C/W
PD
= PINT + PI/O
PINT
= IDD × VDD, Watts - Chip Internal Power
PI/O
= Power Dissipation on Input and Output Pins — User Determined
For most applications PI/O < PINT and can be ignored. An approximate relationship between PD and TJ (if PI/O is
neglected) is:
P D = K ÷ ( T J + 273°C )
(2)
Solving equations 1 and 2 for K gives:
K = PD × (TA + 273 °C) + ΘJMA × PD 2 (3)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring PD (at
equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1)
and (2) iteratively for any value of TA.
10.3 ESD Protection
Table 45. ESD Protection Characteristics1, 2
Characteristics
ESD Target for Human Body Model
ESD Target for Machine Model
Symbol
Value
Units
HBM
2000
V
MM
200
V
HBM Circuit Description
Rseries
1500
ohms
C
100
pF
MM Circuit Description
Rseries
0
ohms
pF
C
200
Number of pulses per pin (HBM)
positive pulses
negative pulses
—
—
1
1
Number of pulses per pin (MM)
positive pulses
negative pulses
—
—
3
3
Interval of Pulses
—
1
—
—
sec
NOTES:
1 All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for
Automotive Grade Integrated Circuits.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
Preliminary
49
Preliminary Electrical Characteristics
2
A device is defined as a failure if after exposure to ESD pulses the device no longer meets
the device specification requirements. Complete DC parametric and functional testing is
performed per applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
10.4 DC Electrical Specifications
Table 46. DC Electrical Specifications1
Characteristic
Core Supply Voltage
I/O Pad Supply Voltage
Symbol
Min
Max
Unit
VDD
1.35
1.65
V
O VDD
3.0
3.6
V
SD VDD
2.3
2.7
V
Input High Voltage
VIH
0.7 x O VDD
3.6
V
Input Low Voltage
VIL
VSS – 0.3
0.35 x O VDD
V
SSTL I/O Pad Supply Voltage
Input High Voltage SSTL 2.5V I/O Pads
VIH
2.0
2.8
V
Input Low Voltage SSTL 2.5V I/O Pads
VIL
– 0.5
0.8
V
Input High Voltage SSTL 3.3V I/O Pads
VIH
2.0
3.6
V
Input Low Voltage SSTL 3.3V I/O Pads
VIL
– 0.5
0.8
V
VHYS
0.06 x VDD
—
mV
Input Leakage Current
Vin = VDD or VSS, Input-only pins
Iin
–1.0
1.0
µA
High Impedance (Off-State) Leakage Current
Vin = VDD or VSS, All input/output and output pins
IOZ
–1.0
1.0
µA
Output High Voltage (All input/output and all output pins)
IOH = –2.0 mA
VOH
O VDD - 0.5
__
V
Output Low Voltage (All input/output and all output pins)
IOL = 2.0mA
VOL
__
0.5
V
Weak Internal Pull Up Device Current, tested at VIL Max.2
IAPU
-10
- 130
µA
—
—
7
7
Input Hysteresis
3
Input Capacitance
All input-only pins
All input/output (three-state) pins
Cin
Load Capacitance4
Low Drive Strength
High Drive Strength
pF
pF
CL
Core Operating Supply Current 5
Master Mode
WAIT
DOZE
STOP
IDD
I/O Pad Operating Supply Current
Master Mode
Low Power Modes
O IDD
DC Injection Current 3, 6, 7, 8
VNEGCLAMP =VSS– 0.3 V, VPOSCLAMP = VDD + 0.3
Single Pin Limit
Total MCU Limit, Includes sum of all stressed pins
25
50
—
—
—
—
175
15
10
100
mA
mA
mA
µA
—
—
250
250
mA
µA
IIC
mA
-1.0
-10
1.0
10
NOTES:
1
Refer to Table 47 for additional PLL specifications.
2 Refer to the MCF5274 signals chapter for pins having weak internal pull-up devices.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
50
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
3
4
5
6
7
8
This parameter is characterized before qualification rather than 100% tested.
pF load ratings are based on DC loading and are provided as an indication of driver strength. High speed interfaces
require transmission line analysis to determine proper drive strength and termination.
Current measured at maximum system clock frequency, all modules active, and default drive strength with matching
load.
All functional non-supply pins are internally clamped to VSS and their respective VDD.
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the larger of the two values.
Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum
current conditions. If positive injection current (Vin > VDD) is greater than IDD, the injection current may flow out of VDD
and could result in external power supply going out of regulation. Insure external VDD load will shunt current greater
than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if clock rate is very low which would reduce overall power consumption. Also, at
power-up, system clock is not present during the power-up sequence until the PLL has attained lock.
10.5 Oscillator and Phase Lock Loop (PLLMRFM) Electrical
Specifications
Table 47. PLL Electrical Specifications1
Characteristic
Symbol
Min
Max
fref_crystal
fref_ext
fref_1:1
8
8
24
25
25
83
fsys/2
0
fref / 32
166
83
83
MHz
MHZ
MHz
fLOR
100
1000
kHz
fSCM
TBD
TBD
MHz
tcst
—
10
ms
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
—
MHz
PLL Reference Frequency Range
Crystal reference
External reference
1:1 Mode (NOTE: fsys/2 = 2 × fref_1:1)
fcore
Core frequency
CLKOUT Frequency 2
External reference
On-Chip PLL Frequency
Loss of Reference Frequency 3, 5
Self Clocked Mode Frequency
Crystal Start-up Time
4, 5
5, 6
EXTAL Input High Voltage
Crystal Mode
All other modes (Dual Controller (1:1), Bypass, External)
VIHEXT
VIHEXT
EXTAL Input Low Voltage
Crystal Mode
All other modes (Dual Controller (1:1), Bypass, External)
VILEXT
VILEXT
XTAL Output High Voltage
IOH = 1.0 mA
VOH
XTAL Output Low Voltage
IOL = 1.0 mA
VOL
V
V
V
—
V
TBD
XTAL Load Capacitance7
PLL Lock Time
Unit
8
tlpll
Time 6, 9
5
30
pF
—
750
µs
—
—
11
750
ms
µs
Power-up To Lock
With Crystal Reference
Without Crystal Reference10
tlplk
1:1 Mode Clock Skew (between CLKOUT and EXTAL) 11
tskew
-1
1
ns
tdc
40
60
% fsys/2
Duty Cycle of
reference 5
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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Preliminary
51
Preliminary Electrical Characteristics
Table 47. PLL Electrical Specifications1
Characteristic
Symbol
Min
Max
Unit
Frequency un-LOCK Range
fUL
- 3.8
4.1
% fsys/2
Frequency LOCK Range
fLCK
- 1.7
2.0
% fsys/2
—
—
5
.01
% fsys/2
5, 6, 9,12, 13
CLKOUT Period Jitter,
Measured at fsys/2 Max
Peak-to-peak Jitter (Clock edge to clock edge)
Long Term Jitter (Averaged over 2 ms interval)
Cjitter
Frequency Modulation Range Limit14, 15
(fsys/2Max must not be exceeded)
Cmod
0.8
2.2
% fsys/2
ICO Frequency. fico = fref * 2 * (MFD+2)16
fico
48
83
MHz
NOTES:
1
All values given are initial design targets and subject to change.
2 All internal registers retain data at 0 Hz.
3
“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self
clocked mode.
4 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below
fLOR with default MFD/RFD settings.
5 This parameter is guaranteed by characterization before qualification rather than 100% tested.
6 Proper PC board layout procedures must be followed to achieve specifications.
7 Load Capacitance determined from crystal manufacturer specifications and will include circuit board parasitics.
8 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits
in the synthesizer control register (SYNCR).
9 Assuming a reference is available at power up, lock time is measured from the time V
DD and VDDPLL are valid to
RSTOUT negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal start up time
must be added to the PLL lock time to determine the total start-up time.
10 t
-6
lpll = (64 * 4 * 5 + 5 x τ) x Tref, where Tref = 1/Fref_crystal = 1/Fref_ext = 1/Fref_1:1, and τ = 1.57x10 x 2(MFD + 2)
11 PLL is operating in 1:1 PLL mode.
12 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum
fsys/2. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock
signal. Noise injected into the PLL circuitry via VDDPLL and VSSPLL and variation in crystal oscillator frequency
increase the jitter percentage for a given interval.
13 Based on slow system clock of 33MHz maximum frequency.
14 Modulation percentage applies over an interval of 10µs, or equivalently the modulation rate is 100KHz.
15 Modulation rate selected must not result in f
sys/2 value greater than the fsys/2 maximum specified value. Modulation
range determined by hardware design.
16
fsys/2 = fico / (2 * 2RFD)
10.6 External Interface Timing Characteristics
Table 48 lists processor bus input timings.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the CLKOUT output.
All other timing relationships can be derived from these values.
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Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 48. Processor Bus Input Timing Specifications
Characteristic1
Name
B0
CLKOUT
Symbol
Min
Max Unit
tCYC
12
—
ns
tCVCH
9
—
ns
Control Inputs
B1a
Control input valid to CLKOUT
high2
3
B1b
BKPT valid to CLKOUT high
tBKVCH
9
—
ns
B2a
CLKOUT high to control inputs invalid2
tCHCII
0
—
ns
B2b
CLKOUT high to asynchronous control input BKPT invalid3
tBKNCH
0
—
ns
Data Inputs
B4
Data input (D[31:16]) valid to CLKOUT high
tDIVCH
4
—
ns
B5
CLKOUT high to data input (D[31:16]) invalid
tCHDII
0
—
ns
NOTES:
1
Timing specifications have been indicated taking into account the full drive strength for the pads.
2 TEA and TA pins are being referred to as control inputs.
3 Refer to figure A-19.
Timings listed in Table 48 are shown in Figure 7.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
Preliminary
53
Preliminary Electrical Characteristics
* The timings are also valid for inputs sampled on the negative clock edge.
CLKOUT (83MHz)
TSETUP
Input Setup And Hold
Invalid
THOLD
Valid
Invalid
trise
Input Rise Time
Vh = VIH
Vl = VIL
Input Fall Time
Vh = VIH
Vl = VIL
tfall
CLKOUT
B4
B5
Inputs
Figure 7. General Input Timing Requirements
10.7 Processor Bus Output Timing Specifications
Table 49 lists processor bus output timings.
Table 49. External Bus Output Timing Specifications
Name
Characteristic
Symbol
Min
Max
Unit
Control Outputs
B6a
CLKOUT high to chip selects (CS[7:0]) valid 1
tCHCV
—
0.5tCYC + 5
ns
B6b
CLKOUT high to byte enables (BS[3:2])
valid2
tCHBV
—
0.5tCYC + 5
ns
B6c
CLKOUT high to output enable (OE) valid3
tCHOV
—
0.5tCYC + 5
ns
B7
CLKOUT high to control output (BS[3:2], OE) invalid
tCHCOI
0.5tCYC + 1.5
—
ns
B7a
CLKOUT high to chip selects invalid
tCHCI
0.5tCYC + 1.5
—
ns
—
9
ns
Address and Attribute Outputs
B8
CLKOUT high to address (A[23:0]) and control (TS,
TSIZ[1:0], TIP, R/W) valid
tCHAV
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
54
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 49. External Bus Output Timing Specifications (continued)
Name
B9
Characteristic
CLKOUT high to address (A[23:0]) and control (TS,
TSIZ[1:0], TIP, R/W) invalid
Symbol
Min
Max
Unit
tCHAI
1.5
—
ns
Data Outputs
B11
CLKOUT high to data output (D[31:16]) valid
tCHDOV
—
9
ns
B12
CLKOUT high to data output (D[31:16]) invalid
tCHDOI
1.5
—
ns
B13
CLKOUT high to data output (D[31:16]) high impedance
tCHDOZ
—
9
ns
NOTES:
CS transitions after the falling edge of CLKOUT.
2
BS transitions after the falling edge of CLKOUT.
3
OE transitions after the falling edge of CLKOUT.
1
Read/write bus timings listed in Table 49 are shown in Figure 8, Figure 9, and Figure 10.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
Preliminary
55
Preliminary Electrical Characteristics
S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
CLKOUT
B7a
B7a
CSn
A[23:0]
TSIZ[1:0]
TS
B6a
B6a
B8
B8
B8
B9
B9
B9
B8
TIP
B9
B8
B6c
B0
B7
OE
B9
R/W (H)
B8
B6b
B6b
BS[3:2]
B7
B7
B11
B4
B12
D[31:16]
B5
B13
TA (H)
TEA (H)
Figure 8. Read/Write (Internally Terminated) SRAM Bus Timing
Figure 9 shows a bus cycle terminated by TA showing timings listed in Table 49.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
56
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
S0
S1
S2
S3
S4
S5
S0
S1
CLKOUT
B6a
CSn
B7a
B8
B9
A[23:0]
TSIZ[1:0]
B8
B9
TS
B8
B9
TIP
B6c
OE
B7
R/W (H)
B6b
BS[3:2]
B7
B5
B4
D[31:16]
B2a
TA
B1a
TEA (H)
Figure 9. SRAM Read Bus Cycle Terminated by TA
Figure 10 shows an SRAM bus cycle terminated by TEA showing timings listed in Table 49.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
Preliminary
57
Preliminary Electrical Characteristics
S0
S1
S2
S3
S4
S5
S0
S1
CLKOUT
CSn
B6a
B7a
B8
B9
A[23:0]
TSIZ[1:0]
B8
B9
TS
B8
TIP
OE
B9
B6c
B7
R/W (H)
BS[3:2]
B6b
B7
D[31:16]
TA (H)
B1a
TEA
B2a
Figure 10. SRAM Read Bus Cycle Terminated by TEA
10.8 DDR SDRAM AC Timing Characteristics
The DDR SDRAM controller uses SSTL2 and I/O drivers. Either Class I or Class II drive strength is
available and is user programmable. DDR Clock timing specifications are given in Table 50 and Figure 11.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 50. DDR Clock Timing Specifications1
Symbol
Characteristic
Min
Max
Unit
VMP
Clock output mid-point voltage
1.05
1.45
V
VOUT
Clock output voltage level
-0.3
SD VDD + 0.3
V
VID
Clock output differential voltage (peak to peak swing)
0.7
SD VDD + 0.6
V
VIX
Clock crossing point voltage
1.05
1.45
V
NOTES:
1
SD VDD is nominally 2.5V.
SDCLK
VIX
VMP
VIX
VID
SDCLK
Figure 11. DDR Clock Timing Diagram
When using the DDR SDRAM controller the timing numbers in Table 51 must be followed to properly
latch or drive data onto the memory bus. All timing numbers are relative to the two DQS byte lanes.
Table 51. DDR Timing
Characteristic1
NUM
Symbol
Frequency of operation2
Min
Max
Unit
TBD
83
MHz
DD1
Clock Period (DDR_CLKOUT)
tCK
12
TBD
ns
DD2
Pulse Width High3
tCKH
0.45
0.55
tCK
DD3
Pulse Width Low3
tCKl
0.45
0.55
tCK
DD4
DDR_CLKOUT high to DDR address, SD_CKE,
SD_CS[1:0], SD_SCAS, SD_SRAS, SD_WE valid
tCMV
-
0.5 x tCK + 1
ns
DD5
DDR_CLKOUT high to DDR address, SD_CKE, SD_CS,
SD_SCAS, SD_SRAS, SD_WE invalid
tCMH
2
-
ns
DD6
Write command to first SD_DQS Latching Transition
tDQSS
-
1.25
tCK
DD7
SD_DQS high to Data and DM valid (write) - setup4,5
tQS
1.5
-
ns
tQH
1
-
ns
tIS
-
1
ns
hold4
DD8
SD_DQS high to Data and DM invalid (write) -
DD9
SD_DQS high to Data valid (read) - setup6
DD10
SD_DQS high to Data invalid (read) - hold7
DD11
SD_DQS falling edge to CLKOUT high - setup
DD12
DD13
DD14
DQS input read postamble width (tRPST)
DD15
DQS output write preamble width (tWPRE)
DD16
DQS output write postamble width (tWPST)
tWPST
tIH
0.25 x tCK+ 1
-
ns
tDSS
0.5
-
ns
SD_DQS falling edge to CLKOUT high - hold
tDSH
0.5
-
ns
DQS input read preamble width (tRPRE)
tRPRE
0.9
1.1
tCK
tRPST
0.4
0.6
tCK
tWPRE
0.25
—
tCK
0.4
0.6
tCK
NOTES:
1 All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.
2 DDR_CLKOUT operates at half the frequency of the PLLMRFM output and the ColdFire core.
3
tCKH + tCKL must be less than or equal to tCK.
4 D[31:24] is relative to SD_DQS3 and D[23:16] is relative to SD_DQS2.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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Preliminary
59
Preliminary Electrical Characteristics
5
The first data beat will be valid before the first rising edge of SD_DQS and after the SD_DQS write preamble. The
remaining data beats will be valid for each subsequent SD_DQS edge
6
Data input skew is derived from each SD_DQS clock edge. It begins with a SD_DQS transition and ends when the last data
line becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or
other factors).
7 Data input hold is derived from each SD_DQS clock edge. It begins with a SD_DQS transition and ends when the first data
line becomes invalid.
Figure 13 shows a DDR SDRAM write cycle.
DDR_CLKOUT
VIX
VMP
VIX
VID
DDR_CLKOUT
Figure 12. DDR_CLKOUT and DDR_CLKOUT crossover timing
DD1
DD2
DDR_CLKOUT
DD3
DDR_CLKOUT
DD5
SD_CSn,SD_WE,
SD_SRAS,SD_SCAS
CMD
DD6
DD4
A[13:0]
ROW
COL
DD7
DM[3:2]
DD8
SD_DQS[3:2]
DD7
WD1 WD2 WD3 WD4
D[31:16]
DD8
Figure 13. DDR Write Timing
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
DD1
DD2
CLKOUT
DD3
CLKOUT
CL=2
DD5
SD_CSn,SD_WE,
SD_SRAS,SD_SCAS
CMD
CL=2.5
DD4
A[13:0]
ROW
COL
DD9
DQS Read
Preamble
CL = 2
SD_DQS[3:2]
DQS Read
Postamble
DD10
D[31:16]
WD1 WD2 WD3 WD4
DQS Read
DQS Read
Preamble
Postamble
CL = 2.5
SD_DQS[3:2]
D[31:16]
WD1 WD2 WD3 WD4
Figure 14. DDR Read Timing
10.9 General Purpose I/O Timing
GPIO can be configured for certain pins of the QSPI, DDR Control, TIMERS, UARTS, FEC0, FEC1,
Interrupts and USB interfaces. When in GPIO mode the timing specification for these pins is given in
Table 52 and Figure 15.
Table 52. GPIO Timing
NUM
Characteristic
Symbol
Min
Max
Unit
G1
CLKOUT High to GPIO Output Valid
tCHPOV
-
10
ns
G2
CLKOUT High to GPIO Output Invalid
tCHPOI
1.5
-
ns
G3
GPIO Input Valid to CLKOUT High
tPVCH
9
-
ns
G4
CLKOUT High to GPIO Input Invalid
tCHPI
1.5
-
ns
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Freescale Semiconductor
Preliminary
61
Preliminary Electrical Characteristics
CLKOUT
G1
G2
GPIO Outputs
G3
G4
GPIO Inputs
Figure 15. GPIO Timing
10.10 Reset and Configuration Override Timing
Table 53. Reset and Configuration Override Timing
(VDD = 2.7 to 3.6 V, VSS = 0 V, TA = TL to TH)1
NUM
Characteristic
Symbol
Min
Max
Unit
R1
RESET Input valid to CLKOUT High
tRVCH
9
-
ns
R2
CLKOUT High to RESET Input invalid
tCHRI
1.5
-
ns
tRIVT
5
-
tCYC
2
R3
RESET Input valid Time
R4
CLKOUT High to RSTOUT Valid
tCHROV
-
10
ns
R5
RSTOUT valid to Config. Overrides valid
tROVCV
0
-
ns
R6
Configuration Override Setup Time to RSTOUT invalid
tCOS
20
-
tCYC
R7
Configuration Override Hold Time after RSTOUT invalid
tCOH
0
-
ns
R8
RSTOUT invalid to Configuration Override High Impedance
tROICZ
-
1 x tCYC
ns
NOTES:
1
All AC timing is shown with respect to 50% O VDD levels unless otherwise noted.
2
During low power STOP, the synchronizers for the RESET input are bypassed and RESET is asserted asynchronously
to the system. Thus, RESET must be held a minimum of 100 ns.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
62
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Preliminary Electrical Characteristics
CLKOUT
R1
R2
R3
RESET
R4
R4
RSTOUT
R8
R5
R6
R7
Configuration Overrides1:
(RCON, Override pins])
1. Refer to the Coldfire Integration Module (CIM) section for more information.
Figure 16. RESET and Configuration Override Timing
10.11 Fast Ethernet AC Timing Specifications
MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.
10.11.1MII Receive Signal Timing (FECn_RXD[3:0], FECn_RXDV,
FECn_RXER, and FECn_RXCLK)
The receiver functions correctly up to a FECn_RXCLK maximum frequency of 25 MHz +1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
FECn_RXCLK frequency.
Table 54 lists MII receive channel timings.
Table 54. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
M1
FECn_RXD[3:0], FECn_RXDV, FECn_RXER to
FECn_RXCLK setup
5
—
ns
M2
FECn_RXCLK to FECn_RXD[3:0], FECn_RXDV,
FECn_RXER hold
5
—
ns
M3
FECn_RXCLK pulse width high
35%
65%
FECn_RXCLK
period
M4
FECn_RXCLK pulse width low
35%
65%
FECn_RXCLK
period
Figure 17 shows MII receive signal timings listed in Table 54.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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63
Preliminary Electrical Characteristics
M3
FECn_RXCLK (input)
M4
FECn_RXD[3:0] (inputs)
FECn_RXDV
FECn_RXER
M1
M2
Figure 17. MII Receive Signal Timing Diagram
10.11.2MII Transmit Signal Timing (FECn_TXD[3:0], FECn_TXEN,
FECn_TXER, FECn_TXCLK)
Table 55 lists MII transmit channel timings.
The transmitter functions correctly up to a FECn_TXCLK maximum frequency of 25 MHz +1%. There is
no minimum frequency requirement. In addition, the processor clock frequency must exceed twice the
FECn_TXCLK frequency.
The transmit outputs (FECn_TXD[3:0], FECn_TXEN, FECn_TXER) can be programmed to transition
from either the rising or falling edge of FECn_TXCLK, and the timing is the same in either case. This
options allows the use of non-compliant MII PHYs.
Refer to the Ethernet chapter for details of this option and how to enable it.
Table 55. MII transmit channel timings.
Num
Characteristic
Min
Max
Unit
M5
FECn_TXCLK to FECn_TXD[3:0], FECn_TXEN,
FECn_TXER invalid
5
—
ns
M6
FECn_TXCLK to FECn_TXD[3:0], FECn_TXEN,
FECn_TXER valid
—
25
ns
M7
FECn_TXCLK pulse width high
35%
65%
FECn_TXCLK
period
M8
FECn_TXCLK pulse width low
35%
65%
FECn_TXCLK
period
Figure 18 shows MII transmit signal timings listed in Table 55.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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Preliminary Electrical Characteristics
M7
FECn_TXCLK (input)
M5
M8
FECn_TXD[3:0] (outputs)
FECn_TXEN
FECn_TXER
M6
Figure 18. MII Transmit Signal Timing Diagram
10.11.3MII Async Inputs Signal Timing (FECn_CRS and FECn_COL)
Table 56 lists MII asynchronous inputs signal timing.
Table 56. MII asynchronous input signal timing
Num
M9
Characteristic
Min
FECn_CRS, FECn_COL minimum pulse width
1.5
Max
Unit
—
FECn_TXCLK
period
Figure 19 shows MII asynchronous input timings listed in Table 56.
FECn_CRS, FECn_COL
M9
Figure 19. MII Async Inputs Timing Diagram
10.11.4MII Serial Management Channel Timing (FECn_MDIO and
FECn_MDC)
Table 57 lists MII serial management channel timings. The FEC functions correctly with a maximum
MDC frequency of 2.5 MHz.
Table 57. MII serial management channel timings.
Num
Characteristic
Min
Max
Unit
0
—
ns
M10
FECn_MDC falling edge to FECn_MDIO output invalid (minimum
propagation delay)
M11
FECn_MDC falling edge to FECn_MDIO output valid (max prop delay) —
25
ns
M12
FECn_MDIO (input) to FECn_MDC rising edge setup
10
—
ns
M13
FECn_MDIO (input) to FECn_MDC rising edge hold
0
—
ns
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
Preliminary
65
Preliminary Electrical Characteristics
Table 57. MII serial management channel timings.
Num
Characteristic
Min
Max
Unit
M14
FECn_MDC pulse width high
40%
60%
MDC period
M15
FECn_MDC pulse width low
40%
60%
MDC period
Figure 20 shows MII serial management channel timings listed in Table 57.
M14
M15
FECn_MDC (output)
M10
FECn_MDIO (output)
M11
FECn_MDIO (input)
M12
M13
Figure 20. MII Serial Management Channel Timing Diagram
10.11.5USB Interface AC Timing Specifications
Table 58 lists USB Interface timings.
Table 58. USB Interface timings.
Num
Characteristic
Min
Max
Units
US1
USB_CLK frequency of operation
48
48
MHz
US2
USB_CLK fall time (VIH = 2.4 V to VIL = 0.5 V)
—
2
ns
US3
USB_CLK rise time (VIL = 0.5 V to VIH = 2.4 V)
—
2
ns
US4
USB_CLK duty cycle (at 0.5 x O VDD)
45
55
%
Data Inputs
US5
USB_RP, USB_RN, USB_RXD valid to USB_CLK high
6
—
ns
US6
USB_CLK high to USB_RP, USB_RN, USB_RXD invalid
6
—
ns
Data Outputs
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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Preliminary Electrical Characteristics
Table 58. USB Interface timings.
Num
Characteristic
Min
Max
Units
US7
USB_CLK high to USB_TP, USB_TN, USB_SUSP valid
—
12
ns
US8
USB_CLK high to USB_TP, USB_TN, USB_SUSP invalid
3
—
ns
Figure 21 shows USB interface timings listed in Table 58.
US1
USB_CLK
US8
US7
USB Outputs
US5
US6
USB Inputs
trise
Input Rise Time
Vh = VIH
Vl = VIL
Input Fall Time
Vh = VIH
Vl = VIL
tfall
Figure 21. USB Signals timing diagram
10.12 I2C Input/Output Timing Specifications
Table 59 lists specifications for the I2C input timing parameters shown in Figure 22.
Table 59. I2C Input Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
I1
Start condition hold time
2 x tCYC
—
ns
I2
Clock low period
8 x tCYC
—
ns
I3
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH = 2.4 V)
—
1
mS
I4
Data hold time
0
—
ns
I5
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
—
1
mS
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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Preliminary
67
Preliminary Electrical Characteristics
Table 59. I2C Input Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
I6
Clock high time
4 x tCYC
—
ns
I7
Data setup time
0
—
ns
I8
Start condition setup time (for repeated start condition only)
2 x tCYC
—
ns
I9
Stop condition setup time
2 x tCYC
—
ns
Table 60 lists specifications for the I2C output timing parameters shown in Figure 22.
Table 60. I2C Output Timing Specifications between I2C_SCL and I2C_SDA
Num
Characteristic
Min
Max
Units
I11
Start condition hold time
6 x tCYC
—
ns
I2 1
Clock low period
10 x tCYC
—
ns
I3 2
I2C_SCL/I2C_SDA rise time
(VIL = 0.5 V to VIH = 2.4 V)
—
—
µS
I4 1
Data hold time
7 x tCYC
—
ns
—
3
ns
I5
3
I2C_SCL/I2C_SDA fall time
(VIH = 2.4 V to VIL = 0.5 V)
I6 1
Clock high time
10 x tCYC
—
ns
1
Data setup time
2 x tCYC
—
ns
I8 1
Start condition setup time (for repeated start
condition only)
20 x tCYC
—
ns
I9 1
Stop condition setup time
10 x tCYC
—
ns
I7
NOTES:
1 Note: Output numbers depend on the value programmed into the IFDR; an IFDR programmed
with the maximum frequency (IFDR = 0x20) results in minimum output timings as shown in
Table 60. The I2C interface is designed to scale the actual data transition time to move it to the
middle of the I2C_SCL low period. The actual position is affected by the prescale and division
values programmed into the IFDR; however, the numbers given in Table 60 are minimum values.
2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only
actively drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external
signal capacitance and pull-up resistor values.
3
Specified at a nominal 50-pF load.
Figure 22 shows timing for the values in Table 59 and Table 60.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
I2
SCL
I1
I6
I5
I4
I7
I3
I8
I9
SDA
Figure 22. I2C Input/Output Timings
10.13 DMA Timers Timing Specifications
Table 61 lists timer module AC timings.
Table 61. Timer Module AC Timing Specifications
Characteristic 1
Name
Min
Max
Unit
T1
T0IN / T1IN / T2IN / T3IN cycle time
3 x tCYC
—
ns
T2
T0IN / T1IN / T2IN / T3IN pulse width
1 x tCYC
—
ns
NOTES:
1 All timing references to CLKOUT are given to its rising edge.
10.14 QSPI Electrical Specifications
Table 62 lists QSPI timings.
Table 62. QSPI Modules AC Timing Specifications
Name
Characteristic
Min
Max
Unit
QS1
QSPI_CS[3:0] to QSPI_CLK
1
510
tCYC
QS2
QSPI_CLK high to QSPI_DOUT valid.
—
10
ns
QS3
QSPI_CLK high to QSPI_DOUT invalid (Output hold)
2
—
ns
QS4
QSPI_DIN to QSPI_CLK (Input setup)
9
—
ns
QS5
QSPI_DIN to QSPI_CLK (Input hold)
9
—
ns
The values in Table 62 correspond to Figure 23.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
Freescale Semiconductor
Preliminary
69
Preliminary Electrical Characteristics
QS1
QSPI_CS[3:0]
QSPI_CLK
QS2
QSPI_DOUT
QS3
QS4
QS5
QSPI_DIN
Figure 23. QSPI Timing
10.15 JTAG and Boundary Scan Timing
Table 63. JTAG and Boundary Scan Timing
Characteristics1
Num
Symbol
Min
Max
Unit
J1
TCLK Frequency of Operation
fJCYC
DC
1/4
fsys/2
J2
TCLK Cycle Period
tJCYC
4 x tCYC
-
ns
J3
TCLK Clock Pulse Width
tJCW
26
-
ns
J4
TCLK Rise and Fall Times
tJCRF
0
3
ns
J5
Boundary Scan Input Data Setup Time to TCLK Rise
tBSDST
4
-
ns
J6
Boundary Scan Input Data Hold Time after TCLK Rise
tBSDHT
26
-
ns
J7
TCLK Low to Boundary Scan Output Data Valid
tBSDV
0
33
ns
J8
TCLK Low to Boundary Scan Output High Z
tBSDZ
0
33
ns
J9
TMS, TDI Input Data Setup Time to TCLK Rise
tTAPBST
4
-
ns
J10
TMS, TDI Input Data Hold Time after TCLK Rise
tTAPBHT
10
-
ns
J11
TCLK Low to TDO Data Valid
tTDODV
0
26
ns
J12
TCLK Low to TDO High Z
tTDODZ
0
8
ns
J13
TRST Assert Time
tTRSTAT
100
-
ns
J14
TRST Setup Time (Negation) to TCLK High
tTRSTST
10
-
ns
NOTES:
1 JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
70
Preliminary
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Preliminary Electrical Characteristics
J2
J3
J3
VIH
TCLK
(input)
J4
VIL
J4
Figure 24. Test Clock Input Timing
TCLK
VIL
VIH
J5
Data Inputs
J6
Input Data Valid
J7
Data Outputs
Output Data Valid
J8
Data Outputs
J7
Data Outputs
Output Data Valid
Figure 25. Boundary Scan (JTAG) Timing
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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Preliminary
71
Preliminary Electrical Characteristics
TCLK
VIL
VIH
J9
TDI
TMS
J10
Input Data Valid
J11
TDO
Output Data Valid
J12
TDO
J11
TDO
Output Data Valid
Figure 26. Test Access Port Timing
TCLK
14
TRST
13
Figure 27. TRST Timing
10.16 Debug AC Timing Specifications
Table 64 lists specifications for the debug AC timing parameters shown in Figure 29.
Table 64. Debug AC Timing Specification
166 MHz
Num
Characteristic
Units
Min
Max
D0
PSTCLK cycle time
D1
PST, DDATA to CLKOUT setup
4
ns
D2
CLKOUT to PST, DDATA hold
1.5
ns
DSI-to-DSCLK setup
1 x tCYC
ns
DSCLK-to-DSO hold
4 x tCYC
ns
D3
D4
1
0.5
tCYC
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
72
Preliminary
Freescale Semiconductor
Preliminary Electrical Characteristics
Table 64. Debug AC Timing Specification
166 MHz
Num
Characteristic
Units
Min
D5
DSCLK cycle time
D6
Max
5 x tCYC
ns
BKPT input data setup time to CLKOUT Rise
4
ns
D7
BKPT input data hold time to CLKOUT Rise
1.5
ns
D8
CLKOUT high to BKPT high Z
0.0
10.0
ns
NOTES:
1
DSCLK and DSI are synchronized internally. D4 is measured from the synchronized DSCLK input
relative to the rising edge of CLKOUT.
Figure 28 shows real-time trace timing for the values in Table 64.
CLKOUT
D1
D2
PST[3:0]
DDATA[3:0]
Figure 28. Real-Time Trace AC Timing
Figure 29 shows BDM serial port AC timing for the values in Table 64.
CLKOUT
D5
DSCLK
D3
DSI
Current
Next
D4
DSO
Past
Current
Figure 29. BDM Serial Port AC Timing
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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Preliminary
73
Device/Family Documentation List
11
Device/Family Documentation List
Table 65. MCF5275 Documentation
12
Motorola
Document
Number
Title
Revision
Status
MCF5275EC/D
MCF5275 RISC Microprocessor Hardware Specifications
0
This Document
MCF5275RM/D
MCF5275 Reference Manual
0
In Process
MCF5275PB/D
MCF5275 Product Brief
0
Available
MCF5275FS
MCF5275 Fact Sheet
0
In Process
CFPRODFACT/D
The ColdFire Family of 32-Bit Microprocessors Family
Overview and Technology Roadmap
0
Available
MCF5XXXWP
MCF5XXXWP WHITE PAPER: Motorola ColdFire VL
RISC Processors
0
Available
MAPBGAPP
MAPBGA 4-Layer example
0
Available
CFPRM/D
ColdFire Family Programmer's Reference Manual
2
Available
Document Revision History
Table 66 provides a revision history for this hardware specification.
Table 66. Document Revision History
Rev. No.
Substantive Change(s)
1.1
Removed duplicate information in the module description sections. The information is all in the
Signals Description Table.
1
Added Figure 6
0
Initial release.
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1
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Document Revision History
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MCF5275EC/D
Rev. 1.1, 9/2004
• Preliminary