LINER LTC3407A Dual synchronous 600ma, 1.5mhz step-down dc/dc regulator Datasheet

LTC3407A
Dual Synchronous 600mA,
1.5MHz Step-Down
DC/DC Regulator
DESCRIPTION
FEATURES
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High Efficiency: Up to 96%
Low Ripple (35mVP-P) Burst Mode Operation;
IQ = 40μA
1.5MHz Constant Frequency Operation
No Schottky Diodes Required
Low RDS(ON) Internal Switches: 0.35Ω
Current Mode Operation for Excellent Line
and Load Transient Response
Short-Circuit Protected
Low Dropout Operation: 100% Duty Cycle
Ultralow Shutdown Current: IQ < 1μA
Output Voltages from 5V down to 0.6V
Power-On Reset Output
Externally Synchronizable Oscillator
Optional External Soft-Start
Small Thermally Enhanced MSOP and 3mm × 3mm
DFN Packages
APPLICATIONS
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The LTC®3407A is a dual, constant frequency, synchronous
step-down DC/DC converter. Intended for low power applications, it operates from a 2.5V to 5.5V input voltage
range and has a constant 1.5MHz switching frequency,
enabling the use of tiny, low cost capacitors and inductors
1mm or less in height. Each output voltage is adjustable
from 0.6V to 5V. Internal synchronous 0.35Ω, 1A power
switches provide high efficiency without the need for
external Schottky diodes.
A user selectable mode input is provided to allow the user
to trade-off ripple noise for low power efficiency. Burst
Mode® operation provides the highest efficiency at light
loads, while Pulse Skip Mode provides the lowest ripple
noise at light loads.
To further maximize battery life, the P-channel MOSFETs
are turned on continuously in dropout (100% duty cycle),
and both channels draw a total quiescent current of only
40μA. In shutdown, the device draws <1μA.
L, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Protected by U.S. Patents
including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131.
PDAs/Palmtop PCs
Digital Cameras
Cellular Phones
Wireless and DSL Modems
TYPICAL APPLICATION
1mm High 2.5V/1.8V at 600mA Step-Down Regulators
LTC3407A Efficiency/Power Loss Curve
100
VIN = 2.5V
TO 5.5V
RUN/SS2
VIN
RUN/SS1
POR
RESET
LTC3407A
VOUT2 = 2.5V
AT 600mA
2.2μH
2.2μH
SW1
SW2
22pF
22pF
VOUT1 = 1.8V
AT 600mA
0.1
70
60
0.01
50
40
30
0.001
20
10μF
VFB1
VFB2
887k
280k
GND
VIN = 3.3V
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
10
887k
442k
0
10μF
POWER LOSS (W)
MODE/SYNC
1.8V
80
100k
EFFICIENCY (%)
10μF
1
2.5V
90
1
10
100
LOAD CURRENT (mA)
0.0001
1000
3407A TA02
3407A TA01
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LTC3407A
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN Voltage ...................................................– 0.3V to 6V
VFB1, VFB2 Voltages ................................... –0.3V to 1.5V
RUN/SS1, RUN/SS2 Voltages ......................–0.3V to VIN
MODE/SYNC Voltage....................................–0.3V to VIN
SW1, SW2 Voltages ......................... –0.3V to VIN + 0.3V
POR Voltage ................................................. –0.3V to 6V
Operating Temperature Range (Note 2)
LTC3407AE .......................................... –40°C to 85°C
LTC3407AI ......................................... –40°C to 125°C
Junction Temperature (Note 5) ............................. 125°C
Storage Temperature Range...................– 65°C to 150°C
Lead Temperature (Soldering, 10 sec)
LTC3407AMSE Only .......................................... 300°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
VFB1
1
10 VFB2
RUN/SS1
VIN
2
9 RUN/SS2
SW1
4
7 SW2
GND
5
6 MODE/
SYNC
3
11
VFB1
RUN/SS1
VIN
SW1
GND
8 POR
1
2
3
4
5
11
10
9
8
7
6
VFB2
RUN/SS2
POR
SW2
MODE/
SYNC
MSE PACKAGE
10-LEAD PLASTIC MSOP
DD PACKAGE
10-LEAD (3mm × 3mm) PLASTIC DFN
EXPOSED PAD IS PGND (PIN 11)
MUST BE CONNECTED TO GND
TJMAX = 125°C, θJA = 45°C/W, θJC = 10°C/W
EXPOSED PAD IS PGND (PIN 11)
MUST BE CONNECTED TO GND
TJMAX = 125°C, θJA = 45°C/W, θJC = 10°C/W
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3407AEDD#PBF
LTC3407AEDD#TRPBF
LCQN
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC3407AIDD#PBF
LTC3407AIDD#TRPBF
LCQN
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 125°C
LTC3407AEMSE#PBF
LTC3407AEMSE#TRPBF
LTCRZ
10-Lead Plastic MSOP
–40°C to 85°C
LTC3407AIMSE#PBF
LTC3407AIMSE#TRPBF
LTCRZ
10-Lead Plastic MSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, unless otherwise specified. (Note 2)
SYMBOL
PARAMETER
VIN
Operating Voltage Range
CONDITIONS
●
IFB
Feedback Pin Input Current
●
VFB
Feedback Voltage (Note 3)
ΔVLINE REG
Reference Voltage Line Regulation
0°C ≤ TA ≤ 85°C
–40°C ≤ TA ≤ 125°C (LTC3407AI)
VIN = 2.5V to 5.5V (Note 3)
MIN
●
TYP
2.5
0.588
0.585
MAX
UNITS
5.5
V
30
nA
0.6
0.6
0.612
0.612
V
V
0.3
0.5
%/V
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LTC3407A
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, unless otherwise specified. (Note 2)
SYMBOL
PARAMETER
CONDITIONS
MIN
ΔVLOAD REG
Output Voltage Load Regulation
MODE/SYNC = 0V (Note 3)
0.5
IS
Input DC Supply Current
Active Mode
Sleep Mode
Shutdown
(Note 4)
VFB1 = VFB2 = 0.5V
VFB1 = VFB2 = 0.63V, MODE/SYNC = 3.6V
RUN = 0V, VIN = 5.5V, MODE/SYNC = 0V
600
40
0.1
800
60
1
μA
μA
μA
VFBX = 0.6V
1.5
1.8
MHz
●
fOSC
Oscillator Frequency
fSYNC
Synchronization Frequency
ILIM
Peak Switch Current Limit
VIN = 3V, VFBX = 0.5V, Duty Cycle <35%
RDS(ON)
Top Switch On-Resistance
Bottom Switch On-Resistance
ISW(LKG)
POR
1.2
TYP
MAX
%
1.5
0.75
UNITS
MHz
1
1.25
A
(Note 6)
(Note 6)
0.35
0.30
0.45
0.45
Ω
Ω
Switch Leakage Current
VIN = 5V, VRUN = 0V, VFBX = 0V
0.01
1
μA
Power-On Reset Threshold
VFBX Ramping Up, MODE/SYNC = 0V
VFBX Ramping Down, MODE/SYNC = 0V
8.5
–8.5
Power-On Reset On-Resistance
100
Power-On Reset Delay
%
%
200
65,536
Ω
Cycles
VRUN
RUN/SS Threshold Low
RUN/SS Threshold High
●
●
IRUN
RUN/SS Leakage Current
●
VMODE
MODE Threshold Low
0
0.5
V
MODE Threshold High
VIN – 0.5
VIN
V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3407AE is guaranteed to meet specified performance
from 0°C to 85°C. Specifications over the –40°C and 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3407AI is guaranteed over the full
–40°C to 125°C temperature range.
0.3
1
1.5
2
V
V
0.01
1
μA
Note 3: The LTC3407A is tested in a proprietary test mode that connects
VFB to the output of the error amplifier.
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: TJ is calculated from the ambient TA and power dissipation PD
according to the following formula: TJ = TA + (PD • θJA).
Note 6: The DFN switch on-resistance is guaranteed by correlation to
wafer level measurements.
TYPICAL PERFORMANCE CHARACTERISTICS
Burst Mode Operation
Pulse Skipping Mode
SW
5V/DIV
SW
5V/DIV
VOUT
50mV/DIV
VOUT
10mV/DIV
IL
200mA/DIV
IL
100mA/DIV
2μs/DIV
VIN = 3.6V
VOUT = 1.8V
ILOAD = 50mA
CIRCUIT OF FIGURE 3
3407 G01
1μs/DIV
VIN = 3.6V
VOUT = 1.8V
ILOAD = 50mA
CIRCUIT OF FIGURE 3
3407 G02
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LTC3407A
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step
TA = 25°C unless otherwise specified.
Soft Start
VOUT1
200mV/DIV
VOUT2
100mV/DIV
VIN
2V/DIV
IL
500mA/DIV
VOUT1
1V/DIV
ILOAD
500mA/DIV
IL
500mA/DIV
3407 G03
20μs/DIV
VIN = 3.6V
VOUT = 1.8V
ILOAD = 50mA TO 600mA
CIRCUIT OF FIGURE 3
Oscillator Frequency
vs Temperature
Efficiency vs Input Voltage
1.70
100mA
90
600mA
1mA
1.8
1.65
10mA
1.60
FREQUENCY (MHz)
EFFICIENCY (%)
80
70
Oscillator Frequency
vs Supply Voltage
OSCILLATOR FREQUENCY (MHz)
100
60
50
40
30
1.55
1.50
1.45
1.40
20
1.35
10 VOUT = 1.8V
CIRCUIT OF FIGURE 3
0
4
2
3
5
INPUT VOLTAGE (V)
1.30
–50 –25
6
3407 G04
1ms/DIV
VIN = 3.6V
VOUT = 1.8V
ILOAD = 500mA
CIRCUIT OF FIGURE 4
50
25
75
0
TEMPERATURE (°C)
100
1.7
1.6
1.5
1.4
1.3
1.2
125
2
4
3
5
SUPPLY VOLTAGE (V)
3407A G06
6
3407A G07
3407A G05
Reference Voltage
vs Temperature
0.615
RDS(ON) vs Input Voltage
RDS(ON) vs Temperature
500
550
VIN = 3.6V
VIN = 2.7V
500
450
450
0.600
0.595
400
MAIN
SWITCH
RDS(ON) (mΩ)
0.605
RDS(ON) (mΩ)
REFERENCE VOLTAGE (V)
0.610
350
300
0.590
250
0.585
–50 –25
200
SYNCHRONOUS
SWITCH
100
125
3407A G08
1
2
3
4
VIN (V)
VIN = 3.6V
400
350
300
250
200
150
50
25
75
0
TEMPERATURE (°C)
VIN = 4.2V
5
6
7
3407A G09
100
–50 –25
MAIN SWITCH
SYNCHRONOUS SWITCH
0
25 50 75 100 125 150
TEMPERATURE (°C)
3407A G10
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LTC3407A
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current
Efficiency vs Load Current
100
2.7V
4
Burst Mode OPERATION
90
3.3V
3
80
EFFICIENCY (%)
70
60
50
40
2
70
60
PULSE SKIP MODE
50
40
30
30
20
20
10 VOUT = 2.5V Burst Mode OPERATION
CIRCUIT OF FIGURE 3
0
10
100
1
LOAD CURRENT (mA)
10 VIN = 3.6V, VOUT = 1.8V
NO LOAD ON OTHER CHANNEL
0
10
100
1
LOAD CURRENT (mA)
1000
VOUT ERROR(%)
4.2V
80
EFFICIENCY (%)
Load Regulation
100
90
Efficiency vs Load Current
2.7V
Line Regulation
50
40
20
20
10
10
VOUT = 1.2V Burst Mode OPERATION
1
10
100
LOAD CURRENT (mA)
0.3
60
30
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
VOUT = 1.5V Burst Mode OPERATION
0
1000
VOUT = 1.8V
IOUT = 200mA
0.4
4.2V
70
30
0
3.3V
2.7V
VOUT ERROR (%)
EFFICIENCY (%)
40
1000
3407A G13
80
4.2V
50
10
100
LOAD CURRENT (mA)
1
0.5
90
60
VIN = 3.6V, VOUT = 1.8V
NO LOAD ON OTHER CHANNEL
–4
1000
Efficiency vs Load Current
3.3V
70
PULSE SKIP MODE
–1
–3
100
80
0
3407A G12
100
90
1 Burst Mode OPERATION
–2
3407A G11
EFFICIENCY (%)
TA = 25°C unless otherwise specified.
1
10
100
LOAD CURRENT (mA)
3407A G14
1000
–0.5
2
3
4
VIN (V)
5
6
3407A G16
3407A G15
PIN FUNCTIONS
VFB1 (Pin 1): Output Feedback. Receives the feedback voltage from the external resistive divider across the output.
Nominal voltage for this pin is 0.6V.
RUN/SS1 (Pin 2): Regulator 1 Enable and Soft-Start Input.
Forcing this pin to VIN enables regulator 1, while forcing it
to GND causes regulator 1 to shut down. Connect external
RC-network with desired time-constant to enable soft-start
feature. This pin must be driven; do not float.
VIN (Pin 3): Main Power Supply. Must be closely decoupled
to GND.
SW1 (Pin 4): Regulator 1 Switch Node Connection to the
Inductor. This pin swings from VIN to GND.
GND (Pin 5): Main Ground. Connect to the (–) terminal
of COUT, and (–) terminal of CIN.
MODE/SYNC (Pin 6): Combination Mode Selection and
Oscillator Synchronization. This pin controls the operation of the device. When tied to VIN or GND, Burst Mode
operation or pulse skipping mode is selected, respectively.
Do not float this pin. The oscillation frequency can be
synchronized to an external oscillator applied to this pin
and pulse skipping mode is automatically selected.
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LTC3407A
PIN FUNCTIONS
SW2 (Pin 7): Regulator 2 Switch Node Connection to the
Inductor. This pin swings from VIN to GND.
RC-Network with desired time-constant to enable soft-start
feature. This pin must be driven; do not float.
POR (Pin 8): Power-On Reset. This common-drain logic
output is pulled to GND when the output voltage is not
within ±8.5% of regulation and goes high after 216 clock
cycles when both channels are within regulation.
VFB2 (Pin 10): Output Feedback. Receives the feedback
voltage from the external resistive divider across the output.
Nominal voltage for this pin is 0.6V.
Exposed Pad (GND) (Pin 11): Power Ground. Connect to
the (–) terminal of COUT, and (–) terminal of CIN. Must be
soldered to electrical ground on PCB.
RUN/SS2 (Pin 9): Regulator 2 Enable and Soft-Start Input.
Forcing this pin to VIN enables regulator 2, while forcing it
to GND causes regulator 2 to shut down. Connect external
BLOCK DIAGRAM
REGULATOR 1
MODE/SYNC
6
BURST
CLAMP
VIN
SLOPE
COMP
0.6V
+
EA
VFB1
ITH
EN
–
SLEEP
–
1
+
5Ω
ICOMP
+
0.65V
–
BURST
S
Q
RS
LATCH
R
0.55V
–
UVDET
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
UV
+
+
OVDET
ANTI
SHOOTTHRU
4 SW1
OV
–
+
0.65V
Q
IRCMP
SHUTDOWN
–
11 GND
VIN
PGOOD1
RUN/SS1
8 POR
2
0.6V REF
RUN/SS2
9
3 VIN
OSC
OSC
POR
COUNTER
5 GND
PGOOD2
REGULATOR 2 (IDENTICAL TO REGULATOR 1)
7 SW2
VFB2
10
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LTC3407A
OPERATION
The LTC3407A uses a constant frequency, current mode
architecture. The operating frequency is set at 1.5MHz
and can be synchronized to an external oscillator. Both
channels share the same clock and run in-phase. To suit
a variety of applications, the selectable MODE/SYNC pin
allows the user to trade-off noise for efficiency.
The output voltage is set by an external divider returned
to the VFB pins. An error amplifier compares the divided
output voltage with a reference voltage of 0.6V and adjusts
the peak inductor current accordingly. Overvoltage and
undervoltage comparators will pull the POR output low if
the output voltage is not within ±8.5%. The POR output
will go high after 65,536 clock cycles (about 44ms in pulse
skipping mode) of achieving regulation.
the PMOS switch operates intermittently based on load
demand with a fixed peak inductor current. By running
cycles periodically, the switching losses which are dominated by the gate charge losses of the power MOSFETs
are minimized. The main control loop is interrupted when
the output voltage reaches the desired regulated value. A
voltage comparator trips when ITH is below 0.65V, shutting
off the switch and reducing the power. The output capacitor and the inductor supply the power to the load until ITH
exceeds 0.65V, turning on the switch and the main control
loop which starts another cycle.
For lower ripple noise at low currents, the pulse skipping
mode can be used. In this mode, the LTC3407A continues
to switch at a constant frequency down to very low currents, where it will begin skipping pulses.
Main Control Loop
During normal operation, the top power switch (P-channel
MOSFET) is turned on at the beginning of a clock cycle when
the VFB voltage is below the reference voltage. The current
into the inductor and the load increases until the current
limit is reached. The switch turns off and energy stored in
the inductor flows through the bottom switch (N-channel
MOSFET) into the load until the next clock cycle.
Dropout Operation
The peak inductor current is controlled by the internally
compensated ITH voltage, which is the output of the error amplifier.This amplifier compares the VFB pin to the
0.6V reference. When the load current increases, the
VFB voltage decreases slightly below the reference. This
decrease causes the error amplifier to increase the ITH
voltage until the average inductor current matches the
new load current.
An important design consideration is that the RDS(ON)
of the P-channel switch increases with decreasing input
supply voltage (See Typical Performance Characteristics).
Therefore, the user should calculate the power dissipation
when the LTC3407A is used at 100% duty cycle with low
input voltage (See Thermal Considerations in the Applications Information Section).
The main control loop is shut down by pulling the RUN/SS
pin to ground.
Low Supply Operation
Low Current Operation
Two modes are available to control the operation of the
LTC3407A at low currents. Both modes automatically
switch from continuous operation to the selected mode
when the load current is low.
To optimize efficiency, the Burst Mode operation can be
selected. When the load is relatively light, the LTC3407A
automatically switches into Burst Mode operation in which
When the input supply voltage decreases toward the
output voltage, the duty cycle increases to 100% which
is the dropout condition. In dropout, the PMOS switch is
turned on continuously with the output voltage being equal
to the input voltage minus the voltage drops across the
internal P-channel MOSFET and the inductor.
The LTC3407A incorporates an undervoltage lockout circuit
which shuts down the part when the input voltage drops
below about 1.65V to prevent unstable operation.
A general LTC3407A application circuit is shown in
Figure 1. External component selection is driven by the
load requirement, and begins with the selection of the
inductor L. Once the inductor is chosen, CIN and COUT
can be selected.
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LTC3407A
APPLICATIONS INFORMATION
Inductor Core Selection
VIN = 2.5V TO 5.5V
CIN
R7
VIN
BURST*
R6
PULSESKIP*
R5
LTC3407A
RUN/SS2
RUN/SS1
L1
L2
VOUT2
POWER-ON
RESET
POR
MODE/SYNC
VOUT1
SW1
SW2
C2
C1
C4
C3
R4
COUT2
VFB1
VFB2
GND
R3
R2
R1
*MODE/SYNC = 0V: PULSE SKIP
MODE/SYNC = VIN: Burst Mode
COUT1
3407A F01
Figure 1. LTC3407A General Schematic
Inductor Selection
Although the inductor does not influence the operating frequency, the inductor value has a direct effect on
ripple current. The inductor ripple current ΔIL decreases
with higher inductance and increases with higher VIN or
VOUT :
V V
IL = OUT • 1– OUT fO • L VIN Accepting larger values of ΔIL allows the use of low
inductances, but results in higher output voltage ripple,
greater core losses, and lower output current capability. A
reasonable starting point for setting ripple current is ΔIL =
0.3 • ILIM, where ILIM is the peak switch current limit. The
largest ripple current ΔIL occurs at the maximum input
voltage. To guarantee that the ripple current stays below a
specified maximum, the inductor value should be chosen
according to the following equation:
V
V
L = OUT • 1– OUT fO • IL VIN(MAX) The inductor value will also have an effect on Burst Mode
operation. The transition from low current operation
begins when the peak inductor current falls below a level
set by the burst clamp. Lower inductor values result in
higher ripple current which causes this transition to occur
at lower load currents. This causes a dip in efficiency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to increase.
Different core materials and shapes will change the size/
current and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar electrical characterisitics. The choice of which style inductor
to use often depends more on the price vs size requirements and any radiated field/EMI requirements than on
what the LTC3407A requires to operate. Table 1 shows
some typical surface mount inductors that work well in
LTC3407A applications.
Table 1. Representative Surface Mount Inductors
MANUFACTURER
Taiyo
Yuden
PART NUMBER
CB2016T2R2M
CB2012T2R2M
CB2016T3R3M
MAX DC
VALUE CURRENT
2.2μH
2.2μH
3.3μH
510mA
530mA
410mA
DCR
HEIGHT
0.13Ω
0.33Ω
0.27Ω
1.6mm
1.25mm
1.6mm
Panasonic
ELT5KT4R7M
4.7μH
950mA
0.2Ω
1.2mm
Sumida
CDRH2D18/LD
4.7μH
630mA
0.086Ω
2mm
Murata
LQH32CN4R7M23 4.7μH
450mA
0.2Ω
2mm
Taiyo
Yuden
NR30102R2M
NR30104R7M
2.2μH
4.7μH
1100mA
750mA
0.1Ω
0.19Ω
1mm
1mm
FDK
FDKMIPF2520D
FDKMIPF2520D
FDKMIPF2520D
4.7μH
3.3μH
2.2μH
1100mA
1200mA
1300mA
0.11Ω
0.1Ω
0.08Ω
1mm
1mm
1mm
TDK
VLF3010AT4R7MR70
VLF3010AT3R3MR87
VLF3010AT2R2M1R0
4.7μH
700mA
0.28Ω
1mm
3.3μH
870mA
0.17Ω
1mm
2.2μH
1000mA
0.12Ω
1mm
Input Capacitor (CIN) Selection
In continuous mode, the input current of the converter is a
square wave with a duty cycle of approximately VOUT/VIN.
To prevent large voltage transients, a low equivalent series
resistance (ESR) input capacitor sized for the maximum
RMS current must be used. The maximum RMS capacitor
current is given by:
VOUT (VIN – VOUT )
IRMS ≈IMAX
VIN
where the maximum average output current IMAX equals
the peak current minus half the peak-to-peak ripple current, IMAX = ILIM – ΔIL/2.
3407afa
8
LTC3407A
APPLICATIONS INFORMATION
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case is commonly used to
design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours lifetime.
This makes it advisable to further derate the capacitor,
or choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to meet
the size or height requirements of the design. An additional
0.1μF to 1μF ceramic capacitor is also recommended on
VIN for high frequency decoupling, when not using an all
ceramic capacitor solution.
Output Capacitor (COUT) Selection
The selection of COUT is driven by the required ESR to
minimize voltage ripple and load step transients. Typically,
once the ESR requirement is satisfied, the capacitance
is adequate for filtering. The output ripple (ΔVOUT) is
determined by:
1
VOUT IL ESR +
8fO COUT where fO = operating frequency, COUT = output capacitance
and ΔIL = ripple current in the inductor. The output ripple
is highest at maximum input voltage since ΔIL increases
with input voltage. With ΔIL = 0.3 • ILIM the output ripple
will be less than 100mV at maximum VIN and fO = 1.5MHz
with:
ESRCOUT < 150mΩ
Once the ESR requirements for COUT have been met, the
RMS current rating generally far exceeds the IRIPPLE(P-P)
requirement, except for an all ceramic solution.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the capacitance, ESR or
RMS current handling requirement of the application.
Aluminum electrolytic, special polymer, ceramic and dry
tantulum capacitors are all available in surface mount
packages. The OS-CON semiconductor dielectric capacitor
available from Sanyo has the lowest ESR(size) product
of any aluminum electrolytic at a somewhat higher price.
Special polymer capacitors, such as Sanyo POSCAP, offer very low ESR, but have a lower capacitance density
than other types. Tantalum capacitors have the highest
capacitance density. However, they also have a larger
ESR and it is critical that they are surge tested for use in
switching power supplies. An excellent choice is the AVX
TPS series of surface mount tantalums, available in case
heights ranging from 2mm to 4mm. Aluminum electrolytic
capacitors have a significantly larger ESR, and are often
used in extremely cost-sensitive applications provided that
consideration is given to ripple current ratings and long
term reliability. Ceramic capacitors have the lowest ESR
and cost, but also have the lowest capacitance density,
a high voltage and temperature coefficient, and exhibit
audible piezoelectric effects. In addition, the high Q of
ceramic capacitors along with trace inductance can lead
to significant ringing. Other capacitor types include the
Panasonic Special Polymer (SP) capacitors.
In most cases, 0.1μF to 1μF of ceramic capacitors should
also be placed close to the LTC3407A in parallel with the
main capacitors for high frequency decoupling.
Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. These are tempting
for switching regulator use because of their very low ESR.
Unfortunately, the ESR is so low that it can cause loop
stability problems. Solid tantalum capacitor ESR generates a loop “zero” at 5kHz to 50kHz that is instrumental in
giving acceptable loop phase margin. Ceramic capacitors
remain capacitive to beyond 300kHz and usually resonate
with their ESL before ESR becomes effective. Also, ceramic
caps are prone to temperature effects which requires the
designer to check loop stability over the operating temperature range. To minimize their large temperature and
voltage coefficients, only X5R or X7R ceramic capacitors
should be used. A good selection of ceramic capacitors
is available from Taiyo Yuden, TDK, and Murata.
Great care must be taken when using only ceramic input
and output capacitors. When a ceramic capacitor is used
at the input and the power is being supplied through long
wires, such as from a wall adapter, a load step at the output
can induce ringing at the VIN pin. At best, this ringing can
couple to the output and be mistaken as loop instability.
At worst, the ringing at the input can be large enough to
damage the part.
3407afa
9
LTC3407A
APPLICATIONS INFORMATION
Since the ESR of a ceramic capacitor is so low, the input
and output capacitor must instead fulfill a charge storage
requirement. During a load step, the output capacitor must
instantaneously supply the current to support the load
until the feedback loop raises the switch current enough
to support the load. The time required for the feedback
loop to respond is dependent on the compensation and
the output capacitor size. Typically, 3-4 cycles are required
to respond to a load step, but only in the first cycle does
the output drop linearly. The output droop, VDROOP, is
usually about 3 times the linear drop of the first cycle.
Thus, a good place to start is with the output capacitor
size of approximately:
ΔIOUT
COUT ≈ 3
fO • VDROOP
More capacitance may be required depending on the duty
cycle and load step requirements.
In most applications, the input capacitor is merely required
to supply high frequency bypassing, since the impedance
to the supply is very low. A 10μF ceramic capacitor is
usually enough for these conditions.
Setting the Output Voltage
The LTC3407A develops a 0.6V reference voltage between
the feedback pin, VFB, and ground as shown in Figure 1.
The output voltage is set by a resistive divider according
to the following formula:
R2 VOUT = 0.6V 1+ R1
Keeping the current small (<5μA) in these resistors maximizes efficiency, but making them too small may allow
stray capacitance to cause noise problems and reduce the
phase margin of the error amp loop.
To improve the frequency response, a feed-forward capacitor CF may also be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
Power-On Reset
The POR pin is an open-drain output which pulls low when
either regulator is out of regulation. When both output
voltages are within ±8.5% of regulation, a timer is started
which releases POR after 216 clock cycles (about 44ms
in pulse skipping mode). This delay can be significantly
longer in Burst Mode operation with low load currents,
since the clock cycles only occur during a burst and there
could be milliseconds of time between bursts. This can
be bypassed by tying the POR output to the MODE/SYNC
input, to force pulse skipping mode during a reset. In
addition, if the output voltage faults during Burst Mode
sleep, POR could have a slight delay for an undervoltage
output condition and may not respond to an overvoltage
output. This can be avoided by using pulse skipping mode
instead. When either channel is shut down, the POR output
is pulled low, since one or both of the channels are not
in regulation.
Mode Selection & Frequency Synchronization
The MODE/SYNC pin is a multipurpose pin which provides
mode selection and frequency synchronization. Connecting this pin to VIN enables Burst Mode operation, which
provides the best low current efficiency at the cost of a
higher output voltage ripple. When this pin is connected
to ground, pulse skipping operation is selected which
provides the lowest output ripple, at the cost of low current efficiency.
The LTC3407A can also be synchronized to another
LTC3407A by the MODE/SYNC pin. During synchronization, the mode is set to pulse skipping and the top switch
turn-on is synchronized to the rising edge of the external
clock.
Checking Transient Response
The regulator loop response can be checked by looking at the load transient response. Switching regulators
take several cycles to respond to a step in load current.
When a load step occurs, VOUT immediately shifts by an
amount equal to ΔILOAD • ESR, where ESR is the effective
series resistance of COUT. ΔILOAD also begins to charge or
discharge COUT generating a feedback error signal used
by the regulator to return VOUT to its steady-state value.
3407afa
10
LTC3407A
APPLICATIONS INFORMATION
During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard secondorder overshoot/DC ratio cannot be used to determine
phase margin. In addition, a feed-forward capacitor can be
added to improve the high frequency response, as shown
in Figure 1. Capacitors C1 and C2 provide phase lead by
creating high frequency zeros with R2 and R4 respectively,
which improve the phase margin.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a review of control loop theory, refer to Application Note 76.
In some applications, a more severe transient can be caused
by switching in loads with large (>1μF) input capacitors.
The discharged input capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator
can deliver enough current to prevent this problem, if the
switch connecting the load has low resistance and is driven
quickly. The solution is to limit the turn-on speed of the
load switch driver. A Hot Swap™ controller is designed
specifically for this purpose and usually incorporates current limiting, short-circuit protection, and soft-starting.
Soft-Start
The RUN/SS pins provide a means to separately run or shut
down the two regulators. In addition, they can optionally be
used to externally control the rate at which each regulator
starts up and shuts down. Pulling the RUN/SS1 pin below
1V shuts down regulator 1 on the LTC3407A. Forcing this
pin to VIN enables regulator 1. In order to control the rate
at which each regulator turns on and off, connect a resistor
and capacitor to the RUN/SS pins as shown in Figure 1.
The soft-start duration can be calculated by using the
following formula:
V 1 t SS = RSSCSSIn IN
(s)
VIN 1.6 For approximately a 1ms ramp time, use RSS = 4.7MΩ
and CSS = 680pF at VIN = 3.3V.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
%Efficiency = 100% - (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, 4 main sources usually account for most of the
losses in LTC3407A circuits: 1) VIN quiescent current, 2)
switching losses, 3) I2R losses, 4) other losses.
1) The VIN current is the DC supply current given in the
Electrical Characteristics which excludes MOSFET
driver and control currents. VIN current results in a
small (<0.1%) loss that increases with VIN, even at no
load.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from VIN to ground. The resulting dQ/dt is a current
out of VIN that is typically much larger than the DC bias
current. In continuous mode, IGATECHG = fO(QT + QB),
where QT and QB are the gate charges of the internal
top and bottom MOSFET switches. The gate charge
losses are proportional to VIN and thus their effects
will be more pronounced at higher supply voltages.
3) I2R losses are calculated from the DC resistances of
the internal switches, RSW, and external inductor, RL.
In continuous mode, the average output current flows
through inductor L, but is “chopped” between the internal
top and bottom switches. Thus, the series resistance
looking into the SW pin is a function of both top and
bottom MOSFET RDS(ON) and the duty cycle (D) as
follows:
RSW = (RDS(ON)TOP)(D) + (RDS(ON)BOT)(1 – D)
Hot Swap is a registered trademark of Linear Technology Corporation.
3407afa
11
LTC3407A
APPLICATIONS INFORMATION
The RDS(ON) for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses:
I2R losses = IOUT2(RSW + RL)
4) Other ‘hidden’ losses such as copper trace and internal
battery resistances can account for additional efficiency
degradations in portable systems. It is very important
to include these “system” level losses in the design of a
system. The internal battery and fuse resistance losses
can be minimized by making sure that CIN has adequate
charge storage and very low ESR at the switching frequency. Other losses including diode conduction losses
during dead-time and inductor core losses generally
account for less than 2% total additional loss.
Thermal Considerations
In a majority of applications, the LTC3407A does not
dissipate much heat due to its high efficiency. However,
in applications where the LTC3407A is running at high
ambient temperature with low supply voltage and high
duty cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150°C,
both power switches will be turned off and the SW node
will become high impedance.
To prevent the LTC3407A from exceeding the maximum
junction temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
TRISE = PD • θJA
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, TJ, is given by:
TJ = TRISE + TAMBIENT
As an example, consider the case when the LTC3407A is
in dropout on both channels at an input voltage of 2.7V
with a load current of 600mA and an ambient temperature
of 70°C. From the Typical Performance Characteristics
graph of Switch Resistance, the RDS(ON) resistance of
the main switch is 0.425Ω. Therefore, power dissipated
by each channel is:
PD = I2 • RDS(ON) = 153mW
The MS package junction-to-ambient thermal resistance,
θJA, is 45°C/W. Therefore, the junction temperature of
the regulator operating in a 70°C ambient temperature is
approximately:
TJ = 2 • 0.153 • 45 + 70 = 84°C
which is below the absolute maximum junction temperature of 125°C.
Design Example
As a design example, consider using the LTC3407A in a
portable application with a Li-Ion battery. The battery provides a VIN = 2.8V to 4.2V. The load requires a maximum
of 600mA in active mode and 2mA in standby mode. The
output voltage is VOUT = 2.5V. Since the load still needs
power in standby, Burst Mode operation is selected for
good low load efficiency.
First, calculate the inductor value for about 30% ripple
current at maximum VIN:
2.5V
2.5V L=
• 1–
= 2.25μH
1.5MHz • 300mA 4.2V Choosing the closest inductor from a vendor of 2.2μH
inductor, results in a maximum ripple current of:
2.5V
2.5V IL =
• 1
= 307mA
1.5MHz • 2.2μH 4.2V For cost reasons, a ceramic capacitor will be used. COUT
selection is then based on load step droop instead of ESR
requirements. For a 5% output droop:
600mA
COUT ≈ 3
= 9.6μF
1.5MHz • (5% • 2.5V)
The closest standard value is 10μF. Since the output impedance of a Li-Ion battery is very low, CIN is typically 10μF.
3407afa
12
LTC3407A
APPLICATIONS INFORMATION
The output voltage can now be programmed by choosing
the values of R1 and R2. To maintain high efficiency, the
current in these resistors should be kept small. Choosing
2μA with the 0.6V feedback voltage makes R1~300k. A close
standard 1% resistor is 280k, and R2 is then 887k.
The POR pin is a common drain output and requires a pullup resistor. A 100k resistor is used for adequate speed.
Figure 3 shows the complete schematic for this design
example. The specific passive components chosen allow
for a 1mm height power supply that maintains a high efficiency across load.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3407A. These items are also illustrated graphically
in the layout diagram of Figure 2. Check the following in
your layout:
1. Does the capacitor CIN connect to the power VIN (Pin 3)
and GND (exposed pad) as closely as possible? This
capacitor provides the AC current to the internal power
MOSFETs and their drivers.
2. Are COUT and L1 closely connected? The (–) plate of
COUT returns current to GND and the (–) plate of CIN.
3. The resistor divider formed by R1 and R2 must be
connected between the (+) plate of COUT and a ground
sense line terminated near GND (exposed pad). The
feedback signals VFB1 and VFB2 should be routed away
from noisy components and traces, such as the SW lines
(Pins 4 and 7), and their traces should be minimized.
4. Keep sensitive components away from the SW pins. The
input capacitor CIN and the resistors R1 to R4 should be
routed away from the SW traces and the inductors.
5. A ground plane is preferred, but if not available keep
the signal and power grounds segregated with small
signal components returning to the GND pin at one
point. Addtionally the two grounds should not share
the high current paths of CIN or COUT.
6. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected
to VIN or GND.
VIN
CIN
RUN/SS2 VIN RUN/SS1
MODE/SYNC
POR
LTC3407A
L1
L2
VOUT2
SW2
SW1
C5
VFB1
VFB2
R4
COUT2
VOUT1
C4
GND
R3
R2
R1
COUT1
3407A F02
BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 2. LTC3407A Layout Diagram (See Board Layout Checklist)
3407afa
13
LTC3407A
TYPICAL APPLICATIONS
VIN = 2.5V
TO 5.5V
RUN/SS2
VIN
RUN/SS1
VOUT2 = 2.5V
AT 600mA
L1
2.2μH
SW2
R4
887k
VOUT1 = 1.8V
AT 600mA
SW1
C5, 22pF
C3
10μF
C4, 22pF
VFB1
VFB2
1.8V
70
60
50
40
30
R2
R1 604k
301k
GND
R3
280k
2.5V
90
80
LTC3407A
L2
2.2μH
100
POWER-ON
RESET
POR
MODE/SYNC
Efficiency vs Load Current
R5
100k
EFFICIENCY (%)
C1
10μF
C2
10μF
20
VIN = 3.3V
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
10
0
C1, C2, C3: TAIYO YUDEN JMK316BJ106MD
L1, L2: TDK VLF3010AT-2R2M1R0
1
3407A TA03
10
100
LOAD CURRENT (mA)
1000
3407A TA04
Figure 3. 1mm Height Core Supply
VIN = 2.5V TO 5.5V
Efficiency vs Load Current
R7
100k
VIN
LTC3407A
RUN/SS2
VOUT2 = 1.8V
AT 600mA
POWER-ON
RESET
POR
L1
4.7μH
VOUT1 = 1.2V
AT 600mA
SW1
SW2
C2, 22pF
C1, 22pF
C3
680pF
VFB1
VFB2
R3
442k
MODE/SYNC
GND
R1
604k
R2
604k
1.8V
80
C4
680pF
COUT2
10μF
90
RUN/SS1
L2
4.7μH
R4
887k
100
R5
4.7MΩ
EFFICIENCY (%)
CIN
10μF
R6
4.7MΩ
2.5V
70
60
50
40
30
20
COUT1
10μF
VIN = 3.3V
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
10
0
1
CIN, COUT1, COUT2: TAIYO YUDEN JMK316BJ106ML
L1, L2: TDK VLF3010AT-4R7MR70
3407A TA05
10
100
LOAD CURRENT (mA)
1000
3407A TA06
Figure 4. Low Ripple Buck Regulators Using Ceramic Capacitors
3407afa
14
LTC3407A
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
R = 0.115
TYP
0.38 ± 0.10
6
10
5
1
0.675 ±0.05
3.50 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
PACKAGE
OUTLINE
(DD) DFN 1103
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.200 REF
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
MSE Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1664)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.794 p 0.102
(.110 p .004)
5.23
(.206)
MIN
0.889 p 0.127
(.035 p .005)
1
2.06 p 0.102
(.081 p .004)
1.83 p 0.102
(.072 p .004)
2.083 p 0.102 3.20 – 3.45
(.082 p .004) (.126 – .136)
10
0.50
0.305 p 0.038
(.0197)
(.0120 p .0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
3.00 p 0.102
(.118 p .004)
(NOTE 3)
10 9 8 7 6
3.00 p 0.102
(.118 p .004)
(NOTE 4)
4.90 p 0.152
(.193 p .006)
0.254
(.010)
DETAIL “A”
0o – 6o TYP
1 2 3 4 5
GAUGE PLANE
0.53 p 0.152
(.021 p .006)
DETAIL “A”
0.18
(.007)
0.497 p 0.076
(.0196 p .003)
REF
SEATING
PLANE
0.86
(.034)
REF
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
BSC
0.1016 p 0.0508
(.004 p .002)
MSOP (MSE) 0307 REV B
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3407afa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC3407A
TYPICAL APPLICATION
2mm Height Lithium-Ion Single Inductor Buck-Boost Regulator and a Buck Regulator
VIN = 2.8V
TO 4.2V
C1
10μF
RUN/SS2
VIN
LTC3407A
L2
10μH
D1
POWER-ON
RESET
POR
MODE/SYNC
VOUT2 = 3.3V
AT 200mA
R5
100k
RUN/SS1
L1
2.2μH
C4, 22pF
M1
+
C6
47μF
C3
10μF
R4
887k R3
196k
VFB1
VFB2
C1, C2, C3: TAIYO YUDEN JMK316BJ106ML
C6: SANYO 6TPB47M
D1: PHILIPS PMEG2010
GND
R2
R1
887k
442k
C2
10μF
L1: MURATA LQH32CN2R2M33
L2: TOKO A914BYW-100M (D52LC SERIES)
M1: SILICONIX Si2302
Efficiency vs Load Current
3407A TA07
Efficiency vs Load Current
90
100
80
90
3.6V
2.8V
EFFICIENCY (%)
60
50
40
30
2.8V
80
4.2V
70
EFFICIENCY (%)
VOUT1 = 1.8V
AT 600mA
SW1
SW2
4.2V
3.6V
70
60
50
40
30
20
20
VOUT = 3.3V
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
10
VOUT = 1.8V
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
10
0
0
1
10
100
LOAD CURRENT (mA)
1
1000
3407A TA08
10
100
LOAD CURRENT (mA)
1000
3407A TA09
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1.25A (IOUT), 4MHz,
Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA,
ISD <1μA, MSOP-10 Package
LTC3412/LTC3412A
2.5A (IOUT), 4MHz,
Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA,
ISD <1μA, TSSOP-16E Package
LTC3414
4A (IOUT), 4MHz,
Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 64μA,
ISD <1μA, TSSOP-28E Package
LTC3440/LTC3441
600mA/1.2A (IOUT), 2MHz/1MHz,
Synchronous Buck-Boost DC/DC Converter
95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 2.5V, IQ = 25μA,
ISD <1μA, MSOP-10 Package/DFN Package
LTC3548/
LTC3548-1/LTC3548-2
400mA/800mA (IOUT), 2.25MHz,
Dual Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA,
ISD <1μA, MS10E Package/DFN Package
3407afa
16 Linear Technology Corporation
LT 1008 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
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www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2007