Maxim MAX15034 Configurable, single-/dual-output, synchronous buck controller for high-current application Datasheet

19-4218; Rev 1; 10/11
KIT
ATION
EVALU
E
L
B
A
IL
AVA
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
The MAX15034 two-phase, configurable single- or dualoutput buck controller has an input voltage range of
4.75V to 5.5V or 5V to 28V. A mode select input allows
for a dual-output supply or connecting two phases
together for a single-output, high-current supply. Each
output channel of the MAX15034 drives n-channel
MOSFETs and is capable of providing more than 25A of
load current. The MAX15034 uses average currentmode control with a switching frequency up to 1MHz
per phase where each phase is 180° out of phase with
respect to the other. Out-of-phase operation results in
significantly reduced input capacitor ripple current and
output voltage ripple in dual-phase, single-output voltage applications. Each controller has its own high-performance current and voltage-error amplifier that can
be compensated for optimum output filter L-C values
and transient response.
The MAX15034 offers two enable inputs with accurate
turn-on thresholds to allow for output voltage sequencing
of the two outputs. The device’s switching frequency can
be programmed from 100kHz to 1MHz with an external
resistor. The MAX15034 can be synchronized to an
external clock. Each output voltage is adjustable from
0.61V to 5.5V. Additional features include thermal shutdown and hiccup-mode, short-circuit protection. Use the
MAX15034 with adaptive voltage positioning for applications that require a fast transient response or accurate
output voltage regulation.
The MAX15034 is available in a thermally enhanced 28pin TSSOP package capable of dissipating 2.1W. The
device is rated for operation over the -40°C to +125°C
automotive temperature range.
Features
o 4.75V to 5.5V or 5V to 28V Input
o Dual-Output Synchronous Buck Controller
o Configurable for Two Separate Outputs (25A) or
One Single Output (50A)
o Average Current-Mode Control with Accurate
Adjustable Current Limit
o 180° Interleaved Operation Reduces Size of Input
Filter Capacitors
o Limits Reverse Current Sinking When Operated in
Parallel Mode
o Each Output is Adjustable from 0.61V to 5.5V
o Independently Programmable Adaptive Voltage
Positioning
o Monotonic Startup into Prebiased Outputs
o Independent Shutdown for Each Output
o 100kHz to 1MHz per Phase Programmable
Switching Frequency
o Oscillator Frequency Synchronization from
200kHz to 2MHz
o Digital Soft-Start on Outputs
o Hiccup-Mode Overcurrent Protection
o Overtemperature Shutdown
o Thermally Enhanced 28-Pin TSSOP Package
Capable of Dissipating 2.1W
Applications
High-End Computers/Workstations/Servers
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
Graphics Cards
MAX15034AAUI+
-40°C to +125°C
28 TSSOP
Networking Systems
MAX15034BAUI+
-40°C to +125°C
28 TSSOP-EP*
Point-of-Load High-Current/High-Density
Telecom DC-DC Regulators
MAX15034BAUI/V+
-40°C to +125°C
28 TSSOP-EP*
RAID Systems
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
/V Denotes an automotive qualified part.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX15034
General Description
MAX15034
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
ABSOLUTE MAXIMUM RATINGS
IN, LX_ to AGND.....................................................-0.3V to +30V
BST_ to AGND........................................................-0.3V to +35V
DH_ to LX_ ....................................-0.3V to (VBST_ - VLX_) + 0.3V
DL_ to PGND ..............................................-0.3V to (VDD + 0.3V)
BST_ to LX_ ..............................................................-0.3V to +6V
VDD to PGND............................................................-0.3V to +6V
AGND to PGND .....................................................-0.3V to +0.3V
AVGLIMIT, REG, RT/CLKIN, CSP_,
CSN_ to AGND ......................................................-0.3V to +6V
All Other Pins to AGND ............................-0.3V to (VREG + 0.3V)
REG Continuous Output Current
(limited by power dissipation, no thermal or short-circuit
protection).........................................................................67mA
Continuous Power Dissipation (TA = +70°C) (Note 1)
28-Pin TSSOP (derate 14mW/°C above +70°C) ..........1117mW
28-Pin TSSOP-EP (derate 27mW/°C above +70°C)........2162mW
Operating Temperature Range .........................-40°C to +125°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TSSOP
Junction-to-Ambient Thermal Resistance (θJA)..................71.6°C/W
Junction-to-Case Thermal Resistance (θJC)......................13°C/W
TSSOP-EP
Junction-to-Ambient Thermal Resistance (θJA)..................37°C/W
Junction-to-Case Thermal Resistance (θJC)......................2°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(VIN = VREG = VDD = VEN_ = +5V, TA = TJ = TMIN to TMAX, unless otherwise noted, circuit of Figure 6. Typical values are at TA = +25°C.)
(Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM SPECIFICATIONS
Input Voltage Range
VIN
IN and REG shorted together for +5V
operation
Quiescent Supply Current
IIN
fOSC = 500kHz, DH_ or DL_ = open
5
28
4.75
5.50
7
17
4.15
4.5
V
mA
STARTUP/INTERNAL REGULATOR OUTPUT (REG)
REG Undervoltage Lockout
UVLO
Hysteresis
VHYST
VREG rising
4.0
200
REG Output Accuracy
VIN = 5.8V to 28V, ISOURCE = 0 to 65mA
REG Dropout
VIN < 5.8V, ISOURCE = 60mA
4.75
5.10
V
mV
5.30
V
0.5
V
0.620
V
INTERNAL REFERENCE
Internal Reference Voltage
VEAN_
Digital Ramp Period for Soft-Start
Soft-Start Voltage Steps
EAN_ connected to
EAOUT_
(Note 3)
TA = -40°C to +125°C
0.605
0.6125
1024
Clock
cycles
64
Steps
MOSFET DRIVERS
p-Channel Output Driver
Impedance
2
RON_P
1.35
_______________________________________________________________________________________
3
Ω
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
(VIN = VREG = VDD = VEN_ = +5V, TA = TJ = TMIN to TMAX, unless otherwise noted, circuit of Figure 6. Typical values are at TA = +25°C.)
(Note 2)
PARAMETER
SYMBOL
TYP
MAX
UNITS
RON_N
0.45
1.35
Ω
Output Driver Source Current
IDH_, IDL_
2.5
A
Output Driver Sink Current
IDH_, IDL_
5
A
n-Channel Output Driver
Impedance
Nonoverlap Time (Dead Time)
tNO
CONDITIONS
MIN
CDH_ or CDL_ = 5nF
-7.5
+7.5
fSW = 1MHz nominal, RRT = 12.4kΩ
-10
+10
%
RT/CLKIN Output Voltage
VRT/CLKIN
1.225
V
RT/CLKIN Current Sourcing
Capability
IRT/CLKIN
0.5
mA
RT/CLKIN Logic-High Threshold
VRT/CLKIN_H
RT/CLKIN Logic-Low Threshold
VRT/CLKIN_L
RT/CLKIN High Pulse Width
tRT/CLKIN
RT/CLKIN Synchronization
Frequency Range
fRT/CLKIN
2.4
V
0.8
30
200
V
ns
2000
kHz
CURRENT LIMIT
Internal Average Current-Limit
Threshold
VCL_
VCSP_ - VCSN_
20.4
22.5
24.75
mV
Reverse Average Current-Limit
Threshold
VRCL_
VCSP_ - VCSN_
-3.0
-1.53
-0.1
mV
External Average Current-Limit
Threshold Adjustment
VCL_ADJ
AVGLIMIT Ground Threshold
Voltage
VAVGLIMIT_GND
Leakage Current at AVGLIMIT
IAVGLIMIT
Resistor-divider connected from REG
to AVGLIMIT to AGND
VAVGLIMIT 0.6/36
V
550
VAVGLIMIT = 3V
mV
100
nA
DIGITAL FAULT INTEGRATION (DF_)
Number of Switching Cycles to
Shutdown in Current Limit
NSDF_
32,768
Clock
cycles
Number of Switching Cycles to
Recover from Shutdown
NRDF_
524,288
Clock
cycles
RCS_
3.8
kΩ
CURRENT-SENSE AMPLIFIER
CSP_ to CSN_ Input Resistance
Common-Mode Range
Input Offset Voltage
Amplifier Gain
VCMR(CS)
VIN = VREG = 4.75V to 5.5V or
VIN = 5V to 10V
-0.3
+3.6
V
VIN = 7V to 28V
-0.3
+5.5
V
VOS(CS)
100
µV
AV(CS)
36
V/V
_______________________________________________________________________________________
3
MAX15034
ELECTRICAL CHARACTERISTICS (continued)
MAX15034
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VREG = VDD = VEN_ = +5V, TA = TJ = TMIN to TMAX, unless otherwise noted, circuit of Figure 6. Typical values are at TA = +25°C.)
(Note 2)
PARAMETER
-3dB Bandwidth
CSP_ Input Bias Current
SYMBOL
CONDITIONS
MIN
f-3dB
ICSA(IN)
TYP
MAX
4
UNITS
MHz
VCSP_ = 5.5V, sinking
120
VCSP_ = 0V, sourcing
30
µA
CURRENT-ERROR AMPLIFIER (CEA_)
Transconductance
Open-Loop Gain
gm
AVOL(CEA)
No load
550
µS
50
dB
VOLTAGE-ERROR AMPLIFIER (EAOUT_)
Open-Loop Gain
Unity-Gain Bandwidth
EAN_ Input Bias Current
AVOL(EA)
70
dB
fUGEA
3
MHz
100
nA
IBIAS(EA)
VEAN_ = 2.0V
Error-Amplifier Output Clamping
High Voltage
VCLMP_HI (EA)
With respect to VCM
1
V
Error-Amplifier Output Clamping
Low Voltage
VCLMP_LO (EA)
With respect to VCM
-0.234
V
EN_ INPUTS
EN_ Input High Voltage
VENH
EN rising
1.2
EN_ Hysteresis
1.222
1.245
0.05
EN_ Input Leakage Current
IEN
Startup Delay Time to OUT_
tSTART_DELAY
-200
From EN_ rising to VOUT_ rising
+200
1
V
nA
ms
MODE INPUT
MODE Logic-High Threshold
VMODE_H
MODE Logic-Low Threshold
VMODE_L
MODE Input Pulldown
IPULLDWN
2.4
V
0.8
V
5
µA
-2.1
mV
448
Clock
cycles
PREBIASED OUTPUT
Peak Sink Current-Limit
Threshold during Reference
Soft-Start
VCSP_ - VCSN_
Digital Ramp Period for
Stepping Peak Sink Current
Limit after Reference Soft-Start
THERMAL SHUTDOWN
Thermal Shutdown
TSHDN
160
Thermal Shutdown Hysteresis
THYST
10
°C
Note 2: The device is 100% production tested at TA = TJ = +125°C. Limits at TA = -40°C and TA = +25°C are guaranteed by design.
Note 3: The internal reference voltage accuracy is measured at the negative input of the error amplifiers (EAN_). Output voltage
accuracy must include external resistor-divider tolerances.
4
_______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
SUPPLY CURRENT
vs. TEMPERATURE AND FREQUENCY
(VIN = 5V)
100
fSW = 500kHz
12
10
8
fSW = 250kHz
6
16
fSW = 125kHz
4
fSW = 250kHz
6
fSW = 125kHz
2
0
TEMPERATURE (°C)
SUPPLY CURRENT
vs. TEMPERATURE AND FREQUENCY
(VIN = 24V)
SUPPLY CURRENT
vs. OSCILLATOR FREQUENCY
SUPPLY CURRENT
vs. DRIVER LOAD CAPACITANCE
12
fSW = 500kHz
10
8
fSW = 250kHz
6
fSW = 125kHz
4
14
CDH_ = CDL_ = 0
13
12
11
VIN = 12V
VIN = 24V
10
9
8
2
7
0
6
100
VIN = 5V
CLOAD = CDH_ = CDL_
90
80
SUPPLY CURRENT (mA)
fSW = 1MHz
MAX15034 toc03
CDH_ = CDL_ = 0
MAX15034 toc04
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
70
60
50
40
30
20
10
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
200 400 600 800 1000 1200 1400 1600 1800 2000
TEMPERATURE (°C)
FREQUENCY (kHz)
CLOAD (nF)
REG LINE REGULATION
OUTPUT LOAD-TRANSIENT RESPONSE
REG LOAD REGULATION
VIN = 24V
5.05
5
10
15
20
25
30
MAX15034 toc07
5.10
MAX15034 toc05
5.10
0
5.08
MAX15034 toc06
SUPPLY CURRENT (mA)
8
RT (kΩ)
14
IREG = 0
20A
VIN = 12V
5.00
IOUT
10A/div
5.06
VREG (V)
VREG (V)
fSW = 500kHz
10
-40 -25 -10 5 20 35 50 65 80 95 110 125
MAX15034 toc02c
16
12
4
0
0 100 200 300 400 500 600 700 800 900 1000
fSW = 1MHz
14
2
10
CDH_ = CDL_ = 0
MAX15034 toc02b
14
SUPPLY CURRENT (mA)
1000
fSW = 1MHz
CDH_ = CDL_ = 0
SUPPLY CURRENT (mA)
16
MAX15034 toc01
OSCILLATOR FREQUENCY (kHz)
CDH_ = CDL_ = 0
MAX15034 toc02a
OSCILLATOR FREQUENCY vs. RT
10,000
SUPPLY CURRENT
vs. TEMPERATURE AND FREQUENCY
(VIN = 12V)
5.04
VOUT
100mV/div
AC-COUPLED
5.02
VIN = 5.5V
5.00
4.95
IREG = 60mA
4.98
4.96
4.90
0
10 20 30 40 50 60 70 80 90 100
IREG (mA)
MAX15034
Typical Operating Characteristics
(Circuit of Figure 6, TA = +25°C, unless otherwise noted. VIN = 12V, VOUT1 = 0.8V, VOUT2 = 1.3V, fSW = 500kHz per phase.)
5
7
9
11
13
15
17
19
21
23
2ms/div
VIN (V)
_______________________________________________________________________________________
5
Typical Operating Characteristics (continued)
(Circuit of Figure 6, TA = +25°C, unless otherwise noted. VIN = 12V, VOUT1 = 0.8V, VOUT2 = 1.3V, fSW = 500kHz per phase.)
DRIVER RISE TIME
vs. LOAD CAPACITANCE
40
MAX15034 toc08
90
80
35
DH_
DH_
70
MAX15034 toc09
DRIVER FALL TIME
vs. LOAD CAPACITANCE
100
30
DL_
60
tFALL (ns)
tRISE (ns)
MAX15034
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
50
40
25
DL_
20
15
30
10
20
5
10
0
0
0
2
4
6
8 10 12 14 16 18 20 22
0
CLOAD (nF)
2
4
6
8 10 12 14 16 18 20 22
CLOAD (nF)
HIGH-SIDE DRIVER FALL TIME
(VIN = 12V, CLOAD = 10nF)
HIGH-SIDE DRIVER RISE TIME
(VIN = 12V, CLOAD = 10nF)
MAX15034 toc11
MAX15034 toc10
DH_
2V/div
DH_
2V/div
20ns/div
20ns/div
LOW-SIDE DRIVER RISE TIME
(VIN = 12V, CLOAD = 10nF)
LOW-SIDE DRIVER FALL TIME
(VIN = 12V, CLOAD = 10nF)
MAX15034 toc12
MAX15034 toc13
DL_
2V/div
20ns/div
6
DL_
2V/div
20ns/div
_______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
OUT1/OUT2 OUT-OF-PHASE WAVEFORMS
(VOUT1 = 0.8V, VOUT2 = 1.3V)
TURN-ON/TURN-OFF WAVEFORM
MAX15034 toc15
MAX15034 toc14
LX1
10V/div
VOUT1
1V/div
OUT1
100mV/div
EN1
5V/div
LX2
10V/div
VOUT2
1V/div
OUT2
100mV/div
EN2
5V/div
10µs/div
1ms/div
SHORT-CIRCUIT CURRENT WAVEFORMS
(VIN = 5V)
AVERAGE CURRENT LIMIT
vs. VAVGLIMIT
MAX15034 toc16
IOUT2
10A/div
MAX15034 toc17
IOUT1
10A/div
AVERAGE CURRENT LIMIT (mV)
75
60
45
30
15
0
0
200ms/div
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
1.0
1.5
2.0
VAVGLIMIT (V)
2.5
3.0
SWITCHING FREQUENCY
vs. TEMPERATURE
0.615
0.610
0.605
MAX15034 toc19
550
SWITCHING FREQUENCY (kHz)
MAX15034 toc18
INTERNAL REFERENCE VOLTAGE (V)
0.620
0.5
525
500
475
450
-40 -25 -10 5 20 35 50 65 80 95 110 125
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
MAX15034
Typical Operating Characteristics (continued)
(Circuit of Figure 6, TA = +25°C, unless otherwise noted. VIN = 12V, VOUT1 = 0.8V, VOUT2 = 1.3V, fSW = 500kHz per phase.)
Typical Operating Characteristics (continued)
(Circuit of Figure 6, TA = +25°C, unless otherwise noted. VIN = 12V, VOUT1 = 0.8V, VOUT2 = 1.3V, fSW = 500kHz per phase.)
INTERNAL AVERAGE CURRENT LIMIT
vs. TEMPERATURE
INTERNAL AVERAGE REVERSE
CURRENT LIMIT vs. TEMPERATURE
INTERNAL AVERAGE CURRENT LIMIT (mV)
24
23
22
21
20
MAX15034 toc21
0
MAX15034 toc20
25
INTERNAL AVERAGE CURRENT LIMIT (mV)
MAX15034
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-40 -25 -10 5 20 35 50 65 80 95 110 125
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
SOFT-START WAVEFORM
PREBIASED OUTPUT CONDITION
MAX15034 toc22
MAX15034 toc23
EN2
5V/div
VOUT2
500mV/div
VOUT2
500mV/div
DH2
5V/div
VEAN2
200mV/div
DL2
5V/div
0V
400µs/div
EAOUT2
1V/div
400µs/div
PEAK PULLUP AND PULLDOWN CURRENT
OR DRIVER AT DH_ AND DL_
MAX15034 toc24
CLOAD = 10nF
DH_
500mV/div
DL_
500mV/div
200ns/div
8
EN2
5V/div
_______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
PIN
NAME
FUNCTION
1
CSN2
Current-Sense Differential Amplifier Negative Input for Output 2. Connect CSN2 to the negative terminal of
the sense resistor. The differential voltage between CSP2 and CSN2 is internally amplified by the currentsense amplifier (AV(CS) = 36V/V).
2
CSP2
Current-Sense Differential Amplifier Positive Input for Output 2. Connect CSP2 to the positive terminal of the
sense resistor. The differential voltage between CSP2 and CSN2 is internally amplified by the current-sense
amplifier (AV(CS) = 36V/V).
EAOUT2
Voltage Error-Amplifier Output 2. Connect to an external gain-setting feedback resistor. The error-amplifier
gain determines the output voltage load regulation for adaptive voltage positioning. This output also serves
as the compensation network connection from EAOUT2 to EAN2. A resistive network results in a drooped
output-voltage-regulation characteristic. An integrator configuration results in very tight output-voltage
regulation (see the Adaptive Voltage Positioning section).
4
EAN2
Voltage Error-Amplifier Inverting Input for Output 2. Connect a resistive divider from VOUT2 to EAN2 to
AGND to set the output voltage. A compensation network connects from EAOUT2 to EAN2. A resistive
network results in a drooped output-voltage-regulation characteristic. An integrator configuration results in
very tight output-voltage regulation (see the Adaptive Voltage Positioning section).
5
CLP2
Current-Error Amplifier Output 2. Compensate the current loop by connecting an R-C network from CLP2 to
AGND.
6
AVGLIMIT
Average Current-Limit Programming. Connect a resistor-divider between REG, AVGLIMIT, and AGND to set
the average current-limit value (see the Programming Average the Current Limit section).
7
RT/CLKIN
External Clock Input or Internal Frequency-Setting Connection. Connect a resistor from RT/CLKIN to AGND
to set the switching frequency. Connect an external clock at RT/CLKIN for external frequency
synchronization.
8
AGND
Analog Ground
9
MODE
Mode Function Input. MODE selects between a single-output dual phase or a dual-output buck regulator.
When MODE is grounded, VEA1 and VEA2 connect to CEA1 and CEA2, respectively (see Figure 1) and the
device operates as a two-output, out-of-phase buck regulator. When MODE is connected to REG (logic
high), VEA2 is disconnected and VEA1 is routed to both CEA1 and CEA2.
10
CLP1
Current-Error Amplifier Output 1. Compensate the current loop by connecting an R-C network from CLP1 to
AGND.
EAN1
Voltage Error-Amplifier Inverting Input for Output 1. Connect a resistive divider from VOUT1 to EAN1 to
regulate the output voltage. A compensation network connects from EAOUT1 to EAN1. A resistive network
results in a drooped output-voltage-regulation characteristic. An integrator configuration results in very tight
output-voltage regulation (see the Adaptive Voltage Positioning section).
12
EAOUT1
Voltage Error-Amplifier Output 1. Connect to an external gain-setting feedback resistor. The error-amplifier
gain determines the output-voltage-load regulation for adaptive voltage positioning. This output also serves
as the compensation network connection from EAOUT1 to EAN1. A resistive network results in a drooped
output-voltage-regulation characteristic. An integrator configuration results in very tight output-voltage
regulation (see the Adaptive Voltage Positioning section).
13
CSP1
Current-Sense Differential Amplifier Positive Input for Output 1. Connect CSP1 to the positive terminal of the
sense resistor. The differential voltage between CSP1 and CSN1 is internally amplified by the current-sense
amplifier (AV(CS) = 36V/V).
14
CSN1
Current-Sense Differential Amplifier Negative Input for Output 1. Connect CSN1 to the negative terminal of
the sense resistor. The differential voltage between CSP1 and CSN1 is internally amplified by the currentsense amplifier (AV(CS) = 36V/V).
3
11
_______________________________________________________________________________________
9
MAX15034
Pin Description
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
MAX15034
Pin Description (continued)
PIN
NAME
FUNCTION
15
EN1
Output 1 Enable. A logic-low shuts down channel 1’s MOSFET drivers. EN1 can be used for output
sequencing.
16
BST1
Boost Flying-Capacitor Connection. Reservoir capacitor connection for the high-side MOSFET driver
supply. Connect a 0.47µF ceramic capacitor between BST1 and LX1.
17
DH1
High-Side Gate Driver Output 1. DH1 drives the gate of the high-side MOSFET.
18
LX1
External Inductor Connection and Source Connection for the High-Side MOSFET for Output 1. LX1 also
serves as the return terminal for the high-side MOSFET driver.
19
DL1
Low-Side Gate Driver Output 1. Gate driver output for the synchronous MOSFET.
20
VDD
Supply Voltage for Low-Side Drivers. REG powers VDD. Connect a parallel combination of 0.1µF and 1µF
ceramic capacitors from VDD to PGND and a 1Ω resistor from VDD to REG to filter out the high-peak
currents of the driver from the internal circuitry.
21
REG
Internal 5V Regulator Output. REG is derived internally from IN and is used to power the internal bias
circuitry. Bypass REG to AGND with a 4.7µF ceramic capacitor.
22
IN
23
PGND
24
DL2
Low-Side Gate Driver Output 2. Gate driver for the synchronous MOSFET.
25
LX2
External Inductor Connection and Source Connection for the High-Side MOSFET for Output 2. Also serves
as the return terminal for the high-side MOSFET driver.
26
DH2
High-Side Gate Driver Output 2. DH2 drives the gate of the high-side MOSFET.
27
BST2
Boost Flying-Capacitor Connection. Reservoir capacitor connection for the high-side MOSFET driver
supply. Connect a 0.47µF ceramic capacitor between BST2 and LX2.
28
EN2
Output 2 Enable. A logic-low shuts down channel 2’s MOSFET drivers. EN2 can be used for output
sequencing.
—
EP
Supply Voltage Connection. Connect IN to a 5V to 28V input supply.
Power Ground. Source connection for the low-side MOSFET. Connect VDD’s bypass capacitor returns to
PGND.
Exposed Pad. Connect exposed pad to ground plane (MAX15034BAUI only).
Detailed Description
The MAX15034 switching power-supply controller can
be configured two ways. With the MODE input high, this
device operates as single-output, dual-phase, stepdown switching regulators where each output is 180°
out of phase. With MODE connected low, the
MAX15034 operates as a dual-output, step-down
switching regulator. The average current-mode control
topology of the MAX15034 offers high-noise immunity
while having benefits similar to those of peak currentmode control. Average current-mode control has the
intrinsic ability to accurately limit the average current
sourced by the converter during a fault condition. When
a fault condition occurs, the error-amplifier output voltage (EAOUT1 or EAOUT2) that connects to the positive
10
input of the transconductance amplifier (CA1 or CA2) is
clamped, thus limiting the output current.
The MAX15034 has internal logic to ensure each output’s
monotonic startup under prebias load conditions. This
facilitates glitch-free output voltage power-up in the presence of another redundant/parallel voltage regulator.
The MAX15034 contains all blocks necessary for two
independently regulated average current-mode PWM
regulators. This device has two voltage error amplifiers
(VEA1 and VEA2), two current-error amplifiers (CEA1
and CEA2), two current-sensing amplifiers (CA1 and
CA2), two PWM comparators (CPWM1 and CPWM2),
and drivers for both low- and high-side power MOSFETs
(see Figure 1). Each PWM section is also equipped with
a pulse-by-pulse, current-limit protection and a fault
integration block for hiccup protection.
______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
MAX15034
CLP1 10
13 CSP1
CA1
14 CSN1
EAOUT1
12
EAN1
11
DF1 AND
HICCUP
LOGIC
CEA1
VEA1
16 BST1
CPWM1
17 DH1
IN
22
REG
21
VREG = 5V
UVLO
2VP-P
RAMP
CONTROL
AND DRIVER
LOGIC 1
FOR INTERNAL
BIASING
18 LX1
20 VDD
19 DL1
CEN1
EN1
15
AVGLIMIT
6
0°
1.225V
THERMAL
SHUTDOWN
VINTREF = 0.61V
OSCILLATOR
AND PHASE
SPLITTER
1.225V
EXTERNAL FREQUENCY SYNC
27 BST2
180°
CEN2
26 DH2
EN2 28
CONTROL
AND DRIVER
LOGIC 2
2VP-P
RAMP
AGND
7 RT/CLKIN
8
25 LX2
VDD
24 DL2
VEA2
EAN2
4
EAOUT2
3
MODE
9
MUX
CPWM2
23 PGND
CEA2
DF2 AND
HICCUP
LOGIC
2 CSP2
CA2
CLP2
1 CSN2
5
Figure 1. Block Diagram
Two enable comparators (CEN1 and CEN2) are available to control and sequence the two PWM sections
through the enable (EN1 or EN2) inputs. An oscillator,
with an externally programmable frequency generates
two clock pulse trains and two ramps for both PWM
sections. The two clocks and the two ramps are 180°
out of phase with each other.
A linear regulator (REG) generates the 5V to supply the
device. This regulator has the output-current capability
necessary to provide for the MAX15034’s internal
circuitry and the power for the external MOSFET’s gate
drivers. Internal UVLO circuitry ensures that the
MAX15034 starts up when VREG is at the correct voltage levels to guarantee safe operation of the IC and of
the power MOSFETs.
Finally, a thermal-shutdown feature protects the device
during thermal faults and shuts down the MAX15034
when the die temperature exceeds +160°C.
______________________________________________________________________________________
11
MAX15034
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Dual-Output/Dual-Phase Select (MODE)
The MAX15034 can operate as a dual-output, independently regulated buck converter, or as a dual-phase,
single-output buck converter. The MODE input selects
between the two operating modes. When MODE is
grounded (logic-low), VEA1 and VEA2 connect to CEA1
and CEA2, respectively (see Figure 1), and the device
operates as a two-output DC-DC converter. When
MODE is connected to REG (logic-high), VEA2 is disconnected and VEA1 is routed to both CEA1 and CEA2
and the device works as a dual-phase, single-output
buck regulator with each output 180° out of phase with
respect to each other.
Supply Voltage Connections (VIN/VREG)
The MAX15034 accepts a wide input voltage range at
IN of 5V to 28V. An internal linear regulator steps down
VIN to 5.1V (typ) and provides power to the MAX15034.
The output of this regulator is available at REG. For VIN
= 4.75V to 5.5V, connect IN and REG together externally. REG can supply up to 65mA for external loads.
Bypass REG to AGND with a 4.7µF ceramic capacitor
for high-frequency noise rejection and stable operation.
REG supplies the current for the MAX15034’s internal
circuitry and for the MOSFET gate drivers (when connected externally to VDD), and can source up to 65mA.
Calculate the maximum bias current (I BIAS ) for the
MAX15034:
IBIAS = IIN + fSW × ( QGQ1 + QGQ2 + QGQ3 + QGQ4 )
where IIN is the quiescent supply current into IN (4mA,
typ), Q GQ1 , Q GQ2 , Q GQ3 , Q GQ4 are the total gate
charges of MOSFETs Q1 through Q4 at VGS = 5V (see
Figure 6), and fSW is the switching frequency of each
individual phase.
Low-Side MOSFET Driver Supply (VDD)
VDD is the power input for the low-side MOSFET drivers. Connect the regulator output REG externally to
VDD through an R-C lowpass filter. Use a 1Ω resistor
and a parallel combination of 1µF and 0.1µF ceramic
capacitors to filter out the high peak currents of the
MOSFET drivers from the sensitive internal circuitry.
High-Side MOSFET Drive Supply (BST_)
BST1 and BST2 supply the power for the high-side
MOSFET drivers for output 1 and output 2, respectively.
Connect BST1 and BST2 to V DD through rectifier
diodes D1 and D2 (see Figure 6). Connect a 0.1µF
ceramic capacitor between BST_ and LX_.
12
Minimize the trace inductance from BST_ and VDD to
the rectifier diodes, D1 and D2, and from BST_ and LX_
to the boost capacitors, C8 and C9 (see Figure 6). This
is accomplished by using short, wide trace lengths.
Undervoltage Lockout (UVLO)/
Power-On Reset (POR)/Soft-Start
The MAX15034 includes an undervoltage lockout
(UVLO) with hysteresis, and a power-on reset circuit for
converter turn-on and monotonic rise of the output voltage. The UVLO threshold monitors VREG and is internally set between 4.0V and 4.5V with 200mV of
hysteresis. Hysteresis eliminates chattering during
startup. Most of the internal circuitry, including the
oscillator, turns on when V REG reaches 4.5V. The
MAX15034 draws up to 4mA (typ) of current before
VREG reaches the UVLO threshold.
The compensation network at the current-error amplifiers (CLP1 and CLP2) provides an inherent soft-start of
the output voltage. It includes (R14 and C10) in parallel
with C11 at CLP1 and (R15 and C12) in parallel with
C13 at CLP2 (see Figure 6). The voltage at the currenterror amplifier output limits the maximum current available to charge the output capacitors. The capacitor at
CLP_ in conjunction with the finite output-drive current
of the current-error amplifier yields a finite rise time for
the output current and thus, the output voltage.
Setting the Switching Frequency (fSW)
An internal oscillator generates the 180o out-of-phase
clock signals required for both PWM modulators. The
oscillator also generates the 2VP-P voltage ramps necessary for the PWM comparators. The oscillator frequency can be set from 200kHz to 2MHz by an external
resistor (RT) connected from RT/CLKIN to AGND (see
Figure 6). The equation below shows the relationship
between RT and the switching frequency:
fOSC =
2.5 × 1010
Hz
RRT
where RRT is in ohms and the per-phase switching frequency is fSW = fOSC/2.
Use RT/CLKIN as a clock input to synchronize the
MAX15034 to an external frequency (f RT/CLKIN ).
Applying an external clock to RT/CLKIN allows each
PWM section to work at a frequency equal to
fRT/CLKIN/2. An internal comparator with a 1.6V threshold detects fRT/CLKIN. If fRT/CLKIN is present, internal
logic switches from the internal oscillator clock, to the
clock present at RT/CLKIN.
______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Control Loop
The MAX15034 uses an average current-mode control
topology to regulate the output voltage. The control
loop consists of an inner current loop and an outer voltage loop. The inner current loop controls the output
CSN1
RCF
CSP1
current, while the outer voltage loop controls the output
voltage. The inner current loop absorbs the inductor
pole, reducing the order of the outer voltage loop to
that of a single-pole system. Figure 2 is the block diagram of OUT1’s control loop.
The current loop consists of a current-sense resistor,
RSENSE, a current-sense amplifier (CA1), a currenterror amplifier (CEA1), an oscillator providing the carrier ramp, and a PWM comparator (CPWM1). The
precision current-sense amplifier (CA1) amplifies the
sense voltage across RSENSE by a factor of 36. The
inverting input to CEA1 senses the output of CA1. The
output of CEA1 is the difference between the voltageerror amplifier output (EAOUT1) and the gained-up voltage from CA1. The RC compensation network
connected to CLP1 provides external frequency compensation for the respective CEA1 (see the
Compensation section). The start of every clock cycle
enables the high-side driver and initiates a PWM oncycle. Comparator CPWM1 compares the output voltage from CEA1 against a 0 to 2V ramp from the
oscillator. The PWM on-cycle terminates when the ramp
voltage exceeds the error voltage from the current-error
amplifier (CEA1).
CCF
CA 1
CLP1
RF
CCFF
IL
CEA1
CPWM1
VEA1
VIN
RSENSE
VOUT1
DRIVE
2VP-P
R1
COUT
LOAD
VREF = 0.61V
R2
Figure 2. Current and Voltage Loops
______________________________________________________________________________________
13
MAX15034
Hiccup Fault Protection
The MAX15034 includes overload fault protection circuitry
that prevents damage to the power MOSFETs. The fault
protection consists of two digital fault integration blocks
that enable hiccuping under overcurrent conditions. This
circuit works as follows: for every clock cycle the currentlimit threshold is exceeded, the fault integration counter
increments by one count. Thus, if the current-limit condition persists, the counter reaches its shutdown threshold
in 32,768 counts and shuts down the external MOSFETs.
When the MAX15034 shuts down due to a fault, the
counter begins to count down (since the current-limit condition has ended), once every 16 clock cycles. Thus, the
device counts down for 524,288 clock cycles. At this
point, switching resumes. This produces an effective duty
cycle of 6.25% power-up and 93.75% power-down under
fault conditions. With a switching frequency set to
250kHz, power-up and power-down times are approximately 131ms and 2.09s, respectively.
MAX15034
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
The outer voltage control loop consists of the voltageerror amplifier (VEA1). The noninverting input (EAN1) is
externally connected to the midpoint of a resistive voltage-divider from OUT1 to EAN1 to AGND. The voltage
loop gain is set by using an external resistor from the
output of this amplifier (EAOUT1) to its inverting input
(EAN1). The noninverting input of (VEA1) is connected
to the 0.61V internal reference.
Current-Error Amplifier
The MAX15034 features two dedicated transconductance current-error amplifiers CEA1 and CEA2 with a
typical gm of 550µS and 320µA output sink and source
capability. The current-error amplifier outputs (CLP1 and
CLP2) serve as the inverting input to the PWM comparators. CLP1 and CLP2 are externally accessible to provide frequency compensation for the inner current loops
(see CCFF, CCF, and RCF in Figure 2). Compensate the
current-error amplifier so that the inductor current down
slope, which becomes the up slope at the inverting
input of the PWM comparator, is less than the slope of
the internally generated voltage ramp (see the
Compensation section).
PWM Comparator and R-S Flip-Flop
The PWM comparator (CPWM1 or CPWM2) sets the
duty cycle for each cycle by comparing the currenterror amplifier output to a 2VP-P ramp. At the start of
each clock cycle an R-S flip-flop resets and the highside drivers (DH1 and DH2) turn on. The comparator
sets the flip-flop as soon as the ramp voltage exceeds
the current-error amplifier output voltage, thus terminating the on-cycle.
Voltage-Error Amplifier
The voltage-error amplifier (VEA_) sets the gain of the
voltage control loop. Its output clamps to 1.14V and
-0.234V relative to VCM = 0.61V. Set the MAX15034 output voltage by connecting a voltage-divider from the
output to EAN_ to GND (see Figure 4). At no load, the
output of the voltage error amplifier is zero.
The voltage at full load is given by:
⎛
R ⎞
VOUT(FL) = 0.6125 × ⎜ 1 + 1 ⎟ − ∆VOUT
⎝ R2 ⎠
where ∆V OUT is the voltage-positioning window
described in the Adaptive Voltage Positioning section.
Adaptive Voltage Positioning
Powering new-generation ICs requires new techniques
to reduce cost, size, and power dissipation. Voltage
positioning (Figure 5) reduces the total number of output capacitors to meet a given transient response
requirement. Setting the no-load output voltage slightly
higher than the output voltage during nominally loaded
conditions allows a larger downward voltage excursion
when the output current suddenly increases.
Regulating at a lower output voltage under a heavy
load allows a larger upward-voltage excursion when
the output current suddenly decreases. A larger
allowed voltage-step excursion reduces the required
number of output capacitors and/or allows the use of
higher ESR capacitors.
The MAX15034 internal 0.6125V reference provides a
tolerance of ±1.25%. Using 0.1% resistors for R1 and
R2 allows a 4% variation from the nominal output voltage. This available voltage range allows the reduction
of the total number of output capacitors to meet a given
transient response requirement resulting in a voltagepositioning window as shown in Figure 5.
From the allowable voltage-positioning window calculate the value of RF from the equation below.
I
× RSENSE × 36 × R1
RF = OUT
∆VOUT
where ∆VOUT is the allowable voltage-positioning window, RSENSE is the sense resistor, 36 is the currentsense amplifier gain, and R1 is as shown in Figure 4.
Use the equation below to calculate the no load voltage:
⎛
R ⎞
VOUT(NL) = 0.6125 × ⎜ 1 + 1 ⎟
⎝ R2 ⎠
14
______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
MAX15034
VDD
CLP_
AV = 36V/V
CSP_
gm = 500µS
CSN_
PWM
COMPARATOR
GMIN
BST_
S
RAMP
Q
DH_
2 x fSW (V/S)
LX_
CLK
R
Q
DL_
1.225V
PGND
EN_
Figure 3. Current Comparator and MOSFET Driver Logic
VOUT
VOLTAGE-POSITIONING WINDOW
VCNTR + ∆VOUT/2
RF
VCNTR
R1
COUT
EAN_
LOAD
VCNTR - ∆VOUT/2
EAOUT_
R2
VREF = 0.61V
NO LOAD
1/2 LOAD
FULL LOAD
LOAD (A)
Figure 4. Voltage Error Amplifier
MOSFET Gate Drivers (DH_, DL_)
The high-side drivers (DH1 and DH2) and low-side drivers (DL1 and DL2) drive the gates of external n-channel
MOSFETs. The high-peak sink and source current capability of these drivers provides ample drive for the fast
rise and fall times of the switching MOSFETs. Faster rise
and fall times result in reduced switching losses. For lowoutput, voltage-regulating applications where the duty
Figure 5. Defining the Voltage-Positioning Window
cycle is less than 50%, choose high-side MOSFETs (Q2
and Q4, Figure 6) with a moderate RDS(ON) and a very
low gate charge. Choose low-side MOSFETs (Q1 and
Q3, Figure 6) with very low RDS(ON) and moderate gate
charge. The driver block also includes a logic circuit that
provides an adaptive nonoverlap time (30ns typ) to prevent shoot-through currents during transition. Figure 7
shows the dual-phase, single-output buck regulator.
______________________________________________________________________________________
15
MAX15034
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
VIN
IN
VDD
D1
(100mA, 30V)
R3
1Ω
22Ω
C2
1µF
BST1
R1
2mΩ
BST2
Q4
IRF7821
DH1
L1
0.5µH
LX2
MAX15034
DL1
C3
0.1µF
L2
0.8µH
Q3
IRF7832
R2
2mΩ
DL2
1.3V/10A
C7
680µF
PGND
R4
1.74kΩ
CSP1
CSN1
CSP2
EAN1
CSN2
EAOUT2
R8
29.4kΩ
MODE
VREG
R16
100kΩ
R7
4.75kΩ
R9
60.4kΩ
R14
1kΩ
EN1
C10
15nF
CLP1
C14
0.1µF
R17
100kΩ
R6
5.11kΩ
EAN2
EAOUT1
R5
4.64kΩ
C11
120pF
EN2
R15
1kΩ
C15
0.1µF
C12
15nF
CLP2
PGND
RT/CLKIN
AVGLIMIT
AGND
C13
120pF
VREG
RT
24.9kΩ
R18
19.6kΩ
R19
10kΩ
EXTERNAL FREQUENCY SYNC
Figure 6. Dual-Output Buck Regulator
16
C4
4.7µF
C9
0.1µF
DH2
LX1
Q1
IRF7832
C6
680µF
D2
(100mA, 30V)
22Ω
Q2
IRF7821
C8
0.1µF
0.8V/10A
C5
10µF
REG
______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
IN
VDD
D1
(100mA, 30V)
REG
R3
1Ω
22Ω
C2
1µF
BST1
R1
2mΩ
Q4
IRF7821
C9
0.1µF
L2
0.8µH
DH2
LX1
Q1
IRF7832
LX2
Q3
IRF7832
MAX15034
DL1
C6
680µF
C3
0.1µF
C4
4.7µF
BST2
DH1
L1
0.8µH
D2
(100mA, 30V)
22Ω
Q2
IRF7821
C8
0.1µF
1.3V/20A
C5
10µF
R2
2mΩ
DL2
PGND
R4
5.11kΩ
CSP1
CSN1
CSP2
EAN1
CSN2
EAN2
EAOUT1
R5
4.75kΩ
EAOUT2
R8
60.4kΩ
VREG
MODE
R16
100kΩ
R14
1kΩ
EN1
C10
15nF
CLP1
C14
0.1µF
R17
100kΩ
TO REG
C11
120pF
EN2
R15
1kΩ
C15
0.1µF
C12
15nF
CLP2
PGND
RT/CLKIN
C13
120pF
AVGLIMIT
AGND
RT
24.9kΩ
EXTERNAL FREQUENCY SYNC
Figure 7. Dual-Phase, Single-Output Buck Regulator
______________________________________________________________________________________
17
MAX15034
VIN
MAX15034
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Design Procedures
Inductor Selection
The switching frequency per phase, peak-to-peak ripple
current in each phase, and allowable voltage ripple at
the output, determine the inductance value. Selecting
higher switching frequencies reduces the inductance
requirement, but at the cost of lower efficiency due to
the charge/discharge cycle of the gate and drain
capacitances in the switching MOSFETs. The situation
worsens at higher input voltages, since capacitive
switching losses are proportional to the square of the
input voltage. Lower switching frequencies on the other
hand increase the peak-to-peak inductor ripple current
(∆IL), and therefore, increase the MOSFET conduction
losses (see the Power MOSFET Selection section for a
detailed description of MOSFET power loss).
When using higher inductor ripple current, the ripple cancellation in the multiphase topology, reduces the input
and output capacitor RMS ripple current. Use the following equation to determine the minimum inductance value:
L=
VOUT (VIN(MAX) − VOUT )
VIN × fSW × ∆IL
Choose ∆IL to be equal to approximately 30% of the output current per channel. Since ∆IL affects the output-ripple voltage, the inductance value may need minor
adjustment after choosing the output capacitors for fullrated efficiency. Choose inductors from the standard
high-current, surface-mount inductor series available
from various manufacturers. Particular applications may
require custom-made inductors. Use high-frequency core
material for custom inductors. High ∆IL causes large
peak-to-peak flux excursion increasing the core losses at
higher frequencies. The high-frequency operation coupled with high ∆IL, reduces the required minimum inductance and even makes the use of planar inductors
possible. The advantages of using planar magnetics
include low-profile design, excellent current sharing
between phases due to the tight control of parasitics, and
low cost. For example, the minimum inductance at VIN =
12V, VOUT = 0.8V, ∆IL = 3A, and fSW = 500kHz is 0.5µH.
The average current-mode control feature of the
MAX15034 limits the maximum inductor current, which
prevents the inductor from saturating. Choose an
inductor with a saturating current greater than the
worst-case peak inductor current:
IL _ PEAK =
18
24.75 × 10 −3 ∆IL
+
RSENSE
2
where 24.75mV is the maximum average current-limit
threshold for the current-sense amplifier and RSENSE is
the sense resistor.
Power MOSFET Selection
When choosing the MOSFETs, consider the total gate
charge, R DS(ON) , power dissipation, the maximum
drain-to-source voltage, and package thermal impedance. The product of the MOSFET gate charge and onresistance is a figure of merit, with a lower number
signifying better performance. Choose MOSFETs optimized for high-frequency switching applications. The
average gate-drive current from the MAX15034’s output
is proportional to the total capacitance it drives at DH1,
DH2, DL1, and DL2. The power dissipated in the
MAX15034 is proportional to the input voltage and the
average drive current. See the Supply Voltage
Connections (VIN/VREG) and the Low-Side MOSFET
Drives Supply (VDD) sections to determine the maximum total gate charge allowed from all driver outputs
together.
The losses may be broken into four categories: conduction loss, gate drive loss, switching loss, and output loss.
The following simplified power loss equation is true for
both MOSFETs in the synchronous buck-converter:
PLOSS = PCONDUCTION + PGATEDRIVE
+ PSWITCH + POUTPUT
For the low-side MOSFET, the PSWITCH term becomes
virtually zero because the body diode of the MOSFET is
conducting before the MOSFET is turned on.
Tables 1 and 2 describe the different losses and shows
an approximation of the losses during that period.
Input Capacitance
The discontinuous input-current waveform of the buck
converter causes large ripple currents in the input
capacitor. The switching frequency, peak inductor current, and the allowable peak-to-peak voltage ripple
reflected back to the source, dictate the capacitance
requirement. Increasing the number of phases increases the effective switching frequency and lowers the
peak-to-average current ratio, yielding lower input
capacitance requirement. It can be shown that the
worst-case RMS current occurs when only one controller section is operating. The controller section with
the highest output power needs to be used in determining the maximum input RMS ripple current requirement.
Increasing the output current drawn from the other outof-phase controller section results in reducing the input
______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
MAX15034
Table 1. High-Side MOSFET Losses
LOSS
DESCRIPTION
Conduction Loss
Losses associated with MOSFET on-time and
on-resistance. IRMS is a function of load current
and duty cycle.
Gate Drive Loss
Losses associated with charging and
discharging the gate capacitance of the
MOSFET every cycle. Use the MOSFET’s (QG)
specification.
Switching Loss
Losses during the drain voltage and drain
current transitions for every switching cycle.
Losses occur only during the QGS2 and QGD
time period and not during the initial QGS1
period. The initial QGS1 period is the rise in the
gate voltage from zero to VTH. RDH_ is the highside MOSFET driver’s on-resistance and RGATE
is the internal gate resistance of the high-side
MOSFET (QGD and QGS2 are found in the
MOSFET data sheet).
Output Loss
Losses associated with QOSS of the MOSFET
occur every cycle when the high-side MOSFET
turns on. The losses are caused by both
MOSFETs, but are dissipated in the high-side
MOSFET.
ripple current. A low-ESR input capacitor that can handle the maximum input RMS ripple current of one channel must be used. The maximum RMS capacitor ripple
current is given by:
ICIN(RMS) ≈ IMAX
VOUT (VIN − VOUT )
VIN
where IMAX is the full load current of the regulator. VOUT
is the output voltage of the same regulator and CIN is C5
in Figure 6. The ESR of the input capacitors wastes
power from the input and heats up the capacitor.
Reducing the ESR is important to maintain a high overall
efficiency and in reducing the heating of the capacitors.
Output Capacitors
The worst-case peak-to-peak inductor ripple current,
the allowable peak-to-peak output ripple voltage, and
the maximum deviation of the output voltage during
SEGMENT LOSS
PCONDUCTION = IRMS 2 × RDS(ON)
where IRMS ≈
VOUT
× ILOAD
VIN
PGATEDRIVE = VDD × (QG − QGD ) × fSW
PSWITCH = VIN × ILOAD × fSW ×
where IGATE =
POUTPUT =
(QGS2 + QGD )
IGATE
VDD
2 × (RDH _ + RGATE )
QOSS(HS) + QOSS(LS)
2
× VIN × fSW
step loads determine the capacitance and the ESR
requirements for the output capacitors. The output ripple can be approximated as the inductor current ripple
multiplied by the output capacitor’s ESR (RESR_OUT).
The peak-to-peak inductor current ripple is given by:
V
(1 − D)
∆IL = OUT
L × fSW
During a load step, the allowable deviation of the output
voltage during the fast transient load dictates the output
capacitance and ESR. The output capacitors supply the
load step until the controller responds with a greater duty
cycle. The response time (tRESPONSE) depends on the
closed-loop bandwidth of the regulator. The resistive
drop across the capacitor’s ESR and capacitor discharge
causes a voltage drop during a load step. Use a combination of SP polymer and ceramic capacitors for better
transient load and ripple/noise performance.
______________________________________________________________________________________
19
MAX15034
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Table 2. Low-Side MOSFET Losses
LOSS
DESCRIPTION
Conduction Loss
Losses associated with MOSFET on-time, IRMS
is a function of load current and duty cycle.
Gate Drive Loss
Losses associated with charging and
discharging the gate of the MOSFET every
cycle. There is no QGD charging involved in this
MOSFET due to the zero-voltage turn-on. The
charge involved is (QG - QGD).
SEGMENT LOSSES
PCONDUCTION = IRMS 2 × RDS(ON)
where IRMS ≈
VIN − VOUT
× ILOAD
VIN
PGATEDRIVE = VDD × (QG − QGD ) × fSW
Note: The gate drive losses are distributed between the drivers and the MOSFETs in the ratio of the gate driver’s resistance and the
MOSFET’s internal gate resistance.
Keep the maximum output-voltage deviation less than
or equal to the adaptive voltage-positioning window
(∆VOUT). During a load step, assume a 50% contribution each from the output capacitance discharge and
the voltage drop across the ESR (∆VOUT = ∆VESR_OUT
+ ∆VQ_OUT). Use the following equations to calculate
the required ESR and capacitance value:
RESR _ OUT =
COUT =
∆VESR _ OUT
ILOAD _ STEP
ILOAD _ STEP × tRESPONSE
∆VQ _ OUT
where I LOAD_STEP is the step in load current and
t RESPONSE is the response time of the controller.
Controller response time depends on the control-loop
bandwidth. COUT is C6 and C7 in Figure 6.
Current Limit
The MAX15034 incorporates two forward current-limit
protection mechanisms, average current limit and hiccup fault current limit, which accurately limit the output
current per phase. The average current-mode control
technique of the MAX15034 accurately limits the maximum average output current per phase. The
MAX15034 senses the voltage across either a sense
resistor or can implement lossless inductor sense,
sensing the voltage across the parasitic resistance of
the inductor (DCR). Use either mechanism to limit the
maximum inductor current.
20
The minimum average voltage, at which the voltage
across the current-sense resistor is clamped, is either
internally set to 20.4mV or is controlled by the voltage
at AVGLIMIT. The AVGLIMIT ground threshold of
550mV (typ) is the threshold above which the control of
the average current-limit voltage is transferred from the
internal 20.4mV (min) reference to the externally set
VAVGLIMIT. For using the internal average current-limit
value, short AVGLIMIT to AGND. The minimum (internally set) average current limit is set at:
ILIMIT(MIN) =
20.4mV
RSENSE
For example, the current-sense resistor:
RSENSE =
20.4mV
= 2.04mΩ
10A
for a maximum output current limit of 10A. A standard
value is 2mΩ. Also, adjust the value of the currentsense resistor to compensate for parasitics associated
with the PCB. Select a noninductive resistor with an
appropriate wattage rating.
The implementation is shown in Figure 8.
When sensing directly across the inductor, connect an
RC circuit directly across the shunt or inductor (see
Figure 9).
______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
MAX15034
LOUT
RSENSE
VOUT
LX_
MAX15034
CSP_
CSN_
Figure 8. Noninductive Resistive Sense
INDUCTOR
L
DCR
VOUT
LX_
R1
C1
MAX15034
CSP_
R2*
C3*
C2*
CSN_
*OPTIONAL.
Figure 9. Lossless Inductor Sense
Set the RC time constant to be 1.1 to 1.2 times the
inductor time constant (L/DCR). Select C1 to be in the
0.1µF to 0.47µF range, and then calculate R1 from:
R1[kΩ] =
1.2 × L[µH]
DCR[mΩ] × C1[µF]
In some applications, it may be useful to add a resistor
(R2 in Figure 9) in series with the CSN_ connection to
minimize input offset error. Set R2 equal to R1. It may
also prove useful to add capacitor C3 (Figure 9) in
parallel with R2 to aid in short-circuit recovery. Set C3
equal to C1. Finally, it may be helpful to add a 100pF
(C2) capacitor immediately across the CSP_ and CSN_
inputs to minimize high-frequency noise pick-up at the
IC in some applications.
For current-sense resistors that have a noticeable
inductance component, use lossless inductor sense
implementation (and design procedure). See Figure 10.
Table 3 highlights the tradeoffs of each current-sense
method.
Table 3. Current-Sense Configurations
CURRENT-SENSE
ACCURACY
INDUCTOR-SATURATION
PROTECTION
CURRENT-SENSE POWER
LOSS (EFFICIENCY)
Output Current-Sense Resistor
High
Allowed (highest accuracy)
RSENSE x IOUT2
Equivalent Inductor DC Resistance
Low
Allowed
No additional loss
METHOD
______________________________________________________________________________________
21
MAX15034
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
SENSE RESISTOR (INDUCTIVE)
LOUT
ESL
RSENSE
VOUT
LX_
R1
C1
MAX15034
CSP_
R2
C3
C2
CSN_
Figure 10. Inductive Sense Resistor
The MAX15034 provides precision average current-limit
programmability while using standard sense resistors
or shunts. Use the equation below to determine the
appropriate VAVGLIMIT external reference voltage at
AVGLIMIT:
(
)
VAVGLIMIT = 56 × RSENSE [mΩ] × ILOAD(MAX) [A] + 612.5mV
For example, assuming the desired average current
limit is 18A, and RSENSE = 2mΩ.
VAVGLIMIT = ( 2mΩ × 36 × 18 A ) + 612.5mV
= 1910mV = 1.91V
where RSENSE is determined from maximum load current, wattage rating, and circuit parasitics (see above)
and ILOAD(MAX) from circuit requirements. VAVGLIMIT is
the average current-limit reference voltage selected for
a desired ILOAD(MAX) and is set by a resistive voltagedivider from REG to AGND. See the Programming the
Average Current Limit section.
The second current-protection circuit is the hiccup fault
protection as explained in the Hiccup Fault Protection
section. The average current during a short at the output is given by:
IAVG(SHORT) = 0.0625 × ILOAD(MAX)
Programming the Average Current Limit
The MAX15034 average current-limit reference voltage
is set by connecting a resistor-divider network from
REG to AGND, the center node is connected to
AVGLIMIT. The resistive divider’s upper resistor, R1, is
connected between REG and the AVGLIMIT. The resistive divider’s lower resistor, R2, is connected between
the AVGLIMIT and AGND.
The resistor-divider values are determined by first,
choosing R2. To minimize reference noise select R2
such that (R1 + R2) < 100kΩ; a typical value is 10kΩ.
Next, determine R1 from:
⎛ VREG
⎞
R1 = R2 × ⎜
− 1⎟
⎝ VAVGLIMIT
⎠
⎛
⎞
5V
− 1⎟
= 10kΩ × ⎜
⎝ VAVGLIMT(MAX) [V] ⎠
From the example above, assuming VAVGLIMIT = 1.91V:
⎛ 5V
⎞
R1 = 10kΩ × ⎜
− 1 = 16.18kΩ
⎝ 1.91V ⎟⎠
A standard value for R1 is 16.2kΩ. Connect AVGLIMIT
to AGND for default current limit
⎛ 20.4mV ⎞
⎜⎝ R
⎟⎠ .
SENSE
22
______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
IREVERSE =
1.55 × 10−3
RSENSE
Output-Voltage Setting
The output voltage is set by the combination of resistors
R1, R2, and R F as described in the Voltage-Error
Amplifier section. First select a value for resistor R2. Then
calculate the value of R1 from the following equation:
R1 =
(VOUT(NL) − 0.6125)
0.6125
× R2
where VOUT(NL) is the voltage at no load. Then find the
value of RF from the following equation:
I
× RSENSE × 36 × R1
RF = OUT
∆VOUT
where ∆VOUT is the allowable drop in voltage from no
load to full load. RF is R8 and R9, R1 is R4 and R6, R2
is R5 and R7 in Figure 6.
1) The average current tracks the programmed current with a high degree of accuracy.
2) Slope compensation is not required, but there is a
limit to the loop gain at the switching frequency to
achieve stability.
3) Noise immunity is excellent.
4) The average current-mode method can be used to
sense and control the current in any circuit branch.
For stability of the current loop, the amplified inductorcurrent downslope at the negative input of the PWM
comparator (CPWM1 and CPWM2) must not exceed
the ramp slope at the comparator’s positive input. This
puts an upper limit on the current-error amplifier gain at
the switching frequency. The inductor current downslope is given by VOUT/L where L is the value of the
inductor (L1 and L2 in Figure 6) and VOUT is the output
voltage. The amplified inductor current downslope at
the negative input of the PWM comparator is given by:
∆VL VOUT
=
× RSENSE × 36 × gm × RCF
∆t
L
where RSENSE is the current-sense resistor (R1 and R2
in Figure 6) and gM x RCF is the gain of the current-error
amplifier (CEA_) at the switching frequency. The slope
of the ramp at the positive input of the PWM comparator
is 2V x fSW. Use the following equation to calculate the
maximum value of RCF (R14 or R15 in Figure 6).
Compensation
The MAX15034 uses an average current-mode control
scheme to regulate the output voltage (see Figure 2).
The main control loop consists of an inner current loop
and an outer voltage loop. The voltage error amplifier
(VEA1 and VEA2) provides the controlling voltage for
the current loop in each phase. The output inductor is
hidden inside the inner current loop. This simplifies the
design of the outer voltage control loop and also
improves the power-supply dynamics. The objective of
the inner current loop is to control the average inductor
current. The gain-bandwidth characteristic of the current loop can be tailored for optimum performance by
the compensation network at the output of the currenterror amplifier (CEA1 or CEA2). Compared with peak
current-mode control, the current-loop gain crossover
frequency, fC, can be made approximately the same,
but the gain at low frequencies is much higher. This
results in the following advantages over peak currentmode control.
RCF ≤
2 × fSW × L
VOUT × RSENSE × 36 × gm
(1)
The highest crossover frequency fCMAX is given by:
f
× VIN
fCMAX = SW
2π × VOUT
or alternatively:
f
× 2π × VOUT
fSW = CMAX
VIN
Equation (1) can now be rewritten as:
RCF =
π × fC × L
VIN × RS × 9 × gm
(2)
______________________________________________________________________________________
23
MAX15034
Reverse Current Limit
The MAX15034 limits the reverse current when the output capacitor voltage is higher than the preset output
voltage. Calculate the maximum reverse current limit
based on V CLMP_LO and the current-sense resistor
RSENSE.
MAX15034
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
In practical applications, pick the crossover frequency
(fC) in the range of:
fSW
f
< fC < SW
10
2
First calculate RCF in equation 2 above. Calculate CCF
so that:
10
CCF =
2 × π × fC × RCF
where CCF is C10 and C12 in Figure 6.
Calculate CCFF so that:
CCFF =
1
2 × π × fC × 10 × RCF
where CCFF is C11 and C13 in Figure 6.
Applications Information
Independent Turn-On and Turn-Off
The MAX15034 can be used to regulate two outputs
from one controller. Each of the two outputs can be
turned on and off independently of one another by controlling the enable input of each phase (EN1 and EN2).
A logic-low on each enable pin shuts down the
MOSFET drivers for that phase. When the voltage on the
enable pin exceeds 1.2V, the drivers are turned on and
the output can come up to regulation. This method of
turning on the outputs allows the MAX15034 to be used
for power sequencing.
PCB Layout Guidelines
Careful PCB layout is critical to achieve low losses, low
output noise, and clean and stable operation. This is
24
especially true for dual-phase converters where one
channel can affect the other. Use the following guidelines for PCB layout:
1) Place the VDD, REG, and the BST1 and BST2 bypass
capacitors close to the MAX15034.
2) Minimize all high-current switching loops.
3) Keep the power traces and load connections short.
This practice is essential for high efficiency. Use
thick copper PCBs (2oz or higher) to enhance efficiency and minimize trace inductance and resistance.
4) Run the current-sense lines CSP_ and CSN_ very
close to each other to minimize loop areas. Do not
cross these critical signal lines through power circuitry. Sense the current right at the pads of the
current-sense resistors.
5) Place the bank of output capacitors close to the
load.
6) Isolate the power components on the top side from
the analog components on the bottom side with a
ground plane in between.
7) Provide enough copper area around the switching
MOSFETs, inductors, and sense resistors to aid in
thermal dissipation and reducing resistance.
8) Distribute the power components evenly across the
top side for proper heat dissipation.
9) Keep AGND and PGND isolated and connect them
at one single point close to the IC. Do not connect
them together anywhere else.
10) Place all input bypass capacitors for each input as
close to each other as is practical.
______________________________________________________________________________________
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Chip Information
PROCESS: BiCMOS
TOP VIEW
CSN2 1
+
28 EN2
CSP2 2
27 BST2
EAOUT2 3
26 DH2
EAN2 4
25 LX2
CLP2 5
AVGLIMIT 6
24 DL2
MAX15034
RT/CLKIN 7
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
23 PGND
22 IN
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
21-0066
21-0108
90-0171
AGND 8
21 REG
28 TSSOP
U28+2
MODE 9
20 VDD
28 TSSOP-EP
U28E+4
CLP1 10
19 DL1
EAN1 11
18 LX1
EAOUT1 12
17 DH1
CSP1 13
CSN1 14
90-0146
16 BST1
*EXPOSED PAD
15 EN1
TSSOP
*CONNECT EXPOSED PAD TO GROUND PLANE.
MAX15034A DOES NOT HAVE AN EXPOSED PAD.
______________________________________________________________________________________
25
MAX15034
Pin Configuration
Revision History
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
0
7/08
Initial release
—
1
10/11
Updated Ordering Information.
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX15034
MAX15034
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications