MCZ5207SG CAT.No. 1H0100-1E MCZ5207SG APPLICATION NOTE Jan.2013 Ver1.0 LLC Current resonant bridge controller MCZ5207SG + + SHINDENGEN ELECTRIC MFG.CO.,LTD -1- Vo1 MCZ5207SG MCZ5207SG Application Note Cautions for Use Thank you for purchasing our products. This manual contains important information on the safe use of our products. Your safety is of the utmost importance to us. Please read these instructions carefully before using our products. The following symbols mean: ! ! ! Warning Improper use of the products can result in death, serious injury, or expensive damage to equipment. ! Caution Improper use of the products can result in minor injuries or damage to equipment. Warning Warning Although we are constantly making every effort to improve the quality and reliability of our products, there nevertheless remains a certain probability that the semiconductor products may occasionally fail or malfunction. Please take careful precautions against product failures or malfunctions to avoid any injuries, fire accidents or social loss by implementing safety designs such as redundancy designs, designs for fire spread prevention, and designs for preventing malfunctions. Our semiconductor products listed in this document are not designed or manufactured to be used in devices or systems requiring extremely high levels of quality and reliability, or the failure or malfunction of which may directly threaten human lives or cause injury. In the cases where the products are to be used in devices or systems for special applications or devices or systems for specialized applications shown below, always make sure to consult us in advance. Special Applications Transportation devices (automotive, marine, etc.), communication devices for core network, traffic signal devices, fire prevention/anticrime devices, various safety devices, medical devices, etc. Specialized Applications Nuclear power control systems, aircraft and aerospace devices, submarine relay devices, and systems for preserving life, etc. Even if it is not for a special or specialized application, when IC products are to be used for devices or systems that are desired to last for a long period under continuous operation, please make sure to consult us in advance. ! Caution ! Caution ! ! ! Caution Do not attempt under any conditions to repair or modify IC products by yourself. Doing so could result in electric shock, device breakage, fire, and malfunction. When an abnormal condition occurs, an excessive voltage or under voltage may be generated across the output terminals of the circuit. Install preventative measures (e.g. over-voltage protection, over-current protection) for the device by considering the possibility of a malfunction and/or breakage of a load in an abnormal condition. Do not switch on the circuit before confirming the proper connection and polarity of input and output terminals as an erroneous connection may cause breakage of the protection device or smoke/fire. Caution Do not use the circuit beyond the rated input voltage and install a protection device on the input rail to prevent smoke/fire that may be caused from an abnormal condition. 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Index SHINDENGEN ELECTRIC MFG.CO.,LTD -2- MCZ5207SG 1 : General description 1.1 : Features 4 1.2 : Internal block diagram 5 1.3 : Pin assignment 6 1.4 : Functions 6 1.5 : Typical circuit configuration 7 2 : Functional description 2.1: Operation mode 8 2.2: Supply block 8 2.2.1 : IC supply (Vc1) 2.2.2 : Gate driver supply (Vc2) 2.2.3 : High side gate driver supply (VB) 2.3: Functional terminal detail 9-17 2.3.1 : Gate driver output (VGH / VGL) 2.3.2 : Oscilator and Feedback (FB) 2.3.3 : Brown-out protection (Vsen) 2.3.4 : Current peak limiting fast OCP(CS1) 2.3.5 : Fequency clamped slow OLP (CS2/CSO) 2.3.6 : Capacitive mode protection (CS2) 2.3.7 : Safe startup 2.3.8 : Soft start (SST) 2.3.9 : Timer delayed latching protection (SST) 2.3.10 : High side floating VDD (VB) 2.3.11 : Active Stdby (AS) 2.3.12 : Burst mode operation (AS) 2.3.13 : Thermal shutdown 2.4: Thermal shut down protection 17 3 : Selecting components value 3.1: Brown out protection (Vsen) 18 3.2: Oscillator / Feedback (FB) 19 3.3: Soft start / delayed protection timer (SST) 20 3.4: OCP1/OCP2 and anti-capacitive mode protection 20-21 4 : Circuit diagram 4.1: DCDC Configuration example 22 5 : Dimensions 23 5.1: SOP16 (MCZ5207SG) SHINDENGEN ELECTRIC MFG.CO.,LTD -3- MCZ5207SG 1 General description MCZ5207SG is an advanced symmetric LLC current resonant mode controller for bridge converter. Built-in high voltage direct gate drivers, control circuit and optimized protections allow simplified and space/cost-saving design of power supplies for : Large screen flat panel TVs (PDP / LCD ) Document equipment High power adapter CVCC high power LED lighting High power standard PSU High power Audio Amp 1.1 Features 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Robust 600V direct gate driver. Optimized protections (OCP/burst/Timer delayed latch/Thermal) for LLC converter. Bidirectional resonant current sensing. Bidirectional capacitive mode protection. Vcc supply up to 35V with 12.9V/8.7V UVLO . Built-in voltage regulator of 10.5V for gate driver. Independent UVLO for High side/Low side Gate drive VDD. Safe soft starting function to prevent MOSFET didt stress. Brown Out protection Resonant peak current stabilized frequency clamp OLP. NEW Active stdby function to improve light load efficiency. NEW Less than 100mW no load consumption is possible with burst mode operation. NEW Latching protection with external signal is possible. NEW SHINDENGEN ELECTRIC MFG.CO.,LTD -4- MCZ5207SG 1.2 Block diagram （SOP16） 1 16 Latch Reset AS OFF Vc1 st/sp Internal Vref TSD Vc2 OFF Dropper AS ON + - 2 ON/OFF Vc2 st/sp SS-Reset Soft Start charge/ discharge Counter reset 3 R S S Vss Burst ON/OFF Vsen ON/OFF Timer Reset High Voltage Driver 15 SS st/sp Counter x2 times Q Latch Stop 14 LLC STOP SST Latch 4 13 AS Mode 5 OCP Counter 8 times Timer Latch AS Lin OSC Fixed DT Control Logic FB discharge 6 Level Shift 12 11 CSO charge 7 10 OCP1 OCP2 didt1 8 9 Fig 1 . MCZ5207SG internal block diagram SHINDENGEN ELECTRIC MFG.CO.,LTD -5- MCZ5207SG 1.3 Pin assignment 1.Vc1 16.VGH 2.Vsen 15.VS 3.SST 14.VB 4.AS 13.NC 5.FB 12.NC 6.CSO 11.VGL 7.CS1 10.Vc2 8.CS2 9.GND Fig 2 . MCZ5207SG pin assignment 1.4 Functions Pin number symbol description 1 Vc1 2 Vsen Bus Voltage sensing input For brown-out protection and on/off with external signal 3 SST Soft Start and Timer delayed latching protection timing capacitor connecting terminal Latching protection with external signal is supported. 4 AS 5 FB 6 CSO Frequency clamp Current Sensing comparator Output Averaged OLP response is determined. 7 CS1 Current Sensing input for shorted load protection Peak current limiting sensing threshold voltage is +/- 0.5V. 8 CS2 Current Sensing input for frequency clamp and capacitive mode protection Protection point can be adjusted independently of CS1. +/- 0.5V threshold for frequency clamp and +/- 0.1V for anti capacitive mode protection. 9 GND 10 Vc2 11 VGL 12-13 NC 14 VB 15 VS 16 VGH IC supply voltage VCC input up to 35V UVLO(on) = 12.9V / UVLO(off) = 8.7V. Active Stdby / burst operation signal input Feed Back signal input / timing capacitor and resistor connecting terminal F(min) / f(ss) / initial dead time is determined IC Ground terminal Stabilized VDD output for gate drive 10.2V Gate drive output for Low side switch Not connected Bootstrapped floating VDD input for high side gate driver Floating driver reference voltage (= source terminal of high side switch) Gate drive output for High side switch SHINDENGEN ELECTRIC MFG.CO.,LTD -6- MCZ5207SG 1.5 Applicable circuit configuration Most simple SEPP(Single Ended Push-Pull) Input ripple current reduction (Half Bridge) For high power application (Full Bridge) SHINDENGEN ELECTRIC MFG.CO.,LTD -7- MCZ5207SG 2 Functional description 2.1 Operation mode MCZ5207SG operation timing chart is shown in 2.2 and 2.3. Method of selecting components value is described in article 3. MCZ5207SG has three operation mode : 1) Normal operation mode 2) Active stdby mode 3) Burst operation mode Normal operation is assumed in this document unless otherwise specified. Active stdby mode and burst mode operation details are described in 2.3.11 and 2.3.12. 2.2 Supply voltage 2.2.1 IC main supply (Vc1) Vc1 UVLO threshold is 12.9V (start) and 8.7V (stop). When Vc1 terminal voltage reaches to Vc1(start) 12.9V, Vc2 output is enabled and IC operation starts. When Vc1 terminal voltage decreases to less than Vc1(stop) 8.7V, Vc2 output is disabled and IC operation stops. Latching protection is initialized when Vc1 terminal voltage decreases to less than Vc1(latch reset) 8.3V. 2.2.2 Stabilized gate drive VDD (Vc2) Vc2 terminal is an output of internal 10.2V dropper for the gate driver. Vc2 output is also a voltage source of boot strapping high side VDD. Filtering capacitor should be placed close to Vc2 - GND. Please be noticed that gate driving ripple current flows in this Vc2 filtering capacitor, so take care of capacitor ripple current rating. Vc2 output is enabled when Vc1 reaches to Vc1(start) 12.9V. Internal oscillator starts operation when Vc2 terminal voltage reaches to Vc2(start) 9.6V and Gate drive output is enabled. Refer to article 2.3 to see gate drive output timing. 2.2.3 Boot strapped High side floating VDD (VB) VB is the input from Vc2 voltage source through boot strapping diode. Please place boot strap filtering capacitor close to VB – VS terminal. 600V fast and soft recovery FRD like D1NK60 (axial) or D1FK60 (SMD) is recommended as a boot strapping diode, snappy recovery type should not be chosen High side UVLO is implemented watching VB – VS terminal voltage. VB-VS(start) is 7.3V and VBVS(stop) is 5.1V. Undesired linear operation can be prevented by this independent high side VDD UVLO. SHINDENGEN ELECTRIC MFG.CO.,LTD -8- MCZ5207SG 2.3 Functional terminal detail 2.3.1 Gate drive output (VGL and VGH) Gate driver output terminals are VGL (Low side MOSFET) and VGH (High side MOSFET) with 0.18Apk sourcing and 0.4Apk sinking capability. Generic gate drive connection is shown in Fig.3(A). Large Qg gate can be handled with additional sinking diode shown in Fig.3(B),(C). In this case snappy recovery diode is not recommended. Soft recovery fast switching or SBD is recommended like D1NS4 (40V axial SBD) or M1FM3 (30V SMD SBD). Fig. 3 . Gate drive circuits 2.3.2 Oscillator (FB) The timing of gate drive pulse VGL and VGH is determined by charging and discharging time period of timing capacitor Ct (connected between FB and GND). Gate output is enabled during Ct discharging period. VGL and VGH are alternately outputted to drive each gate of MOSFETs. During Ct charging period, both VGL and VGH are simultaneously disabled to prevent shoot through of MOSFETs, this time period is known as Dead time (DT),. DT is depend on Ct and Rt value. Please refer to electric characteristics charts Fig.4 . FBL – VGL/VGH timing SHINDENGEN ELECTRIC MFG.CO.,LTD -9- MCZ5207SG Operating frequency is varied by controlling Ct discharging current. (Fig.5) Dead time expands according to operating frequency increase, thus ZVS (Zero Voltage Switching) operation can be easily achieved in wide input/output range and various resonant condition. Minimum operating frequency (fmin) is determined by timing capacitor Ct and timing resistor Rt. Maximum operating frequency (fmax) is determined by Ct ,Rt and Rfmax connected in series to FB control loop. Less than 500kHz is recommended in continuous operation. Soft starting frequency (fss) is determined by Ct value, fss and fmax is independent so undesired frequency increase can be avoided under heavy CCM LLC operation. f requency vs DT freq uency vs d uty 700 60 FB=2200pF FB=1800pF FB=1500pF FB=1000pF FB=820pF FB=470pF d uty [%] 50 45 40 FB=2200pF FB=1800pF FB=1500pF FB=1000pF FB=820pF FB=470pF 600 DT [ns ] 55 35 30 500 400 300 25 200 20 0 100 200 300 400 500 600 0 100 200 300 400 500 600 f requency [k Hz] f requency [k H z] Fig. 5 . Gate output duty/dead time vs frequency 2.3.3 Brown-out protection (Vsen) Vsen terminal monitors the input bus voltage and determines Csst discharge ON/OFF according to Vsen terminal voltage. This input UVLO function prevents excessive resonant rush current flow and capacitive mode operation under various input brown-out condition. Timing chart of Vsen brown-out protection is shown in Fig. 6 Under input bus voltage increasing condition , Csst starts to be charged when Vsen terminal voltage reaches to Vsen1(ss-reset) 3.55V and Gate output is enabled when SST terminal voltage reaches to Vss(st) 0.6V. Operating frequency decreases according to SST terminal voltage increases. And under input bus voltage decreasing condition, Csst starts to be discharged when Vsen terminal voltage decreases to Vsen2(ss-reset) 3.25V. Operating frequency increases gradually according to SST terminal voltage decreases and Gate output is disabled when SST terminal voltage reaches to less than Vss(sp) 0.5V. Vsen brownout threshold voltage is switched automatically according to AS terminal voltage status. Normal operation (AS OFF) AS operation mode (AS ON) Burst operation mode : Vsen ON 3.55V / Vsen OFF 3.25V : Vsen ON 1.0V / Vsen OFF 0.9V : Vsen ON 1.0V / Vsen OFF 0.9V 3.5V 3.2V Vsen 1.0V 0.9V Vc1 SST 12.9V 0.6V 0.5V 0.5V FB VGH VGL AS Fig. 6 . Brown-out protection timing SHINDENGEN ELECTRIC MFG.CO.,LTD - 10 - 0.6V MCZ5207SG 2.3.4 Dynamic peak current limiting OCP (CS1) Shorted load protection (OCP1, hereinafter) is a fast response cycle by cycle peak current limiter. When CS1 terminal voltage reached to CS1 threshold ( +/- 0.5V ), gate drive output is disabled instantaneously and Ct and also Csst starts to be charged . 0.5V threshold is low enough so sensing loss is not high even when using current sensing resistor method. Fig. 7 shows the timing charts of OCP1 operation and Csst charging detail is described in article 2.3.8. LEB is enabled during FB(top) 4.65V to 4.4V time period. So even heavy non-ZVS surge current cannot trigger OCP1. From OCP1 detection to Ct charging has 200nsec time delay due to internal filter. FBL(Top) OCP blanking period OCP internal filter delay blanking threshold voltage 4.4 V FBL(Bottom) +0.5V CS1 0V -0.5V VGH VGL Fig. 7 OCP1 operation timing 2.3.5 Frequency clamped averaging OLP (CS2 and CSO) The MCZ5207SG has frequency clamped Over Load Protection (OCP2, hereinafter). When CS2 terminal voltage reaches to +/-0.5V, CSO starts to be charged and operating frequency increases according to CSO terminal voltage increases. Operating frequency and CSO terminal voltage is shown in Fig. 8 Please be noticed that OCP2 operating point is independent from OCP1, so desired operating point can be adjusted. Fig.8 Operating frequency vs CSO terminal voltage SHINDENGEN ELECTRIC MFG.CO.,LTD - 11 - Fig. 9 CSO terminal MCZ5207SG 2.3.6 Anti-Capacitive mode protection (CS2) The MCZ5207SG adopts anti-capacitive mode protection to prevent damgerous MOSFET body diode di/dtoperation. When CS2 terminal voltage crosses Vdi/dt(+/-) +/- 0.1V before expected gate turn off , gate output is instantaneously disabled. (shown in Fig.10) During high side MOSFET ON period, high side gate turns off and Ct starts charged immediately when CS2 terminal voltage reaches to +0.1V in negative direction.And during low side MOSFET ON period, low side gate turns off and Ct starts to be charged when CS2 turminal voltage reaches to -0.1V in possitive direction. To prevent malfunction caused by switching surge voltage , capacitive mode protection is disabled during VFB > VFB(msk) 4.4V . Even if CS2 terminal voltage crosses this threshold during this time period, anti-capacitive mode protection does not work. Timer delayed latching protection is enabled only when LLC is operating in AS mode. - Normal and burst mode : Csst will not be charged in anti-capacitive mode protection - AS mode : Csst will be charged during anti-capacitive mode protection operates. This anti- capacitive mode protection results in LLC operating always in above ZVS region, so feedback - control turnaround never occurs. FB(Top) Blanking period delay time 4.4V FB(Bottom) +0.06V CSL 0V -0.06V VGH VGL Fig. 10 . Anti-capacitive mode protection timing 2.3.7 Safe-startup protection (Tss(3)) The MCZ5207SG has another di/dt protection at startup period to prevent too fast turn-off before body diode conduction period ends. nd On 2 VGL output period, VFB (bottom) threshold voltage is switched to lower value and results in increase of ON time period . Timing chart is shown in Fig.11. SHINDENGEN ELECTRIC MFG.CO.,LTD - 12 - MCZ5207SG VFB(Top) VFB(Bottom) Vth (Tss3) VGH VGL IDH IDL 1st bootstrap charging current Fig. 11 Tss(3) operation timing chart 2.3.8 Soft start (SST) During starting period , operating frequency decreases from soft start frequency (fss) to stabilized frequency proportionally to SST terminal voltage to prevent excessive resonant current or output inrush current and capacitive mode operation. Csst starts to be charged under two conditions as below : 1. 2. Vc1 > Vc1(start) 12.9V AND Vsen terminal voltage > Vsen1(ss-reset) or Vsen3(ss-reset) Oscillator starts operation at Vsst = 0.6V and operating frequency is stabilized before Vsst reaches to Vss(open) 2.1V. Fig.12 shows frequency and Vsst characteristics . V S S T vs fre qu e n c y 500 Ct=1500pF Ct=1200pF Ct=1000pF Ct=820pF 450 fr e qu e n c y [ kH z] 400 350 300 250 200 150 100 50 0 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 VSST [ V ] Fig. 12 Operation frequency and SST terminal voltage 2.3.9 Timer delayed latching protection (SST) Csst also functions as latching protection timing capacitor. SST terminal capacitor Csst starts to be charged in two condition as following: 1. OCP1 or OCP2 operates continuously 2. Anti-capacitive mode protection operates in AS mode. OR When Csst is charged continuously and SST terminal voltage reaches to Vtimer(set) 3.5V, long interval intermittent protection starts. After specified time period, normal operation restarts when abnormal condition was removed. If abnormal condition has not been removed, IC enters into latched off mode after second intermittent operation finished. SHINDENGEN ELECTRIC MFG.CO.,LTD - 13 - MCZ5207SG To initialize latching status, restart Vc1 to Vc1<8.3V. Protection timing chart is shown in Fig.13. Csst charging current is depend on CSO terminal voltage during continuous OCP2 operation. Table 1. Csst charging current Protection status Csst charging current 40uA 1.9uA 40uA 40uA OCP1 1.0V < Vcso < 1.75V Vcso 1.75V Anti-capacitive (during AS mode) OCP2 Internal latching counter is initialized in two conditions as following: 1) Vsst decreases to 2.1V ( recovered to normal operation ) 2) Csst discharging condition (Vc1 ON/OFF, Vsen on/off) Latching counter initialization helps to avoid undesirable latching. When abnormal condition is counted twice, IC enters into latched stop mode. Vc1 Vc1(start) 12.9V Vc1(stop) 8.7V Shorted load condition Short time over load MOSFET Idrain OCP operates Abnormal status signal (IC internal） OCP operates Vtimer1 OCP operates 3.5V 2.1V SST 1.5V 0.6V Vtimer2 0.35V Fig. 13 Csst timing chart 2.3.10 Boot strapping circuit High side floating VDD (VB-VS) capacitor is charged during conduction period of low side MOSFET as shown in Fig.14. VB – VS voltage is simply equals to (Vc2 – Vf of Dboot). Although very stable operation is possible due to stabilized Vc2 voltage, if huge negative surge voltage superimposed to VB, please add zener diode clamp of 15V to avoid high side logic malfunction. This surge voltage is caused by parasitic inductance in main switching loop and huge turn off current . SHINDENGEN ELECTRIC MFG.CO.,LTD - 14 - MCZ5207SG Cboot 0.1 uF 16V Np Dboot D1NK60 D1FK60 VGH VS VB VGL Vc2 PGND MCZ5207SG Fig. 14 Boot Strapping circuit SHINDENGEN ELECTRIC MFG.CO.,LTD - 15 - MCZ5207SG 2.3.11 Active stdby asymmetric operation (AS) The MCZ5207SG has asymmetric operation mode called Active Standby Mode to improve light load efficiency. When AS terminal voltage less than Vas(on) 0.8V, operation enters into asymmetric operation mode. After entering in AS mode, operation will return to normal symmetric operation mode when AS terminal voltage reaches to more than Vas(off) 1.0V. To avoid undesirable AS mode operation, add 1nF – 10nF closed to AS terminal. (Even when AS function is not used, add filtering capacitor .) AS terminal open voltage is 2.5V. Circuit configuration is shown in Fig. 15. Fig. 15 AS signal configuration example When AS signal is not applied (Vas(open) 2.5V), VGH and VGL output is symmetrically 50% duty cycle, and if AS terminal is pulled down externally to less than 2.2V, Ct charging threshold of low side MOSFET starts decreasing. This threshold decreasing is proportional to AS terminal voltage and finally reaches to bottom value of threshold when AS terminal voltage reaches to 1.0V. Decreasing of Ct discharging threshold results in VGL pulse width increasing. Maximum duty unbalance is 1:2 (VGH : VGL). Fig. 16 Asymmetric Gate output example When operation is switched to AS mode, - Vsen threshold (SS-Reset) is switched from 3.55V/3.25V to 1.0V/0.9V. - Csst charging enabled if anti-capacitive protection operates. SHINDENGEN ELECTRIC MFG.CO.,LTD - 16 - MCZ5207SG 2.3.12 Burst mode operation (AS) BURST mode operation starts when more than 4.5V external voltage is applied to AS terminal. Csst is discharged to 0.5V that results in gate output disabled. And when AS terminal voltage decreases to 4.0V , Csst starts to be charged and starting cycle begins. During burst mode operation, Csst charging current is switched from 30uA to 60uA to shorten starting time period. Also Vsen threshold voltage is switched to 1.0V(on) / 0.9V(off) preparing to PFC stopped LLC operation. Operation will recover to normal continuous operation when AS terminal voltage decreases to 3.0V or less. Hi BURST signal Lo Vsen Vo(reg) V output Vsst 0.6V 0.5V 0V 4.5V 4.0V 3.0V 2.1V VAS VGL/VGH operation mode Vsen threshold Symmetric Asymmetric Symmetric Asymmetric Symmetric 3.5/3.2V 1.0/0.9V 3.5/3.2V 1.0/0.9V 3.5/3.2V SST charge up Fig. 17 Burst mode operation timing Fig. 18 BURST w/external signal configuration example 2.4 Thermal shut down protection (TSD) The MCZ5207SG implements Thermal Shut Down protection. Threshold temperature is TSD 140C min. with 40C hysteresis. During TSD mode, IC operation entirely stops. SHINDENGEN ELECTRIC MFG.CO.,LTD - 17 - MCZ5207SG Selecting components value 3.1 Input Brown out protection (Vsen) Vsen SS reset threshold voltage is 3.55V/3.25V. (AS mode OFF) 1.0V/0.9V. (AS mode ON) Vsen terminal sink current is less than 0.2uA,so 20uA or more sensing bias current is recommended not to be affected by the sink current. Connect a capacitor of 1000 to 10000pF between Vsen and GND for filtering. Vbulk input RvsenseH Low side resistor, RvsenseL(init) is obtained from formula (1). Correct value of Vbulkreset threshold is obtained from formula (2) using actual value of RvsenseL. In AS mode operation, use formula (3). R VsenceL (init) SS Reset RvsenseL 1000pF~ 10000pF Vc1 Vc1& Vc2 UVLO + 3 AS OFF 3.55V/3.25V AS ON Burst ON 1.0V/0.9V Vbulkreset Internal Vref 5V 3.25 R VsenseH Vbulkreset - 3.25 R VsenseH R VsenseL 3.25 R VsenseL Vbulkreset (AS ON) AS pin low : AS ON Fig. 19 Vsen internal block SHINDENGEN ELECTRIC MFG.CO.,LTD - 18 - ･･･（1） ･･･（2） R VsenseH R VsenseL 0.9 ･･･（3） R VsenseL MCZ5207SG 3.2 Oscillator / Feedback (FB) Operating frequency can be controlled by pulling current from FB terminal. Ct , Rt and Rfb connected to FB terminal determine minimum frequency (fmin),maximum frequency (fmax) , starting frequency (fss) and dead time (DT). 3.2.1 dead time and soft start frequency (Ct ) Dead time and soft start frequency fss are determined by Ct capacitance. Select Ct capacitance from characteristic specification sheet. Capacitance value of Ct of 470pF to 2200pF is recommended due to the relation with dead time. 3.2.2 Minimum frequency fmin (Rt resistance) Minimum frequency fmin is determined by Rt value. (Connect between FB and GND.) Relation between Rt resistance and frequency is shown in characteristic specification sheet. The estimated value of fmin is obtained from formula (4) to (6). tcharge is a dead time and tdischarge is ON time period of VGL/VGH. Calculated value is an estimated value including small error due to comparator delay time of around 100nsec. (VFBL(bottom) : 3.5V , VFBL(top) : 4.65V ) tch arg e Rt Ct VFB(top ) 3 Rt 7.0 10 VFB( top ) tdisch arg e Rt Ct ln f min VFB( bottom ) VFB(top ) Rt Ct VFB(bottom ) Rt 7.0 10 3 VFB(bottom ) ---- (4) ---- (5) 1 ---- (6) 2 t ch arg e t disch arg e 3.2.3 Maximum frequency fmax (FB resistor) Maximum frequency fmax is determined Rt and Rfb value. Check the characteristic specification sheet and determine the maximum frequency. SHINDENGEN ELECTRIC MFG.CO.,LTD - 19 - MCZ5207SG 3.3 Soft start / Timer delayed protection (SST) Soft start charging current Iss(charge) is 30uA. When SST voltage rises to 0.6V, gate output starts and timer charging is enabled when SST voltage rises to 1.5V. Soft starting time tss is a time period in which SST voltage rises from 0.6V to 1.5V. tss is obtained from formula (7). Operating frequency and tss 0.9 Css 30 10 6 ・・・(7) Timer charging current Itimer(charge)1 is 40uA and output disable threshold voltage is 3.5V. Thus, Timer charging time ttimer is obtained from formula (8). ttimer 1.4 Css 40 10 6 ・・・(8) Timer charging current is different when OCP2 is operating. If CSO terminal voltage is less than 1.75V, charging current Itimer(charge)2 is 1.9uA,so time period to operation stop (VSST=3.5V) Ttimer is obtained from formula (9). ttimer 1.4 Css 1.9 10 6 ・・・(9) If CSO terminal voltage is grater than1.75V, charging current Itimer(charge)3 = 40uA ,so time period to operation stoop Ttimer is obtained from formula (8). Csst discharging current Itimer(discharge) is 6.5uA and operation restarts when SST terminal voltage decreases to less than Vtimer(reset) 0.35V . So gate output disabling time period is obtained from formula (10). t timer ( dis ) 3.15 C ss 6.5 10 6 ・・・(10) 3.4 OCP1/OCP2 and anti-capacitive mode protection (CS1/CS2) Current sensing connection example is shown in Fig.20 Type (a) is CS1/2 independent sensing and (b) shows CS1/2 common sensing connection. Generally OCP2 operating point is lower than OCP1’s . In this condition OCP2 stabilizes LLC operating frequency in transient over load / peak load condition and OCP1 finally halts entire LLC operation in shorted load condition. Current sensing resistor Rocpdet is calculated from desired OCP threshold Ipk using formula (11). When the connection is assumed as type(a) , tentative value of RocpL(init) is obtained from formula(12) and correct value of resonant current peak Ipk(ACT)is calculated from formula(13) using actual value of RocpL. Considering CS1/2 terminal sourcing current 95uA, 10 – 47 ohm is recommended for RocpH. CS2 terminal sensing voltage is also used for ant-capacitive mode protection. CS2 operating point should be determined considering +/-0.10V capacitive mode protection threshold. Connect filtering capacitor of 1nF to 10nF close to CS1 or CS2 terminal to suppress OCP malfunction. Frequency stabilized OLP (OCP2) realizes smooth constant power output characteristics and resonant current envelope, they are very suitable for Audio amp or huge peak current flowing application. Actual example of output characteristics is shown in Fig.21. Please be noticed that setting CS2 operating point to too high level causes undesirable anticapacitive mode protecting operation in normal load condition. SHINDENGEN ELECTRIC MFG.CO.,LTD - 20 - Cr Cr MCZ5207SG (a) CS1/2 independent sensing (b) CS1/2 common sensing Fig. 20 CS1 and CS2 current sensing circuit R ocp det(init ) R ocpL (1 / 2) Ipk ( ACT ) 0.5 Ipk [ohm] ・・・(11) 0.5 R ocpH(1 / 2) [ohm] ・・・ (12) Ipk R ocp det 0.5 R ocpH(1 / 2) R ocpL (1 / 2) R ocpL (1 / 2 ) R ocp det 0.5 [ A ] ・・・ (13) V out output V/I characteristics I out Fig. 21 OLP characteristics example SHINDENGEN ELECTRIC MFG.CO.,LTD - 21 - MCZ5207SG 4 Circuit diagram 4.1 Configuration example of DC to DC dual output LLC SHINDENGEN ELECTRIC MFG.CO.,LTD - 22 - MCZ5207SG 5 Dimension 5.1 SOP16 (MCZ5207SG) SHINDENGEN ELECTRIC MFG.CO.,LTD - 23 - MCZ5207SG Notes: SHINDENGEN ELECTRIC MFG.CO.,LTD - 24 -