A42L2604 Series Preliminary 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE Document Title 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE Revision History History Issue Date Remark 0.0 Initial issue June 13, 2001 Preliminary 0.1 Modify symbol HE dimensions in TSOP 24L package information July 10, 2001 0.2 Add -45 grade and modify the AC, DC data November 30, 2001 0.3 Modify DC data and all parts guarantee self-refresh mode Rev. No. Add -U type spec. PRELIMINARY (June, 2002, Version 0.3) June 10, 2002 AMIC Technology, Inc. A42L2604 Series Preliminary 4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE Features n Organization: 4,194,304 words X 4 bits n Part Identification - A42L2604 (2K Ref.) n Single 3.3V power supply/built-in VBB generator n Low power consumption - Operating: 80mA (-45 max) - Standby: 1.0mA (TTL), 1.5mA (CMOS), 350µA (Self-refresh current) n High speed - 45/50 ns RAS access time - 20/22 ns column address access time - 12/13 ns CAS access time - 18/20 ns EDO Page Mode Cycle Time n Industrial operating temperature range: -40°C to +85°C for -U n Fast Page Mode with Extended Data Out n 2K Refresh Cycle in 32ms n Read-modify-write, RAS -only, CAS -before- RAS , Hidden refresh capability n TTL-compatible, three-state I/O n JEDEC standard packages - 300mil, 24/26-pin SOJ - 300mil, 24/26-pin TSOP type II package General Description cycle with a feature called Extended Data Out (EDO). This allow random access of up to 2048(2K Ref.) words within a row at a 56/50 MHz EDO cycle, making the A42L2604 ideally suited for graphics, digital signal processing and high performance computing systems. The A42L2604 is a new generation randomly accessed memory for graphics, organized in a 4,194,304-word by 4-bit configuration. This product can execute Write and Read operation via CAS pin. The A42L2604 offers an accelerated Fast Page Mode Pin Configuration n SOJ n TSOP Pin Descriptions VCC 1 26 VSS VCC 1 26 VSS I/O 0 2 25 I/O 3 I/O 0 2 25 I/O 3 I/O 1 3 24 I/O 2 I/O 1 3 24 I/O 2 5 23 CAS WE 4 22 OE RAS 5 NC 6 A10 8 A0 9 A1 A2 21 A9 NC 6 19 A8 A10 8 18 A7 A0 9 10 17 A6 A1 11 16 A5 A2 A3 12 15 A4 VCC 13 14 VSS PRELIMINARY 23 CAS 22 OE 21 A9 19 A8 18 A7 10 17 A6 11 16 A5 A3 12 15 A4 VCC 13 14 VSS A42L2604V 4 A42L2604S WE RAS (June, 2002, Version 0.3) Symbol 1 Description A0 – A10 Address Inputs (2K product) I/O0 - I/O3 Data Input/Output RAS Row Address Strobe CAS Column Address Strobe WE Write Enable OE Output Enable VCC 3.3V Power Supply VSS Ground NC No Connection AMIC Technology, Inc. A42L2604 Series Selection Guide Symbol Description -45 -50 Unit tRAC Maximum RAS Access Time 45 50 ns tAA Maximum Column Address Access Time 20 22 ns tCAC Maximum CAS Access Time 12 13 ns tOEA Maximum Output Enable ( OE ) Access Time 12 13 ns tRC Minimum Read or Write Cycle Time 76 84 ns tPC Minimum EDO Cycle Time 18 20 ns Functional Description The A42L2604 reads and writes data by multiplexing an 22-bit address into a 11-bit(2K) row and column address. RAS and CAS are used to strobe the row address and the column address, respectively. valid as long as RAS and OE are low, and WE is high; this is the only characteristic which differentiates Extended Data Out operation from a standard Read or Fast Page Read. A Read cycle is performed by holding the WE signal high during RAS / CAS operation. A Write cycle is executed by A memory cycle is terminated by returning both RAS and CAS high. Memory cell data will retain its correct state by maintaining power and accessing all 2048(2K) combinations of the 11-bit(2K) row addresses, regardless of sequence, at least once every 32ms through any RAS cycle (Read, Write) or RAS Refresh cycle ( RAS -only, CBR, or Hidden). The CBR Refresh cycle automatically controls the row addresses by invoking the refresh counter and controller. holding the WE signal low during RAS / CAS operation; the input data is latched by the falling edge of WE or CAS , whichever occurs later. The data inputs and outputs are routed through 4 common I/O pins, with RAS , CAS , WE and OE controlling the in direction. EDO Page Mode operation all 2048(2K) columns within a selected row to be randomly accessed at a high data rate. A EDO Page Mode cycle is initiated with a row address latched by RAS followed by a column address latched by CAS . While holding RAS low, CAS can be toggled to strobe changing column addresses, thus achieving shorter cycle times. The A42L2604 offers an accelerated Fast Page Mode cycle through a feature called Extended Data Out, which keeps the output drivers on during the CAS precharge time (tcp). Since data can be output after CAS goes high, the user is not required to wait for valid data to appear before starting the next access cycle. Data-out will remain PRELIMINARY (June, 2002, Version 0.3) Power-On The initial application of the VCC supply requires a 200 µs wait followed by a minimum of any eight initialization cycles containing a RAS clock. During Power-On, the VCC current is dependent on the input levels of RAS and CAS . It is recommended that RAS and CAS track with VCC or be held at a valid VIH during Power-On to avoid current surges. 2 AMIC Technology, Inc. A42L2604 Series Block Diagram RAS CAS Vcc Control Clocks VBB Generator Vss WE Refresh Timer Row Decoder Refresh control Refresh Counter A0~A10 A0~A10 Data out Buffer I/O0 to I/O3 OE Row Address Buffer Col. Address Buffer Recommended Operating Conditions Symbol Memory Array 4,194,304 X 4 Cells Sense Amps & I/O Data in Buffer Description Column Decoder (Ta = 0°C to +70°C or -40°C to +85°C) Min. Typ. Max. Unit 3.0 3.3 3.6 V VCC Power Supply VSS Input High Voltage 0 0 0 V VIH Input High Voltage 2.0 - VCC + 0.3 V VIL Input Low Voltage -0.5 - 0.8 V PRELIMINARY (June, 2002, Version 0.3) 3 AMIC Technology, Inc. A42L2604 Series Truth Table Function RAS CAS Standby H Read: Word L Read Write: Word (Early) Write (Early) Address I/Os WE OE H X X X High-Z L H L Row/Col. Data Out L L H L Row/Col. Data Out L L L X Row/Col. Data In L L L X Row/Col. Data In Read-Write L L H→L L→H Row/Col. Data Out → Data In EDO-Page-Mode Read: Hi-Z -First cycle -Subsequent Cycles L L H→L H H H→L H→L Row/Col. Col. Data Out Data Out EDO-Page-Mode Write (Early) -First cycle -Subsequent Cycles L L H→L H→L L L X X Row/Col. Col. Data In Data In EDO-Page-Mode Read-Write -First cycle -Subsequent Cycles L L H→L H→L L→H H→L H→L L→H Row/Col. Col. Data Out → Data In L→H→L L H L Row/Col. Data Out L→H→L L L X Row/Col. Data In → High-Z L H X X Row High-Z CBR Refresh H→L L X X X High-Z Self Refresh H→L L H X X High-Z Hidden Refresh Read Hidden Refresh Write RAS -Only Refresh PRELIMINARY (June, 2002, Version 0.3) H→L 4 Data Out → Data In AMIC Technology, Inc. A42L2604 Series Absolute Maximum Ratings* *Comments Input Voltage (Vin) . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V Output Voltage (Vout) . . . . . . . . . . . . . . . . -0.5V to +4.6V Power Supply Voltage (VCC) . . . . . . . . . . . -0.5V to +4.6V Operating Temperature (TOPR) . . . . . . . . . . 0°C to +70°C Storage Temperature (TSTG) . . . . . . . . . -55°C to +150°C Soldering Temperature X Time (TSOLDER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C X 10sec Power Dissipation (PD) . . . . . . . . . . . . . . . . . . . . . . . . 1W Short Circuit Output Current (Iout) . . . . . . . . . . . . . 50mA Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of these specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC Electrical Characteristics (VCC = 3.3V ± 0.3V, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C) -45 Symbol -50 Parameter Unit Min. Max. Min. Max. Test Conditions Notes IIL Input Leakage Current -5 +5 -5 +5 µA 0V ≤ Vin ≤ Vin + 0.3V Pins not under Test = 0V IOL Output Leakage Current -5 +5 -5 +5 µA DOUT disabled, 0V ≤ Vout ≤ + VCC ICC1 Operating Power Supply Current - 80 - 75 mA RAS , UCAS , LCAS and Address cycling; tRC = min. ICC2 TTL Standby Power Supply Current - 1.5 - 1.5 mA RAS = UCAS = LCAS =VIH ICC3 Average Power Supply Current, RAS Refresh Mode - 80 - 75 mA RAS and Address cycling, UCAS = LCAS = VIH, tRC = min. 1 ICC4 EDO Page Mode Average Power Supply Current - 80 - 75 mA RAS = VIL, UCAS , LCAS and Address cycling; tPC = min. 1, 2 ICC5 CAS -before- RAS Refresh Power Supply Current - 80 - 75 mA RAS , UCAS and LCAS cycling; tRC = min. ICC6 CMOS Standby Power Supply Current - 1.0 - 1.0 mA RAS = UCAS = LCAS = VCC - 0.2V ICC7 Self Refresh Mode Current - 350 - 350 µA RAS = CAS ≤VSS+0.2V All other input high levels are VCC-0.2V or input low levels are VSS +0.2V 2.4 - 2.4 - V IOUT = -2.0mA - 0.4 - 0.4 V IOUT =2.0mA VOH VOL Output Voltage PRELIMINARY (June, 2002, Version 0.3) 5 1, 2 1 AMIC Technology, Inc. A42L2604 Series AC Characteristics (VCC = 3.3V ± 0.3V, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C) Test Conditions: Input timing reference level: VIH/VIL=2.0V/0.8V Output reference level: VOH/VOL=2.0V/0.8V Output Load: 2TTL gate + CL (50pF) Assumed tT=2ns # Std Symbol -45 -50 Parameter Min. Max. Min. Max. Unit Notes 4, 5 tT Transition Time (Rise or Fall) 1 50 1 50 ns 1 tRC Random Read or Write Cycle Time 76 - 84 - ns 2 tRP RAS Precharge Time 27 - 30 - ns 3 tRAS RAS Pulse Width 45 10K 50 10K ns 4 tCAS CAS Pulse Width 7 10K 8 10K ns 5 tRCD RAS to CAS Delay Time 10 33 11 37 ns 6 6 tRAD RAS to Column Address Delay Time 8 25 9 28 ns 7 7 tRSH CAS to RAS Hold Time 7 - 8 - ns 8 tCSH CAS Hold Time 35 - 37 - ns 9 tCRP CAS to RAS Precharge Time 5 - 5 - ns 10 tASR Row Address Setup Time 0 - 0 - ns 11 tRAH Row Address Hold Time 7 - 8 - ns 12 tCLZ CAS to Output in Low Z 3 - 3 - ns 8 13 tRAC Access Time from RAS - 45 - 50 ns 6,7 14 tCAC Access Time from CAS - 12 - 13 ns 6, 12 15 tAA Access Time from Column Address - 20 - 22 ns 7, 12 16 tOEA Access Time from OE - 12 - 13 ns 17 tAR Column Address Hold Time from RAS 40 - 45 - ns 18 tRCS Read Command Setup Time 0 - 0 - ns 19 tRCH Read Command Hold Time 0 - 0 - ns PRELIMINARY (June, 2002, Version 0.3) 6 9 AMIC Technology, Inc. A42L2604 Series AC Characteristics (continued) (VCC = 3.3V ± 0.3V, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C) Test Conditions: Input timing reference level: VIH/VIL=2.0V/0.8V Output reference level: VOH/VOL=2.0V/0.8V Output Load: 2TTL gate + CL (50pF) Assumed tT=2ns # Std Symbol -45 -50 Parameter Min. Max. Min. Max. Unit Notes 9 20 tRRH Read Command Hold Time Reference to RAS 0 - 0 - ns 21 tRAL Column Address to RAS Lead Time 20 - 22 - ns 22 TCOH Output Hold After CAS Low 2 - 3 - ns 23 tOFF Output Buffer Turn-Off Delay Time - 2 - 3 ns 24 tASC Column Address Setup Time 0 - 0 - ns 25 tCAH Column Address Hold Time 7 - 8 - ns 26 tOES OE Low to CAS High Set Up 10 - 10 - ns 27 tWCS Write Command Setup Time 0 - 0 - ns 11 28 tWCH Write Command Hold Time 7 - 8 - ns 11 29 tWCR Write Command Hold Time to RAS 40 - 45 - ns 30 tWP Write Command Pulse Width 7 - 8 - ns 31 tRWL Write Command to RAS Lead Time 12 - 13 - ns 32 tCWL Write Command to CAS Lead Time 7 - 8 - ns 33 tDS Data-in setup Time 0 - 0 - ns 34 tDH Data-in Hold Time 7 - 8 - ns 35 tDHR Data-in Hold Time to RAS 40 - 45 - ns 36 tRWC Read-Modify-Write Cycle Time 104 - 114 - ns 37 tRWD RAS to WE Delay Time (Read-Modify-Write) 59 - 65 - ns 11 38 tCWD CAS to WE Delay Time (Read-Modify-Write) 26 - 28 - ns 11 39 tAWD 34 - 37 - ns 11 Column Address to WE Delay Time 8, 10 (Read-Modify-Write) PRELIMINARY (June, 2002, Version 0.3) 7 AMIC Technology, Inc. A42L2604 Series AC Characteristics (continued) (VCC = 3.3V ± 0.3V, VSS = 0V, Ta = 0°C to +70°C or -40°C to +85°C) Test Conditions: Input timing reference level: VIH/VIL=2.0V/0.8V Output reference level: VOH/VOL=2.0V/0.8V Output Load: 2TTL gate + CL (50pF) Assumed tT=2ns # Std Symbol -45 -50 Parameter Unit Min. Max. Min. Max. Notes 40 tOEH OE Hold Time from WE 7 - 8 - ns 41 tOEP OE High Pulse Width 5 - 5 - ns 42 tPC Read or Write Cycle Time (EDO Page) 18 - 20 - ns 13 43 tCPA - 21 - 23 ns 12 Access Time from CAS Precharge (EDO Page) 44 tCP CAS Precharge Time 7 - 8 - ns 45 tPCM EDO Page Mode RMW Cycle Time 46 - 50 - ns 46 tCRW EDO Page Mode CAS Pulse Width (RMW) 35 - 38 - ns 47 tRASP RAS Pulse Width 45 200K 50 200K ns 48 tCSR CAS Setup Time ( CAS -before- RAS ) 5 - 5 - ns 3 49 tCHR CAS Hold Time 10 - 10 - ns 3 50 tRPC RAS to CAS Precharge Time 10 - 10 - ns 51 tOEZ Output Buffer Turn-off Delay from OE - 2 - 3 ns 52 tRASS RAS pulse width ( C -B- R self refresh) 100 - 100 - µs 53 tRPS RAS precharge time ( C -B- R self refresh) 76 - 84 - ns 54 tCHS CAS hold time ( C -B- R self refresh) -50 - -50 - ns PRELIMINARY (EDO Page) ( CAS -before- RAS ) (June, 2002, Version 0.3) 8 8 AMIC Technology, Inc. A42L2604 Series Notes: 1. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate. 2. ICC1 and ICC4 depend on output loading. Specified values are obtained with the outputs open. 3. An initial pause of 200µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS -before- RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks. 4. AC Characteristics assume tT = 2ns. All AC parameters are measured with a load equivalent to two TTL loads and 50pF, VIL (min.) ≥ GND and VIH (max.) ≤ VCC. 5. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. 6. Operation within the tRCD (max.) limit insures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled exclusively by tCAC. 7. Operation within the tRAD (max.) limit insures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled exclusively by tAA. 8. Assumes three state test load (5pF and a 500Ω Thevenin equivalent). 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. tOFF (max.) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. 11. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (min.) and tWCH ≥ tWCH (min.), the cycle is an early write cycle and data-out pins will remain open circuit, high impedance, throughout the entire cycle. If tRWD ≥ tRWD (min.) , tCWD ≥ tCWD (min.) and tAWD ≥ tAWD (min.), the cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. 12. Access time is determined by the longer of tAA or tCAC or tCPA. 13. tASC ≥ tCP to achieve tPC (min.) and tCPA (max.) values. PRELIMINARY (June, 2002, Version 0.3) 9 AMIC Technology, Inc. A42L2604 Series Word Read Cycle tRC(1) tRAS(3) tRP(2) RAS tCSH(8) tCRP(9) tRCD(5) tRSH(7) tCRP(9) tCAS(4) CAS tRAD(6) tASR(10) Address tRAL(21) tRAH(11) tASC(24) Row Address tCAH(25) Column Address tAR(17) tRCH(19) tRCS(18) tRRH(20) WE tOEA(16) OE tCAC(14) tAA(15) tRAC(13) I/O 0 ~ I/O 3 tOFF(23) tOEZ(51) High-Z Valid Data-out tCLZ(12) : High or Low PRELIMINARY (June, 2002, Version 0.3) 10 AMIC Technology, Inc. A42L2604 Series Word Write Cycle (Early Write) tRC(1) tRAS(3) tRP(2) RAS tCSH(8) tCRP(9) tRCD(5) tRSH(7) tCRP(9) tCAS(4) CAS tAR(17) tRAD(6) tASR(10) tRAL(21) tRAH(11) tCAH(25) tASC(24) Address Row Address Column Address tWCR(29) tCWL(32) tRWL(31) tWP(30) WE tWCS(27) tWCH(28) OE tDHR(35) tDS(33) I/O 0 ~ I/O 3 tDH(34) Valid Data-in : High or Low PRELIMINARY (June, 2002, Version 0.3) 11 AMIC Technology, Inc. A42L2604 Series Word Write Cycle (Late Write) tRC(1) tRAS(3) tRP(2) RAS tCSH(8) tCRP(9) tRCD(5) tRSH(7) tCRP(9) tCAS(4) CAS tAR(17) tRAD(6) tASR(10) tRAL(21) tRAH(11) tCAH(25) tASC(24) Address Row Address Column Address tCWL(32) tRWL(31) tWCR(29) tWP(30) WE tOEH(40) OE tDHR(35) tDS(33) I/O 0 ~ I/O 3 tDH(34) High-Z Vaild Data-in : High or Low PRELIMINARY (June, 2002, Version 0.3) 12 AMIC Technology, Inc. A42L2604 Series Word Read-Modify-Write Cycle tRWC(36) tRAS(3) tRP(2) RAS tCSH(8) tCRP(9) tRCD(5) tRSH(7) tCRP(9) CAS tAR(17) tRAD(6) tASR(10) Address tRAH(11) tASC(24) Row Address tCAH(25) Column Address tAWD(39) tCWL(32) tCWD38) tRCS(18) tRWD(37) tRWL(31) WE tWP(30) tOEA(16) tOEZ(51) OE tOEH(40) tCAC(14) tAA(15) tDS(33) tDH(34) tRAC(13) I/O 0 ~ I/O 3 High-Z Data-out Data-in tCLZ(12) : High or Low PRELIMINARY (June, 2002, Version 0.3) 13 AMIC Technology, Inc. A42L2604 Series EDO Page Mode Word Read Cycle tRASP(47) tRP(2) RAS tCSH(8) tCRP(9) tPC(42) tRSH(7) tCRP(9) tRCD(5) tCP(44) tCAS(4) tCAS(4) tCAS(4) CAS tCSH(8) tAR(16) tASR(10) Address tRAD(6) tRAH(11) tRAL(21) tCAH(25) tCAH(25) tASC(24) tASC(24) Row Column Column tCAH(25) Column tRCS(18) tRCS(18) tRCH(19) tRCH(25) tRCS(18) WE tAA(15) tAA(15) tRRH(20) tCPA(43) tOEA(16) tOEA(16) tOES(26) OE tCAC(14) tRAC(13) tCAC(14) tOEP(41) tCOH(22) tCLZ(12) I/O 0 ~ I/O 3 Data-out tOFF(23) tCAC(14) tOEZ(51) tOEZ(51) Data-out Data-out tCLZ(12) : High or Low PRELIMINARY (June, 2002, Version 0.3) 14 AMIC Technology, Inc. A42L2604 Series EDO Page Mode Early Word Write Cycle tRASP(47) tRP(2) RAS tCSH(8) tCRP(9) tPC(42) tRSH(7) tCRP(9) tRCD(5) tCAS(4) tCP(44) tCAS(4) tCP(44) tCAS(4) CAS tRAL(21) tRAD(6) tASR(10) Address tCAH(25) tRAH(11) tASC(24) tCAH(25) tASC(24) Row tCAH(25) tASC(24) Column Column tCWL(32) tCWL(32) Column tCWL(32) tRWL(31) tWCS(27) tWCS(27) tWCS(27) tWCH(28) tWCH(28) tWCH(28) WE tWP(30) tWP(30) tWP(30) OE tDH(34) tDS(33) I/O 0 ~ I/O 3 tDH(34) tDS(33) Data-in tDH(34) tDS(33) Data-in Data-in : High or Low PRELIMINARY (June, 2002, Version 0.3) 15 AMIC Technology, Inc. A42L2604 Series EDO Page Mode Word Read-Modify-Write Cycle tRP(2) tRASP(47) RAS tCSH(8) tCRP(9) tPCM(45) tRSH(7) tCRP(9) tRCD(5) tCRW(46) tCP(44) tCP(44) tCRW(46) tCRW(46) CAS tRAL(21) tRAD(6) tASR(10) tCAH(25) tRAH(11) Address Row tCAH(25) tCAH(25) tASC(24) tASC(24) Column tASC(24) Column Column tCWL(32) tCWL(32) tCWL(32) tRWD(37) tRWL(31) tRCS(18) tCWD(38) tCWD(38) tCWD(38) WE tWP(30) tAWD(39) tWP(30) tAWD(39) tOEA(16) tWP(30) tAWD(39) tOEA(16) tOEA(16) OE tOEH(40) tCAC(14) tCPA(43) tAA(15) tOEZ(51) tAA(15) tOEZ(51) tDH(34) tRAC(13) tOEZ(51) tDH(34) tDH(34) tDS(33) tDS(33) tDS(33) I/O 0 ~ I/O 3 tCPA(43) tAA(15) High-Z tCLZ(12) tCLZ(12) tCLZ(12) Data-in Data-out Data-in Data-out Data-in Data-out : High or Low PRELIMINARY (June, 2002, Version 0.3) 16 AMIC Technology, Inc. A42L2604 Series RAS Only Refresh Cycle tRC(1) tRAS(3) tRP(2) RAS tRPC(50) tCRP(9) CAS tASR(10) tRAH(11) Row Address Note: WE, OE = Don't care. : High or Low CAS Before RAS Refresh Cycle tRC(1) tRP(2) tRAS(3) tRP(2) RAS tRPC(50) tCHR(49) tCSR(48) tPC(44) CAS tOFF(23) High-Z I/O 0 ~ I/O 3 Note: WE, OE, Address = Don't care. PRELIMINARY (June, 2002, Version 0.3) : High or Low 17 AMIC Technology, Inc. A42L2604 Series Hidden Refresh Cycle (Word Read) tRC(1) tRC(1) tRAS(3) tRP(2) tRAS(3) tRP(2) RAS tAR(17) tCRP(9) tRSH(7) tRCD(5) tCHR(49) tCRP(9) UCAS LCAS tRAD(6) tASR(10) tRAL(21) tCAH(25) tRAH(11) tASC(24) A0~A8 Row Column tRCS(18) tRRH(20) WE tAA(15) tOEZ(51) tOEA(16) OE tCAC(14) tOFF(23) tCLZ(12) tRAC(13) I/O0 ~ I/O 15 High-Z Valid Data-out : High or Low PRELIMINARY (June, 2002, Version 0.3) 18 AMIC Technology, Inc. A42L2604 Series Hidden Refresh Cycle (Early Word Write) tRC(1) tRC(1) tRAS(3) tRP(2) tRAS(3) tRP(2) RAS tAR(17) tCRP(9) tCHR(49) tRSH(7) tRCD(5) tCRP(9) CAS tRAD(6) tASR(10) tRAH(11) tRAL(21) tCAH(25) tASC(24) Address Row Column tWCS(27) tWCH(28) tWP(30) WE OE tDS(33) I/O 0 ~ I/O 3 tDH(34) Valid Data-in : High or Low PRELIMINARY (June, 2002, Version 0.3) 19 AMIC Technology, Inc. A42L2604 Series EDO Page Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write) tRP(2) tRASP(47) RAS tCSH(8) tPC(42) tRCD(5) tCRP(9) tCAS(4) tPC(42) tCP(44) tCAS(4) tRSH(7) tCP(44) tCAS(4) tCPR(9) CAS tRAL(21) tRAD(6) tASR(10) Address tASC(24) tRAH(11) tASC(24) Row tCAH(25) tASC(24) tCAH(25) Column Column tCAH(25) Column tRCH(19) tRCS(18) tWCS(27) WE tWCH(28) tAA(15) tAA(15) tCAP(43) tDS(33) tDH(34) tRAC(13) tCAC(14) tCAC(14) tOEA(16) OE tCOH(22) I/O 0 ~ I/O 3 Data-out Data-out Data-in : High or Low PRELIMINARY (June, 2002, Version 0.3) 20 AMIC Technology, Inc. A42L2604 Series Self Refresh Mode tRP(2) tRASS(52) tRPS(53) RAS tCHS(54) tCSR(48) tRPC(50) tCRP(9) UCAS LCAS tCP(44) tASR(10) ROW A0 ~ A10 COL tOFF(23) High-Z I/O 0 ~ I/O 3 : High or Low Note: WE, OE = Don't care. n Self Refresh Mode. a. Entering the Self Refresh Mode: The A42L2604 Self Refresh Mode is entered by using CAS before RAS cycle and holding RAS and CAS signal “low” longer than 100µs. b. Continuing the Self Refresh Mode: The Self Refresh Mode is continued by holding RAS “low” after entering the Self Refresh Mode. It does not depend on CAS being “high” or “low” after entering the Self Refresh Mode continue the Self Refresh Mode. c. Exiting the Self Refresh Mode: The A42L2604 exits the Self Refresh Mode when the RAS signal is brought “high”. PRELIMINARY (June, 2002, Version 0.3) 21 AMIC Technology, Inc. A42L2604 Series Capacitance (f = 1MHz, Ta = Room Temperature, VCC = 3.3V ± 10%) Symbol Signals CIN1 A0 – A10 CIN2 RAS , CAS , Parameter Max. Unit Test Conditions 5 pF Vin = 0V Input Capacitance 7 pF Vin = 0V I/O Capacitance 7 pF Vin = Vout = 0V 45ns 50ns WE , OE CI/O I/O0 - I/O3 Ordering Codes Package RAS Access Time Refresh Cycle Self-Refresh SOJ 24/26L (300mil) A42L2604S-45 A42L2604S-50 2K Yes TSOP 24/26L type II (300mil) A42L2604V-45 A42L2604V-50 2K Yes TSOP 24/26L type II (300mil) A42L2604V-45U A42L2604V-50U 2K Yes Note: -U is for industrial operating temperature range. PRELIMINARY (June, 2002, Version 0.3) 22 AMIC Technology, Inc. A42L2604 Series Package Information SOJ 24/26L (300mil) Outline Dimensions unit: inches/mm 18 13 6 7 12 E1 19 1 E D 24 -yS b b2 A A A1 A2 C Pin 1 Identifier e Seating Plane 0.004 E2 y Dimensions in inches Symbol A θ Dimensions in mm Min Nom Max Min Nom Max A - - 0.140 - - 3.56 A1 0.070 0.080 0.090 1.78 2.03 2.29 A2 0.095 0.100 0.105 2.41 2.54 2.67 b 0.016 0.018 0.022 0.41 0.46 0.56 b2 0.026 0.028 0.032 0.66 0.71 0.81 C 0.008 0.010 0.014 0.20 0.25 0.36 D - 0.675 0.686 - 17.15 17.42 E 0.327 0.337 0.347 8.31 8.56 8.81 E1 0.295 0.300 0.305 7.49 7.62 7.75 E2 0.245 0.265 0.285 6.22 6.73 7.24 e 0.044 0.050 0.056 1.12 1.27 1.42 S - - 0.048 - - 1.22 θ 0° - 10° 0° - 10° Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension E2 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash. PRELIMINARY (June, 2002, Version 0.3) 23 AMIC Technology, Inc. A42L2604 Series Package Information TSOP 24/26L (TYPE II) (300mil) Outline Dimensions 13 E HE 0.010 24 unit: inches/mm θ L1 1 12 e B A A1 S D A2 c D y L1 Dimensions in inches Symbol Min Nom Max L Dimensions in mm Min Nom Max A - - 0.047 - - 1.20 A1 0.002 - - 0.05 - - A2 0.037 0.039 0.041 0.95 1.00 1.05 B 0.012 0.016 0.020 0.30 0.40 0.50 c - 0.005 - - 0.127 - D 0.671 0.675 0.679 17.04 17.14 17.24 E 0.298 0.300 0.302 7.57 7.62 7.67 e - 0.050 - - 1.27 - HE 0.355 0.363 0.371 9.02 9.22 9.42 L - 0.031 - - 0.80 - L1 0.016 0.020 0.024 0.40 0.50 0.60 S - 0.037 - - 0.95 - y - - 0.004 - - 0.10 0° - 0° - 5° θ 5° Notes: 1. Dimension D&E do not included interlead flash. 2. Dimension B does not included dambar protrusion / intrusion. 3. Dimension S includes end flash. PRELIMINARY (June, 2002, Version 0.3) 24 AMIC Technology, Inc.