IDT74FCT2373AT/CT FAST CMOS OCTAL TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE FAST CMOS OCTAL TRANSPARENT LATCH IDT74FCT2373AT/CT FEATURES: DESCRIPTION: • • • • The FCT2373T is an octal transparent latch built using an advanced dual metal CMOS technology. These octal latches have 3-state outputs and are intended for bus oriented applications. The flip-flops appear transparent to the data when Latch Enable (LE) is high. When LE is low, the data that meets the set-up time is latched. Data appears on the bus when the Output Enable (OE) is low. When OE is high, the bus output is in the high-impedance state. The FCT2373T has balanced drive outputs with current limiting resistors. This offers low ground bounce, minimal undershoot and controlled output fall times-reducing the need for external series terminating resistors. The FCT2373T parts are plug-in replacements for FCT373T parts. • • • • A and C grades Low input and output leakage ≤1µA (max.) CMOS power levels True TTL input and output compatibility: – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) Meets or exceeds JEDEC standard 18 specifications Resistor outputs -15mA IOH, 12mA IOL Reduced system switching noise Available in QSOP package FUNCTIONAL BLOCK DIAGRAM D0 D2 D1 D D3 D D O D O G D7 D D O G G D6 D5 D O O G D4 D O O G O G G G LE OE O0 O1 O2 O3 The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE O4 O5 O6 O7 JUNE 2006 1 © 2006 Integrated Device Technology, Inc. DSC-5497/6 IDT74FCT2373AT/CT FAST CMOS OCTAL TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE PIN CONFIGURATION OE 1 ABSOLUTE MAXIMUM RATINGS(1) 20 VCC O0 2 19 D0 3 18 D7 D1 4 17 D6 O1 5 16 O6 O2 6 15 O5 D2 7 14 D5 O7 Symbol Description VTERM(2) Max Unit VTERM(3) Terminal Voltage with Respect to GND –0.5 to +7 V Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V TSTG Storage Temperature –65 to +150 °C IOUT DC Output Current –60 to +120 mA NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. 3. Output and I/O terminals only. CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) Symbol D3 O3 GND 8 13 D4 9 12 O4 10 11 LE Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 6 10 pF COUT Output Capacitance VOUT = 0V 8 12 pF NOTE: 1. This parameter is measured at characterization but not tested. QSOP TOP VIEW PIN DESCRIPTION Pin Names Dx Description Data Inputs LE Latch Enable Input (Active HIGH) OE Output Enable Input (Active LOW) Ox 3-State Outputs FUNCTION TABLE(1) Dx L H X Inputs LE H H X NOTE: 1. H = HIGH Voltage Level X = Don’t Care L = LOW Voltage Level Z = High Impedance 2 OE L L H Outputs Ox L H Z IDT74FCT2373AT/CT FAST CMOS OCTAL TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = –40°C to +85°C, VCC = 5.0V ±5% Symbol Test Conditions(1) Parameter Min. Typ.(2) Max. Unit 2 — — V VIH Input HIGH Level Guaranteed Logic HIGH Level VIL Input LOW Level Guaranteed Logic LOW Level — — 0.8 V IIH Input HIGH Current(4) VCC = Max. VI = 2.7V — — ±1 µA IIL Input LOW Current(4) VCC = Max. VI = 0.5V — — ±1 µA IOZH High Impedance Output Current VCC = Max. VI = 2.7V — — ±1 µA IOZL (3-State Output Pins)(4) VI = 0.5V — — ±1 II Input HIGH Current(4) VCC = Max., VI = VCC (Max.) — — ±1 µA VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V VH Input Hysteresis — 200 — mV ICC Quiescent Power Supply Current — 0.01 1 mA Min. 16 -16 2.4 Typ.(2) 48 -48 3.3 Max. — — — Unit mA mA V — 0.3 0.5 V — VCC = Max. VIN = GND or VCC OUTPUT DRIVE CHARACTERISTICS Symbol IODL IODH VOH VOL Parameter Output LOW Current Output HIGH Current Output HIGH Voltage Output LOW Voltage Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V(3) VCC = Min IOH = –15mA VIN = VIH or VIL VCC = Min IOL = 12mA VIN = VIH or VIL NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. The test limit for this parameter is ±5μA at TA = -55°C. 3 IDT74FCT2373AT/CT FAST CMOS OCTAL TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE POWER SUPPLY CHARACTERISTICS Test Conditions(1) Min. Typ.(2) Max. Unit — 0.5 2 mA VIN = VCC VIN = GND — 0.06 0.12 mA/ MHz VCC = Max. Outputs Open fi = 10MHz VIN = VCC VIN = GND — 0.6 2.2 mA 50% Duty Cycle OE = GND LE = Vcc VIN = 3.4V VIN = GND — 0.9 3.2 VCC = Max. Outputs Open fi = 2.5MHz VIN = VCC VIN = GND — 1.2 3.4(5) 50% Duty Cycle OE = GND LE = Vcc VIN = 3.4V VIN = GND — 3.2 11.4(5) Symbol Parameter ΔICC Quiescent Power Supply Current TTL Inputs HIGH VCC = Max. VIN = 3.4V(3) ICCD Dynamic Power Supply Current(4) VCC = Max. Outputs Open OE = GND One Input Toggling 50% Duty Cycle IC Total Power Supply Current(6) One BitToggling Eight Bits Toggling NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input; (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of ΔICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ΔICC DHNT + ICCD (fCP/2+ fiNi) ICC = Quiescent Current ΔICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Output Frequency Ni = Number of Outputs at fi All currents are in milliamps and all frequencies are in megahertz. 4 IDT74FCT2373AT/CT FAST CMOS OCTAL TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE(1) 74FCT2373AT 74FCT2373CT Parameter Condition(1) Min.(2) Max. Min.(2) Max. Unit tPLH Propagation Delay CL = 50 pF 1.5 5.2 1.5 4.2 ns tPHL Dx to Ox RL = 500Ω tPLH Propagation Delay 2 8.5 2 5.5 ns tPHL LE to Ox tPZH Output Enable Time 1.5 6.5 1.5 5.5 ns Output Disable Time 1.5 5.5 1.5 5 ns — 2 — ns Symbol tPZL tPHZ tPLZ tSU Set-up Time HIGH or LOW, Dx to LE 2 tH Hold Time HIGH or LOW, Dx to LE 1.5 — 1.5 — ns tW LE Pulse Width HIGH(3) 5 — 5 — ns NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This parameter is guaranteed but not tested. 5 IDT74FCT2373AT/CT FAST CMOS OCTAL TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS V CC SWITCH POSITION 7.0V 500W V OUT VIN Pulse Generator D.U.T . 50pF RT 500W CL Test Switch Open Drain Disable Low Enable Low Closed All Other Tests Open DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Octal Link Test Circuits for All Outputs DATA INPUT tH tSU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tREM tSU 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 1.5V 3V 1.5V 0V tH Pulse Width Octal Link Octal Link Set-Up, Hold, and Release Times ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V DISABLE 3V CONTROL INPUT 1.5V OUTPUT NORMALLY LOW 3V 1.5V 0V SWITCH CLOSED 3.5V 1.5V tPZH OUTPUT NORMALLY HIGH SWITCH OPEN 0V tPLZ tPZL VOH 1.5V VOL 3.5V 0.3V VOL tPHZ 0.3V VOH 1.5V 0V Octal Link 0V Octal Link Propagation Delay Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 6 IDT74FCT2373AT/CT FAST CMOS OCTAL TRANSPARENT LATCH INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION XXXX IDT XX FCT Device Type Temp. Range XX Package Q QG Quarter-size Small Outline Package QSOP - Green 2373AT Octal Transparent Latch 2373CT 74 CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 – 40°C to +85°C for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 7 for Tech Support: [email protected]