AVAGO MGA-82563 0.1â 6 ghz 3 v, 17 dbm amplifier Datasheet

MGA-82563
0.1– 6 GHz 3 V, 17 dBm Amplifier
Data Sheet
Description
Features
Avago’s MGA-82563 is an economical, easy-to-use GaAs
MMIC amplifier that offers excellent power and low noise
figure for applications from 0.1 to 6 GHz. Packaged in an
ultra-miniature SOT-363 package, it requires half the
board space of a SOT-143 package.
x Lead-free Option Available
The input and output of the amplifier are matched to
50: (below 2:1 VSWR) across the entire bandwidth,
eliminating the expense of external matching. The amplifier allows a wide dynamic range by offering a 2.2 dB
NF coupled with a +31 dBm Output IP3.
x 2.2 dB Noise Figure at 2.0 GHz
The circuit uses state-of-the-art PHEMT technology
with proven reliability. On-chip bias circuitry allows operation from a single +3 V power supply, while resistive
feedback ensures stability (K>1) over all frequencies and
temperatures.
Applications
Surface Mount Package
Simplified Schematic
x +17.3 dBm P1 dB at 2.0 GHz
+20 dBm Psat at 2.0 GHz
x Single +3V Supply
x 13.2 dB Gain at 2.0 GHz
x Ultra-miniature Package
x Unconditionally Stable
x Buffer or Driver Amp for PCS,
PHS, ISM, SATCOM and WLL Applications
x High Dynamic Range LNA
SOT-363 (SC-70)
OUTPUT
and Vd
6
INPUT
3
Pin Connections and Package Marking
BIAS
BIAS
GND 2
INPUT 3
Note:
82x
GND 1
6 OUTPUT
and Vd
5 GND
GND
1, 2, 4, 5
4 GND
Package marking provides orientation and identification.
"82" = Device Code
"x" = Date code character identifies month of manufacture
Attention: Observe precautions for
handling electrostatic sensitive devices.
ESD Human Body Model (Class 0)
Refer to Avago Application Note A004R:
Electrostatic Discharge Damage and Control.
MGA-82563 Absolute Maximum Ratings
Thermal Resistance [2]:
Tch-c = 180°C/W
Units
Absolute
Maximum[1]
Vd
Device Voltage, RF Output
to Ground
V
5.0
Vgd
Device Voltage, Gate
to Drain
V
-6.0
1. Permanent damage may occur if any
of these limits are exceeded.
Vin
Range of RF Input Voltage
to Ground
V
+0.5 to -1.0
2. TC = 25°C (TC is defined to be the temperature at the top of the package.)
Symbol
Parameter
Notes:
Pin
CW RF Input Power
dBm
+13
T ch
Channel Temperature
°C
165
TSTG
Storage Temperature
°C
-65 to 150
MGA-82563 Electrical Specifications, TC = 25°C, ZO = 50 Ω, Vd = 3 V
Symbol
G test
Parameters and Test Conditions
Gain in test circuit[1]
Units
f = 2.0 GHz
NFtest
Noise Figure in test circuit
[1]
f = 2.0 GHz
NF50
Noise Figure in 50 Ω system
f = 0.5 GHz
f = 1.0 GHz
f = 2.0 GHz
f = 3.0 GHz
f = 4.0 GHz
f = 6.0 GHz
dB
f = 0.5 GHz
f = 1.0 GHz
f = 2.0 GHz
f = 3.0 GHz
f = 4.0 GHz
f = 6.0 GHz
dB
f = 0.5 GHz
f = 1.0 GHz
f = 2.0 GHz
f = 3.0 GHz
f = 4.0 GHz
f = 6.0 GHz
dBm
f = 2.0 GHz
dBm
|S21|2
P1 dB
IP3
Gain in 50 Ω system
Output Power at 1 dB Gain Compression
Output Third Order Intercept Point
Min.
Typ.
Max.
Std Dev [2]
12.0
13.2
15
0.35
2.2
2.9
0.20
2.3
2.2
2.2
2.2
2.4
2.7
14.7
14.5
13.5
12.1
10.7
8.8
0.35
17.4
17.5
17.3
17.1
17.0
16.8
0.54
+31
VSWRin
Input VSWR
f = 0.2–5.0 GHz
1.8:1
VSWRout
Output VSWR
f = 0.2–5.0 GHz
1.2:1
Id
Device Current
mA
0.20
63
84
1.0
101
Notes:
1. Guaranteed specifications are 100% tested in the circuit in Figure 10 in the Applications Information section.
2. Standard deviation number is based on measurement of at least 500 parts from three non-consecutive wafer lots during the initial characterization of this product, and is intended to be used as an estimate for distribution of the typical specification.
2
MGA-82563 Typical Performance, TC = 25° C, Vd = 3 V
16
5
19
4
18
3
17
NOISE FIGURE (dB)
12
GAIN (dB)
10
8
6
4
2
TA = +85C
TA = +25C
TA = –40C
2
P1 dB (dBm)
14
TA = +85C
TA = +25C
TA = –40C
1
0
1
2
3
4
5
6
TA = +85C
TA = +25C
TA = –40C
15
0
0
16
14
0
1
2
FREQUENCY (GHz)
3
4
5
6
0
1
2
Figure 1. 50 Power Gain vs. Frequency and
Temperature.
Figure 2. Noise Figure (into 50 ) vs. Frequency and
Temperature.
16
3
4
5
6
FREQUENCY (GHz)
FREQUENCY (GHz)
Figure 3. Output Power @ 1 dB Gain Compression vs.
Frequency and Temperature.
5
19
4
18
3
17
NOISE FIGURE (dB)
10
8
6
2
Vd = 3.3V
Vd = 3.0V
Vd = 2.7V
4
2
Vd = 3.3V
Vd = 3.0V
Vd = 2.7V
1
0
1
2
3
4
5
6
0
1
2
FREQUENCY (GHz)
4
5
6
3.5
1
DEVICE CURRENT (mA)
2.5
Input
2
16
100
14
70
60
TA = +85C
TA = +25C
TA = -40C
40
Output
2
3
4
5
FREQUENCY (GHz)
Figure 7. Input and Output VSWR into 50 vs.
Frequency.
6
6
10
8
6
NF
2
10
1
5
4
20
0
4
Gain
12
80
50
3
Figure 6. Output Power @ 1 dB Gain Compression vs.
Frequency and Voltage.
110
30
1.5
2
FREQUENCY (GHz)
90
3
3
0
Figure 5. Noise Figure (into 50 ) vs.
Frequency and Voltage.
4
VSWR (n:1)
3
FREQUENCY (GHz)
Figure 4. 50 Power Gain vs. Frequency and Voltage.
1
Vd = 3.3V
Vd = 3.0V
Vd = 2.7V
14
0
0
16
15
GAIN and NF (dB)
GAIN (dB)
12
P1 dB (dBm)
14
0
0
1
2
3
DEVICE VOLTAGE (V)
Figure 8. Device Current vs. Voltage and
Temperature.
4
0
1
2
3
4
5
6
FREQUENCY (GHz)
Figure 9. Minimum Noise Figure and Associated Gain
vs. Frequency.
MGA-82563 Typical Scattering Parameters[1], TC = 25°C, Z O = 50 Ω, Vd = 3 V
Freq.
S11
S
S
K
Mag
Ang
dB
Mag
Ang
dB
Mag
Ang
Mag
Ang
Factor
0.1
0.2
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
0.48
0.35
0.29
0.29
0.29
0.29
0.29
0.28
0.28
0.29
0.30
0.32
0.34
0.36
0.38
0.40
-39
-35
-37
-57
-78
-99
-118
-138
-158
-177
166
151
136
123
110
97
15.71
14.81
14.34
13.95
13.50
12.99
12.45
11.84
11.24
10.67
10.11
9.58
9.07
8.57
8.06
7.51
6.10
5.50
5.21
4.98
4.73
4.46
4.19
3.91
3.65
3.42
3.20
3.01
2.84
2.68
2.53
2.37
164
165
159
144
128
114
99
86
74
61
50
38
27
16
5
-5
-23
-22
-22
-22
-22
-22
-21
-21
-21
-20
-20
-19
-19
-19
-19
-18
0.070
0.076
0.079
0.080
0.082
0.085
0.089
0.093
0.098
0.103
0.107
0.112
0.117
0.121
0.125
0.126
27
14
6
3
2
1
-1
-3
-6
-9
-13
-18
-23
-29
-35
-41
0.16
0.12
0.11
0.11
0.10
0.10
0.10
0.11
0.12
0.13
0.15
0.16
0.18
0.19
0.22
0.24
-99
-134
177
156
142
131
124
118
111
106
100
94
87
82
74
66
1.02
1.20
1.29
1.33
1.37
1.41
1.44
1.48
1.51
1.52
1.53
1.54
1.55
1.54
1.55
1.59
MGA-82563 Typical Noise Parameters[1]
TC = 25°C, Z O = 50 Ω, Vd = 3 V
*opt
Frequency
GHz
NFO
dB
Mag.
Ang.
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
2.10
2.10
2.10
2.12
2.12
2.15
2.16
2.16
2.19
2.18
2.19
2.23
2.28
2.39
0.15
0.15
0.14
0.15
0.15
0.144
0.14
0.15
0.17
0.20
0.22
0.25
0.27
0.29
25
45
65
75
94
113
134
155
177
-166
-152
-138
-125
-111
Note:
1. Reference plane per Figure 11 in Applications Information section.
4
S
GHz
Rn / 50 Ω
—
1.20
0.60
0.29
0.27
0.25
0.23
0.21
0.19
0.18
0.18
0.18
0.19
0.23
0.28
MGA-82563 Applications Information
Introduction
This medium power GaAs MMIC amplifier was developed
for commercial wireless applications from 100 MHz to 6
GHz. The MGA-82563 runs on only 3 volts and typically
requires only 84 mA to deliver over 17 dBm of output
power at 1 dB gain compression.
The 17.3 dBm output power (P1 dB) makes the MGA82563 extremely useful for pre-driver and driver stages
in transmit cascades or for final output stages in lower
power systems. For transmitter gain stage applications
that require even higher output power, the MGA-82563
can provide 100 mW (20 dBm) of saturated output power with a power added efficiency approaching 50%. The
low cost of the MGA-82563 makes it feasible to power
combine two (or more) devices for even higher output
power amplifiers.
The MGA-82563 offers an excellent combination of high
linearity (+31 dBm output IP3) and very low noise figure
(2.2 dB) for applications requiring a very high dynamic
range.
The MGA-82563 uses resistive feedback to simultaneously achieve flat gain over a wide bandwidth and to
match the input and output impedances to 50Ω. The
MGA-82563 is also unconditionally stable (K>1) over its
entire frequency range, making it both very easy to use
and yielding consistent performance in the manufacture
of high volume wireless products.
An innovative internal bias circuit regulates the device’s
internal current to enable the MGA-82563 to operate
over a wide temperature range with a single, positive
power supply of 3 volts. The MGA-82563 will operate
with reduced power and gain with a bias supply as low
as 1.5 volts.
Test Circuit
The circuit shown in Figure 10 is used for 100% RF testing
of Gain and Noise Figure. The test circuit is merely a 50Ω input/output PC board with a RFC at the output to apply DC
bias to the device under test. Tests in this circuit are used to
guarantee the NFtest and Gtest parameters shown in the table
of Electrical Specifications.
100 pF
82
RF
INPUT
RF
OUTPUT
22 nH
RFC
Vd
100 pF
Figure 10. Test Circuit.
5
Phase Reference Planes
The positions of the reference planes used to specify the
S-Parameters and Noise Parameters for this device are
shown in Figure 11. As seen in the illustration, the reference planes are located at the point where the package
leads contact the test circuit.
REFERENCE
PLANES
TEST CIRCUIT
Figure 11. Phase Reference Planes.
Specifications and Statistical Parameters
Several categories of parameters appear within this data
sheet. Parameters may be described with values that are
either “minimum or maximum,”“typical,” or “standard deviations.”
The values for parameters are based on comprehensive
product characterization data, in which automated measurements are made on of a minimum of 500 parts taken
from 3 non-consecutive process lots of semiconductor
wafers. The data derived from product characterization
tends to be normally distributed, e.g., fits the standard
“bell curve.”
Parameters considered to be the most important to
system performance are bounded by minimum or maximum values. For the MGA-82563, these parameters are:
Gain (Gtest), Noise Figure (NFtest), and Device Current (Id).
Each of these guaranteed parameters is 100% tested.
Values for most of the parameters in the table of Electrical Specifications that are described by typical data are
the mathematical mean (P), of the normal distribution
taken from the characterization data. For parameters
where measurements or mathematical averaging may
not be practical, such as the Noise and S-parameter tables or performance curves, the data represents a nominal part taken from the “center” of the characterization
distribution. Typical values are intended to be used as a
basis for electrical design.
To assist designers in optimizing not only the immediate
circuit using the MGA-82563, but to also optimize and
evaluate trade-offs that affect a complete wireless system, the standard deviation (V) is provided for many of
the Electrical Specifications parameters (at 25°) in addition to the mean. The standard deviation is a measure of
the variability about the mean. It will be recalled that a
normal distribution is completely described by the mean
and standard deviation.
Standard statistics tables or calculations provide the
probability of a parameter falling between any two
values, usually symmetrically located about the mean.
Referring to Figure 12 for example, the probability of a
parameter being between ±1V is 68.3%; between ±2V is
95.4%; and between ±3V is 99.7%.
68%
95%
99%
-3σ
-2σ
-1σ Mean (μ) +1σ +2σ
(typical)
+3σ
Parameter Value
Figure 12. Normal Distribution.
FR-4 or G-10 printed circuit board materials are a good
choice for most low cost wireless applications. Typical
board thickness is 0.020 to 0.031 inches. The width of the
50 Ω microstriplines on PC boards in this thickness range
is also very convenient for mounting chip components
such as the series inductor at the input or DC blocking
and bypass capacitors.
For higher frequencies or for noise figure critical applications, the additional cost of PTFE/glass dielectric materials may be warranted to minimize transmission line
loss at the amplifier’s input. A 0.5 inch length of 50 Ω
microstripline on FR-4, for example, has approximately
0.3 dB loss at 4 GHz. This loss will add directly to the
noise figure of the MGA-82563.
Biasing
RF Layout
The RF layout in Figure 13 is suggested as a starting point
for microstripline designs using the MGA-82563 amplifier. Adequate grounding is needed to obtain optimum
per formance and to maintain stability. All of the ground
pins of the MMIC should be connected to the RF groundplane on the backside of the PCB by means of plated
through holes (vias) that are placed near the package
terminals. As a minimum, one via should be located next
to each ground pin to ensure good RF grounding. It is a
good practice to use multiple vias to further minimize
ground path inductance.
50 Ω
82
RF Input
PCB Material
RF Output
and Vd
50 Ω
The MGA-82563 is a voltage-biased device and is
designed to operate from a single, +3 volt power supply
with a typical current drain of 84 mA. The internal current regulation circuit allows the amplifier to be operated with voltages as low as +1.5 volts. Refer to the section
titled “Operation at Bias Voltages Other than 3 Volts” for
information on performance and precau tions when using other voltages.
Typical Application Example
The printed circuit layout in Figure 14 can serve as a design guide. This layout is a microstripline design (solid
groundplane on the backside of the circuit board) with a
50 Ω input and output. The circuit is fabricated on 0.031inch thick FR-4 dielectric material. Plated through holes
(vias) are used to bring the ground to the top side of the
circuit where needed. Multiple vias are used to reduce
the inductance of the paths to ground.
Figure 13. RF Layout.
OUT
In addition to the RF considerations, the use of multiple
vias for grounding is important for the purpose of providing a lower resistance thermal path to the heatsink.
It is recommended that the PCB pads for the ground pins
not be connected together underneath the body of the
package. PCB traces hidden under the package cannot
be adequately inspected for SMT solder quality.
6
IN
+V
MGA-8-A
Figure 14. PCB Layout.
A schematic diagram of the application circuit is shown
in Figure 15. DC blocking capacitors (C1 and C2) are used
at the input and output of the MMIC to isolate the device from adjacent circuits. While the input terminal of
the MGA-82563 is at ground potential, it is not a current
sink. If the input is connected to a preceding stage that
has a voltage present, the use of the DC blocking capacitor (C1) is required.
C2
The value of the DC blocking and RF bypass capacitors
(C1 - C3) should be chosen to provide a small reactance
(typically <5 ohms) at the lowest operating frequency.
The reactance of the RF choke (RFC) should be high (e.g.,
several hundred ohms) at the lowest frequency of operation.
Vd
C4
RFC
RF
Input
C1
C2
RF
Output
Figure 15. Schematic Diagram.
DC bias is applied to the MGA-82563 through the RF
Output pin. An inductor (RFC), or length of high impedance transmission line (preferably O/4 at the band center), is used to isolate the RF from the DC supply.
The power supply is bypassed to ground with capacitor
C3 to keep RF off of the DC lines and to prevent gain dips
or peaks in the response of the amplifier.
An additional bypass capacitor, C4, may be added to the
bias line near the Vd connection to eliminate unwanted
feedback through bias lines that could cause oscillation.
C4 will not normally be needed unless several stages are
cascaded using a common power supply.
OUT
C1
C2
IN
RFC
C3
+V
MGA-8-A
Figure 16. Complete Application Circuit.
7
When multiple bypass capacitors are used, consideration
should be given to potential resonances. It is important
to ensure that the capacitors when combined with additional parasitic L’s and C’s on the circuit board do not
form resonant circuits. The addition of a small value resistor in the bias supply line between bypass capacitors
will often “de-Q” the bias circuit and eliminate the effect
of a resonance.
C4
The MGA-82563’s response at low frequencies is limited
to approximately 100 MHz by the size of capacitors integrated on the MMIC chip.
The input and output of the MGA-82563 are well matched
to 50 Ω. Without external matching elements, the input VSWR of the MGA-82563 is ≤ 2.0:1 from 300 MHz
to 6 GHz and the Output VSWR is ≤ 1.6:1 from 100 MHz
through 6 GHz.
For applications requiring minimum noise figure (NFo), some
improvement over a 50Ω match is possible by matching the
signal input to the optimum noise match impedance, *o, as
specified in the “Typical Noise Parameters” table. The data
in the table shows the noise match to be very close to 50Ω.
The completed application amplifier with all components and SMA connectors is shown in Figure 16.
For applications such as pre-driver, driver, and output
stages in transmitters, the MGA-82563 can be operated
in saturation to deliver up to 100 mW (20 dBm) of output
power. The power added efficiency approaches 50% at
these power levels.
There are several design considerations related to reliability and performance that should be taken into account when operating the amplifier in saturation.
First of all, it is important that the stage preceding the
MGA-82563 not overdrive the device. Referring to the
“Absolute Maximum Ratings” table, the maximum
allowable input power is +13 dBm. This should be regarded as the input power level above which the device
could be permanently damaged.
Driving the amplifier into saturation will also affect electrical performance. Figure 17 presents the Output Power, Third Order Intercept Point (Output IP3), and Power
Added Efficiency (PAE) as a function of Input Power. This
data represents performance into a 50Ω load. Since the
output impedance of the device changes when driven
into saturation, it is possible to obtain even more output
power with a “power match.” The optimum impedance
match for maximum output power is dependent on specific frequency and actual output power level and can be
arrived at empirically.
50
Pout and IP3 (dBm), PAE (%)
IP3
30
20
Power
10
0
-20
-15
-10
-5
0
Like other active devices, the intermodulation products
of the MGA-82563 increase as the device is driven further into nonlinear operation. The 3rd, 5th, and 7th order
intermodulation products of the MGA-82563 are shown
in Figure 18 along with the fundamental response. This
data was measured in the test circuit in Figure 10.
30
20
10
Pout
0
-10
-20
-30
-40
3rd
-50
-60
-30
7th
5th
-15
-10
-5
0
5
10
15
20
FREQUENCY (GHz)
Figure 18. Intermodulation Products vs. Input Power.
(Vd = 3.0 V)
Operation at Bias Voltages Other than 3 Volts
PAE
40
-10
Increased efficiency (up to 45% at full output power) is
another benefit of saturated operation. At high output
power levels, the bias supply current drops by about
15%. This is normal and is taken into account for the PAE
data in Figure 17.
Pout, 3rd, 5th, 7th HARMONICS (dBm)
Operation in Saturation for Higher Output Power
5
10
While the MGA-82563 is designed primarily for use in +3
volt applications, the internal bias regulation circuitry allows it to be operated with power supply voltages from
+1.5 to +4 volts. Performance of Gain, Noise Figure, and
Output Power over a wide range of bias voltage is shown
in Figure 19. (This data was measured in the test circuit
in Figure 10.) As can be seen, the gain and NF are fairly
flat, but an increase in output power is possible by using
higher voltages. The use of +4 volts increases the P1dB by
over 2 dBm.
POWER IN (dBm)
Figure 17. Output Power, IP3, and Power-Added-Efficiency vs. Input Power.
(Vd = 3.0 V)
As the input power is increased beyond the linear range
of the amplifier, the gain becomes more compressed.
Gain as a function of either input or output power may
be derived from Figure 17. Gain compression renders the
amplifier less sensitive to variations in the power level
from the preceding stage. This can be a benefit in systems requiring fairly constant output power levels from
the MGA-82563.
8
If bias voltages greater than 3 volts are used, particular
attention should be given to thermal management. Refer to the “Thermal Design Considerations” section for
more details.
of less dependency on current variation in the amplifiers
since the forward voltage drop of a diode is somewhat
current independent.
22
20
Power
18
NF, GAIN, P1 dB (dB)
16
Reverse breakdown diodes (e.g., Zener diodes) could
also be used as in Figure 20c. However, care should be
taken to ensure that the noise generated by diodes in
either Zener or reverse breakdown is adequately filtered
(e.g., bypassed to ground) such that the diode’s noise is
not added to the amplifier’s signal.
Gain
14
12
10
8
6
4
NF
2
0
0
1
2
3
4
SUPPLY VOLTAGE (V)
Note that the voltage-dropping component in each of
these three methods must be able to safely dissipate up
to 200 mW.
Figure 19. Gain, Noise Figure, and Output Power vs. Supply Voltage.
There are several means of biasing the MGA-82563 at
3 volts in systems that use higher power supply voltages.
The simplest method, shown in Figure 20a, is to use a
series resistor to drop the device voltage to 3 volts. For
example, a 24 Ω resistor will drop a 5-volt supply to 3
volts at the nominal current of 84 mA. Some variation in
performance could be expected for this method due to
variations in current within the specified 63 to 101 mA
min/max range.
+5 V
+5 V
24 Ω
SOT-363 PCB Footprint
A recommended PCB pad layout for the miniature SOT363 (SC-70) package used by the MGA-82563 is shown in
Figure 21 (dimensions are in inches). This layout provides
ample allowance for package placement by automated
assembly equipment without adding parasitics that
could impair the high frequency RF performance of the
MGA-82563. The layout is shown with a nominal SOT-363
package footprint superimposed on the PCB pads.
+5 V
Silicon
Diodes
Zener
Diode
(b)
(c)
0.026
0.079
(a)
Figure 20. Biasing From Higher Supply Voltages.
A second method illustrated in Figure 20b, is to use forward-biased diodes in series with the power supply. For
example, three silicon diodes connected in series will
drop a 5-volt supply to approximately 3 volts.
The use of the series diode approach has the advantage
9
0.039
0.018
Dimensions in inches.
Figure 21. Recommended PCB Pad Layout for Avago’s SC70 6L/SOT-363 Products.
Package Dimensions
Part Number Ordering Information
Outline 63 (SOT-363/SC-70)
HE
Part Number
No. of Devices
Container
MGA-82563-TR1G
3000
7" Reel
MGA-82563-BLKG
100
antistatic bag
E
e
D
Q1
A2
A
c
A1
L
b
DIMENSIONS (mm)
SYMBOL
E
D
HE
A
A2
A1
Q1
e
b
c
L
MAX.
1.35
2.25
2.40
1.10
1.00
0.10
0.40
MIN.
1.15
1.80
1.80
0.80
0.80
0.00
0.10
0.650 BCS
0.30
0.20
0.30
0.15
0.10
0.10
NOTES:
1. All dimensions are in mm.
2. Dimensions are inclusive of plating.
3. Dimensions are exclusive of mold flash & metal burr.
4. All specifications comply to EIAJ SC70.
5. Die is facing up for mold and facing down for trim/form,
ie: reverse trim/form.
6. Package surface to be mirror finish.
Device Orientation
REEL
TOP VIEW
END VIEW
4 mm
CARRIER
TAPE
USER
FEED
DIRECTION
COVER TAPE
10
8 mm
82
82
82
82
Tape Dimensions and Product Orientation
For Outline 63
P
P2
D
P0
E
F
W
C
D1
t1 (CARRIER TAPE THICKNESS)
Tt (COVER TAPE THICKNESS)
K0
10° MAX.
A0
DESCRIPTION
10° MAX.
B0
SYMBOL
SIZE (mm)
SIZE (INCHES)
CAVITY
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
A0
B0
K0
P
D1
2.40 ± 0.10
2.40 ± 0.10
1.20 ± 0.10
4.00 ± 0.10
1.00 + 0.25
0.094 ± 0.004
0.094 ± 0.004
0.047 ± 0.004
0.157 ± 0.004
0.039 + 0.010
PERFORATION
DIAMETER
PITCH
POSITION
D
P0
E
1.55 ± 0.10
4.00 ± 0.10
1.75 ± 0.10
0.061 + 0.002
0.157 ± 0.004
0.069 ± 0.004
CARRIER TAPE
WIDTH
THICKNESS
W
t1
8.00 + 0.30 - 0.10
0.254 ± 0.02
0.315 + 0.012
0.0100 ± 0.0008
COVER TAPE
WIDTH
TAPE THICKNESS
C
Tt
5.40 ± 0.10
0.062 ± 0.001
0.205 + 0.004
0.0025 ± 0.0004
DISTANCE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
F
3.50 ± 0.05
0.138 ± 0.002
CAVITY TO PERFORATION
(LENGTH DIRECTION)
P2
2.00 ± 0.05
0.079 ± 0.002
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2010 Avago Technologies. All rights reserved. Obsoletes AV01-0198EN
AV02-1985EN - May 22, 2010