TI1 OPA2650UB Dual wideband, low power voltage feedback operational amplifier Datasheet

®
OPA
OPA2650
265
OPA
0
265
0
Dual Wideband, Low Power Voltage Feedback
OPERATIONAL AMPLIFIER
FEATURES
DESCRIPTION
● LOW POWER: 50mW/Chan.
The OPA2650 is a dual, low power, wideband voltage
feedback operational amplifier. It features a high bandwidth of 360MHz as well as a 12-bit settling time of
only 20ns. The low distortion allows its use in communications applications, while the wide bandwidth and
true differential input stage make it suitable for use in
a variety of active filter applications. Its low distortion
gives exceptional performance for telecommunications, medical imaging and video applications.
● UNITY GAIN STABLE BANDWIDTH:
360MHz
● FAST SETTLING TIME: 20ns to 0.01%
● LOW HARMONICS: –77dBc at 5MHz
● DIFFERENTIAL GAIN/PHASE ERROR:
0.01%/0.025°
● HIGH OUTPUT CURRENT: 85mA
APPLICATIONS
● HIGH RESOLUTION VIDEO
● BASEBAND AMPLIFIER
● CCD IMAGING AMPLIFIER
● ULTRASOUND SIGNAL PROCESSING
● ADC/DAC GAIN AMPLIFIER
● ACTIVE FILTERS
The OPA2650 is internally compensated for unitygain stability. This amplifier has a fully symmetrical
differential input due to its “classical” operational
amplifier circuit architecture. Its unusual combination
of speed, accuracy and low power make it an outstanding choice for many portable, multi-channel and other
high speed applications, where power is at a premium.
The OPA2650 is also available in single (OPA650)
and quad (OPA4650) configurations.
+VS
● HIGH SPEED INTEGRATORS
● DIFFERENTIAL AMPLIFIER
Non-Inverting
Input
Output
Stage
Inverting
Input
Current
Mirror
Output
CC
–VS
NOTE: Diagram shows only one-half of the OPA2650.
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Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
®
© 1994 Burr-Brown Corporation
SBOS043
PDS-1266C
1
OPA2650
Printed in U.S.A. June, 1997
SPECIFICATIONS
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. RFB = 25Ω for a gain of +1.
OPA2650P, U, E
PARAMETER
CONDITIONS
FREQUENCY RESPONSE
Closed-Loop Bandwidth(2)
Gain Bandwidth Product
Bandwidth for 0.1dB Flatness(2)
Slew Rate(3)
Over Temperature Range
Rise Time
Fall Time
Settling Time
0.01%
0.1%
1%
Spurious Free Dynamic Range
Differential Gain
Differential Phase
Crosstalk(2)
INPUT OFFSET VOLTAGE
Input Offset Voltage
Average Drift
Power Supply Rejection (+VS)
(–VS)
INPUT BIAS CURRENT
Input Bias Current
Over Temperature Range
Input Offset Current
Over Temperature Range
MIN
G = +1
G = +2
G = +5
G = +10
G ≥ +5
G = +2
G = +1, 2V Step
G = +1, 0.2V Step
G = +1, 0.2V Step
G = +1, 2V Step
G = +1, 2V Step
G = +1, 2V Step
G = +1, f = 5.0MHz, VO = 2Vp-p
RL = 100Ω
RL = 402Ω
G = +2, NTSC, VO = 1.4Vp-p, RL = 150Ω
G = +2, NTSC, VO = 1.4Vp-p, RL = 150Ω
Input Referred, 5MHz, Channel-to-Channel
INPUT IMPEDANCE
Differential
Common-Mode
OPEN-LOOP GAIN
Open-Loop Voltage Gain
Over Temperature Range
OUTPUT
Voltage Output
Over Temperature Range
Output Current, Sourcing
Over Temperature Range
Output Current, Sinking
Over Temperature Range
Short Circuit Current
Output Resistance
POWER SUPPLY
Specified Operating Voltage
Operating Voltage Range
Quiescent Current
Over Temperature Range
THERMAL CHARACTERISTICS
Temperature Range
Thermal Resistance, θJA
P 8-Pin DIP
U SO-8
E MSOP-8
MAX
UNITS
✻
✻
✻
✻
✻
✻
✻
✻
72
77
0.01
0.025
–84
✻
✻
✻
✻
✻
dB
dB
%
Degrees
dB
5
VCM = 0V
0.5
20
30
1
3
Input Referred, VCM = ±0.5V
MAX
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
ns
ns
ns
ns
VCM = 0V
±2.2
65
TYP
✻(1)
✻
✻
✻
±5
60
47
OPA2650PB, UB
MIN
360
108
32
16
160
21
240
220
1
1
20
11
6.7
±1
±3
76
54
VCM = 0V
Input Referred, VS = ±4.5V to ±5.5V
INPUT NOISE
Input Voltage Noise
Noise Density, f = 100Hz
f = 10kHz
f ≥ 1MHz
Integrated Noise
fB = 10Hz to 100MHz
Input Bias Current Noise
Noise Density, f ≥ 0.1MHz
INPUT VOLTAGE RANGE
Common-Mode Input Range
Over Temperature Range
Common-Mode Rejection
TYP
70
50
±1
✻
✻
✻
±3
mV
µV/°C
dB
dB
✻
10
20
0.5
2
µA
µA
µA
µA
0.2
43
9.4
8.4
✻
✻
✻
nV/√Hz
nV/√Hz
nV/√Hz
84
✻
µVrms
1.2
✻
pA/√Hz
✻
✻
V
V
dB
✻
✻
KΩ || pF
MΩ || pF
±2.8
✻
70
90
15 || 1
16 || 1
VO = ±2V, RL = 100Ω
45
43
51
47
45
✻
dB
dB
No Load
RL = 250Ω
RL = 100Ω
±2.2
±2.2
±2.0
75
65
65
35
±3.0
±2.5
±2.3
110
±2.4
±2.4
±2.2
✻
✻
✻
✻
✻
✻
✻
✻
V
V
V
mA
mA
mA
mA
mA
Ω
85
✻
✻
150
0.08
f < 100kHz, G = +1
±4.5
Both Channels, VS = ±5V
Specification: P, U, E, PB, UB
Junction to Ambient
±5
±11
–40
100
125
150
✻
✻
±5.5
±15.5
±17.5
✻
+85
✻
✻
✻
✻
✻
✻
✻
±13.5
±16
V
V
mA
mA
✻
°C
°C/W
°C/W
°C/W
NOTES: (1) An asterisk (✻) specifies the same value as the grade to the left. (2) Frequency response can be strongly influenced by PC board parasitics. The
demonstration boards show low parasitic layouts for this part. Refer to the demonstration board layout for details. (3) Slew rate is rate of change from 10% to 90%
of output voltage step.
®
OPA2650
2
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................................................................. ±5.5V
Internal Power Dissipation ........................... See Thermal Characteristics
Differential Input Voltage .................................................................. ±1.2V
Input Voltage Range ............................................................................ ±VS
Storage Temperature Range: P, PB, U, UB, E ............ –40°C to +125°C
Lead Temperature (DIP, soldering, 10s) ...................................... +300°C
(SO-8 and MSOP-8, soldering, 3s) ................ +260°C
Junction Temperature (TJ ) ............................................................ +175°C
Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown
Corporation recommends that all integrated circuits be handled
and stored using appropriate ESD protection methods.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet published specifications.
PIN CONFIGURATION
Top View
DIP/SO-8/MSOP-8
Output 1
1
8
+VS
–Input 1
2
7
Output 2
+Input 1
3
6
–Input 2
–VS
4
5
+Input 2
PACKAGE/ORDERING INFORMATION
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
TEMPERATURE
RANGE
PACKAGE
MARKING(2)
ORDERING
NUMBER(3)
OPA2650P
OPA2650PB
8-Pin Plastic DIP
8-Pin Plastic DIP
006
006
–40°C to +85°C
–40°C to +85°C
OPA2650P
OPA2650PB
OPA2650P
OPA2650PB
OPA2650U
OPA2650UB
SO-8 Surface Mount
SO-8 Surface Mount
182
182
–40°C to +85°C
–40°C to +85°C
OPA2650U
OPA2650UB
OPA2650U
OPA2650UB
MSOP-8
337
–40°C to +85°C
B50
OPA2650E-250
OPA2650E-2500
PRODUCT
OPA2650E
NOTE: (1) For detailed drawing and dimension table, see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) The “B” grade will be marked with a “B”
by pin 8. (3) The MSOP-8 is available on 7" tape and reel with 250 parts, and on 14" tape and reel with 2500 parts. For example, ordering 250 pieces of “OPA2650E250” will get a single 250 piece tape and reel. Refer to Appendix B of Burr-Brown IC Data Book for detailed Tape and Reel Mechanical information.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use
of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the
circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
3
OPA2650
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. RFB = 25Ω for a gain of +1.
COMMON-MODE REJECTION
vs INPUT COMMON-MODE VOLTAGE
AOL, PSR AND CMRR vs TEMPERATURE
100
90
AOL, PSR and CMRR (dB)
Common Mode-Rejection (dB)
100
90
80
70
CMRR
80
PSR+
70
PSR–
60
AOL
50
40
60
–4
–3
–2
–1
0
1
2
3
–50
4
–25
0
25
50
75
125
Temperature (°C)
Common-Mode Voltage (V)
INPUT BIAS CURRENT vs TEMPERATURE
SUPPLY CURRENT vs TEMPERATURE
6
3
12
2
4
1
Supply Current (mA)
5
Offset Voltage (mV)
Input Bias Current (µA)
IB
10
IQ
VOS
3
–50
0
–25
0
25
50
75
9
–75
100
–50
–25
0
25
50
75
100
Temperature (°C)
Temperature (°C)
OUTPUT CURRENT vs TEMPERATURE
INPUT VOLTAGE AND CURRENT NOISE
vs FREQUENCY
110
125
100
Input Current Noise (pA/√Hz)
100
+
IO
90
80
IO–
70
Input Voltage Noise (nV/√Hz)
Outrput Current (±mA)
11
Voltage Noise
10
Non-inverting and
Inverting Current Noise
1
–50
–25
0
25
50
75
100
100
®
OPA2650
1k
10k
Frequency (Hz)
Temperature (°C)
4
100k
1M
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. RFB = 25Ω for a gain of +1.
RECOMMENDED ISOLATION RESISTANCE
vs CAPACITIVE LOAD
SMALL SIGNAL TRANSIENT RESPONSE
(G = +1)
40
200
Isolation Resistance, RISO (Ω)
160
120
Output Voltage (mV)
30
25Ω
20
RISO
OPA2650
10
CL
80
40
0
–40
–80
–120
1kΩ
–160
0
–200
0
20
40
60
80
100
Time (5ns/div)
Capacitive Load, C (pF)
L
LARGE SIGNAL TRANSIENT RESPONSE
(G = +1)
CLOSED-LOOP BANDWIDTH (G = +1)
2.0
6
1.6
3
DIP Bandwidth
= 366MHz
0.8
0.4
Gain (dB)
Output Voltage (V)
1.2
0
–0.4
0
–3
SO-8 Bandwidth
= 331MHz
–0.8
–1.2
–6
MSOP-8 Bandwidth
= 281MHz
–1.6
–2.0
–9
1M
Time (5ns/div)
10M
100M
1G
Frequency (Hz)
CLOSED-LOOP BANDWIDTH (G = +5)
CLOSED-LOOP BANDWIDTH (G = +2)
20
9
MSOP-8/SO-8/DIP Bandwidth = 108MHz
6
17
3
14
Gain (dB)
Gain (dB)
MSOP-8/SO-8/DIP Bandwidth = 31MHz
0
11
–3
8
–6
5
2
–9
1M
10M
100M
1M
1G
10M
100M
Frequency (Hz)
Frequency (Hz)
®
5
OPA2650
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. RFB = 25Ω for a gain of +1.
OPEN-LOOP GAIN AND PHASE
vs FREQUENCY
CLOSED-LOOP BANDWIDTH (G = +10)
60
23
0
Gain
40
17
Gain (dB)
Gain (dB)
50
MSOP-8/SO-8/DIP Bandwidth = 16MHz
20
+45
14
11
–45
Phase
30
–90
20
–135
10
–180
Phase (°)
26
8
5
0
2
1M
10M
–225
1k
100M
10k
Frequency (Hz)
100k
1M
10M
Frequency (Hz)
100M
1G
HARMONIC DISTORTION
vs TEMPERATURE (G = +1, fO = 5MHz)
HARMONIC DISTORTION vs FREQUENCY
(G = +1, VO = 2Vp-p)
–60
–45
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
–50
–55
–60
–65
–70
–75
–80
3fO
–85
–90
2fO
–95
100k
10M
1M
–65
3fO
–70
2fO
–75
–80
–75
100M
Frequency (Hz)
–50
–25
0
25
5MHz HARMONIC DISTORTION
vs OUTPUT SWING
75
100
125
10MHz HARMONIC DISTORTION
vs OUTPUT SWING
–60
–50
G = +2
Harmonic Distortion (dBc)
G = +2
Harmonic Distortion (dBc)
50
Temperature (°C)
–70
–80
3fO
2fO
–90
–100
–60
3fO
2fO
–70
–80
–90
0.1
1
10
0.1
Output Swing (Vp-p)
®
OPA2650
1
Output Swing (Vp-p)
6
10
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. RFB = 25Ω for a gain of +1.
HARMONIC DISTORTION vs GAIN
(f = 5MHZ, VO = 2Vp-p)
Harmonic Distortion (dBc)
–40
3fO
–50
–60
2fO
–70
–80
1
2
3
4
5
6
7
8
9
10
Non-Inverting Gain (V/V)
APPLICATIONS INFORMATION
opened in all of the ground and power planes. Otherwise,
ground and power planes should be unbroken elsewhere on
the board.
DISCUSSION OF PERFORMANCE
The OPA2650 is a dual low power, wideband voltage feedback operational amplifier. Each channel is internally compensated to provide unity gain stability. The OPA2650’s
voltage feedback architecture features true differential and
fully symmetrical inputs. This minimizes offset errors, making the OPA2650 well suited for implementing filter and
instrumentation designs. As a dual operational amplifier,
OPA2650 is an ideal choice for designs requiring multiple
channels where reduction of board space, power dissipation
and cost are critical. Its AC performance is optimized to
provide a gain bandwidth product of 160MHz and a fast 0.1%
settling time of 11ns, which is an important consideration in
high speed data conversion applications. Along with its
excellent settling characteristics, the low DC input offset of
±1mV and drift of ±3µV/°C support high accuracy requirements. In applications requiring a higher slew rate and wider
bandwidth, such as video and high bit rate digital communications, consider the dual current feedback OPA2658.
b) Minimize the distance (< 0.25") from the two power pins
to high frequency 0.1µF decoupling capacitors. At the pins,
the ground and power plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power and
ground traces to minimize inductance between the pins and
the decoupling capacitors. Larger (2.2µF to 6.8µF) decoupling
capacitors, effective at lower frequencies, should also be
used. These may be placed somewhat farther from the
device and may be shared among several devices in the same
area of the PC board.
c) Careful selection and placement of external components will preserve the high frequency performance of the
OPA2650. Resistors should be a very low reactance type.
Surface mount resistors work best and allow a tighter overall
layout. Metal film or carbon composition axially-leaded
resistors can also provide good high frequency performance.
Again, keep their leads as short as possible. Never use
wirewound type resistors in a high frequency application.
Since the output pin and the inverting input pin are most
sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to
the package pins. Other network components, such as noninverting input termination resistors, should also be placed
close to the package.
Even with a low parasitic capacitance shunting the resistor,
excessively high resistor values can create significant time
constants and degrade performance. Good metal film or
surface mount resistors have approximately 0.2pF in shunt
with the resistor. For resistor values > 1.5kΩ, this adds a
pole and/or zero below 500MHz that can affect circuit
CIRCUIT LAYOUT AND BASIC OPERATION
Achieving optimum performance with a high frequency amplifier like the OPA2650 requires careful attention to layout
parasitics and selection of external components. Recommendations for PC board layout and component selection include:
a) Minimize parasitic capacitance to any ac ground for all
of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability; on the noninverting input it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be
®
7
OPA2650
operation. Keep resistor values as low as possible consistent
with output loading considerations. The 402Ω feedback
used for the Typical Performance Plots is a good starting
point for design. Note that a 25Ω feedback resistor, rather
than a direct short, is suggested for a unity gain follower.
This effectively reduces the Q of what would otherwise be
a parasitic inductance (the feedback wire) into the parasitic
capacitance at the inverting input.
fied total supply voltage of 11V. Higher supply voltages can
break down internal junctions possibly leading to catastrophic
failure. Single supply operation is possible as long as common mode voltage constraints are observed. The common
mode input and output voltage specifications can be interpreted as a required headroom to the supply voltage. Observing this input and output headroom requirement will allow
non-standard or single supply operation. Figure 1 shows one
approach to single-supply operation.
d) Connections to other wideband devices on the board
may be made with short direct traces or through on-board
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50 to 100 mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set RISO from
the plot of recommended RISO vs capacitive load. Low
parasitic loads may not need an RISO since the OPA2650 is
nominally compensated to operate with a 2pF parasitic load.
If a long trace is required and the 6dB signal loss intrinsic to
doubly terminated transmission lines is acceptable, implement a matched impedance transmission line using microstrip
or stripline techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50Ω environment is not necessary on board, and in fact a higher impedance environment will improve distortion as shown in the
distortion vs load plot. With a characteristic impedance
defined based on board material and desired trace dimensions, a matching series resistor into the trace from the
output of the amplifier is used as well as a terminating shunt
resistor at the input of the destination device. Remember
also that the terminating impedance will be the parallel
combination of the shunt resistor and the input impedance of
the destination device; the total effective impedance should
match the trace impedance. Multiple destination devices are
best handled as separate transmission lines, each with their
own series and shunt terminations.
If the 6dB attenuation loss of a doubly terminated line is
unacceptable, a long trace can be series-terminated at the
source end only. This will help isolate the line capacitance
from the op amp output, but will not preserve signal integrity
as well as a doubly terminated line. If the shunt impedance
at the destination end is finite, there will be some signal
attenuation due to the voltage divider formed by the series
and shunt impedances.
e) Sockets are not recommended for high speed parts like
the OPA2650. The additional lead length and pin-to-pin
capacitance introduced by the socket creates an extremely
troublesome parasitic network which can make it almost
impossible to achieve a smooth, stable response. Best results
are obtained by soldering the part onto the board. If socketing for the DIP package is desired, high frequency flush
mount pins (e.g., McKenzie Technology #710C) can give
good results.
+VS
R
VAC
VS
2
VOUT =
VS
+ 2•VAC
2
ROUT
1/2
OPA2650
R
RL
402Ω
402Ω
FIGURE 1. Single Supply Operation.
OFFSET VOLTAGE ADJUSTMENT
If additional offset adjustment is needed, the circuit in
Figure 2 can be used without degrading offset drift with
temperature. Avoid external adjustment whenever possible
since extraneous noise, such as power supply noise, can be
inadvertently coupled into the amplifier’s inverting input
terminal. Remember that additional offset errors can be
created by the amplifier’s input bias currents. Whenever
possible, match the impedance seen by both inputs as is
shown with R3. This will reduce the output offset voltage
caused by the amplifier’s input offset current.
R2
+VCC
RTrim
20kΩ
1/2
OPA2650
47kΩ
–VCC
NOTE: (1) R3 is
optional and can
be used to cancel
offset errors due
to input bias currents.
0.1µF
R1
(1)
R3 = R1 || R2
VIN or Ground
Output Trim Range ≅ +VCC R2
RTrim
SUPPLY VOLTAGES
The OPA2650 is nominally specified for operation using ±5V
power supplies. A 10% tolerance on the supplies, or an ECL
–5.2V for the negative supply, is within the maximum speci-
FIGURE 2. Offset Voltage Trim.
®
OPA2650
+VS
8
to –VCC R2
RTrim
ESD PROTECTION
ESD damage has been well recognized for MOSFET devices, but any semiconductor device is vulnerable to this
potentially damaging source. This is particularly true for
very high speed, fine geometry processes.
ESD damage can cause subtle changes in amplifier input
characteristics without necessarily destroying the device. In
precision operational amplifiers, this may cause a noticeable
degradation of offset voltage and drift. Therefore, ESD
handling precautions are strongly recommended when handling the OPA2650.
supply current for both channels times the total supply
voltage across the part. PDL1 and PDL2 will depend on the
required output signals and loads. For a grounded resistive
loads, and equal bipolar supplies, they would be at a
maximum when the outputs are fixed at a voltage equal to
1/2 either supply voltage. Under this condition, PDL1 = VS2/
(4•RL1) where RL1 includes feedback network loading. P DL2
is calculated the same way.
Note that it is the power in the output stages, and not into
the loads, that determines internal power dissipation.
Operating junction temperature (TJ) is given by TA + PD
θJA, where TA is the ambient temperature.
As an example, compute the maximum TJ for an OPA2650U
where both op amps are at G = +2, RL = 100Ω, RFB = 402Ω,
±VS = ±5V, and at the specified maximum TA = +85°C.
This gives:
OUTPUT DRIVE CAPABILITY
The OPA2650 has been optimized to drive 75Ω and 100Ω
resistive loads. The device can drive 2Vp-p into a 75Ω
load. This high-output drive capability makes the OPA2650
an ideal choice for a wide range of RF, IF, and video
applications. In many cases, additional buffer amplifiers
are unneeded.
P DQ = (10V •17.5mA ) = 175mW
P DL1 = P DL2 =
Many demanding high-speed applications such as driving
A/D converters require op amps with low wideband output
impedance. For example, low output impedance is essential
when driving the signal-dependent capacitances at the inputs
of flash A/D converters. As shown in Figure 3, the OPA2650
maintains very low-closed loop output impedance over frequency. Closed-loop output impedance increases with frequency since loop gain decreases with frequency.
CAPACITIVE LOADS
The OPA2650’s output stage has been optimized to drive low
resistive loads. Capacitive loads, however, will decrease the
amplifier’s phase margin which may cause high frequency
peaking or oscillations. Capacitive loads greater than 10pF
should be isolated by connecting a small resistance, usually
15Ω to 30Ω, in series with the output as shown in Figure 4.
This is particularly important when driving high capacitance
loads such as flash A/D converters. Increasing the gain from
+1 will improve the capacitive load drive due to increased
phase margin.
Output Impedance (Ω)
G = +1
100
10
In general, capacitive loads should be minimized for optimum high frequency performance. Coax lines can be driven
if the cable is properly terminated. The capacitance of coax
cable (29pF/foot for RG-58) will not load the amplifier
when the coaxial cable or transmission line is terminated in
its characteristic impedance.
1
0.1
0.01
1M
10M
= 70mW
T J = 85° C + 0.315W •125° C / W = 124° C
1k
100k
4 • (100Ω || 804Ω )
P D = 175mW + 2 ( 70mW ) = 315mW
SMALL-SIGNAL OUTPUT IMPEDANCE
vs FREQUENCY
10k
(5V )2
100M
Frequency (Hz)
FIGURE 3. Small-Signal Output Impedance vs Frequency.
25Ω
THERMAL CONSIDERATIONS
The OPA2650 will not require heatsinking under most
operating conditions. Maximum desired junction temperature will set a maximum allowed internal power dissipation
as described below. In no case should the maximum junction
temperature be allowed to exceed 175°C.
(RISO typically 15Ω to 30Ω)
RISO
OPA2650
RL
The total internal power dissipation (PD) is a the sum of
quiescent power (PDQ) and additional power dissipated in
the two output stages (PDL1 and PDL2) while delivering load
power. Quiescent power is simply the specified no-load
CL
FIGURE 4. Driving Capacitive Loads.
®
9
OPA2650
FREQUENCY RESPONSE COMPENSATION
Each channel of the OPA2650 is internally compensated to
be stable at unity gain with a nominal 60° phase margin.
This lends itself well to wideband integrator and buffer
applications. Phase margin and frequency response flatness
will improve at higher gains. Recall that an inverting gain of
–1 is equivalent to a gain of +2 for bandwidth purposes, i.e.,
noise gain = 2. The external compensation techniques developed for voltage feedback op amps can be applied to this
device. For example, in the non-inverting configuration,
placing a capacitor across the feedback resistor will reduce
the gain to +1 starting at f = (1/2πRFCF). Alternatively, in the
inverting configuration, the bandwidth may be limited without modifying the inverting gain by placing a series RC
network to ground on the inverting node. This has the effect
of increasing the noise gain at high frequencies, thereby
limiting the bandwidth for the inverting input signal through
the gain-bandwidth product.
At higher gains, the gain-bandwidth of this voltage feedback
topology will limit bandwidth according to the open-loop
frequency response curve. For applications requiring a wider
bandwidth at higher gains, consider the dual current feedback model, OPA2658. In applications where a large feedback resistor is required (such as photodiode transimpedance
circuits), precautions must be taken to avoid gain peaking
due to the pole formed by the feedback resistor and the
capacitance on the inverting input. This pole can be compensated by connecting a small capacitor in parallel with the
feedback resistor, creating a cancelling zero term. In other
high-gain applications, use of a three-resistor “T” connection will reduce the feedback network impedance which
reacts with the parasitic capacitance at the summing node.
The percentage change in closed-loop gain over a specified
change in output voltage level is defined as dG. dP is defined
as the change in degrees of the closed-loop phase over the
same output voltage change. dG and dP are both specified at
the NTSC sub-carrier frequency of 3.58MHz. dG and dP
increase closed-loop gain and output voltage transition. All
measurements were performed using a Tektronix model
VM700 Video Measurement Set.
PULSE SETTLING TIME
FIGURE 5. 5MHz Harmonic Distortion vs Load Resistance.
DISTORTION
The OPA2650’s harmonic distortion characteristics into a
100Ω load are shown versus frequency and power output in
the typical performance curves. Distortion can be significantly improved by increasing the load resistance as illustrated in Figure 5. Remember to include the contribution of
the feedback resistance when calculating the effective load
resistance seen by the amplifier.
–60
Harmonic Distortion (dBc)
(G = +1, fO = 5MHz)
2fO
–80
3fO
–90
10
20
50
100
200
500
1k
Load Resistance (Ω)
High speed amplifiers like the OPA2650 are capable of
extremely fast settling time with a pulse input. Excellent
frequency response flatness and phase linearity are required
to get the best settling times. As shown in the specifications
table, settling time for a 2V step at a gain of +1 for the
OPA2650 is extremely fast. The specification is defined as
the time required, after the input transition, for the output to
settle within a specified error band around its final value. For
a 2V step, 1% settling corresponds to an error band of
±20mV, 0.1% to an error band of ±2mV, and 0.01% to an
error band of ±0.2mV. For the best settling times, particularly into an ADC capacitive load, little or no peaking in the
frequency response can be allowed. Using the recommended
RISO for capacitive loads will limit this peaking and reduce
the settling times. Fast, extremely fine scale settling (0.01%)
requires close attention to ground return currents in the
supply decoupling capacitors. For highest performance, consider the OPA642 which offers considerably higher open
loop DC gain.
CROSSTALK
Crosstalk is the undesired result of the signal of one channel
mixing with and reproducing itself in the output of the other
channel. Crosstalk occurs in most multichannel integrated
circuits. In dual devices, the effect of crosstalk is measured by
driving one channel and observing the output of the undriven
channel over various frequencies. The magnitude of this effect
is referenced in terms of channel-to-channel crosstalk and
expressed in decibels. “Input referred” points to the fact that
there is a direct correlation between gain and crosstalk, therefore at increased gain, crosstalk also increases by a factor
equal to that of the gain. Figure 6 illustrates the measured
effect of crosstalk in the OPA2650U.
SPICE MODELS
Computer simulation of circuit performance using SPICE is
often useful when analyzing the performance of analog
circuits and systems. This is particularly true for Video and
RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. SPICE
models are available on a disk from the Burr-Brown Applications Department.
DIFFERENTIAL GAIN AND PHASE
Differential Gain (dG) and Differential Phase (dP) are among
the more important specifications for video applications.
®
OPA2650
–70
10
DEMONSTRATION BOARDS
Demonstration boards are available for each OPA2650 package style. These boards implement a very low parasitic
layout that will produce the excellent frequency and pulse
responses shown in the Typical Performance Curves. For
each package style, the recommended demonstration boards
are:
0
G = +1
–10
Crosstalk (dB)
–20
–30
–40
–50
–60
–70
DEMONSTRATION BOARD
PACKAGE
PRODUCT
–80
DEM-OPA265xP
8-Pin DIP
OPA2650P
OPA2650PB
DEM-OPA265xU
SO-8
OPA2650U
OPA2650UB
DEM-OPA26xxE
MSOP-8
OPA2650E
–90
–100
1M
10M
100M
400M
Frequency (Hz)
Contact your local Burr-Brown sales office or distributor to
order demonstration boards.
FIGURE 6. Channel-to-Channel Crosstalk.
TYPICAL APPLICATION
402Ω
402Ω
75Ω Transmission Line
75Ω
1/2
OPA2650
VOUT
Video
Input
75Ω
75Ω
FIGURE 7. Low Distortion Video Amplifier.
®
11
OPA2650
R12
J5
R13
–InB
R11
C3
2.2µF
R16
1
+5V
2
C1
0.1µF
GND
P1
6
R9
J4
5
+InB
R8
7
R14
1
R1
J6
OutB
R10
R3
J2
8
1/2
OPA2650
R4
–InA
R2
R15
2
R6
J3
3
+InA
1/2
OPA2650
4
J1
OutA
1
R5
R7
C2
0.1µF
GND
2
–5V
P2
C4
2.2µF
FIGURE 8. Circuit Detail for DEM-OPA265xP Demonstration Board.
DEM-OPA265xP Demonstration Board Layout
(A)
(B)
(C)
(D)
FIGURE 9. Evaluation Board Silkscreen (Solder Side). 9b. Evaluation Board Silkscreen (Component Side). 9c. Evaluation
Board Layout (Solder Side). 9d. Evaluation Board (Component Side).
®
OPA2650
12
IMPORTANT NOTICE
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
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Copyright  2000, Texas Instruments Incorporated
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