HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM Features ◆ ◆ ◆ ◆ ◆ True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Military: 25/35/55ns (max.) – Industrial: 55ns (max.) – Commercial: 20/25/35/55ns (max.) Low-power operation – IDT7008S Active: 750mW (typ.) Standby: 5mW (typ.) – IDT7008L Active: 750mW (typ.) Standby: 1mW (typ.) Dual chip enables allow for depth expansion without external logic ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ IDT7008S/L IDT7008 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port TTL-compatible, single 5V (±10%) power supply Available in 84-pin PGA, 84-pin PLCC, and a 100-pin TQFP Industrial temperature range (–40°C to +85°C) is available for selected speeds Functional Block Diagram R/WL CE0L CE1L OEL R/WR CE0R CE1R OE R I/O Control I/O0-7L I/O Control I/O0-7R (1,2) (1,2) BUSYL A15L A0L BUSY R 64Kx8 MEMORY ARRAY 7008 Address Decoder 16 CE0L CE1L OEL R/W L Address Decoder A15R A0R 16 ARBITRATION INTERRUPT SEMAPHORE LOGIC SEML (2) INTL (1) M/S NOTES: 1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull). CE0R CE1R OER R/WR SEM R (2) INT R 3198 drw 01 MAY 2000 1 ©2000 Integrated Device Technology, Inc. DSC 3198/6 IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Description The IDT7008 is a high-speed 64K x 8 Dual-Port Static RAM. The IDT7008 is designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by the chip enables (CE0 and CE1) permit the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 750mW of power. The IDT7008 is packaged in a 84-pin Ceramic Pin Grid Array (PGA), a 84-pin Plastic Leadless Chip Carrier (PLCC) and a 100-pin Thin Quad Flatpack (TQFP). INDEX 11 10 9 12 13 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 73 14 72 15 71 70 16 17 69 18 19 20 21 22 23 IDT7008J J84-1(4) 84-Pin PLCC Top View(5) 68 67 66 65 64 63 25 62 61 26 60 27 28 59 24 29 58 57 30 56 NOTES: 1. This text does not indicate orientation of the actual part marking. 2. All Vcc pins must be connected to power supply. 3. Package body is approximately 1.15 in x 1.15 in x .17 in. 4. This package code is used to reference the package diagram. 5. All GND pins must be connected to ground supply. 2 GND NC 55 31 54 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 A7L A8L A9L A10L A11L A12L A13L A14L A15L NC Vcc NC NC CE0L CE1L SEML RIWL OEL GND A6R A5R A4R A3R A2R A1R A0R INTR BUSYR M/S GND BUSYL INTL NC A0L A1L A2L A3L A4L A5L A6L GND NC A7R A8R A9R A10R A11R A12R A13R A14R A15R NC GND NC NC CE0R CE1R SEMR R/WR OER GND Pin Configurations(1,2,3) NC I/O7R I/O6R I/O5R I/O4R I/O3R Vcc I/O2R I/O1R I/O0R GND Vcc I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L , 3198 drw 02 IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges NC NC A6L A5L A4L A3L A2L A1L A0L NC INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A5R A6R NC NC Pin Configurations(1,2,3) (con't.) Index NC NC A7L A8L A9L A10L A11L A12L A13L A14L A15L NC Vcc NC NC NC NC CE0L CE1L SEML R/WL OEL GND NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 72 5 71 6 70 7 69 8 68 67 9 IDT7008PF PN100-1(4) 10 11 66 65 64 12 100-Pin TQFP Top View(5) 13 63 15 62 61 16 60 17 59 18 58 19 57 20 56 21 55 22 54 23 53 14 52 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 24 NC NC A7R A8R A9R A10R A11R A12R A13R A14R A15R NC GND NC NC NC NC CE0R CE1R SEMR R/WR OER GND GND NC , GND NC I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L Vcc GND I/O0R I/O1R I/O2R Vcc I/O3R I/O4R I/O5R I/O6R I/O7R NC NC NC 3198 drw 03 NOTES: 1. This text does not indicate orientation of the actual part marking. 2. All Vcc pins must be connected to power supply. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. All GND pins must be connected to ground supply. 3 6.42 IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Pin Configurations(1,2,3) (con't) 63 11 61 A7R 64 66 A4R 10 CE0R 45 OER 44 R/WR 43 GND 52 IDT7008G G84-3(4) 32 84-Pin PGA Top View(5) 78 80 79 A1L 81 82 7 A5L 1 A4L 84 2 A7L 3 A6L A 5 A8L 4 A9L B 11 8 A11L 6 10 A14L 9 A10L A12L C D 12 14 15 A15L E I/O6L 17 CE0L NC 13 22 20 R/WL 16 GND 18 NC SEML OEL F G H J I/O4L 24 I/O7L 19 CE1L I/O2L 25 23 NC Vcc A13L I/O0L 27 I/O3L 83 Vcc 30 I/O1L 26 A2L A3L Vcc 29 GND I/O1R 36 31 28 A0L NC I/O3R 34 I/O2R GND GND I/O5R 37 35 I/O0R 74 A0R INTL 33 M/S I/O6R 39 I/O7R 73 NC 40 NC 41 NC GND 42 GND I/O4R INTR 77 76 01 46 SEMR 47 50 CE1R 53 A13R 48 NC 38 70 75 02 49 A14R 57 71 06 BUSYL 03 56 A11R 51 NC A2R BUSYR 04 59 A8R 54 A15R A5R A1R 72 05 55 A12R 68 69 07 62 A6R A3R 08 58 A10R 65 67 09 60 A9R I/O5L 21 GND K NC , L 3198 drw 04 INDEX NOTES: 1. All Vcc pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately 1.12 in x 1.12 in x .16 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part marking. Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A15L A0R - A15R Address I/O0L - I/O7L I/O0R - I/O7R Data Input/Output SEML SEMR Semaphore Enable INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag M/S Master or Slave Select VCC Power GND Ground 3198 tbl 01 4 IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Truth Table I: Chip Enable(1) CE CE0 CE1 VIL VIH < 0.2V >VCC -0.2V Port Selected (CMOS Active) VIH X Port Deselected (TTL Inactive) X VIL Port Deselected (TTL Inactive) >VCC -0.2V X Port Deselected (CMOS Inactive) X <0.2V Port Deselected (CMOS Inactive) L H Mode Port Selected (TTL Active) 3198 tbl 02 NOTES: 1. Chip Enable references are shown above with the actual CE0 and CE1 levels, CE is a reference only. Truth Table II: Non-Contention Read/Write Control Inputs(1) Outputs R/W OE SEM I/O0-7 H X X H High-Z Deselected: Power-Down L L X H DATA IN Write to memory L H L H DATAOUT X X H X High-Z CE (2) Mode Read memory Outputs Disabled 3198 tbl 03 NOTES: 1. A0L – A15L ≠ A0R – A15R. 2. Refer to Chip Enable Truth Table. Truth Table III: Semaphore Read/Write Control(1) Inputs CE Outputs R/W OE SEM I/O0-7 H H L L DATAOUT Read Semaphore Flag Data Out H ↑ X L DATAIN Write I/O0 into Semaphore Flag L ______ (2) L X X Mode Not Allowed NOTES: 1. There are eight semaphore flags written to via I/O0 and read from all the I/Os (I/O0-I/O7). These eight semaphore flags are addressed by A0-A2. 2. Refer to Chip Enable Truth Table. 5 6.42 3198 tbl 04 IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Absolute Maximum Ratings(1) Symbol Rating Commercial & Industrial Military Unit Terminal Voltage with Respect to GND -0.5 to +7.0 -0.5 to +7.0 V Temperature Under Bias -55 to +125 Recommended DC Operating Conditions Symbol VTERM(2) TBIAS TSTG Storage Temperature IOUT DC Output Current -65 to +135 -65 to +150 -65 to +150 50 50 o o C C VCC Supply Voltage GND Ground Military Commercial Industrial GND Vcc -55 C to+125 C 0V 5.0V + 10% 0OC to +70OC 0V 5.0V + 10% -40OC to +85OC 0V 5.0V + 10% Unit 4.5 5.0 5.5 V 0 0 0 V Input High Voltage 2.2 ____ VIL Input Low Voltage -0.5(1) ____ (2) 6.0 0.8 V V Capacitance (TA = +25°C, f = 1.0mhz) (TQFP Only) Maximum Operating Temperature and Supply Voltage(1,2) O Max. VIH S ym b o l O Typ. NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%. 3198 tbl 05 Ambient Temperature Min. 3198 tbl 07 mA NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%. Grade Parameter P aram eter(1) CIN Input Capacitance COUT Output Capacitance Condi ti ons(2) M ax. Uni t VIN = 3dV 9 pF VOUT = 3dV 10 pF 3198 tbl 08 NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. 3198 tbl 06 NOTES: 1. This is the parameter TA. This is the "instant on" case tempreature. 2. Industrial Temperature: for other speeds, packages and powers contact your sales office. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(2) (VCC = 5.0V ± 10%) 7008S Symbol Min. Max. Min. Max. Unit |ILI| Input Leakage Current(1) VCC = 5.5V, VIN = 0V to V CC ___ 10 ___ 5 µA |ILO | Output Leakage Current CE = VIH, VOUT = 0V to V CC ___ 10 ___ 5 µA IOL = 4mA ___ 0.4 ___ 0.4 V 2.4 ___ 2.4 ___ VOL V OH Parameter Output Low Voltage Output High Voltage Test Conditions 7008L IOH = -4mA V 3198 tbl 09 NOTES: 1. At Vcc < 2.0V, input leakages are undefined. 2. Refer to Chip Enable Truth Table. 6 IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,6,7) (VCC = 5.0V ± 10%) 7008X20 Com'l Only Symbol ICC ISB1 ISB2 ISB3 ISB4 Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - All CMOS Level Inputs) Full Standby Current (One Port - All CMOS Level Inputs) Test Condition CE = VIL , Outputs Disabled SEM = V IH f = fMAX (3) CEL = CER = VIH SEMR = SEML = VIH f = fMAX (3) CE"A" = V IL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX (3) SEMR = SEML = V IH Both Ports CEL and CER > VCC - 0.2V V IN > V CC - 0.2V or V IN < 0.2V, f = 0(4) SEMR = SEML > VCC - 0.2V CE"A" < 0.2V and CE"B" > V CC - 0.2V(5) SEMR = SEML > VCC - 0.2V V IN > V CC - 0.2V or V IN < 0.2V Active Port Outputs Disabled f = fMAX (3) Version 7008X25 Com'l & Military Typ.(2) Max. Typ.(2) Max. Unit mA COM'L S L 190 180 325 285 180 170 305 265 MIL & IND S L ___ ___ ___ ___ 170 170 345 305 COM'L S L 50 50 90 70 40 40 85 60 MIL & IND S L ___ ___ ___ ___ 40 40 100 80 COM'L S L 115 115 215 185 105 105 200 170 MIL & IND S L ___ ___ ___ ___ 105 105 230 200 COM'L S L 1.0 0.2 15 5 1.0 0.2 15 5 MIL & IND S L ___ ___ ___ ___ 1.0 0.2 30 10 COM'L S L 110 110 190 160 100 100 170 145 MIL & IND S L ___ ___ ___ ___ 100 100 200 175 mA mA mA mA 3198 tbl 10a 7008X35 Com'l & Military Symbol ICC ISB1 ISB2 ISB3 ISB4 Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - All CMOS Level Inputs) Full Standby Current (One Port - All CMOS Level Inputs) Test Condition CE = VIL , Outputs Disabled SEM = V IH f = fMAX (3) CEL = CER = VIH SEMR = SEML = VIH CE"A" = V IL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX (3) SEMR = SEML = V IH Both Ports CEL and CER > VCC - 0.2V V IN > V CC - 0.2V or V IN < 0.2V, f = 0(4) SEMR = SEML > VCC - 0.2V CE"A" < 0.2V and CE"B" > V CC - 0.2V(5) SEMR = SEML > VCC - 0.2V V IN > V CC - 0.2V or V IN < 0.2V Active Port Outputs Disabled f = fMAX (3) Version 7008X55 Com'l, Ind & Military Typ.(2) Max. Typ.(2) Max. Unit mA COM'L S L 160 160 295 255 150 150 270 230 MIL & IND S L 160 160 335 295 150 150 310 270 COM'L S L 30 30 85 60 20 20 85 60 MIL & IND S L 20 20 100 80 13 13 100 80 COM'L S L 95 95 185 155 85 85 165 135 MIL & IND S L 95 95 215 185 85 85 195 165 COM'L S L 1.0 0.2 15 5 1.0 0.2 15 5 MIL & IND S L 1.0 0.2 30 10 1.0 0.2 30 10 COM'L S L 90 90 160 135 80 80 135 110 MIL & IND S L 90 90 190 165 80 80 175 150 mA mA mA mA 3198 tbl 10b NOTES: 1. 'X' in part numbers indicates power rating (S or L) 2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.) 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 6. Refer to Chip Enable Truth Table. 7. Industrial Temperature: for other speeds, packages and powers contact your sales office. 7 6.42 IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges AC Test Conditions 5V Input Pulse Levels GND to 3.0V Input Rise/Fall Times 893Ω 5ns Max. Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load 5V DATAOUT BUSY INT 893Ω DATAOUT 30pF 347Ω 347Ω 5pF* Figures 1 and 2 3198 tbl 11 3198 drw 05 3198 drw 06 Figure 1. AC Output Test Load Figure 2. Output Test Load (for t LZ, tHZ, tWZ, tOW) * Including scope and jig. Waveform of Read Cycles(5) tRC ADDR (4) tAA (4) tACE CE(6) tAOE (4) OE R/W tLZ tOH (1) (4) DATAOUT VALID DATA tHZ (2) BUSYOUT tBDD (3,4) 3198 drw 07 Timing of Power-Up Power-Down CE ICC (6) tPU tPD ISB 3198 drw 08 , NOTES: 1. Timing depends on which signal is asserted last, OE or CE. 2. Timing depends on which signal is de-asserted first CE or OE. 3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no relation to valid output data. 4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD . 5. SEM = VIH. 6. Refer to Chip Enable Truth Table. 8 IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6,7) 7008X20 Com'l Only Symbol Parameter 7008X25 Com'l & Military 7008X35 Com'l & Military 7008X55 Com'l, Ind & Military Min. Max. Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 20 ____ 25 ____ 35 ____ 55 ____ ns tAA Address Access Time ____ 20 ____ 25 ____ 35 ____ 55 ns tACE tAOE tOH (4) ____ 20 ____ 25 ____ 35 ____ 55 ns Output Enable Access Time ____ 12 ____ 13 ____ 20 ____ 30 ns 3 ____ 3 ____ 3 ____ 3 ____ ns 3 ____ 3 ____ 3 ____ 3 ____ ns ____ 12 ____ 15 ____ 15 ____ 25 ns 0 ____ 0 ____ 0 ____ 0 ____ ns ____ 20 ____ 25 ____ 35 ____ 50 ns 12 ____ 15 ____ 15 ____ ns ____ 25 ____ 35 ____ 55 ns Chip Enable Access Time Output Hold from Address Change (1,2) tLZ Output Low-Z Time tHZ Output High-Z Time (1,2) tPU Chip Enab le to Power Up Time (2) (2) tPD Chip Disable to Power Down Time tSOP Semaphore Flag Update Pulse (OE or SEM) 10 ____ tSAA Semaphore Address Access Time ____ 20 3198 tbl 12 AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(6,7) 7008X20 Com'l Only Symbol Parameter 7008X25 Com'l & Military 7008X35 Com'l & Military 7008X55 Com'l, Ind & Military Min. Max. Min. Max. Min. Max. Min. Max. Unit WRITE CYCLE tWC Write Cycle Time 20 ____ 25 ____ 35 ____ 55 ____ ns tEW Chip Enable to End-of-Write (3) 15 ____ 20 ____ 30 ____ 45 ____ ns 15 ____ 20 ____ 30 ____ 45 ____ ns 0 ____ 0 ____ 0 ____ 0 ____ ns 15 ____ 20 ____ 25 ____ 40 ____ ns ns tAW tAS tWP Address Valid to End-of-Write Address Set-up Time (3) Write Pulse Width tWR Write Recovery Time 0 ____ 0 ____ 0 ____ 0 ____ tDW Data Valid to End-of-Write 15 ____ 15 ____ 15 ____ 30 ____ ns ____ 12 ____ 15 ____ 15 ____ 25 ns 0 ____ 0 ____ 0 ____ 0 ____ ns ____ 12 ____ 15 ____ 15 ____ 25 ns 0 ____ 0 ____ 0 ____ 0 ____ ns 5 ____ 5 ____ 5 ____ 5 ____ ns 5 ____ 5 ____ 5 ____ 5 ____ tHZ tDH tWZ Output High-Z Time Data Hold Time (1,2) (5) (1,2) Write Enable to Output in High-Z tOW Output Active from End-of-Write tSWRD SEM Flag Write to Read Time tSPS SEM Flag Contention Window (1,2,5) ns 3198 tbl 13 NOTES: 1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranted by device characterization, but is not production tested. 3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. 4. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE= VIH and SEM = VIL. 5. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 6. 'X' in part numbers indicates power rating (s or L). 7. Industrial Temperature: for other speeds, packages and powers contact your sales office. 9 6.42 IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8) tWC ADDRESS tHZ (7) OE tAW (9,10) CE or SEM tWP (2) tAS(6) tWR (3) R/W tWZ (7) DATAOUT tOW (4) (4) tDW tDH DATAIN 3198 drw 09 Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5) tWC ADDRESS tAW CE or SEM(9,10) tAS (6) (3) tEW (2) tWR R/W tDW tDH DATAIN 3198 drw 10 NOTES: 1. R/W or CE must be HIGH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + t DW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP . 9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition. 10. Refer to Chip Enable Truth Table. 10 IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Semaphore Read after Write Timing, Either Side(1) tSAA A0-A2 VALID ADDRESS tAW tOH VALID ADDRESS tWR tACE tEW SEM tDW tSOP DATAOUT VALID(2) DATAIN VALID DATA0 tAS tWP tDH R/W tSWRD OE tAOE tSOP Write Cycle Read Cycle 3198 drw 11 NOTES: 1. CE = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table). 2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O15 ) equal to the semaphore value. Timing Waveform of Semaphore Write Contention(1,3,4) A0"A"-A2"A" (2) SIDE "A" MATCH R/W"A" SEM"A" tSPS A0"B"-A2"B" (2) SIDE "B" MATCH R/W"B" SEM"B" 3198 drw 12 NOTES: 1. DOR = DOL = VIL, CEL = CE R = VIH (Refer to Chip Enable Truth Table). 2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A". 3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH. 4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag. 11 6.42 IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6,7) 7008X20 Com'l Only Symbol Parameter 7008X25 Com'l & Military 7008X35 Com'l & Military 7008X55 Com'l, Ind & Military Min. Max. Min. Max. Min. Max. Min. Max. Unit BUSY TIMING (M/S=V IH) tBAA BUSY Access Time from Address Match ____ 20 ____ 20 ____ 20 ____ 45 ns tBDA BUSY Disable Time from Address Not Matched ____ 20 ____ 20 ____ 20 ____ 40 ns tBAC BUSY Access Time from Chip Enable Low ____ 20 ____ 20 ____ 20 ____ 40 ns tBDC BUSY Access Time from Chip Enable High ____ 17 ____ 17 ____ 20 ____ 35 ns tAPS Arbitration Priority Set-up Time (2) 5 ____ 5 ____ 5 ____ 5 ____ ns tBDD BUSY Disable to Valid Data ____ 20 ____ 25 ____ 35 ____ 55 ns tWH Write Hold After BUSY(5) 15 ____ 17 ____ 25 ____ 25 ____ ns 0 ____ 0 ____ 0 ____ 0 ____ ns 15 ____ 17 ____ 25 ____ 25 ____ ns ____ 45 ____ 50 ____ 60 ____ 80 ns 30 ____ 35 ____ 45 ____ 65 ns (3) BUSY TIMING (M/S=V IL) tWB BUSY Input to Write (4) tWH Write Hold After BUSY (5) PORT-TO-PORT DELAY TIMING tWDD tDDD Write Pulse to Data Delay (1) Write Data Valid to Read Data Delay (1) ____ 3198 tbl 14 NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or t DDD – tDW (actual). 4. To ensure that the write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. 'X' in part numbers indicates power rating (S or L). 7. Industrial Temperature: for other speeds, packages and powers contact your sales office. 12 IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Timing Waveform of Write with Port-to-Port Read and BUSY(2,5) (M/S = VIH)(4) tWC ADDR"A" MATCH tWP R/W"A" tDH tDW DATAIN "A" VALID tAPS (1) ADDR"B" MATCH tBDA tBDD BUSY"B" tWDD DATAOUT "B" VALID tDDD (3) NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE). 2. CEL = CER = VIL, refer to Chip Enable Truth Table. 3. OE = VIL for the reading port. 4. If M/S = VIL (SLAVE), then BUSY is an input (BUSY"A" = VIH and BUSY"B" = "don't care", for this example). 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". Timing Waveform of Write with BUSY (M/S = VIL) tWP R/W"A" tWB(3) BUSY"B" tWH (1) R/W"B" (2) 3198 drw 14 NOTES: 1. tWH must be met for both BUSY input (SLAVE) and output (MASTER). 2. BUSY is asserted on port "B" blocking R/W"B" , until BUSY"B" goes HIGH. 3. tWB is only for the 'Slave' version. 13 6.42 3198 drw 13 IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Waveform of BUSY Arbitration Controlled by CE Timing(1,3) (M/S = VIH) ADDR"A" and "B" ADDRESSES MATCH CE"A" tAPS (2) CE"B" tBAC tBDC BUSY"B" 3198 drw 15 Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing(1) (M/S = VIH) ADDR"A" ADDRESS "N" tAPS (2) ADDR"B" MATCHING ADDRESS "N" tBAA tBDA BUSY"B" 3198 drw 16 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. 2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted. 3. Refer to Chip Enable Truth Table. AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,2) 7008X20 Com'l Only Symbol Parameter 7008X25 Com'l & Military 7008X35 Com'l & Military 7008X55 Com'l, Ind & Military Min. Max. Min. Max. Min. Max. Min. Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ 0 ____ ns 20 ____ 20 ____ 25 ____ 40 ns 20 ____ 20 ____ 25 ____ 40 ns tINS Interrupt Set Time ____ tINR Interrupt Reset Time ____ NOTES: 1. 'X' in part numbers indicates power rating (S or L). 2. Industrial Temperature: for other speeds, packages and powers contact your sales office. 14 3198 tbl 15 IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Waveform of Interrupt Timing(1,5) tWC ADDR"A" INTERRUPT SET ADDRESS (2) (3) tAS tWR (4) CE"A" R/W"A" tINS (3) INT"B" 3198 drw 17 tRC ADDR"B" INTERRUPT CLEAR ADDRESS (2) tAS(3) CE"B" OE"B" tINR (3) INT"B" 3198 drw 18 NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. 2. See Interrupt Truth Table. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. 5. Refer to Chip Enable Truth Table. Truth Table IV Interrupt Flag(1,4,5) Left Port R/WL L X X X CE L X X L OEL X X X L Right Port A15L-A0L FFFF INTL X R/WR X CE X OER X A15R-A0R X INTR Function (2) Set Right INTR Flag (3) L X X X L L FFFF H Reset Right INTR Flag X (3) L L X FFFE X Set Left INTL Flag (2) X X X X X Reset Left INTL Flag FFFE L H 3198 tbl 16 NOTES: 1. Assumes BUSYL = BUSYR =VIH. 2. If BUSYL = V IL, then no change. 3. If BUSYR = VIL, then no change. 4. INTL and INTR must be initialized at power-up. 5. Refer to Chip Enable Truth Table. 15 6.42 IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Truth Table V Address BUSY Arbitration(4) Inputs Outputs CEL CER A OL-A15L AOR -A15R BUSYL(1) BUSYR(1) Function X X NO MATCH H H Normal H X MATCH H H Normal X H MATCH H H Normal L L MATCH (2) (2) Write Inhibit(3) 3198 tbl 17 NOTES: 1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7008 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSY R = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously. 3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when BUSYR outputs are driving LOW regardless of actual logic level on the pin. 4. Refer to Chip Enable Truth Table. Truth Table VI Example of Semaphore Procurement Sequence(1,2,3) Functions D0 - D7 Left D0 - D7 Right Status No Action 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token Right Port Writes "1" to Semaphore 1 1 Semaphore free Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token Left Port Writes "1" to Semaphore 1 1 Semaphore free NOTES: 1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7008. 2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0-A2. 3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table. 3198 tbl 18 Functional Description The IDT7008 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT7008 has an automatic power down feature controlled by CE. The CE0 and CE1 control the on-chip power down circuitry that permits the respective port to go into a standby mode when not selected (CE HIGH). When a port is enabled, access to the entire memory array is permitted. Interrupts If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location FFFE (HEX), where a write is defined as CER = R/WR = VIL per the Truth Table. The left port clears the interrupt through access of address location FFFE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location FFFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location FFFF. The message (8 bits) at FFFE or FFFF is userdefined since it is an addressable SRAM location. If the interrupt function is not used, address locations FFFE and FFFF are not used as mail boxes, but as part of the random access memory. Refer to Table IV for the interrupt operation. 16 IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Busy Logic Busy Logic provides a hardware indication that both ports of the RAM have accessed the same location at the same time. It also allows one of the two accesses to proceed and signals the other side that the RAM is “busy”. The BUSY pin can then be used to stall the access until the operation on the other side is completed. If a write operation has been attempted from the side that receives a BUSY indication, the write signal is gated internally to prevent the write from proceeding. The use of BUSY logic is not required or desirable for all applications. In some cases it may be useful to logically OR the BUSY outputs together and use any BUSY indication as an interrupt source to flag the event of an illegal or illogical operation. If the write inhibit function of BUSY logic is not desirable, the BUSY logic can be disabled by placing the part in slave mode with the M/S pin. Once in slave mode the BUSY pin operates solely as a write inhibit input pin. Normal operation can be programmed by tying the BUSY pins HIGH. If desired, unintended write operations can be prevented to a port by tying the BUSY pin for that port LOW. The BUSY outputs on the IDT7008 RAM in master mode, are pushpull type outputs and do not require pull up resistors to operate. If these RAMs are being expanded in depth, then the BUSY indication for the resulting array requires the use of an external AND gate. A16 CE0 MASTER Dual Port RAM CE0 SLAVE Dual Port RAM BUSY (L) BUSY (R) BUSY (L) BUSY (R) CE1 MASTER Dual Port RAM CE1 SLAVE Dual Port RAM BUSY (L) BUSY (R) BUSY (L) BUSY (R) , 3198 drw 19 Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7008 RAMs. Width Expansion Busy Logic Master/Slave Arrays When expanding an IDT7008 RAM array in width while using BUSY logic, one master part is used to decide which side of the RAMs array will receive a BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT7008 RAM the BUSY pin is an output if the part is used as a master (M/S pin = VIH), and the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown in Figure 3. If two or more master parts were used when expanding in width, a split decision could result with one master indicating BUSY on one side of the array and another master indicating BUSY on one other side of the array. This would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. The BUSY arbitration, on a master, is based on the chip enable and address signals only. It ignores whether an access is a read or write. In a master/slave array, both address and chip enable must be valid long enough for a BUSY flag to be output from the master before the actual write pulse can be initiated with the R/W signal. Failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. Semaphores The IDT7008 is an extremely fast Dual-Port 64K x 8 CMOS Static RAM with an additional 8 address locations dedicated to binary semaphore flags. These flags allow either processor on the left or right side of the Dual-Port RAM to claim a privilege over the other processor for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the Dual-Port RAM or any other shared resource. The Dual-Port RAM features a fast access time, and both ports are completely independent of each other. This means that the activity on the left port in no way slows the access time of the right port. Both ports are identical in function to standard CMOS Static RAM and can be read from, or written to, at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous READ/WRITE of, a nonsemaphore location. Semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the Dual-Port RAM. These devices have an automatic power-down feature controlled by CE, the Dual-Port RAM enable, and SEM, the semaphore enable. The CE and SEM pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. This is the condition which is shown in Truth Table II where CE and SEM are both HIGH. Systems which can best use the IDT7008 contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. These systems can benefit from a per-formance increase offered by the IDT7008s hardware semaphores, which provide a lockout mechanism without requiring complex programming. Software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated in varying configurations. The IDT7008 does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. An advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. This can prove to be a major advantage in very highspeed systems. How the Semaphore Flags Work The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphores provide a hardware assist for a use assignment method called “Token Passing Allocation.” In this method, the state of a semaphore latch is used as a token indicating that shared resource is in use. If the left processor wants to use this resource, it requests the token by setting the latch. This processor then verifies its success in setting the latch by reading it. If it was successful, it proceeds to assume control over the shared resource. If it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. The left processor can then either repeatedly request that semaphore’s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via 17 6.42 IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM the set and test sequence. Once the right side has relinquished the token, the left side should succeed in gaining control. The semaphore flags are active LOW. A token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. The eight semaphore flags reside within the IDT7008 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, CE, and R/W) as they would be used in accessing a standard Static RAM. Each of the flags has a unique address which can be accessed by either side through address pins A0 – A2. When accessing the semaphores, none of the other address pins has any effect. When writing to a semaphore, only data pin D0 is used. If a LOW level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see Table VI). That semaphore can now only be modified by the side showing the zero. When a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. The fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (A thorough discussion on the use of this feature follows shortly.) A zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. When a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros. The read value is latched into one side’s output register when that side's semaphore select (SEM) and output enable (OE) signals go active. This serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. Because of this latch, a repeated read of a semaphore in a test loop must cause either signal (SEM or OE) to go inactive or the output will never change. A sequence WRITE/READ must be used by the semaphore in order to guarantee that no system level contention will occur. A processor requests access to shared resources by attempting to write a zero into a semaphore location. If the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see Table VI). As an example, assume a processor writes a zero to the left port at a free semaphore location. On a subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in question. Meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right Military, Industrial and Commercial Temperature Ranges side during subsequent read. Had a sequence of READ/WRITE been used instead, system contention problems could have occurred during the gap between the read and write cycles. It is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. The reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag LOW and the other side HIGH. This condition will continue until a one is written to the same semaphore request latch. Should the other side’s semaphore request latch have been written to a zero in the meantime, the semaphore flag will flip L PORT R PORT SEMAPHORE REQUEST FLIP FLOP D0 D Q SEMAPHORE REQUEST FLIP FLOP Q D WRITE SEMAPHORE READ D0 WRITE SEMAPHORE READ 3198 drw 20 Figure 4. IDT7008 Semaphore Logic over to the other side as soon as a one is written into the first side’s request latch. The second side’s flag will now stay LOW until its semaphore request latch is written to a one. From this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. The critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. The semaphore logic is specially designed to resolve this problem. If simultaneous requests are made, the logic guarantees that only one side receives the token. If one side is earlier than the other in making the request, the first side to make the request will receive the token. If both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. One caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. As with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. Initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. 18 , IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges Ordering Information IDT XXXXX Device Type A 999 A A Power Speed Package Process/ Temperature Range Blank I(1) B Commercial (0°C to +70°C) Industrial (-40°C to + 85°C) Military (-55°C to +125°C) Compliant to MIL-PRF-38535 QML PF G J 100-pin TQFP (PN100-1) 108-pin PGA (G108-1) 84-pin PLCC (J84-1) 20 25 35 55 Commercial Only Commercial & Military Commercial & Military Commercial, Industrial & Military S L Standard Power Low Power 7008 512K (64K x 8) Dual-Port RAM Speed in nanoseconds , 3198 drw 21 NOTE: 1. Industrial temperature range is available on selected TQFP packages in standard power. For other speeds, packages and powers contact your sales office. Datasheet Document History 1/6/99: 6/3/99: 11/10/99: 5/8/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Pages 2 and 3 Added additional notes to pin configurations Changed drawing format Replaced IDT logo Page 6 Increased storage temperature parameter Clarified TA parameter Page 7 DC Electrical paramters–changed wording from "open" to "disabled" Changed ±200mV to 0mV in notes CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-5166 fax: 408-492-8674 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 19 6.42 for Tech Support: 831-754-4613 [email protected]