EDI8L32256C 256Kx32 SRAM Module 256Kx32, 5V Static Ram Features 256Kx32 bit CMOS Static DSP Memory Solution • Texas Instruments TMS320C3x, TMS320C4x • Analog SHARCTM DSP • Motorola DSP96002 Random Access Memory Array • Fast Access Times: 15, 17, 20 and 25ns • Individual Byte Enables • User Configurable Organization with Minimal Additional Logic • Master Output Enable and Write Control • TTL Compatible Inputs and Outputs • Fully Static, No Clocks Surface Mount Package • 68 Lead PLCC, No. 99, JEDEC MO-47AE • Small Footprint, 0.990 Sq. In. • Multiple Ground Pins for Maximum Noise Immunity Single +5V (±5%) Supply Operation The EDI8L32256C is a high speed, 5V, 8 megabit SRAM. The device is available with access times of 15, 17, 20 and 25ns, allowing the creation of a no wait state DSP memory solution. The device can be configured as a 256Kx32 and used to create a single chip external data memory solution for Texas Instruments' TMS320C30/31, TMS 320C32 or TMS320C4x, Motorola's DSP96002 and Analog Device's SHARCTM DSP. Alternatively the device's chip enables can be used to configure it as a 512Kx16. A 512Kx48 program memory array for Analog's SHARCTM DSP is created using three devices. If this memory is too deep, two 256Kx24s (EDI8L24256C) can be used to create a 256Kx48 array or two 128Kx24s (EDI8L24128C) can be used to create a 128Kx48 array. The device provides a 32% space savings when compared to two monolithic 256Kx16, 44 pin SOJs. The device provides a memory upgrade of the EDI8L32128C (128Kx32) and the EDI8L3265C (64Kx32). For more memory the device can be upgraded to the EDI8L32512C (512Kx32). NOTE: Solder Reflow temperature should not exceed 260°C for 10 seconds. DQ16 NC A17 BS3\ BS2\ BS1\ BSØ\ E1\ VCC NC EØ\ G\ W\ A16 A15 A14 DQ15 Pin Configurations and Block Diagram 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 Pin Names 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 VCC DQ7 DQ6 DQ5 DQ4 VSS DQ3 DQ2 DQ1 DQ31 A6 A5 A4 A3 A2 A1 AØ VCC A13 A12 A11 A10 A9 A8 A7 DQØ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 DQ17 DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC DQ24 DQ25 DQ26 DQ27 VSS DQ28 DQ29 DQ30 AØ-A17 EØ-E1 BSØ-BS3 W G DQØ-DQ31 VCC VSS NC AØ-A17 G W EØ E1 BSØ BS1 BS2 BS3 Address Inputs Chip Enables (One per Word) Byte Selects (One per Byte) Master Write Enable Master Output Enable Common Data Input/Output Power (+5V±5%) Ground No Connection 18 256Kx32 Memory Array Note: For memory upgrade information refer to page 8, Figure 8 "EDI MCM-L upgrade path". Electronic Designs Incorporated • One Research Drive • Westborough, MA 01581USA • 508-366-5151 • FAX 508-836-4850 • http://www.electronic-designs.com 1 EDI8L32256C Rev. 4 3/98 ECO#9662 DQØ-DQ7 DQ8-DQ15 DQ16-DQ23 DQ24-DQ31 Absolute Maximum Ratings* Recommended DC Operating Conditions Voltage on any pin relative to VSS Operating Temperature TA (Ambient) Commercial Industrial Storage Temperature Power Dissipation Output Current. Junction Temperature, TJ Parameter Sym Supply Voltage VCC Supply Voltage VSS Input High Voltage VIH Input Low Voltage VIL -0.5V to 7.0V 0°C to + 70°C -40°C to +85°C -55°C to +125°C 3.1 Watts 20 mA 175°C Min 4.75 0 2.2 -0.3 Typ Max Units 5.0 5.25 V 0 0 V -- VCC+0.5 V -0.8 V AC Test Conditions *Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load VSS to 3.0V 5ns 1.5V Figure 1 (note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF) Figure 1 Figure 2 VCC VCC 480 Q 480 Q 255 255 30 pF 5 pF DC Electrical Characteristics Parameter Sym Operating Power Supply Current ICC1 Standby (TTL) Supply Current ICC2 Full StandbySupply Current ICC3 Input Leakage Current Output Leakage Current Output High Volltage Output Low Voltage ILI ILO VOH VOL Conditions W= VIL, II/O = 0mA, Min Cycle E ≥ VIH, VIN ≤ VIL or VIN ≥ VIH, f=ØMHz E ≥ VCC-0.2V VIN ≥ VCC-0.2V or VIN ≤ 0.2V VIN = 0V to VCC V I/O = 0V to VCC IOH = -4.0mA IOL = 8.0mA Truth Table E W G H X X L H H L X X L H L L L X Min Max 15/17 575 20/25 480 Units mA 120 120 mA 20 20 mA ± 10 ±10 µA µA V V 2.4 0.4 Capacitance BSØ-3 Mode X Standby X Output Disable H Output Disable L Read L Write Output High Z High Z High Z DOUT DIN Power ICC2,ICC3, ICC1 ICC1 ICC1 ICC1 (f=1.0MHz, VIN=VCC or VSS) Parameter Address Lines Data Lines Write & Output Enable Lines Chip Enable Lines/Byte Select X Means Don't Care EDI8L32256C 256Kx32 SRAM Module 2 EDI8L32256C Rev. 4 3/98 ECO#9662 Sym CA CD/Q W, G E, BS Max 20 10 6 9 Unit pF pF pF pF EDI8L32256C 256Kx32 SRAM Module AC Characteristics Read Cycle Symbol JEDEC Alt. TAVAV TRC TAVQV TAA TELQV TACS TBLQX TBLZ TELQX TCLZ TBLQX TBLZ TEHQZ TCHZ TBHQZ TBHZ TAVQX TOH TGLQV TOE TGLQX TOLZ TGHQZ TOHZ Parameter Read Cycle Time Address Access Time Chip Enable Access Time Byte Select Access Time Chip Enable to Output in Low Z (1) Byte Select to Output in Low Z Chip Disable to Output in High Z (1) Byte Select to Output in High Z Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1) 15ns 17ns 20ns 25ns Min Max Min Max Min Max Min Max 15 17 20 25 15 17 20 25 15 17 20 25 15 17 20 25 3 3 3 3 3 3 3 3 8 8 10 10 8 8 10 10 3 3 3 3 6 8 10 10 2 2 2 2 5 6 8 10 Read Cycle 1 - W High, G, E Low TAVAV ADDRESS 1 A TAVQV ADDRESS 2 TAVQX DATA 1 Q DATA 2 Read Cycle 2 - W High TAVAV A BSx,E TAVQV TELQV TEHQZ TELQX G TGLQV TGHQZ TGLQX Q 3 EDI8L32256C Rev. 4 3/98 ECO#9662 Units ns ns ns ns ns ns ns ns ns ns ns ns AC Characteristics Write Cycle Parameter Write Cycle Time Chip Enable to End of Write Byte Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1) Symbol JEDEC Alt. TAVAV TWC TELWH TCW TELEH TCW TBLWH TBW TAVWL TAS TAVEL TAS TAVWH TAW TAVEH TAW TWLWH TWP TWLEH TWP TWHAX TWR TEHAX TWR TWHDX TDH TEHDX TDH TWLQZ TWHZ TDVWH TDW TDVEH TDW TWHQX TWLZ 15ns 17ns 20ns 25ns Min Max Min Max Min Max Min Max Units 15 17 20 25 ns 9 10 15 20 ns 9 10 15 20 ns 9 10 15 20 ns 0 0 0 0 ns 0 0 0 0 ns 10 12 15 15 ns 10 12 15 15 ns 10 12 15 15 ns 10 12 15 15 ns 0 0 0 0 ns 0 0 0 0 ns 0 0 0 0 ns 0 0 0 0 ns 0 6 0 7 0 7 0 10 ns 6 8 8 12 ns 6 8 8 12 ns 2 2 2 2 ns Note 1: Parameter guaranteed, but not tested. Write Cycle 1 - W Controlled TAVAV A BSx,E TELWH TAVWH TWHAX TWLWH W TAVWL TDVWH D TWHDX DATA VALID TWLQZ HIGH Z Q EDI8L32256C 256Kx32 SRAM Module 4 EDI8L32256C Rev. 4 3/98 ECO#9662 TWHQX EDI8L32256C 256Kx32 SRAM Module Write Cycle 2 - E Controlled TAVAV A TAVEL TELEH BSx, E TEHAX TAVEH TWLEH W TDVEH TEHDX DATA VALID D HIGH Z Q Ordering Information Commercial (0°C to 70°C) Part Number EDI8L32256C15AC EDI8L32256C17AC EDI8L32256C20AC EDI8L32256C25AC Industrial (-40°C to +85°C) Speed (ns) 15 17 20 25 Package No. 99 99 99 99 Package Description Package No. 99 68 Lead PLCC JEDEC MO-47AE Weight = 4.2g Theta JA = 40°C/W Part Number Speed (ns) 17 20 25 EDI8L32256C17AI EDI8L32256C20AI EDI8L32256C25AI 0.995 Max 0.956 Max 0.995 Max 0.956 Max Theta JC = 15°C/W 0.180 Max 0.040 Max 0.020 0.015 0.930 0.890 0.050 BSC 0.115 Max Electronic Designs Incorporated • One Research Drive • Westborough, MA 01581USA • 508-366-5151 • FAX 508-836-4850 • http://www.electronic-designs.com Electronic Designs Inc. reserves the right to change specifications without notice. CAGE No. 66301 5 EDI8L32256C Rev. 4 3/98 ECO#9662 Package No. 99 99 99