Preliminary FLASH MEMORY K9E2G08U0M Document Title 256M x 8 Bits NAND Flash Memory Revision History Revision No. History Draft Date Remark 0.0 Initial issue. June. 8th 2004 Advanced 0.1 1. Technical note is changed Oct. 25th 2004 Preliminary 0.2 1. The flow chart to creat the initial invalid block table is changed. May 6th 2005 Preliminary Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site. http://www.samsung.com/Products/Semiconductor/ The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you. 1 Preliminary FLASH MEMORY K9E2G08U0M 256M x 8 Bits NAND Flash Memory PRODUCT LIST Part Number K9E2G08U0M-Y,P Vcc Range Organization 2.7V ~ 3.6V X8 K9E2G08U0M-V,F PKG Type TSOP1 WSOP1 FEATURES • Voltage Supply : 2.7V ~ 3.6V • Organization - Memory Cell Array : (256M + 8,192K)bits x 8bits - Data Register : (512 + 16)bits x 8bits • Automatic Program and Erase - Page Program : (512 + 16)bits x 8bits - Block Erase : (16K + 512)Bytes • Page Read Operation - Page Size : (512 + 16)Bytes - Random Access : 15µs(Max.) - Serial Page Access : 50ns(Min.) • Fast Write Cycle Time - Program time : 200µs(Typ.) - Block Erase Time : 2ms(Typ.) • Command/Address/Data Multiplexed I/O Port • Hardware Data Protection - Program/Erase Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology - Endurance : 100K Program/Erase Cycles - Data Retention : 10 Years • Command Register Operation • Intelligent Copy-Back • Unique ID for Copyright Protection • Package - K9E2G08U0M-YCB0/YIB0 48 - Pin TSOP I (12 X 20 / 0.5 mm pitch) - K9E2G08U0M-VCB0/VIB0 48 - Pin WSOP I (12 X 17 X 0.7mm) - K9E2G08U0M-PCB0/PIB0 48 - Pin TSOP I (12 X 20 / 0.5 mm pitch)- Pb-free Package - K9E2G08U0M-FCB0/FIB0 48 - Pin WSOP I (12 X 17 X 0.7mm)- Pb-free Package * K9E2G08U0M-V,F(WSOPI ), K9E2G08U0M-Y,P(TSOP1) is the same device as except package type. GENERAL DESCRIPTION Offered in 256Mx8bits, the K9E2G08U0M is 2Gbit with spare 64Mbit capacity. The device is offered in 3.3V Vcc. Its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be performed in typical 200µs on the 528-bytes and an erase operation can be performed in typical 2ms on a 16K-bytes block. Data in the page can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write control automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9E2G08U0M′s extended reliability of 100K program/ erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9E2G08U0M is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility. 2 Preliminary FLASH MEMORY K9E2G08U0M PIN CONFIGURATION (TSOP1) K9E2G08U0M-YCB0,PCB0/YIB0,PIB0 N.C N.C N.C N.C N.C N.C R/B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) 48 - TSOP1 - 1220AF 0.10 MAX 0.004 Unit :mm/Inch #48 #24 #25 12.40 0.488 MAX 12.00 0.472 +0.003 ( 0.25 ) 0.010 #1 0.008-0.001 0.50 0.0197 0.16 -0.03 +0.075 18.40±0.10 0.724±0.004 0~8° 0.45~0.75 0.018~0.030 +0.003 0.005-0.001 0.25 0.010 TYP 1.00±0.05 0.039±0.002 0.125 0.035 +0.07 0.20 -0.03 +0.07 20.00±0.20 0.787±0.008 ( 0.50 ) 0.020 3 1.20 0.047MAX 0.05 0.002 MIN Preliminary FLASH MEMORY K9E2G08U0M PIN CONFIGURATION (WSOP1) K9E2G08U0M-VCB0,FCB0/VIB0,FIB0 N.C N.C DNU N.C N.C N.C R/B RE CE DNU N.C Vcc Vss N.C DNU CLE ALE WE WP N.C N.C DNU N.C N.C N.C N.C DNU N.C I/O7 I/O6 I/O5 I/O4 N.C DNU N.C Vcc Vss N.C DNU N.C I/O3 I/O2 I/O1 I/O0 N.C DNU N.C N.C 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PACKAGE DIMENSIONS 48-PIN LEAD PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I) 48 - WSOP1 - 1217F Unit :mm 0.70 MAX 0.58±0.04 15.40±0.10 #48 #24 #25 0.20 0.50TYP (0.50±0.06) 12.40MAX 12.00±0.10 +0.07 -0.03 0.16 +0.07 -0.03 #1 0° ~ 0.10 +0.075 -0.035 (0.01Min) 8° 0.45~0.75 17.00±0.20 4 Preliminary FLASH MEMORY K9E2G08U0M PIN DESCRIPTION Pin Name Pin Function I/O0 ~ I/O7 DATA INPUTS/OUTPUTS The I/O pins are used to input command, address and data, and to output data during read operations. The I/ O pins float to high-z when the chip is deselected or when the outputs are disabled. CLE COMMAND LATCH ENABLE The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. ALE ADDRESS LATCH ENABLE The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high. CE CHIP ENABLE The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase opertion. Regarding CE control during read operation, refer to ’Page read’ section of Device operation . RE READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WE WRITE ENABLE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. WP WRITE PROTECT The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the WP pin is active low. R/B READY/BUSY OUTPUT The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. VccQ OUTPUT BUFFER POWER VCCQ is the power supply for Output Buffer. VccQ is internally connected to Vcc, thus should be biased to Vcc. Vcc POWER VCC is the power supply for device. Vss GROUND N.C NO CONNECTION Lead is not internally connected. DNU DO NOT USE Leave it disconnected. NOTE : Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected. 5 Preliminary FLASH MEMORY K9E2G08U0M Figure 1. K9E2G08U0M FUNCTIONAL BLOCK DIAGRAM VCC VSS A9 - A27 X-Buffers Latches & Decoders A0 - A7 Y-Buffers Latches & Decoders 2G + 64M Bits NAND Flash ARRAY (512 + 16)Bytes x 524,288 Page Register & S/A A8 Y-Gating Command Command Register I/O Buffers & Latches Control Logic & High Voltage Generator CE RE WE VCC/VCCQ VSS Output Driver Global Buffers I/0 0 I/0 7 CLE ALE WP Figure 2. K9E2G08U0M ARRAY ORGANIZATION 1 Block = 32 Pages = (16K + 512) Bytes 256K Pages (=8,192 Blocks) 1st half Page Register 2nd half Page Register (=256 Bytes) (=256 Bytes) 1 Page = 528 Bytes 1 Block = 528 Bytes x 32 Pages = (16K + 512) Bytes 1 Device = 528Bytes x 32Pages x 16,384 Blocks = 2,112 Mbits 8 bits 512Bytes 16 Bytes I/O 0 ~ I/O 7 Page Register 512 Bytes I/O 0 I/O 1 16 Bytes I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 1st Cycle A0 A1 A2 A3 A4 A5 A6 A7 2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16 3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24 4th Cycle A25 A26 A27 *L *L *L *L *L NOTE : Column Address : Starting Address of the Register. 00h Command(Read) : Defines the starting address of the 1st half of the register. 01h Command(Read) : Defines the starting address of the 2nd half of the register. * A8 is set to "Low" or "High" by the 00h or 01h Command. * L must be set to "Low". * The device ignores any additional input of address cycles than reguired. 6 Column Address Row Address (Page Address) Preliminary FLASH MEMORY K9E2G08U0M Product Introduction The K9E2G08U0M is a 2,112Mbits(2,214,592,512 bits) memory organized as 524,288 rows(pages) by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-bytes data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32 pages formed two NAND structures. A NAND structure consists of 16 cells. Total 1,056 NAND structures reside in a block. The array organization is shown in Figure 2. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 16,384 separately erasable 16K-bytes blocks. It indicates that the bit by bit erase operation is prohibited on the K9E2G08U0M. The K9E2G08U0M has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 256M byte physical space requires 28 addresses, thereby requiring four cycles for byte-level addressing : 1 cycle of column address, 3 cycles of row address, in that order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase operation, however, only the 3 cycles of row address are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9E2G08U0M. The device provides simultaneous program/erase capability up to four pages/blocks. By dividing the memory array into eight 256Mbit separate planes, simultaneous multi-plane operation dramatically increases program/erase performance by 4X while still maintaining the conventional 512 bytes structure. The extended pass/fail status for multi-plane program/erase allows system software to quickly identify the failing page/block out of selected multiple pages/blocks. Usage of multi-plane operations will be described further throughout this document. In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another of the same plane without the need for transporting the data to and from the external buffer memory. Since the time-consuming burstreading and data-input cycles are removed, system performance for solid-state disk application is significantly increased. The device includes one block sized OTP(One Time Programmable), which can be used to increase system security or to provide identification capabilities. Detailed information can be obtained by contact with Samsung. Table 1. Command Sets Function 1’st Cycle 2’nd Cycle 3’rd Cycle 4’th Cycle 5’th Cycle Read 1 00h/01h(1) - - - - Read 2 50h - - - - Read ID 90h/91h - - - - FFh - - - - Page Program (True)(2) 80h 10h - - - Page Program (Dummy)(2) 80h 11h - - - 00h 8Ah 10h - - 03h 8Ah 11h - - Reset Copy-Back Program(True)(2) Copy-Back Program(Dummy) Block Erase Multi-Plane Block Erase Read Status Read Multi-Plane Status (2) Acceptable Command during Busy O 60h D0h - - - 60h----60h D0h - - - 70h - - - - O - - - - O (3) 71h NOTE : 1. The 00h/01h command defines starting address of the 1st/2nd half of registers. After data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half register(00h) on the next cycle. 2. Page Program(True) and Copy-Back Program(True) are available on 1 plane operation. Page Program(Dummy) and Copy-Back Program(Dummy) are available on the 2nd, 3rd, 4th plane of multi-plane operation. 3. The 71h command should be used for read status of Multi Plane operation. Caution : Any undefined command inputs are prohibited except for above command set of Table 1. 7 Preliminary FLASH MEMORY K9E2G08U0M Memory Map The device is arranged in eight 256Mbit memory planes. Each plane contains 2,048 blocks and 528 byte page registers. This allows it to perform simultaneous page program and block erase by selecting one page or block from each plane. The block address map is configured so that multi-plane program/erase operations can be executed for every four sequential blocks by dividing the memory array into plane 0~3 or plane 4~7 separately. For example, multi-plane program/erase operations into plane 2,3,4 and 5 are prohibited. Figure 3. Memory Array Map Plane 0 (2048 Block) Block 0 Plane 2 (2048 Block) Plane 1 (2048 Block) Block 2 Block 1 Plane 3 (2048 Block) Block 3 Page 0 Page 0 Page 0 Page 0 Page 1 Page 1 Page 1 Page 1 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 Block 8188 Block 8190 Block 8189 Block 8191 Page 0 Page 0 Page 0 Page 0 Page 1 Page 1 Page 1 Page 1 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 528byte Page Registers 528byte Page Registers 528byte Page Registers 528byte Page Registers Plane 4 (2048 Block) Plane 5 (2048 Block) Plane 6 (2048 Block) Plane 7 (2048 Block) Block 8192 Block 8194 Block 8193 Block 8195 Page 0 Page 0 Page 0 Page 0 Page 1 Page 1 Page 1 Page 1 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 Block 16380 Block 16381 Block 16382 Block 16383 Page 0 Page 0 Page 0 Page 0 Page 1 Page 1 Page 1 Page 1 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 528byte Page Registers 528byte Page Registers 528byte Page Registers 528byte Page Registers 8 Preliminary FLASH MEMORY K9E2G08U0M ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Temperature Under Bias Symbol Rating VIN/OUT -0.6 to +4.6 VCC/VCCQ -0.6 to +4.6 K9E2G08U0M-XCB0 V -10 to +125 TBIAS K9E2G08U0M-XIB0 Unit °C -40 to +125 Storage Temperature TSTG -65 to +150 °C Short Circuit Current IOS 5 mA NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns. 2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND at the condision of K9E2G08U0M-XCB0 : TA=0 to 70°C or K9E2G08U0M-XIB0 : TA=-40 to 85°C) Parameter Supply Voltage Symbol Min Typ. Max Unit VCC 2.7 3.3 3.6 V VCCQ 2.7 3.3 3.6 V VSS 0 0 0 V DC AND OPERATING CHARACTERISTICS (Recommended operating conditions otherwise noted.) Paramete Symbol Test Conditions Sequential Read ICC1 tRC=50ns, CE=VIL, IOUT=0mA - 15 30 Program ICC2 - - 15 30 Erase ICC3 - - 15 30 Stand-by Current(TTL) ISB1 CE=VIH, WP=0V/VCC - - 1 Stand-by Current(CMOS) ISB2 Operating Current Min Typ Max CE=VCC-0.2, WP=0V/VCC - 20 100 Input Leakage Current ILI VIN=0 to Vcc(max) - - ±20 Output Leakage Current ILO VOUT=0 to Vcc(max) - - ±20 Input High Voltage VIH Input Low Voltage, All inputs VIL Output High Voltage Level VOH I/O pins 2.0 - VCCQ+0.3 Except I/O pins 2.0 - VCC+0.3 - -0.3 - 0.8 2.4 - - IOH=-400µA Output Low Voltage Level VOL IOL=2.1mA - - 0.4 Output Low Current(R/B) IOL(R/B) VOL=0.4V 8 10 - Notes : 1. Typical values are measured at Vcc=3.3V, TA=25°C. And not 100% tested. 9 Unit mA µA V mA Preliminary FLASH MEMORY K9E2G08U0M VALID BLOCK Parameter Valid Block Number Symbol Min Typ. Max Unit NVB 16,104 - 16,384 Blocks NOTE : 1. The K9E2G08U0M may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks. 2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction up to 1K Program/Erase cycles. 3. Minimum 2,013 valid blocks are guaranteed for each contiguous 256Mb memory space. AC TEST CONDITION (K9E2G08U0M-XCB0 :TA=0 to 70°C, K9E2G08U0M-XIB0:TA=-40 to 85°C) Parameter Value Input Pulse Levels 0.4V to 2.4V Input Rise and Fall Times 5ns Input and Output Timing Levels 1.5V VccQ=3.0V+/-10% : 1 TTL GATE and CL= 50pF VccQ=3.3V+/-10% : 1 TTL GATE and CL=100pF Output Load CAPACITANCE(TA=25°C, VCC=3.3V, f=1.0MHz) Symbol Test Condition Min Max Unit Input/Output Capacitance Item CI/O VIL=0V - 10 pF Input Capacitance CIN VIN=0V - 10 pF NOTE : Capacitance is periodically sampled and not 100% tested. MODE SELECTION CLE ALE CE H L L H H L L L L L L L H L L L H X X X X X X X X RE WP L H X L H X L L H H H L H H H H Data Input X Data Output H X During Read (Busy) X X H During Program (Busy) X X H During Erase (Busy) L Write Protect X (1) X WE X X X H X X Mode Read Mode Write Mode Command Input Address Input (4 clocks) Command Input Address Input (4 clocks) 0V/VCC(2) Stand-by NOTE : 1. X can be VIL or VIH. 2. WP should be biased to CMOS high or CMOS low for standby. Program / Erase Characteristics Parameter Program Time Dummy Busy Time for Multi Plane Program Number of Partial Program Cycles in the Same Page Block Erase Time Main Array Spare Array Symbol Min Typ Max Unit tPROG(1) - 200 500 µs 1 10 µs - 1 cycle tDBSY Nop tBERS - - 2 cycle - 2 3 ms NOTE : 1.Typical Program time is defined as the time within which more than 50% of the whole pages are programmed at Vcc of 3.3V and 25’c 10 Preliminary FLASH MEMORY K9E2G08U0M AC Timing Characteristics for Command / Address / Data Input Parameter Symbol Min Max Unit CLE Set-up Time tCLS 0 - ns CLE Hold Time tCLH 5 - ns CE Setup Time tCS 0 .- ns CE Hold Time tCH 5 - ns WE Pulse Width tWP ALE Setup Time tALS ALE Hold Time tALH 5 - ns Data Setup Time tDS 20 - ns 25 (1) 0 - ns - ns Data Hold Time tDH 5 - ns Write Cycle Time tWC 45 - ns WE High Hold Time tWH 15 - ns NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns. AC Characteristics for Operation Symbol Min Max Unit Data Transfer from Cell to Register Parameter tR - 15 µs ALE to RE Delay tAR 10 - ns CLE to RE Delay tCLR 10 - ns Ready to RE Low tRR 20 - ns RE Pulse Width tRP 25 - ns WE High to Busy tWB - 100 ns Read Cycle Time tRC 50 - ns CE Access Time tCEA - 45 ns RE Access Time tREA - 30 ns RE High to Output Hi-Z tRHZ - 30 ns CE High to Output Hi-Z tCHZ - 20 ns RE or CE High to Output hold tOH 15 - ns RE High Hold Time tREH 15 - ns tIR 0 - ns WE High to RE Low tWHR 60 - ns Device Resetting Time(Read/Program/Erase) tRST - 5/10/500(1) µs Last RE High to Busy(at sequential read) tRB - 100 ns CE High to Ready(in case of interception by CE at read) tCRY - 50 + tr(R/B)(3) ns CE High Hold Time(at the last serial read) tCEH 100 - ns Output Hi-Z to RE Low (2) NOTE : 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us. 2. To break the sequential read cycle, CE must be held high for longer time than tCEH. 3. The time to Ready depends on the value of the pull-up resistor tied R/B pin. 11 Preliminary FLASH MEMORY K9E2G08U0M NAND Flash Technical Notes Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is so called as the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction up to 1K Program/Erase cycles. Identifying Initial Invalid Block(s) All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s) status is defined by the 6th byte in the spare area. Samsung makes sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 517. Since the initial invalid block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure 4). Any intentional erasure of the initial invalid block information is prohibited. Start Set Block Address = 0 Increment Block Address Create (or update) Initial Invalid Block(s) Table No * Check "FFh" at the column address 517 of the 1st and 2nd page in the block Check "FFh" ? Yes No Last Block ? Yes End Figure 4. Flow chart to create initial invalid block table. 12 Preliminary FLASH MEMORY K9E2G08U0M NAND Flash Technical Notes (Continued) Error in write or read operation Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block replacement. The said additional block failure rate does not include those reclaimed blocks. Failure Mode Write Read ECC Detection and Countermeasure sequence Erase Failure Status Read after Erase --> Block Replacement Program Failure Status Read after Program --> Block Replacement Single Bit Failure Verify ECC -> ECC Correction : Error Correcting Code --> Hamming Code etc. Example) 1bit correction & 2bits detection Program Flow Chart Start Write 80h Write Address Write Data Write 10h Read Status Register I/O 6 = 1 ? or R/B = 1 ? * Program Error No Yes No I/O 0 = 0 ? Yes Program Completed * 13 : If program operation results in an error, map out the block including the page in error and copy the target data to another block. Preliminary FLASH MEMORY K9E2G08U0M NAND Flash Technical Notes (Continued) Erase Flow Chart Read Flow Chart Start Start Write 60h Write 00h Write Block Address Write Address Write D0h Read Data Read Status Register ECC Generation No I/O 6 = 1 ? or R/B = 1 ? Reclaim the Error * No Verify ECC Yes Yes Erase Error No Page Read Completed I/O 0 = 0 ? Yes Erase Completed * : If erase operation results in an error, map out the failing block and replace it with another block. Block Replacement 1st ∼ (n-1)th nth { Block A 2 an error occurs. (page) 1st ∼ (n-1)th nth Buffer memory of the controller. { Block B 1 (page) * Step1. When an error happens in the nth page of the Block ’A’ during erase or program operation. * Step2. Copy the nth page data of the Block ’A’ in the buffer memory to the nth page of another free block. (Block ’B’) * Step3. Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’. * Step4. Do not further erase Block ’A’ by creating an ’invalid Block’ table or other appropriate scheme. 14 Preliminary FLASH MEMORY K9E2G08U0M Pointer Operation of K9E2G08U0M Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’ command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets the pointer to ’C’ area(512~527byte). With these commands, the starting column address can be set to any of a whole page(0~527byte). ’00h’ or ’50h’ is sustained until another address pointer command is inputted. ’01h’ command, however, is effective only for one operation. After any operation of Read, Program, Erase, Reset, Power_Up is executed once with ’01h’ command, the address pointer returns to ’A’ area by itself. To program data starting from ’A’ or ’C’ area, ’00h’ or ’50h’ command must be inputted before ’80h’ command is written. A complete read operation prior to ’80h’ command is not necessary. To program data starting from ’B’ area, ’01h’ command must be inputted right before ’80h’ command is written. Table 2. Destination of the pointer Command Pointer position Area 00h 01h 50h 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte 1st half array(A) 2nd half array(B) spare array(C) "A" area (00h plane) "B" area (01h plane) "C" area (50h plane) 256 Bytes 256 Bytes 16 Bytes "A" "B" "C" Internal Page Register Pointer select commnad (00h, 01h, 50h) Pointer Figure 5. Block Diagram of Pointer Operation (1) Command input sequence for programming ’A’ area The address pointer is set to ’A’ area(0~255), and sustained Address / Data input 00h 80h Address / Data input 10h 00h ’A’,’B’,’C’ area can be programmed. It depends on how many data are inputted. 80h 10h ’00h’ command can be omitted. (2) Command input sequence for programming ’B’ area The address pointer is set to ’B’ area(256~511), and will be reset to ’A’ area after every program operation is executed. Address / Data input 01h 80h Address / Data input 10h 01h ’B’, ’C’ area can be programmed. It depends on how many data are inputted. 80h 10h ’01h’ command must be rewritten before every program operation (3) Command input sequence for programming ’C’ area The address pointer is set to ’C’ area(512~527), and sustained Address / Data input 50h 80h Address / Data input 10h 50h Only ’C’ area can be programmed. 80h ’50h’ command can be omitted. 15 10h Preliminary FLASH MEMORY K9E2G08U0M System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528bytes page registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption. Figure 6. Program Operation with CE don’t-care. CLE CE don’t-care WE ≈ ≈ CE ALE I/OX 80h Start Add.(4Cycle) tCS Data Input tCH Data Input 10h tCEA CE CE RE tWP tREA WE I/OX out Figure 7. Read Operation with CE don’t-care. CLE CE must be held low during tR CE don’t-care ≈ CE RE ALE tR R/B WE I/OX 00h Data Output(sequential) Start Add.(4Cycle) 16 Preliminary FLASH MEMORY K9E2G08U0M * Command Latch Cycle CLE tCLS tCLH tCS tCH CE tWP WE tALH tALS ALE tDH tDS Command I/OX * Address Latch Cycle tCLS CLE tCS tWC tWC tWC CE tWP tWP WE tWH tALH tALS tWH tALH tALS tALS tWP tWP tWH tALH tALS tALH ALE tDS I/OX tDH A0~A7 tDS tDH A9~A16 17 tDS tDH A17~A24 tDS tDH A25~A27 Preliminary FLASH MEMORY K9E2G08U0M * Input Data Latch Cycle tCLH CLE tCH CE tWC tALS ALE tWP tWH tDH tDS tDH tDS tDH ≈ tDS tWP ≈ tWP WE I/Ox DIN n DIN 1 ≈ DIN 0 * Serial access Cycle after Read(CLE=L, WE=H, ALE=L) tRC ≈ CE tREA tREA ≈ tREH tCHZ* tOH tREA RE tRHZ* tRHZ* I/Ox Dout Dout ≈ tOH Dout ≈ tRR R/B NOTES : Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 18 Preliminary FLASH MEMORY K9E2G08U0M * Status Read Cycle tCLR CLE tCLS tCLH tCS CE tWP tCH WE tCEA tCHZ tOH tWHR RE tDS I/OX tDH tRHZ tREA tIR tOH Status Output 70h READ1 OPERATION(READ ONE PAGE) CLE tCEH ≈ CE tCHZ tOH ≈ tWC WE ≈ ≈ tWB ALE tCRY tAR tR tRHZ tOH ≈ tRC N Address ≈ RE A9 ~ A16 Column Address R/B A17 ~ A24 A25 ~ A27 Page(Row) Address Busy 19 Dout N Dout N+1 Dout N+2 ≈ ≈ 00h or 01h A0 ~ A7 ≈ I/OX ≈ tRR Dout m tRB Preliminary FLASH MEMORY K9E2G08U0M Read1 Operation(Intercepted by CE) CLE ≈ ≈ CE WE ≈ ≈ tWB ALE tCHZ tOH tAR tRC ≈ tR RE I/OX 00h or 01h A0 ~ A7 A9 ~ A16 A17 ~ A24 A25 ~ A27 ≈ tRR Dout N Dout N+1 Dout N+2 Page(Row) Address Column Address Busy ≈ R/B Read2 Operation(Read One Page) CLE CE WE tR tWB ALE tAR RE I/OX 50h A0 ~ A7 Dout n+M A9 ~ A16 A17 ~ A24 A25 ~ A27 R/B ≈ ≈ tRR n+m Selected Row M Address A0~A3 : Valid Address A4~A7 : Don′t care 512 16 Start address M 20 Preliminary FLASH MEMORY K9E2G08U0M Sequential Row Read Operation ( Within a Block ) ≈ CLE ≈ ≈ CE WE ≈ ≈ ≈ Dout 1 Dout 527 ≈ ≈ Busy Dout 0 ≈ ≈ Dout 527 Ready Busy R/B Dout N+1 Dout N ≈ A0 ~ A7 A9 ~ A16 A17 ~ A24 A25 ~ A27 ≈ ≈ 00h ≈ RE I/OX ≈ ≈ ALE M M+1 N Output Output Page Program Operation CLE CE tWC ≈ tWC tWC WE tWB tPROG ALE I/OX 80h A0 ~ A7 A9 ~ A16 A17 ~ A24 A25 ~ A27 Sequential Data Column Input Command Address Page(Row) Address ≈ ≈ RE Din Din 10h N 527 1 up to 528 Byte Data Program Command Serial Input ≈ R/B 70h 21 I/O0 Read Status Command I/O0=0 Successful Program I/O0=1 Error in Program Preliminary FLASH MEMORY K9E2G08U0M BLOCK ERASE OPERATION(ERASE ONE BLOCK) CLE CE tWC WE tWB tBERS ALE RE I/OX 60h A9 ~ A16 A17 ~ A24 A25 ~ A27 DOh 70h I/O 0 Page(Row) Address Busy R/B Erase Setup Command Erase Command 22 Read Status Command I/O0=0 Successful Erase I/O0=1 Error in Erase 23 R/B I/OX RE ALE WE CE CLE Sequential Data Input Command 80h tWC Max. three times repeatable Page(Row) Address Din m tDBSY : typ. 1us max. 10us tDBSY 80h I/O0~7 R/B 80h A0 ~ A7 & A9 ~ A27 528 Byte Data Address & Data Input 11h tDBSY 80h A0 ~ A7 & A9 ~ A27 528 Byte Data Address & Data Input 11h tDBSY 80h Din N A0 ~ A7 & A9 ~ A27 528 Byte Data Address & Data Input 11h tDBSY Last Plane Input & Program A0 ~ A7 A9 ~ A16 A17 ~ A24 A25 ~ A27 tPROG A0 ~ A7 & A9 ~ A27 528 Byte Data Address & Data Input 10h Program Confirm Command (True) 80h Din 527 tWB tPROG 10h I/O 71h Read Multi-Plane Status Command 71h K9E2G08U0M Ex.) Four-Plane Page Program into Plane 0~3 or Plane 4~7 Column Address Din N tWB 11h Program 1 up to 528 Byte Data Command (Dummy) Serial Input A0 ~ A7 A9 ~ A16 A17 ~ A24 A25 ~ A27 ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ Multi-Plane Page Program Operation Preliminary FLASH MEMORY Preliminary FLASH MEMORY K9E2G08U0M Multi-Plane Block Erase Operation into Plane 0~3 or Plane 4~7 CLE CE tWC WE tBERS tWB ALE RE I/OX 60h A9 ~ A16 A17 ~ A24 A25 ~ A27 DOh 71h I/O 0 Page(Row) Address Busy R/B Erase Setup Command Erase Confirm Command I/O0=0 Successful Erase I/O0=1 Error in Erase Read Multi-Plane Status Command Max. 4 times repeatable * For Multi-Plane Erase operation, Block address to be erased should be repeated before "D0H" command. Ex.) Four-Plane Block Erase Operation R/B I/O0~7 tBERS 60h Address 60h A9 ~ A27 60h A9 ~ A27 60h A9 ~ A27 24 A9 ~ A27 D0h 71h Preliminary FLASH MEMORY K9E2G08U0M Read ID Operation (90 ID) CLE CE WE ALE RE tREA I/OX 90h Read ID Command 00h ECh 71h Maker Code Device Code Address. 1cycle ID Defintition Table 90 ID : Access command = 90H 1st Byte 2nd Byte 3rd Byte 4th Byte Value Description ECh 71h A5h C0h Maker Code Device Code Must be don’t -cared Supports Multi Plane Operation Read ID Operation (91 ID) CLE CE WE ALE RE tREA I/OX 91h Read ID Command 00h Address. 1cycle 20h Extended ID Code 25 A5h C0h Multi Plane Code Preliminary FLASH MEMORY K9E2G08U0M ≈ CLE ≈≈ ≈ ≈ ≈ ≈ ≈ Copy-Back Program Operation ≈ ≈ CE tWC WE tWB ≈ ≈ ALE tWB tPROG R/B Page(Row) Address 8Ah A0~A7 A9~A16 A17~A24 A25~A27 10h Column Address Busy Page(Row) Address ≈ A0~A7 A9~A16 A17~A24 A25~A27 Column Address 70h I/O0 Read Status Command Busy ≈ 00h ≈ I/OX ≈ RE ≈≈ tR Copy-Back Data Input Command 26 I/O0=0 Successful Program I/O0=1 Error in Program Preliminary FLASH MEMORY K9E2G08U0M Device Operation PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with four address cycles. Once the command is latched, it does not need to be written for the following page read operation. Three types of operations are available : random read, serial page read and sequential row read. The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred to the data registers in less than 15µs(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. If CE goes high before the device returns to Ready, the random read operation is interrupted and Busy returns to Ready as the defined by tCRY. Since the operation was aborted, the serial page read does not output valid data. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last column address. The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of 512 to 527 byte may be selectively accessed by writing the Read2 command. Addresses A0 to A3 set the starting address of the spare area while addresses A4 to A7 are ignored. The Read1 command(00h/01h) is needed to move the pointer back to the main area. Figures 8 to 10 show typical sequence and timings for each read operation. After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 12µs again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the next block, read command and address must be given. Figures 9, 10 show typical sequence and timings for sequential row read operation. Figure 8-1. Read1 Operation CLE CE WE ALE tR R/B RE I/O0~7 00h Data Output(Sequential) Start Add.(4Cycle) A0 ~ A7 & A9 ~ A27 (00h Command) 1) (01h Command) 1st half array Main array Data Field Spare Field 2st half array Data Field Spare Field NOTE : 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. 27 Preliminary FLASH MEMORY K9E2G08U0M Figure 8-2. Read2 Operation CLE CE WE ALE tR R/B RE 50h I/OX Data Output(Sequential) Start Add.(4Cycle) A0 ~ A3 & A9 ~ A27 (A4 ~ A7 : Don’t care) Spare Field Main array Data Field Spare Field Figure 9. Sequential Row Read1 Operation I/OX 00h 01h Start Add.(4Cycle) Data Output A0 ~ A7 & A9 ~ A27 1st Data Output Data Output 2nd (528 Byte) Nth (528 Byte) ( 01h Command) ( 00h Command) 1st half array tR ≈ tR tR R/B 2nd half array 1st half array 2nd half array 1st 2nd Nth Block Data Field 1st 2nd Nth Data Field Spare Field Spare Field The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is readout, the sequential read operation must be terminated by bringing CE high. When the page address moves onto the next block, read command and address must be given. 28 Preliminary FLASH MEMORY K9E2G08U0M Figure 10. Sequential Row Read2 Operation I/OX 50h Start Add.(4Cycle) ≈ tR tR R/B Data Output A0 ~ A3 & A9 ~ A27 (A4 ~ A7 : Don’t Care) 1st tR Data Output Data Output 2nd (16Byte) Nth (16Byte) 1st Block Nth Data Field Spare Field PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes up to 528 byte, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 1 for main array and 2 for spare array. The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the attached technical notes. The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address input and then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state control automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 11). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register. Figure 11. Program & Read Status Operation tPROG R/B I/O0~7 80h Address & Data Input 10h 70h I/O0 A0 ~ A7 & A9 ~ A27 528 Bytes Data Fail 29 Pass Preliminary FLASH MEMORY K9E2G08U0M BLOCK ERASE The Erase operation is done on a block(16K Bytes) basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only address A14 to A27 is valid while A9 to A13 is ignored. The Erase Confirm command(D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 12 details the sequence. Figure 12. Block Erase Operation tBERS R/B I/OX 60h Address Input(3Cycle) Pass I/O0 70h D0h Block Add. : A14 ~ A27 Fail Multi-Plane Page Program into Plane 0~3 or Plane 4~7 Multi-Plane Page Program is an extension of Page Program, which is executed for a single plane with 528 bytes page register. Since the device is equipped with four memory planes, activating the four sets of 528 bytes page register enables a simultaneous programming of four pages. Partial activation of four planes is also permitted. After writing the first set of data up to 528 byte into the selected page register, Dummy Page Program command (11h) instead of actual Page Program (10h) is inputted to finish data-loading of the current plane and move to the next plane. Since no programming process is involved, R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate 71h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set of data for one of the other planes is inputted with the same command and address sequences. After inputting data for the last plane, actual True Page Program (10h) instead of dumy Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages are programmed simultaneously, pass/fail status is available for each page when the program operation completes. The extended status bits (I/O1 through I/ O 4) are checked by inputting the Read Multi-Plane Status Register. Status bit of I/O 0 is set to "1" when any of the pages fails. MultiPlane page Program with "01h" pointer is not supported, thus prohibited. Figure 13. Four-Plane Page Program tDBSY R/B I/OX 80h Address & 11h Data Input A0 ~ A7 & A9 ~ A27 tDBSY 80h Address & Data Input tPROG tDBSY 11h 80h 11h 80h Address & Data Input 11h 80h 11h 80h Address & Data Input 10h 528 bytes Data Input 80h 11h Plane 0 (2,048 Blocks) 80h Plane 2 (2,048 Blocks) Plane 1 (2,048 Blocks) 10h Plane 3 (2,048 Blocks) Block 0 Block 1 Block 2 Block 3 Block 4 Block 5 Block 6 Block 7 Block 8,184 Block 8,188 Block 8,186 Block 8,190 Block 8,185 Block 8,189 30 Block 8,187 Block 8,191 71h Preliminary FLASH MEMORY K9E2G08U0M Restriction in addressing with Multi Plane Page Program While any block in each plane may be addressable for Multi-Plane Page Program, the five least significant addresses(A9-A13) for the selected pages at one operation must be the same. Figure 14 shows an example where 2nd page of each addressed block is selected for four planes. However, any arbitrary sequence is allowed in addressing multiple planes as shown in Figure15. Figure 14. Multi-Plane Program & Read Status Operation Block 0 Plane 3 (2,048 Blocks) Plane 2 (2,048 Blocks) Plane 1 (2,048 Blocks) Plane 0 (2,048 Blocks) Block 2 Block 1 Block 3 Page 0 Page 0 Page 0 Page 0 Page 1 Page 1 Page 1 Page 1 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 Page 30 Page 31 Figure 15. Addressing Multiple Planes 80h Plane 2 11h Plane 0 80h 80h 11h Plane3 11h 80h Plane 1 10h Figure 16. Multi-Plane Page Program & Read Status Operation tPROG R/B Last Plane input I/O0~7 80h Address & Data Input 10h Pass I/O 71h A0 ~ A7 & A9 ~ A27 528 bytes Fail Multi-Plane Block Erase into Plane 0~3 or Plane 4~7 Basic concept of Multi-Plane Block Erase operation is identical to that of Multi-Plane Page Program. Up to four blocks, one from each plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command followed by three address cycles) may be repeated up to four times for erasing up to four blocks. Only one block should be selected from each plane. The Erase Confirm command initiates the actual erasing process. The completion is detected by analyzing R/B pin or Ready/Busy status (I/O 6). Upon the erase completion, pass/fail status of each block is examined by reading extended pass/fail status(I/O 1 through I/O 4). Figure 17. Four Block Erase Operation R/B I/OX tBERS 60h Address (3 Cycle) 60h Address (3 Cycle) 60h Address (3 Cycle) 60h Address (3 Cycle) D0h 71h I/O A0 ~ A7 & A9 ~ A27 Fail 31 Pass Preliminary FLASH MEMORY K9E2G08U0M Copy-Back Program The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the plane to another page within the same plane without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential execution of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read operation with "00h" command and the address of the source page moves the whole 528bytes data into the internal page registers. As soon as the device returns to Ready state, Page-Copy Data-input command (8Ah) with the address cycles of destination page followed may be written. The Program Confirm command (10h) is required to actually begin the programming operation. Copy-Back Program operation is allowed only within the same memory plane. Once the Copy-Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase. A14, A15 and A27 must be the same between source and target page. Figure18 shows the command sequence for single plane operation. "When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if Copy-Back operations are accumulated over time, bit error due to charge loss is not checked by external error detection/correction scheme. For this reason, two bit error correction is recommended for the use of CopyBack operation." Figure 18. 1-page Copy-Back program Operation tR R/B I/OX 00h Add.(4Cycles) A0 ~ A7 & A9 ~ A27 Source Address tPROG 8Ah Add.(4Cycles) A0 ~ A7 & A9 ~ A27 Destination Address 32 10h 70h I/O0 Fail Pass Preliminary FLASH MEMORY K9E2G08U0M Multi-Plane Copy-Back Program Multi-Plane Copy-Back Program is an extension of one page Copy-Back Program into four plane operation. Since the device is equipped with four memory planes, activating the four sets of 528 bytes page registers enables a simultaneous Multi-Plane CopyBack programming of four pages. Partial activation of four planes is also permitted. First, normal read operation with the "00h"command and address of the source page moves the whole 528 byte data into internal page buffers. Any further read operation for transferring the addressed pages to the corresponding page register must be executed with "03h" command instead of "00h" command. Any plane may be selected without regard to "00h" or "03h". Up to four planes may be addressed. Data moved into the internal page registers are loaded into the destination plane addresses. After the input of command sequences for reading the source pages, the same procedure as Multi-Plane Page programming except for a replacement address command with "8Ah" is executed. Since no programming process is involved during data loading at the destination plane address , R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate 71h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). After inputting data for the last plane, actual True Page Program (10h) instead of dummy Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages are programmed simultaneously, pass/fail status is available for each page when the program operation completes. No pointer operation is supported with Multi-Plane Copy-Back Program. Once the Multi-Plane Copy-Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase once the Multi-Plane Copy-Back Program is finished. Figure 19. 4-plane Copy-Back Program Max Three Times Repeatable Source Address Input 00h Plane 0 (2,048 Blocks) Block 1 Block 5 4089 Block 8,185 Block 8,189 Block 8,184 Block 8,188 Plane 3 (2,048 Blocks) Plane 2 (2,048 Blocks) Plane 1 (2,048 Blocks) Block 0 Block 4 03h 03h 03h Block 2 Block 3 Block 6 Block 7 Block 8,187 Block 8,191 Block 8,186 Block 8,190 Max Three Times Repeatable Destination Address Input 8Ah 11h Plane 0 (2,048 Blocks) Block 0 Block 4 Block 8,184 Block 8,188 8Ah 11h Plane 1 (2,048 Blocks) 8Ah 11h Plane 2 (2,048 Blocks) 8Ah 10h Plane 3 (2,048 Blocks) Block 1 Block 2 Block 3 Block 5 Block 6 Block 7 Block 8,185 Block 8,189 33 Block 8,186 Block 8,190 Block 8,187 Block 8,191 I/OX 00h 03h tR A0 ~ A7 & A9 ~ A27 Source Address Add.( 4Cyc.) 03h tR A0 ~ A7 & A9 ~ A27 Source Address Add.( 4Cyc.) Max. 4 times ( 4 Cycle Source Address Input) repeatable tR : Normal Read Busy A0 ~ A7 & A9 ~ A27 Source Address Add.(4Cyc.) tR ≈ ≈ R/B tDBSY Add.(4Cyc.) 11h Max. 4 times (4 Cycle Destination Address Input) repeatable tPROG Add.(4Cyc.) 10h A0 ~ A7 & A9 ~ A27 Destination Address 8Ah tDBSY A0 ~ A7 & A9 ~ A27 Destination Address 8Ah tDBSY : Typical 1us, Max 10us A0 ~ A7 & A9 ~ A27 Destination Address Add.(4Cyc.) 11h ≈ ≈ 8Ah ≈ ≈ Figure 20. Four-Plane Copy-Back Page Program (Continued) 71h Preliminary K9E2G08U0M FLASH MEMORY 34 Preliminary FLASH MEMORY K9E2G08U0M READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 4 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command(00h or 50h) should be given before sequential page read cycle. For Read Status of Multi Plane Program/Erase, the Read Multi-Plane Status command(71h) should be used to find out whether multi-plane program or erase operation is completed, and whether the program or erase operation is completed successfully. The pass/fail status data must be checked only in the Ready condition after the completion of Multi-Plane program or erase operation. Table4. Read Staus Register Definition I/O No. Status Definition by 70h Command I/O 0 Total Pass/Fail I/O 1 Plane 0 Pass/Fail I/O 2 Plane 1 Pass/Fail I/O 3 I/O 4 Pass : "0" Definition by 71h Command Fail : "1" Pass : "0"(1) Fail : "1" Must be don’t -cared (2) Pass : "0" Fail : "1" Must be don’t -cared Pass : "0"(2) Fail : "1" Plane 2 Pass/Fail Must be don’t -cared (2) Pass : "0" Fail : "1" Plane 3 Pass/Fail Must be don’t -cared Pass : "0"(2) Fail : "1" I/O 5 Reserved I/O 6 Device Operation Must be don’t -cared I/O 7 Write Protect Must be don’t-cared Busy : "0" Ready : "1" Protected : "0" Not Protected : "1" Busy : "0" Ready : "1" Protected : "0" Not Protected : "1" NOTE : 1. I/O 0 describes combined Pass/Fail condition for all planes. If any of the selected multiple pages/blocks fails in Program/ Erase operation, it sets "Fail" flag. 2. The pass/fail status applies only to the corresponding plane. Read ID The device has 2 types of Read ID command, i.e. Read ID (1) command 90h and Read ID (2) command 91h. The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Four read cycles sequentially output the manufacture code(ECh), and the device code (79h), Reserved(A5h), Multi plane operation code(C0h) respectively. A5h must be don’t-cared. C0h means that device supports Multi Plane operation. The command register remains in Read ID mode until further commands are issued to it. Read ID (2) command 91h provides Multi-Plane(4-Plane) operations availability. If ID code read out by 91h is 20h, it indicates the device has Multi-Plane(4-Plane) operations. Figure 21-1 & 21-2 show the operation sequence. Figure 21-1. Read ID (1) Operation CLE tCEA CE WE tAR ALE RE I/O0~7 tWHR 90h 00h Address. 1cycle tREA ECh Maker code 35 71h Device code A5h C0h Multi-Plane code Preliminary FLASH MEMORY K9E2G08U0M Figure 21-2. Read ID (2) Operation CLE tCEA CE WE tAR ALE RE I/O0~7 tWHR 91h 00h tREA 20h Extended ID Code Address. 1cycle RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. Refer to table 5 for device status after reset operation. If the device is already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Refer to Figure 22 below. Figure 22. RESET Operation tRST R/B I/O0~7 FFh Table5. Device Status Operation Mode After Power-up After Reset Read 1 Waiting for next command 36 Preliminary FLASH MEMORY K9E2G08U0M READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 23). Its value can be determined by the following guidance. Rp VCC ibusy Ready Vcc R/B open drain output VOH VOL : 0.4V, VOH : 2.4V CL VOL Busy tf tr GND Device @ Vcc = 3.3V, Ta = 25°C , CL = 100pF Ibusy tr,tf [s] 300n 200n 1.2 300 3m 200 0.8 2m tr 100 100n 3.6 1K 0.6 tf 3.6 3.6 3.6 2K 3K Rp(ohm) 4K Ibusy [A] 400 2.4 1m Fig 23 Rp vs tr ,tf & Rp vs ibusy Rp value guidance Rp(min) = 3.2V VCC(Max.) - VOL(Max.) IOL + ΣIL = 8mA + ΣIL where IL is the sum of the input currents of all devices tied to the R/B pin. Rp(max) is determined by maximum permissible limit of tr 37 Preliminary FLASH MEMORY K9E2G08U0M Data Protection & Power-up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10µs is required before internal circuit gets ready for any command sequences as shown in Figure 24. The two step command sequence for program/erase provides additional software protection. ≈ Figure 24. AC Waveforms for Power Transition ~ 2.5V High ≈ VCC WE 10µs ≈ ≈ WP 38 ~ 2.5V