Intel AP0C51BH Chmos single-chip 8-bit microcontroller Datasheet

80C31BH/80C51BH/87C51
MCSÉ 51
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
Automotive
Y
Extended Automotive Temperature
Range ( b 40§ C to a 125§ C Ambient)
Y
Programmable Serial Port
Y
TTL- and CMOS-Compatible Logic
Levels
Y
High Performance CHMOS Process
Y
Power Control Modes
Y
64K External Program Memory Space
Y
4 Kbyte On-Chip ROM/EPROM
Y
64K External Data Memory Space
Y
128 x 8-bit RAM
Y
IDLE and POWER DOWN Modes
Y
32 Programmable I/O Lines
Y
ONCE Mode Facilitates System Testing
Y
Two 16-Bit Timer/Counters
Y
Y
5 Interrupt Sources
Available in 12 MHz and 16 MHz
Versions
Quick-Pulse EPROM Programming
Y
Y
Available in PLCC and DIP Packages
Y
2-Level Program Memory Lock EPROM
Y
Boolean Processor
(See Packaging Specification, Order Ý231369)
The MCSÉ 51 CHMOS microcontroller products are fabricated on Intel’s reliable CHMOS process and are
functionally compatible with the standard MCS 51 HMOS microcontroller products. This technology combines
the high speed and density characteristics of HMOS with the low power attributes of CHMOS. This combination expands the effectiveness of the powerful MCS 51 microcontroller architecture and instruction set.
Like the MCS 51 HMOS microcontroller versions, the MCS 51 CHMOS microcontroller products have the
following features: 4 Kbytes of EPROM/ROM (87C51/80C51BH respectively); 128 bytes of RAM; 32 I/O lines;
two 16-bit timer/counters; a five-source two-level interrupt structure; a full duplex serial port; and on-chip
oscillator and clock circuitry. In addition, the MCS 51 CHMOS microcontroller products exhibit low operating
power, along with two software selectable modes of reduced activity for further power reductionÐIdle and
Power Down.
The Idle mode freezes the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to
continue functioning. The Power Down mode saves the RAM contents but freezes the oscillator, causing all
other chip functions to be inoperative.
The 87C51 is the EPROM version of the 80C51BH. It contains 4 Kbytes of on-chip program memory that can
be electrically programmed, and can be erased by exposure to ultraviolet light. The 87C51 EPROM array uses
a modified Quick-Pulse Programming algorithm, by which the entire 4 Kbyte array can be programmed in about
12 seconds.
NOTICE:
This datasheet contains information on products in full production. Specifications within this datasheet
are subject to change without notice. Verify with your local Intel sales office that you have the latest
datasheet before finalizing a design.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
COPYRIGHT © INTEL CORPORATION, 1995
January 1995
Order Number: 270419-007
AUTOMOTIVE 80C31BH/80C51BH/87C51
270419 – 1
Figure 1. MCSÉ 51 Microcontroller Architectural Block Diagram
2
AUTOMOTIVE 80C31BH/80C51BH/87C51
automotive temperature range option, operational
characteristics are guaranteed over the temperature
range of b 40§ C to a 125§ C ambient.
80C31BH/80C51BH/87C51
PRODUCT OPTIONS
Intel’s extended and automotive temperature range
products are designed to meet the needs of those
applications whose operating requirements exceed
commercial standards.
With the extended temperature range option, operational characteristics are guaranteed over the temperature range of b 40§ C to a 85§ C ambient. For the
The automotive and extended temperature versions
of the MCS 51 microcontroller product families are
available with or without burn-in options as listed in
Table 1.
As shown in Figure 2, temperature, burn-in, and
package options are identified by a one- or two-letter
prefix to the part number.
270419 – 2
*Example:
AN80C51 indicates an automotive temperature range version of the 80C51 in a PLCC package with 4 Kbyte ROM
program memory.
Figure 2. MCSÉ 51 Microcontroller Product Family Nomenclature
Table 1. Temperature Options
Temperature
Designation
Operating
Temperature
§ C Ambient
Burn-In
Options
Extended
T
L
b 40 to a 85
b 40 to a 85
Standard
Extended
Automotive
A
B
b 40 to a 125
b 40 to a 125
Standard
Extended
Temperature
Classification
3
AUTOMOTIVE 80C31BH/80C51BH/87C51
Diagrams are for pin reference only. Package sizes are not to scale.
270419 – 3
Pin (PDIP)
*EPROM only
**Do not connect reserved pins
270419 – 4
Pad (PLCC)
Figure 3. Pin Connections
PIN DESCRIPTION
VCC: Supply voltage during normal, Idle, and Power
Down operations.
VSS: Circuit ground.
VSS1: VSS1Ð(EPROM PLCC only) secondary
ground. Provided to reduce ground bounce and improve power supply bypassing.
current (IIL, on the datasheet) because of the internal pullups.
Port 1 also receives the low-order address bytes
during EPROM programming and program verification.
NOTE:
This pin is not a substitute for the VSS pin (pin 22).
For ROM and ROMless, pin 1 is reservedÐdo not
connect.
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pullups. Port 2 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally being pulled low will source
current (IIL, on the data sheet) because of the internal pullups.
Port 0: Port 0 is an 8-bit open drain bidirectional I/O
port. As an output port each pin can sink 8 LS TTL
inputs. Port 0 pins that have 1s written to them float,
and in that state can be used as high-impedance
inputs.
Port 2 emits the high-order address byte during
fetches from external Program memory and during
accesses to external Data Memory that use 16-bit
address (MOVX @ DPTR). In this application it uses
strong internal pullups when emitting 1s.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external memory. In this
application it uses strong internal pullups when emitting 1s.
During accesses to external Data Memory that use
8-bit addresses (MOVX @ Ri), Port 2 emits the contents of the P2 Special Function Register.
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullups are required
during program verification.
Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pullups. Port 1 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally being pulled low will source
4
Port 2 also receives some control signals and the
high-order address bits during EPROM programming
and program verification.
Port 3: Port 3 is an 8-bit bidirectional I/O port with
internal pullups. Port 3 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally being pulled low will source
current (IIL, on the datasheet) because of the pullups.
AUTOMOTIVE 80C31BH/80C51BH/87C51
Port 3 also serves the functions of various special
features of the MCS 51 microcontroller family, as
listed below:
Pin
Name
Alternate Function
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RXD
TXD
INT0
INT1
T0
T1
WR
RD
Serial Input Line
Serial Output Line
External Interrupt 0
External Interrupt 1
Timer 0 External Input
Timer 1 External Input
External Data Memory Write Strobe
External Data Memory Read Strobe
270419 – 5
Figure 4. Using the On-Chip Oscillator
Port 3 also receives some control signals for
EPROM programming and program verification.
RESET: Reset input. A logic high on this pin for two
machine cycles while the oscillator is running resets
the device. An internal pulldown resistor permits a
power-on reset to be generated using only an external capacitor to VCC.
ALE/PROG (EPROM Only): Address Latch Enable
output signal for latching the low byte of the address
during accesses to external memory. This pin is also
the program pulse input (PROG) during EPROM programming.
In normal operation ALE is emitted at a constant
rate of 1/6 the oscillator frequency, and may be
used for external timing or clocking purposes. Note,
however, that one ALE pulse is skipped during each
access to external Data Memory.
PSEN: Program Store Enable is the Read strobe
to External Program Memory. When the
87C51/80C51BH is executing from Internal Program
Memory, PSEN is inactive (high). When the device is
executing code from External Program Memory,
PSEN is activated twice each machine cycle, except
that two PSEN activations are skipped during each
access to External Data Memory.
EA/VPP: External Access enable. EA must be
strapped to VSS in order to enable the
87C51/80C51BH to fetch code from External Program Memory locations starting at 0000H up to
0FFFFH. [Note, however, that if either of the Lock
Bits is programmed, the logic level at EA is internally
latched during reset.] (EPROM only.)
EA must be strapped to VCC for internal program
execution.
VPP (EPROM Only): This pin also receives the
12.75V programming supply voltage (VPP) during
EPROM programming.
270419 – 6
Figure 5. External Clock Drive
XTAL1: Input to the inverting oscillator amplifier and
input to the internal clock generating circuits.
XTAL2: Output from the inverting oscillator amplifier.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 4.
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 is left unconnected, as shown in Figure 5. There are no requirements on the duty cycle of the external clock signal,
since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the Datasheet must be observed.
IDLE MODE
In Idle Mode, the CPU puts itself to sleep while all
the on-chip peripherals remain active. The mode is
invoked by software. The content of the on-chip
RAM and all the Special Functions Registers remain
unchanged during this mode. The Idle Mode can be
terminated by any enabled interrupt or by a hardware reset.
It should be noted that when Idle is terminated by a
hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm
takes control. On-chip hardware inhibits access to
5
AUTOMOTIVE 80C31BH/80C51BH/87C51
Mode
Table 2. Status of the External Pins During Idle and Power Down
Program
ALE
PSEN
PORT0
PORT1
PORT2
Memory
PORT3
Idle
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power Down
Internal
0
0
Data
Data
Data
Data
Power Down
External
0
0
Float
Data
Data
Data
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Applications Handbook, and Application Note AP-252, ‘‘Designing with the 80C51BH.’’
internal RAM in this event, but access to the port
pins is not inhibited. To eliminate the possibility of an
unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that
invokes Idle should not be one that writes to a port
pin or to external memory.
DESIGN CONSIDERATIONS
# At power on, the voltage on VCC and RST must
come up at the same time for a proper start-up.
# Before entering the Power Down mode the contents of the Carry Bit and B.7 must be equal.
# When the Idle mode is terminated by a hardware
POWER DOWN MODE
In the Power Down mode the oscillator is stopped,
and the instruction that invokes Power Down is the
last instruction executed. The on-chip RAM and
Special Function Registers retain their values until
the Power Down mode is terminated.
The only exit from Power Down is a hardware reset.
Reset redefines the SFRs but does not change the
on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and
must be held active long enough to allow the oscillator to restart and stabilize.
reset, the device normally resumes program execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins
in not inhibited. To eliminate the possibility of an
unexpected write when Idle is terminated by reset, the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory.
# An external oscillator may encounter as much as
a 100 pF load at XTAL1 when it starts up. This is
due to interaction between the amplifier and its
feedback capacitance. Once the external signal
meets the VIL and VIH specifications the capacitance will not exceed 20 pF.
# For EPROM versions exposure to light when the
device is in operation may cause logic errors. For
this reason, it is suggested that an opaque label
be placed over the window when the die is exposed to ambient light.
6
AUTOMOTIVE 80C31BH/80C51BH/87C51
PROGRAM MEMORY LOCK
(EPROM Only)
The 87C51 contains two program memory lock
schemes: Encrypted Verify and Lock Bits.
Encrypted Verify: The 87C51 implements a 32byte EPROM array that can be programmed by the
customer, and which can then be used to encrypt
the program code bytes during EPROM verification.
The EPROM verification procedure is performed as
usual, except that each code byte comes out logically X-NORed with one of the 32 key bytes. The key
bytes are gone through in sequence. Therefore, to
read the ROM code, one has to know the 32 key
bytes in their proper sequence.
Lock Bits: Also on the chip are two Lock Bits which
can be left unprogrammed (U) or can be programmed (P) to obtain the following additional features:
Bit 1
Bit 2
Additional Features
U
U
none
P
U
# Externally fetched code can not
access internal Program Memory.
# Further programming disabled.
U
P
(Reserved for Future definition.)
P
P
# Externally fetched code can not
access internal Program Memory.
# Further programming disabled.
# Program verification is disabled.
When Lock Bit 1 is programmed, the logic level at
the EA pin is sampled and latched during reset. If
the device is powered up without a reset, the latch
initializes to a random value, and holds that value
until reset is activated. It is necessary that the
latched value of EA be in agreement with the current
logic level at that pin in order for the device to function properly.
ONCE MODE
The ONCE (‘‘on-circuit emulation’’) mode facilitates
testing and debugging of systems using the 87C51
without the 87C51 having to be removed from the
circuit. The ONCE mode is invoked by:
1. Pull ALE low while the device is in reset and
PSEN is high;
2. Hold ALE low as RST is deactivated.
While the device is in ONCE mode, the Port 0 pins
go into a float state, and the other port pins and ALE
and PSEN are weakly pulled high. The oscillator circuit remains active. While the 87C51 is in this mode,
an emulator or test CPU can be used to drive the
circuit. Normal operation is restored when a normal
reset is applied.
7
AUTOMOTIVE 80C31BH/80C51BH/87C51
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Ambient Temperature Under Bias b 40§ C to a 125§ C
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b 65§ C to a 150§ C
Voltage on EA/VPP Pin to VSS ÀÀÀÀÀÀÀ0V to a 13.0V
Voltage on Any Other Pin to VSS ÀÀ b 0.5V to a 6.5V
IOL per I/O pin ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15 mA
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W
(Based on package heat transfer limitations, not device power consumption).
Typical Junction Temperature (TJ) ÀÀÀÀÀÀÀÀ a 135§ C
(Based upon ambient temperature at a 125§ C)
Typical Thermal Resistance Junction-to-Ambient
(iJA):
PDIP ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ75§ C/W
PLCCÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ46§ C/W
DC CHARACTERISTICS:
(TA e b 40§ C to a 125§ C; VCC e 5V g 10% (5V g 20% EPROM Only); VSS e 0V)
Symbol
Parameter
VIL
Input Low Voltage (Except EA)
VIL1
Input Low Voltage to EA
VIH
Min
Typ(1)
Max
Unit
(87C51/80C51BH)
Test
Conditions
b 0.5
0.2 VCCb0.25
0
0.2 VCCb0.45
V
V
Input High Voltage (Except XTAL1, RST)
0.2VCC a 1.0
VCC a 0.5
V
VIH1
Input High Voltage (XTAL1, RST)
0.7 VCC a 0.1
VCC a 0.5
V
VOL
Output Low Voltage (Ports 1, 2, 3)
0.45(7)
V
IOL e 1.6 mA(2)
VOL1
Output Low Voltage (Port 0, ALE, PSEN)
0.45(7)
V
IOL e 3.2 mA(2)
VOH
Output High Voltage
(Ports 1, 2, 3, ALE, PSEN)
2.4
V
IOH e b60 mA
0.9 VCC
V
IOH e b10 mA
VOH1
Output High Voltage (Port 0 in
External Bus Mode)
2.4
V
IOH e b800 mA
0.9 VCC
V
IOH e b80 mA(3)
IIL
Logical 0 Input Current (Ports 1, 2, 3)
b 75
mA
ITL
Logical 1-to-0 transition current
(Ports 1, 2, 3)
b 750
mA
ILI
Input Leakage Current (Port 0)
g 10
mA
VIN e VIL or VIH
ICC
Power Supply Current:
Active Mode @ 12 MHz (5)
Idle Mode @ 12 MHz (5)
Power Down Mode
25/20
6/5
100/75
mA
mA
mA
VCC e 2.2V to 5.5V
300
KX
10
pF
RRST
Internal Reset Pulldown Resistor
CIO
Pin Capacitance
11.5
1.3
3
50
VIN e 0.45 V
(4)
(6)
NOTES:
1. ‘‘Typicals’’ are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The
values listed are at room temp, 5V.
2. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1to-0 transitions during bus operations. In the worst cases (capacitive loading l 100pF), the noise pulse on the ALE pin may
exceed 0.8V. In such cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt
Trigger STROBE input.
3. Capacitive loading on Ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9 VCC
specification when the address bits are stabilizing.
8
AUTOMOTIVE 80C31BH/80C51BH/87C51
NOTES: (Continued)
4. Pins of Ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition
current reaches its maximum value when VIN is approximately 2V.
5. ICCMAX at other frequencies is given by:
Active Mode: 87C51
ICCMAX e 0.94 c FREQ a 13.71
80Cx1BH ICCMAX e 1.47 c FREQ a 2.36
Idle Mode:
ICCMAX e 0.14 c FREQ a 3.81
where FREQ is the external oscillator frequency in MHz. ICCMAX is given in mA. See Figure 6.
6. See Figures 7 through 10 for ICC test conditions. Minimum VCC for Power Down is 2.0V.
7. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
10 mA
Maximum IOL per port pin:
Maximum IOL per 8-bit port
Port 0:
26 mA
Ports 1, 2, and 3:
15 mA
71 mA
Maximum total IOL for all output pins:
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
270419 – 10
270419 – 7
Figure 8. ICC Test Condition, Idle Mode.
All other pins are disconnected.
Figure 6. ICC vs. FREQ. Valid only
within frequency specifications of the
device under test.
270419 – 11
Figure 9. ICC Test Condition, Power Down
Mode. All other pins are disconnected.
270419 – 8
Figure 7. ICC Test Condition, Active Mode.
All other pins are disconnected.
270419 – 9
Figure 10. Clock Signal Waveform for ICC tests in Active and Idle Modes.
TCLCH e TCHCL e 5 ns.
9
AUTOMOTIVE 80C31BH/80C51BH/87C51
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a ‘T’ (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
A:Address.
C:Clock.
D:Input data.
H:Logic level HIGH.
I:Instruction (program memory contents).
L:Logic level LOW, or ALE.
P:PSEN.
Q:Output data.
R:RD signal.
T:Time.
V:Valid.
W:WR signal.
X:No longer a valid logic level.
Z:Float.
For example,
TAVLL e Time from Address Valid to ALE Low.
TLLPL e Time from ALE Low to PSEN Low.
AC CHARACTERISTICS:
(TA e b 40§ C to a 125§ C; VCC e 5V g 10% (5V g 20% EPROM Only);
VSS e 0V; Load Capacitance for Port 0, ALE, and PSEN e 100 pF; Load Capacitance for All Other
Outputs e 80 pF)
EXTERNAL PROGRAM AND DATA MEMORY CHARACTERISTICS
Symbol
1/TCLCL
Parameter
12 MHz Osc
Variable Oscillator
Min
Min
Max
3.5
12 – 16
Max
Oscillator Frequency
87C51/80C51BH/80C31BH
Units
MHz
TLHLL
ALE Pulse Width
127
2TCLCL b 40
ns
TAVLL
TLLAX
TLLIV
Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instr In
28
48
TCLCL b 55
TCLCL b 35
ns
ns
ns
TLLPL
TPLPH
ALE Low to PSEN Low
PSEN Pulse Width
43
205
TPLIV
TPXIX
TPXIZ
TAVIV
PSEN Low to Valid Instr In
Input Instr Hold After PSEN
Input Instr Float After PSEN
Address Valid to Valid Instr In
TPLAZ
PSEN Low to Address Float
TRLRH
TWLWH
TRLDV
TRHDX
RD Pulse Width
WR Pulse Width
RD Low to Valid Data In
Data Hold After RD High
TRHDZ
TLLDV
TAVDV
Data Float After RD High
ALE Low to Valid Data In
Address Valid to Valid Data In
TLLWL
TAVWL
TQVWX
TWHQX
TRLAZ
TWHLH
ALE Low to RD or WR Low
Address Valid to RD or WR Low
Data Valid to WR Transition
Data Hold After WR High
RD Low to Address Float
RD or WR High to ALE High
10
224
4TCLCL b 110
TCLCL b 40
3TCLCL b 45
135
0
3TCLCL b 115
10
400
6TCLCL b 100
400
6TCLCL b 100
252
0
10
ns
5TCLCL b 165
0
97
517
585
43
TCLCL b 25
5TCLCL b 105
ns
ns
ns
ns
0
59
312
200
203
23
33
ns
ns
300
0
123
3TCLCL b 50
4TCLCL b 130
TCLCL b 60
TCLCL b 50
TCLCL b 40
ns
ns
ns
ns
2TCLCL b 70
8TCLCL b 150
9TCLCL b 165
ns
ns
ns
3TCLCL a 50
ns
ns
ns
ns
ns
ns
0
TCLCL a 40
AUTOMOTIVE 80C31BH/80C51BH/87C51
EXTERNAL PROGRAM MEMORY READ CYCLE
270419 – 12
EXTERNAL DATA MEMORY READ CYCLE
270419 – 13
EXTERNAL DATA MEMORY WRITE CYCLE
270419 – 14
11
AUTOMOTIVE 80C31BH/80C51BH/87C51
EXTERNAL CLOCK DRIVE
Symbol
Parameter
EXTERNAL CLOCK DRIVE WAVEFORM
Min Max Units
1/TCLCL Oscillator Frequency
3.5
3.5
12
16
MHz
TCHCX
High Time
20
TCLCX
Low Time
20
TCLCH
Rise Time
20
ns
TCHCL
Fall Time
20
ns
ns
270419 – 17
ns
SERIAL PORT TIMINGÐSHIFT REGISTER MODE
Symbol
12 MHz
Oscillator
Parameter
Min
TXLXL
Serial Port Clock Cycle Time
Max
Variable
Oscillator
Min
Units
Max
1.0
12TCLCL
ns
ns
TQVXH
Output Data Setup to Clock Rising Edge
700
10TCLCL b 133
TXHQX
Output Data Hold After Clock Rising Edge
50
2TCLCL b 117
TXHDX
Input Data Hold After Clock Rising Edge
0
TXHDV
Clock Rising Edge to Input Data Valid
ms
0
700
ns
10TCLCL b 133
ns
SHIFT REGISTER MODE TIMING WAVEFORMS
270419 – 15
AC TESTING INPUT, OUTPUT WAVEFORMS
270419 – 16
AC inputs during testing are driven at VCC b 0.5 for a Logic ‘‘1’’
and 0.45V for a Logic ‘‘0.’’ Timing measurements are made at VIH
min for a Logic ‘‘1’’ and VIL max for a Logic ‘‘0’’.
12
FLOAT WAVEFORMS
270419 – 18
For timing purposes a port pin is no longer floating when a 100
mV change from load voltage occurs, and begins to float when a
100 mV change from the loaded VOH/VOL level occurs. IOL/IOH
t g 20 mA.
AUTOMOTIVE 80C31BH/80C51BH/87C51
EPROM CHARACTERISTICS
(EPROM Only)
to identify the device. The signature bytes identify
the device as an 87C51 manufactured by Intel.
The 87C51 is programmed by a modified QuickPulse Programming algorithm. It differs from older
methods in the value used for VPP (Programming
Supply Voltage) and in the width and number of the
ALE/PROG pulses.
Table 3 shows the logic levels for reading the signature byte, and for programming the Program Memory, the Encryption Table, and the Lock Bits. The circuit configuration and waveforms for Quick-Pulse
Programming are shown in Figures 11 and 12. Figure 13 shows the circuit configuration for normal
Program Memory verification.
The 87C51 contains two signature bytes that can be
read and used by an EPROM programming system
Table 3. EPROM Programming Modes
MODE
RST
PSEN
Read Signature
1
0
Program Code Data
1
0
Verify Code Data
1
0
Pgm Encryption Table
1
0
Pgm Lock Bit 1
1
0
Pgm Lock Bit 2
1
0
ALE/
PROG
EA/
VPP
P2.7
P2.6
P3.7
P3.6
1
1
0
0
0
0
0*
VPP
1
0
1
1
1
1
0
0
1
1
0*
VPP
1
0
1
0
0*
VPP
1
1
1
1
0*
VPP
1
1
0
0
NOTES:
‘‘1’’ e Valid high for that pin
‘‘0’’ e Valid low for that pin
VPP e 12.75V g 0.25V
VCC e 5V g 20% during programming and verification
*ALE/PROG receives 25 programming pulses while VPP is held at 12.75V. Each programming pulse is low for 100 ms
( g 10 ms) and high for a minimum of 10 ms.
270419 – 19
Figure 11. Programming Configuration
13
AUTOMOTIVE 80C31BH/80C51BH/87C51
270419 – 20
Figure 12. PROG Waveforms
Quick-Pulse Programming
(EPROM Only)
The setup for Microcontroller Quick-Pulse Programming is shown in Figure 11. Note that the 87C51 is
running with a 4 to 6 MHz oscillator. The reason the
oscillator needs to be running is that the device is
executing internal address and program data transfers.
The address of the EPROM location to be programmed is applied to Ports 1 and 2, as shown in
Figure 11. The code byte to be programmed into
that location is applied to Port 0. RST, PSEN, and
pins of Ports 2 and 3 specified in Table 3 are held at
the ‘‘Program Code Data’’ levels indicated in Table
2. Then ALE/PROG is pulsed low 25 times as
shown in Figure 12.
through 1FH, using the ‘‘Pgm Encryption Table’’ levels. Don’t forget that after the Encryption Table is
programmed, verify cycles will produce only encrypted data.
To program the Lock Bits, repeat the 25-pulse programming sequence using the ‘‘Pgm Lock Bit’’ levels. After one Lock Bit is programmed, further programming of the Code Memory and Encryption Table is disabled. However, the other Lock Bit can still
be programmed.
Note that the EA/VPP pin must not be allowed to go
above the maximum specified VPP level for any
amount of time. Even a narrow glitch above that voltage level can cause permanent damage to the device. The VPP source should be well regulated and
free of glitches and overshoot.
To program the Encryption Table, repeat the 25pulse programming sequence for addresses 0
270419 – 21
Figure 13. Program Verification
14
AUTOMOTIVE 80C31BH/80C51BH/87C51
Program Verification
(EPROM Only)
Program/Verify Algorithms
(EPROM Only)
If Lock Bit 2 has not been programmed, the on-chip
Program Memory can be read out for program verification. The address of the Program Memory location
to be read is applied to Ports 1 and 2 as shown in
Figure 13. The other pins are held at the ‘‘Verify
Code Data’’ levels indicated in Table 3. The contents of the addressed location will be emitted on
Port 0. External pullups are required on Port 0 for
this operation. Detailed timing specifications are
shown in later sections of this datasheet.
Any algorithm in agreement with the conditions listed in Table 3, and which satisfies the timing specifications, is suitable.
If the Encryption Table has been programmed, the
data presented at Port 0 will be the Exclusive NOR
of the program byte with one of the encryption bytes.
The user will have to know the Encryption Table
contents in order to correctly decode the verification
data. The Encryption Table itself can not be read
out.
Reading the Signature Bytes
(EPROM Only)
The signature bytes are read by the same procedure
as a normal verification of locations 030H and 031H,
except that P3.6 and P3.7 need to be pulled to a
logic low. The values returned are:
(030H) e 89H indicates manufactured by Intel
Erasure Characteristics
(EPROM Only)
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelengths shorter
than approximately 4,000 Angstroms. Since sunlight
and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in
room level fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to
this type of exposure, it is suggested that an opaque
label be placed over the window.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec/cm2. Exposing the
EPROM to an ultraviolet lamp of 12,000 mW/cm2
rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
Erasure leaves the array in an all 1s state.
(031H) e 57H indicates 87C51
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS:
(TA e 21§ C to 27§ C, VCC e 5V g 20%, VSS e 0V)
Parameter
Min
Max
VPP
Symbol
Programming Supply Voltage
12.5
13.0
V
IPP
Programming Supply Current
50
mA
1/TCLCL
Oscillator Frequency
6
MHz
TAVGL
Address Setup to PROG Low
TGHAX
Address Hold After PROG
48TCLCL
TDVGL
Data Setup to PROG Low
48TCLCL
TGHDX
Data Hold After PROG
48TCLCL
TEHSH
P2.7 (ENABLE) High to VPP
48TCLCL
TSHGL
VPP Setup to PROG Low
10
ms
TGHSL
VPP Hold After PROG
10
ms
TGLGH
PROG Width
90
TAVQV
Address to Data Valid
48TCLCL
TELQV
ENABLE Low to Data Valid
48TCLCL
TEHQZ
Data Float After ENABLE
0
TGHGL
PROG High to PROG Low
10
4
Units
48TCLCL
110
ms
48TCLCL
ms
15
AUTOMOTIVE 80C31BH/80C51BH/87C51
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
270419 – 22
*FOR PROGRAMMING CONDITIONS SEE FIGURE 11.
FOR VERIFICATION CONDITIONS SEE FIGURE 13.
DATASHEET REVISION SUMMARY
The following are the key differences between this datasheet and the -006 version:
1. The ‘‘preliminary’’ status was removed and replaced with production status (no label).
2. Trademark was updated.
The following are the key differences between the -005 and the -006 version of the datasheet:
1. Preliminary notice added to Title page.
2.
3.
4.
5.
Figure 3 Pin Connections the NC** pins are now Reserved** pins.
Figure 3 Pin Connections RST pin is now RESET pin.
RST pin description is now RESET pin description.
Figure 4 the capacitor values have been removed.
6. CERDIP part reference in the D.C. Characteristics section has been removed.
7. ICC Max characteristics have been corrected to reflect test program conditions.
8. TAVIV and TRLDV formulas changed to correlate 12 MHz timings.
The following are the key differences between the -004 and the -005 version of this datasheet:
1. Removed references to burn-in options in Table 1 and added explanation of burn-in offered. Removed
references to commercial temperatures.
2. Deleted reference to ‘‘ b 1’’ designation 16 MHz.
3. Differentiated VCC for ROM/ROMless and EPROM.
The following are the key differences between the -002 and the -003 version of this datasheet:
1. Changed the title to 80C31BH/80C51BH/87C51 CHMOS Single-Chip 8-Bit Microcontroller.
2. Added the pin count for each package version in Figure 2.
3. Removed references to burn-in options in Table 1.
4. Added external oscillator start-up design considerations.
The following are the key differences between the -002 and the -001 version of the 80C51BH datasheet:
1. Maximum IOL per I/O pin added.
2. Note 7 on Maximum Current Specifications added to DC Characterstics.
3. Datasheet Revision Summary added.
16