CML Semiconductor Products
CTCSS Signalling Processor
FX818
D/818/4 July 1997
1.0
Features
Provisional Issue
•
Fast CTCSS Detection
•
Programmable Tone Decoder
•
Non Predictive Tone Detection
•
Programmable Modulator Drivers
•
Low Power 3.3V/5V Operation
•
Programmable Tone Encoders
•
Variable Gain Audio Filter
•
Compact (SSOP and SOIC)
Packaging
1.1
Brief Description
The FX818 is an innovative CTCSS Codec designed for the latest generation of Land Mobile Radio equipment.
The FX818 is full duplex and has many advanced features which assist the operation of modern CTCSS based
systems. The FX818 is electrically, physically and software compatible with the FX828. It permits
manufacturers to add new features to their equipment with minimal design changes.
The FX818 incorporates a programmable tone decoder which can be set to respond to between 1 and 15
CTCSS tones with minimum software intervention. In addition, a 'Fast' CTCSS detector can respond to a
single programmed tone in 60ms, or can be used to provide an output if any CTCSS tone is present at the
detector input. A high resolution tone encoder performs accurate generation of any CTCSS tone in current use.
High pass and low pass filters are included to provide filtering for CTCSS and Voice band signals. On chip
audio summation amplifier and digital adjustable modulator drivers ensure easy integration into equipment.
The FX818 along with the FX828 is offered in a choice of small SSOP and SOIC 24-pin packages. It may be
used with 3.0 to 5.5 volt supply.
1997 Consumer Microcircuits Limited
CTCSS Signalling Processor
FX818
CONTENTS
Section
Page
1.0 Features .......................................................................................................... 1
1.2 Block Diagram ................................................................................................ 3
1.3 Signal List ....................................................................................................... 4
1.3 Signal List ....................................................................................................... 4
1.4 External Components .................................................................................... 6
1.4 External Components .................................................................................... 6
1.5 General Description ....................................................................................... 7
1.5.1 Software Description ..................................................................... 7
1.6 Application Notes......................................................................................... 18
1.6.1 General .......................................................................................... 18
1.6.2 Transmitter ................................................................................... 18
1.6.3 Receiver (Decode) ........................................................................ 18
1.6.4 Receiver (Fast Detect) ................................................................. 19
1.6.5 General Purpose Timer................................................................ 19
1.6.6 Tx / Fast Rx Tone Table ............................................................... 19
1.6.7 Rx Program Tone Table............................................................... 20
1.7 Performance Specification .......................................................................... 21
1.7.1 Electrical Performance ................................................................ 21
1.7.2 Packaging ..................................................................................... 26
Note:
As this product is still in development, it is likely that a number of changes and additions will be made to
this specification. Items marked TBD or left blank will be included in later issues.
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1.2
FX818
Block Diagram
Figure 1 Block Diagram
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1.3
FX818
Signal List
Package
D2/D5
Signal
Pin No.
Name
Description
Type
1
XTALN
O/P
The inverted output of the on-chip oscillator.
2
XTAL/CLOCK
I/P
The input to the on-chip oscillator, for external
Xtal circuit or clock.
3
SERIAL CLOCK
I/P
The "C-BUS" serial clock input. This clock,
produced by the µController, is used for transfer
timing of commands and data to and from the
device. See "C-BUS" Timing Diagram (Figure
4).
4
COMMAND DATA
I/P
The "C-BUS" serial data input from the
µController. Data is loaded into this device in
8-bit bytes, MSB (B7) first, and LSB (B0) last,
synchronised to the SERIAL CLOCK. See
"C-BUS" Timing Diagram (Figure 4).
5
REPLY DATA
O/P
The "C-BUS" serial data output to the
µController. The transmission of REPLY DATA
bytes is synchronised to the SERIAL CLOCK
under the control of the CSN input. This 3-state
output is held at high impedance when not
sending data to the µController. See "C-BUS"
Timing Diagram (Figure 4).
6
CSN
I/P
The "C-BUS" data loading control function: this
input is provided by the µController. Data
transfer sequences are initiated, completed or
aborted by the CSN signal. See "C-BUS" Timing
Diagram (Figure 4).
7
IRQN
O/P
This output indicates an interrupt condition to the
µController by going to a logic "0". This is a
"wire-ORable" output, enabling the connection of
up to 8 peripherals to 1 interrupt port on the
µController. This pin has a low impedance
pulldown to logic "0" when active and a highimpedance when inactive. An external pullup
resistor is required.
The conditions that cause interrupts are
indicated in the IRQ FLAG register and are
effective if not masked out by a corresponding
bit in the IRQ MASK register.
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1.3
FX818
Signal List (continued)
Package
D2/D5
Signal
Pin No.
Name
Description
Type
8
9
NC
NC
10
A/D CAP
11
NC
12
Vss
13
VBIAS
O/P
A bias line for the internal circuitry, held at ½
VDD. This pin must be decoupled by a capacitor
mounted close to the device pins.
14
RX AMP IN
I/P
The inverting input to the Rx input amplifier.
15
RX AMP OUT
O/P
The output of the Rx input amplifier and the input
to the audio filter section.
16
RX AUDIO OUT
O/P
Output of the Rx audio filter section.
17
NC
18
SUM IN
I/P
Input to the audio summing amplifier.
19
SUM OUT
O/P
Output of the audio summing amplifier.
20
MOD1 IN
I/P
Input to MOD1 audio gain control.
21
TX SUB AUDIO OUT
O/P
Output of the CTCSS tone generator.
22
MOD1
O/P
Output of MOD1 audio gain control.
23
MOD2
O/P
Output of MOD2 audio gain control.
24
VDD
Notes: I/P =
O/P =
) No internal connection. Do not make
) any connection to these pins.
O/P
An internal reference voltage for the A to D,
decoupled to VSS by an external capacitor.
No internal connection. Do not make any
connection to this pin.
Power
The negative supply rail (ground).
No internal connection. Do not make any
connection to this pin.
Power
The positive supply rail. Levels and voltages are
dependent upon this supply. This pin should be
decoupled to VSS by a capacitor.
Input
Output
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CTCSS Signalling Processor
1.4
External Components
C1
C2
C3
C4
C5
C6
C7
C8
Notes:
FX818
22pF
22pF
100pF
0.1µF
100pF
0.1µF
Note 2
0.1µF
±20%
±20%
±20%
±20%
±20%
±20%
±20%
±20%
R1
R2
R3
R4
R5
R6
1M
100k
100k
Note 2
22k
Note 1
±5%
±10%
±10%
±10%
±10%
±10%
X1
4.032MHz
±100ppm
1. R2, R6 and C3 form the gain components for the Summing Amplifier. R6 should be chosen as
required from the system specification, using the following formula:
Tx Sub Audio Gain
= −
R2
R6
2. R3, R4, C5 and C7 form the gain components for the Rx Input Amplifier. R4 should be chosen
as required by the signal level, using the following formula:
Gain
= −
R3
R4
C7 x R4 should be chosen so as not to compromise the low frequency performance of this
product.
Figure 2 Recommended External Components
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1.5
FX818
General Description
The FX818 is a programmable CTCSS sub-audio encoder/decoder for use in land mobile radio equipment, see
Figure 1.
The receiver section of the FX818 has a fast/predictive tone detector which operates in parallel with a tone
decoder. The latter decodes a user-programmable set of up to 15 tones and performs a more accurate (but
slower) analysis of the tones detected by the fast/predictive tone detector, which is a single detector that is
switchable to provide either a fast response to any CTCSS tone (FAST DETECT mode) or a fast response to a
single user-programmed CTCSS tone (PREDICTIVE mode).
The high pass audio filter is designed to filter out the CTCSS sub-audio tones. The summing and modulation
amplifiers allow the audio modulation to be controlled digitally via the C-BUS. A general purpose timer is
included.
Each function, and the routing of signals, is flexible and may be configured or controlled by the user's software.
1.5.1
Software Description
Address/Commands
Instructions and data are transferred, via "C-BUS", in accordance with the timing information given in
Figure 4.
Instruction and data transactions to and from the FX818 consist of an Address/Command (A/C) byte
followed by either:
(i)
(ii)
a further instruction or data (1 or 2 bytes) or
a status or Rx data reply (1 byte)
8-bit Write Only Registers
HEX
ADDRESS/
COMMAND
$01
REGISTER
NAME
GENERAL
BIT 7
(D7)
BIT 6
(D6)
BIT 5
(D5)
BIT 4
(D4)
BIT 3
(D3)
BIT 2
(D2)
BIT 1
(D1)
BIT 0
(D0)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
FAST
DETECT
ENABLE
0
0
0
0
LSB
FAST CTCSS
MODE
RESET
CTCSS
$80
SUB-AUDIO
CONTROL
TX
DECODER
ENABLE
ENABLE
CTCSS DECODER BANDWIDTH
$82
SUB-AUDIO
MSB
SET-UP
BIT 3
BIT 2
GENERAL
BPF
BPF
6dB
CONTROL
ENABLE
UN-MUTE
PAD
BIT 1
0
BIT 0
DETECT/
PREDICTIVE
0
0
TIMER
TIMER
0
0
0
ENABLE
RE-CYCLE
BIT 2
BIT 1
BIT 0
0
0
0
BPF
$88
GENERAL
$8B
$8E
GENERAL PURPOSE TIMER
PURPOSE
MSB
TIMER
BIT 7
IRQ
MASK
0
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LSB
BIT 6
BIT 5
BIT 4
BIT 3
GPT
CTCSS
CTCSS
IRQ
IRQ
FAST IRQ
MASK
MASK
MASK
0
0
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CTCSS Signalling Processor
FX818
16-bit Write Only Registers
HEX
ADDRESS/
COMMAND
REGISTER
NAME
BIT 7
(D7)
BIT 6
(D6)
BIT 5
(D5)
BIT 4
(D4)
BIT 3
(D3)
CTCSS TX/
$83
BIT 2
(D2)
BIT 1
(D1)
BIT 0
(D0)
CTCSS TX / FAST RX FREQUENCY
FAST RX
CTCSS (TX)
FREQUENCY (1)
NOTONE
MSB
0
0
CTCSS TX/
BIT 12
BIT 11
BIT 10
BIT 9
BIT 8
BIT 1
BIT 0
CTCSS TX / FAST RX FREQUENCY
FAST RX
FREQUENCY (2)
LSB
BIT 7
CTCSS RX
$84
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
LSB
MSB
BIT 0
BIT 11
CTCSS TONE ADDRESS
PROGRAM
MSB
(1)
BIT 3
BIT 2
BIT 1
CTCSS RX
CTCSS FREQUENCY
BIT 10
BIT 9
BIT 8
BIT 2
BIT 1
BIT 0
BIT 1
BIT 0
BIT 1
BIT 0
CTCSS FREQUENCY
PROGRAM
(2)
$8A
LSB
BIT 7
BIT 6
BIT 5
BIT 4
MOD 1
MSB
ENABLE
BIT 4
MOD 2
MSB
ENABLE
BIT 4
BIT 3
AUDIO
MOD 1
CONTROL
(1)
0
0
LSB
BIT 3
BIT 2
AUDIO
MOD 2
CONTROL
(2)
0
0
LSB
BIT 3
BIT 2
Write Only Register Description
GENERAL RESET (Hex address $01)
The reset command has no data attached to it. It sets the device registers into the specific (all powersaved)
states as listed below:
REGISTER NAME
SUB-AUDIO CONTROL
SUB-AUDIO STATUS
SUB-AUDIO SET-UP
CTCSS TX / FAST RX
FREQUENCY
CTCSS TX / FAST RX
FREQUENCY
CTCSS RX PROGRAM
CTCSS RX PROGRAM
GENERAL CONTROL
AUDIO CONTROL
AUDIO CONTROL
GENERAL PURPOSE TIMER
IRQ MASK
IRQ FLAG
(1)
HEX
ADDRESS
$80
$81
$82
$83
(2)
(1)
(2)
(1)
(2)
$84
$88
$8A
$8B
$8E
$8F
BIT 7
(D7)
0
0
0
0
BIT 6
(D6)
0
0
0
0
BIT 5
(D5)
0
0
0
0
BIT 4
(D4)
0
0
0
0
BIT 3
(D3)
0
X
0
0
BIT 2
(D2)
0
X
0
0
BIT 1
(D1)
0
X
0
0
BIT 0
D0)
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X = undefined
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FX818
SUB-AUDIO CONTROL Register (Hex address $80)
This register is used to control the functions of the device as described below:
CTCSS TX ENABLE
and DECODER
ENABLE
(Bits 7 and 6)
These two bits enable and disable the CTCSS decoder (Rx) or transmitter (Tx)
according to the table below:
Tx
Bit 7
0
0
1
1
Rx
Bit 6
0
1
0
1
Function
Tx disabled, Rx disabled
Tx disabled, Rx enabled
Tx enabled, Rx disabled
Tx enabled, Rx enabled
CTCSS FAST
DETECT ENABLE
(Bit 5)
When this bit is "1", the "FAST CTCSS DETECT" or "FAST CTCSS
PREDICTIVE" mode is enabled, depending upon the setting of FAST CTCSS
MODE (Bit 3 SUB-AUDIO SET-UP Register, $82). When this bit is "0", both
"FAST CTCSS DETECT" and "FAST CTCSS PREDICTIVE" tone detectors are
disabled.
(Bits 4, 3, 2, 1 and 0)
Reserved for future use. These bits should be set to "0".
SUB-AUDIO SET-UP Register (Hex address $82)
This register is used to define the CTCSS parameters, as described below:
CTCSS DECODER
BANDWIDTH
(Bits 7, 6, 5 and 4)
These four bits set the bandwidth of the CTCSS tone decoder according to
the table below:
Bit 7
1
1
1
1
1
1
1
1
FAST CTCSS MODE
(Bit 3)
Bit 6
0
0
0
0
1
1
1
1
Bit 5
0
0
1
1
0
0
1
1
Bit 4
0
1
0
1
0
1
0
1
BANDWIDTH
Will Decode
Will Not Decode
±1.1%
±2.4%
±1.3%
±2.7%
±1.6%
±2.9%
±1.8%
±3.2%
±2.0%
±3.5%
±2.2%
±3.7%
±2.5%
±4.0%
±2.7%
±4.2%
When CTCSS FAST DETECT ENABLE (Bit 5 SUB-AUDIO CONTROL Register,
$80) is "1", this bit selects the "FAST CTCSS DETECT" or the "FAST CTCSS
PREDICTIVE" mode, according to the table below:
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FX818
DETECT/
PREDICTIVE
Bit 3
0
1
Function
DETECT mode
PREDICTIVE mode
If the CTCSS FAST DETECT ENABLE bit is "0" then both modes are
deselected.
(Bits 2, 1 and 0)
Reserved for future use. These should be set to "0".
GENERAL CONTROL Register (Hex address $88)
This register is used to control the functions of the device as described below:
BPF ENABLE
(Bit 7)
When this bit is "1" the audio band-pass filter is enabled. When this bit is "0" the
audio band-pass filter is disabled (powersaved).
BPF UN-MUTE
(Bit 6)
When this bit is "1" the audio band-pass filter output is switched to the RX
AUDIO OUT pin. When this bit is "0" the output of the filter is disconnected from
RX AUDIO OUT, which is then in a high impedance state.
This control, along with BPF ENABLE, allows the filter to power up and settle
internally before switching the output on, to avoid clicks when coming out of
powersave.
BPF 6dB PAD
(Bit 5)
When this bit is "1" a 6dB attenuator is inserted into the output of the audio
band-pass filter. When this bit is "0" the output of the audio band-pass filter is
not attenuated.
(Bits 4, 3 and 2)
Reserved for future use. These should be set to "0".
TIMER ENABLE
(Bit 1)
When this bit goes to a "1" the general purpose timer is restarted and its internal
register is re-loaded from the value specified in the GENERAL PURPOSE
TIMER Register (Hex address $8B). It will then count down from the count held
in its internal register. When this bit is "0" the count down is disabled and the
last pre-programmed value is retained in the timer's internal register.
TIMER RE-CYCLE
(Bit 0)
When this bit is "1" the general purpose timer will re-load its internal register from
the value specified in the GENERAL PURPOSE TIMER Register (Hex Address
$8B) when the count in the internal register reaches zero (i.e. the timeout has
expired). It then restarts the count down, so that the timer continuously cycles.
When this bit is "0" the general purpose timer will stop when the count in the
internal register reaches zero (i.e. the timeout has expired). The timer can only
be restarted by reloading a value into the GENERAL PURPOSE TIMER Register
(Hex address $8B).
If this bit is switched from "1" to "0" whilst the timer is enabled then the timer will
complete the present count before stopping.
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FX818
GENERAL PURPOSE TIMER (GPT) Register (Hex address $8B)
This register is used to preset the value of a countdown timer. Once a binary value has been loaded into this
register, it will be automatically transferred to an internal register within the timer. This internal register is then
decremented at each count interval (1ms) until it reaches zero. On reaching zero, the GPT IRQ FLAG in the
IRQ FLAG Register (Hex address $8F) is set to "1". An interrupt is generated on the IRQN pin if the GPT IRQ
MASK in the IRQ MASK Register (Hex address $8E) is "1" otherwise the GPT IRQ FLAG remains set to "1"
and no interrupt is generated.
When the internal register has reached a count of zero, the action of the timer depends on the setting of the
TIMER RE-CYCLE bit in the GENERAL CONTROL Register (Hex address $88). If the TIMER RE-CYCLE bit
is "1" then the timer will re-load the countdown value from the GENERAL PURPOSE TIMER Register and
restart the countdown from this value. If the TIME RE-CYCLE bit is "0" then the timer will stop and no further
action or timer interrupts will take place until the GENERAL PURPOSE TIMER Register is re-loaded. Loading
the GENERAL PURPOSE TIMER with "0" will cause the timer circuitry to be disabled (i.e. powersaved).
IRQ MASK Register (Hex address $8E)
This register is used to control the interrupts (IRQs) as described below:
(Bits 7, 5, 4, 1 and 0)
Reserved for future use. These should be set to "0".
GPT IRQ MASK
(Bit 6)
When this bit is set to "1" it enables an interrupt that occurs when GPT IRQ
FLAG (Bit 6, IRQ FLAG Register, $8F) changes from "0" to "1". When this
bit is "0" the interrupt is masked.
CTCSS IRQ MASK
(Bit 3)
When this bit is set to "1" it enables an interrupt that occurs when CTCSS
IRQ FLAG (Bit 3, IRQ FLAG Register, $8F) changes from "0" to "1". When
this bit is "0" the interrupt is masked.
CTCSS FAST IRQ
MASK
(Bit 2)
When this bit is set to "1" it enables an interrupt that occurs when CTCSS
FAST IRQ FLAG (Bit 2, IRQ FLAG Register, $8F) changes from "0" to "1".
When this bit is "0" the interrupt is masked.
CTCSS TX/FAST RX FREQUENCY Register (Hex address $83)
This is a 16-bit register. Byte (1) is sent first. When the CTCSS fast detector is enabled, the bits 0 to 12 define
the receive frequency the fast predictive detector is looking for according to the formula below.
When the CTCSS transmitter is enabled, the bits 0 to 12 control the frequency of the transmitted CTCSS tones
according to the formula below.
When the fast detector and the transmitter are both enabled, the bits 0 to 12 define the receive frequency the
fast predictive detector is looking for and the frequency of the transmitted tone according to the formula below
(i.e. Tx tone = predictive tone).
A=
fXTAL (Hz)
16 x fTONE (Hz)
where A is the binary number programmed into the 13 bits.
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FX818
When Bit 7 (in the first 8 bits) is set to "1" the tone output is set at VBIAS or NOTONE without regard to the
number "A" programmed. When Bit 7 is "0" the programmed tone is set on the output. Programming the bits 0
to 12 to "0" puts the Tx into powersave and the output goes to VBIAS. Powersave is also achieved by disabling
the Tx and the FAST DETECT.
CTCSS RX PROGRAM Register (Hex address $84)
This is a 16-bit register. Byte (1) is sent first. The two bytes are used to program the centre frequencies of up
to 15 tones in the sub-audio band that will be decoded by the receiver.
Each tone is identified by its address in bits 7, 6, 5 and 4 of byte (1). The remaining 12 bits contain the data
representing the tone frequency according to the formula below. If a tone is not required the 12 bits should be
set to zero.
Byte 1
Bit
7
Bit
6
Bit
5
Bit
4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Bit
3
Byte 2
Bit
2
Bit
1
Bit
0
Bit
7
Bit
6
<-------------------- N -------------------- >
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
<-------------------- R ------------------->
N is the binary representation of the
following decimal number (n):
R is the nearest 6-bit binary
representation of (r), where:
n = INT (948982 x fTONE / fXTAL)
r = ((237245/fXTAL) - (n/(4 x fTONE))) x 8400
Example: To program 100Hz when using the recommended 4.032MHz Xtal.
n =
=
N =
INT (948982 x 100 / 4.032 x 10^6)
INT (23.536) = 23
010111 (binary)
r
((237245 / 4.032 x 10^6) - (23 / (4 x 100))) x 8400
11.26 (round up if exactly halfway)
=
=
R =
=
11
001011 (binary)
Thus the 12-bit code is 010111001011
The Hex address represented by bits 7, 6, 5 and 4 in byte (1) is used as the code to indicate which tone has
been decoded. This code appears in bits 3, 2, 1 and 0 of the SUB-AUDIO STATUS Register (Hex address
$81). The 15 programmed tones use Hex addresses $0 - $E.
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FX818
AUDIO CONTROL Register (Hex address $8A)
This is a 16-bit register. Byte (1) is sent first. The six least significant bits of the first byte in this register are
used to set the attenuation of the Modulator 1 amplifier and the six least significant bits of the second byte in
this register are used to set the attenuation of the Modulator 2 amplifier, according to the tables below:
BYTE 1
5
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
BYTE 2
Mod. 1 Attenuation
Disabled (VBIAS)
>40dB
12.0dB
11.6dB
11.2dB
10.8dB
10.4dB
10.0dB
9.6dB
9.2dB
8.8dB
8.4dB
8.0dB
7.6dB
7.2dB
6.8dB
6.4dB
6.0dB
5.6dB
5.2dB
4.8dB
4.4dB
4.0dB
3.6dB
3.2dB
2.8dB
2.4dB
2.0dB
1.6dB
1.2dB
0.8dB
0.4dB
0dB
5
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Mod. 2 Attenuation
Disabled (VBIAS)
>40dB
6.0dB
5.8dB
5.6dB
5.4dB
5.2dB
5.0dB
4.8dB
4.6dB
4.4dB
4.2dB
4.0dB
3.8dB
3.6dB
3.4dB
3.2dB
3.0dB
2.8dB
2.6dB
2.4dB
2.2dB
2.0dB
1.8dB
1.6dB
1.4dB
1.2dB
1.0dB
0.8dB
0.6dB
0.4dB
0.2dB
0dB
X = don't care
MOD1 ENABLE
(Bit 5, first byte)
When this bit is "1" the MOD1 attenuator is enabled.
When this bit is "0" the MOD1 attenuator is disabled (i.e. powersaved).
MOD2 ENABLE
(Bit 5, second byte)
When this bit is "1" the MOD2 attenuator and the SUMMER AMP are enabled.
When this bit is "0" they are both disabled (i.e. powersaved).
(Bits 7 and 6, first
and second bytes)
Reserved for future use. These should be set to "0"
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D/818/4
CTCSS Signalling Processor
FX818
8-bit Read Only Registers
HEX
ADDRESS/
COMMAND
$81
$8F
REGISTER
NAME
BIT 7
(D7)
SUB-AUDIO
STATUS
0
IRQ FLAG
0
BIT 6
(D6)
CTCSS
FAST
TONE
GP TIMER
IRQ
FLAG
BIT 5
(D5)
BIT 4
(D4)
BIT 3
(D3)
0
TONE
DECODE
MSB
BIT 3
CTCSS
IRQ
FLAG
BIT 2
(D2)
BIT 1
(D1)
BIT 0
(D0)
CTCSS RX TONE
0
0
BIT 2
CTCSS FAST
IRQ
FLAG
BIT 1
LSB
BIT 0
0
0
Read Only Register Description
SUB-AUDIO STATUS Register (Hex address $81)
This register is used to indicate the status of the device as described below:
(Bit 7)
Reserved for future use. This will be set to "0" but should be ignored by user's
software.
CTCSS FAST TONE
(Bit 6)
When Bit 5 in the SUB-AUDIO CONTROL Register and Bit 3 in the SUB-AUDIO
SET-UP Register are set to enable FAST CTCSS DETECT mode, this bit will be
set to "1" if a periodic tone is detected. If no periodic tone is detected this bit will
be "0".
When bits 5 and 3 are set to enable FAST CTCSS PREDICTIVE mode, this bit
will be set to "1" if a periodic tone that matches the frequency programmed in the
CTCSS TX/FAST RX Register is detected. If no match is found this bit will be
"0".
When Bit 5 in the SUB-AUDIO CONTROL Register is set to "0" this bit will be
"0".
(Bit 5)
Reserved for future use. This will be set to "0" but should be ignored by the
user's software.
TONE DECODE
(Bits 4)
This bit indicates the status of the tone decoder. A "1" indicates a tone has been
detected (TONE DECODE) and a "0" indicates the loss of the tone (NOTONE).
TONE DECODE means that a tone has been decoded and its characteristics are
defined by the bandwidth (See SUB-AUDIO SET-UP Register bits 7, 6, 5 and 4)
and the CTCSS RX TONE number (See SUB-AUDIO STATUS Register bits 3,
2, 1 and 0).
When Bit 6 in the SUB-AUDIO CONTROL Register is set to "0" the TONE
DECODE bit 4 will be set to "0".
Identification of a valid tone which is not in the pre-programmed list of up to 15
tones will cause the decoder to move to the TONE DECODE state with the RX
TONE address of "1111" in bits 3, 2, 1 and 0; indicting a valid, but unrecognised,
tone. Loss of tone will cause the NOTONE timer to be started. If loss of tone
continues for the duration of the timeout period, then the decoder will move to
NOTONE state and the identification of pre-programmed tones will start again.
1997 Consumer Microcircuits Limited
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D/818/4
CTCSS Signalling Processor
CTCSS RX TONE
(Bits 3, 2, 1 and 0)
FX818
These four bits hold a Hex number from $0 to $F. Numbers $0 to $E represent
the address of the CTCSS tone decoded according to the tones programmed in
the CTCSS RX PROGRAM Register, $84. The Hex number $F indicates the
presence of any tone that is not described by CTCSS DECODER BANDWIDTH
(Bits 7, 6, 5 and 4, SUB-AUDIO SET-UP Register, $82) and CTCSS
FREQUENCY (Bits 11 - 0, CTCSS RX PROGRAM Register, $84).
IRQ FLAG Register (Hex address $8F)
This register is used to indicate when the device requires attention as below:
(Bits 7, 5, 4, 1 and 0)
Reserved for future use. These will be set to "0" but should be ignored by user's
software.
GPT IRQ FLAG
(Bit 6)
When the general purpose timer has reached zero in its internal register, this bit
will be set to "1" to indicate the timeout has expired. This bit is cleared to "0" by a
read of the IRQ FLAG Register (Hex address $8F).
CTCSS IRQ FLAG
(Bit 3)
When CTCSS RX DECODE (Bit 4, SUB-AUDIO STATUS Register, $81)
changes state this bit will be set to "1".
This bit is cleared to "0" by a read of the IRQ FLAG Register (Hex address $8F).
CTCSS FAST IRQ
FLAG
(Bit 2)
When CTCSS FAST TONE (Bit 6, SUB-AUDIO STATUS Register, $81) changes
state this bit will be set to "1".
This bit is cleared to "0" by a read of the IRQ FLAG Register (Hex address $8F).
1997 Consumer Microcircuits Limited
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D/818/4
CTCSS Signalling Processor
FX818
The flow chart shows the following modes of operation for the example below:
1.
2.
3.
4.
Decode
Decode and Fast Detect
Decode & Fast Predictive
Transmit, e.g. Tx = 100Hz
)
) e.g. Address 3 = 100Hz, bandwidth = ±2.7%, interrupt enabled
)
Note: $8X is the Hex address/command.
1997 Consumer Microcircuits Limited
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D/818/4
CTCSS Signalling Processor
FX818
The flow chart shows the decoder, fast detect/fast predictive and transmitter enabled with the following
example:
1.
2.
3.
4.
Tx tone generator = 100Hz
Decoder programmed with 100Hz in address 3
Bandwidth setting = ±2.7%
Interrupt enabled
Note: $8X is the Hex address/command.
1997 Consumer Microcircuits Limited
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D/818/4
CTCSS Signalling Processor
1.6
FX818
Application Notes
1.6.1 General
The FX818 is intended for use in radio systems where sub-audio signalling is required for functions such as
trunking, control, selective calling or group calling.
The CTCSS fast/predictive detector is useful for the detection of occupied channels indicating either the
presence of any sub-audio tone, or range of tones, depending if it is set in fast detect or predictive mode. This
will increase the efficiency of scanning and trunking systems, reducing the average time allocated to assessing
each channel.
The facility to decode any of up to 15 programmed tones allows the use of tones for various signalling functions
such as masking a free channel or identifying sub groups within a user's groups.
Adjustable decoder bandwidths permits certainty and signal to noise performance to be traded when
congestion or range limits the system performance.
1.6.2 Transmitter
The transmitter is enabled with Bit 7 in the "SUB-AUDIO CONTROL" register ($80).
The Tx frequency is set using Bit 0 to Bit 12 in the CTCSS TX/FAST RX register ($83) using the formula below:
fXTAL (Hz)
A=
16 x fTONE (Hz)
where A is the binary number programmed into the 13 bits.
When Bit 7 (in the first 8 bits) is set to "1" the tone output is set at VBIAS or NOTONE without regard to the
number "A" programmed. When Bit 7 is "0" the programmed tone is set on the output. Programming the bits 0
to 12 to "0" puts the Tx into powersave and the output goes to VBIAS. Powersave is also achieved by disabling
the Tx and the FAST DETECT (Bits 7 and 5 in the "SUB-AUDIO CONTROL" register $80).
1.6.3 Receiver (Decode)
The CTCSS Receiver (Decoder) should first be set up according to the desired characteristics. This entails
setting the CTCSS decoder bandwidth in the "SUB-AUDIO SET-UP" register ($82), also programming the
centre frequencies of the desired tones in the "CTCSS RX PROGRAM" register ($84). (It can hold up to 15
different tones). Any tone can be in any location. During operation when the device is receiving, the tones are
scanned in the sequence of their location, i.e. $0 first and $E last and once a tone is detected the remaining
tones are not checked. Therefore if two tones are close enough in frequency for their bandwidths to overlap
then the one in the lowest location will be detected.
The CTCSS IRQ MASK in the "IRQ MASK" register ($8E) should also be set as required.
The CTCSS DECODER ENABLE in the "SUB-AUDIO CONTROL" register ($80) should then be set to "1".
Whilst in the Decode mode the FAST DETECT may be enabled (see below). (Bit 5 in the SUB-AUDIO
CONTROL register $80).
When the receiver detects a change in its present state an IRQ will be generated and Bit 3 of the IRQ FLAG
register ($8F) will indicate this.
The change that occurred can be read from Bit 4 of the SUB-AUDIO STATUS register ($81) and if a tone is
indicated by these bits then the number of that tone can be read from Bits 3, 2, 1 and 0 of the same register.
1997 Consumer Microcircuits Limited
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D/818/4
CTCSS Signalling Processor
FX818
1.6.4 Receiver (Fast/Predictive Detector)
This is used for detecting, in the fastest possible time, that sub-audio tones are present on the Rx channel.
Response time is optimised for speed at the expense of frequency resolution.
It can operate in parallel to the Rx decoder. It is enabled using Bit 5 of the "SUB-AUDIO CONTROL" register
($80). It has an IRQ which may be unmasked with Bit 2 of the "IRQ MASK" register ($8E). The "FAST
CTCSS MODE DETECT/PREDICTIVE" Bit 3 in the "SUB-AUDIO SET UP" register ($82) allows for one of two
alternatives in the FAST mode. In DETECT mode it will detect any periodic tone in the sub-audio band and
when in PREDICTIVE mode it will detect specific tones determined by the frequency set in the "CTCSS
TX/FAST RX" register ($83) and the fixed PREDICTIVE mode bandwidth. Successful detection is indicated by
the CTCSS FAST IRQ FLAG Bit 2 in the IRQ FLAG register ($8F), and the CTCSS FAST TONE Bit 6 in the
SUB-AUDIO STATUS register ($81).
1.6.5 General Purpose Timer (GPT)
This may be used in conjunction with the Rx Decoder to form part of the decode algorithm or as a timer for any
other purpose. It has an 8-bit value register "GENERAL PURPOSE TIMER" register ($8B) set in units of
1msec, an IRQ FLAG Bit 6 of the "IRQ FLAG" register ($8F) and an IRQ MASK Bit 6 "IRQ MASK" register
($8E).
1.6.6 Tx / Fast Rx Tone Table
The following table lists the commonly used CTCSS tones and the corresponding values for programming the
transmitter frequency / fast predictive frequency register (Hex address $83).
Freq.
(Hz)
67.0
69.3
71.9
74.4
77.0
79.7
82.5
85.4
88.5
91.5
94.8
97.4
100.0
103.5
107.2
110.9
Byte 1
(hex)
E
E
D
D
C
C
B
B
B
A
A
A
9
9
9
8
Byte 2
(hex)
B1
34
B1
3B
C9
5A
EF
87
1F
C2
62
1B
D8
83
2F
E0
1997 Consumer Microcircuits Limited
Freq.
(Hz)
114.8
118.8
123.0
127.3
131.8
136.5
141.3
146.2
151.4
156.7
159.8
162.2
167.9
173.8
179.9
183.5
Byte 1
(hex)
8
8
8
7
7
7
6
6
6
6
6
6
5
5
5
5
19
Byte 2
(hex)
93
49
1
BC
78
36
F7
BC
80
48
29
12
DD
AA
79
5D
Freq.
(Hz)
186.2
189.9
192.8
196.6
199.5
203.5
206.5
210.7
218.1
225.7
229.1
233.6
241.8
250.3
254.1
Byte 1
(hex)
5
5
5
5
4
4
4
4
4
4
4
4
4
3
3
Byte 2
(hex)
49
2F
1B
2
EF
D6
C4
AC
83
5D
4C
37
12
EF
E0
D/818/4
CTCSS Signalling Processor
FX818
1.6.7 Rx Program Tone Table
The following table lists the commonly used CTCSS tones together with the values for programming the
“CTCSS RX PROGRAM” register (Hex address $84).
N.B.
The values for byte 1 and 2 below apply to tone address 0 only. These values will vary depending on
the location they are programmed into.
Freq.
(Hz)
67.0
69.3
71.9
74.4
77.0
79.7
82.5
85.4
88.5
91.5
94.8
97.4
100.0
103.5
107.2
110.9
Byte 1
(hex)
3
4
4
4
4
4
4
5
5
5
5
5
5
6
6
6
Byte 2
(hex)
D8
9
1B
4E
83
94
CB
2
14
4C
87
94
CB
7
45
82
1997 Consumer Microcircuits Limited
Freq.
(Hz)
114.8
118.8
123.0
127.3
131.8
136.5
141.3
146.2
151.4
156.7
159.8
162.2
167.9
173.8
179.9
183.5
Byte 1
(hex)
6
6
7
7
7
8
8
8
8
9
9
9
9
A
A
A
20
Byte 2
(hex)
C0
D1
10
50
C0
2
44
86
C9
C
48
82
C6
B
84
C2
Freq.
(Hz)
186.2
189.9
192.8
196.6
199.5
203.5
206.5
210.7
218.1
225.7
229.1
233.6
241.8
250.3
254.1
Byte 1
(hex)
A
B
B
B
B
B
C
C
C
D
D
D
E
E
E
Byte 2
(hex)
C9
8
44
83
8A
C9
6
46
C3
41
48
89
8
88
C7
D/818/4
CTCSS Signalling Processor
1.7
Performance Specification
1.7.1
Electrical Performance
FX818
Absolute Maximum Ratings
Exceeding these maximum ratings can result in damage to the device.
Min.
-0.3
-0.3
-30
-20
Max.
7.0
VDD + 0.3
+30
+20
Units
V
V
mA
mA
D2 Package
Total Allowable Power Dissipation at Tamb = 25°C
... Derating
Storage Temperature
Operating Temperature
Min.
Max.
800
13
+125
+85
Units
mW
mW/°C
°C
°C
D5 Package
Total Allowable Power Dissipation at Tamb = 25°C
... Derating
Storage Temperature
Operating Temperature
Min.
Max.
550
9
+125
+85
Units
mW
mW/°C
°C
°C
Max.
5.5
+85
4.0324032
Units
V
°C
MHz
Supply (VDD - VSS)
Voltage on any pin to VSS
Current into or out of VDD and VSS pins
Current into or out of any other pin
-55
-40
-55
-40
Operating Limits
Correct operation of the device outside these limits is not implied.
Notes
Supply (VDD - VSS)
Operating Temperature
Xtal Frequency
1997 Consumer Microcircuits Limited
21
Min.
3.0
-40
4.0315968
D/818/4
CTCSS Signalling Processor
FX818
Operating Characteristics
For the following conditions unless otherwise specified:
Xtal Frequency = 4.032MHz
Audio Level 0dB ref = 308mVrms at 1kHz
VDD = 3.3V to 5.0V, Tamb = -40°C to +85°C.
Composite Signal = 308mVrms at 1kHz + 75mVrms Noise + 31mVrms Sub-Audio Signal
Noise Bandwidth = 5kHz Band Limited Gaussian
DC Parameters
At VDD = 3.3V
IDD (powersaved, VDD = 5.0V)
IDD (powersaved, VDD = 3.3V)
IDD (Tx/Rx Operating VDD = 5.0V)
IDD (Tx/Rx Operating VDD = 3.3V)
"C-BUS" Interface
Input Logic "1"
Input Logic "0"
Input Leakage Current (Logic "1" or "0")
Input Capacitance
Output Logic "1" (IOH = 120µA)
Output Logic "0" (IOL = 360µA)
"Off" State Leakage Current (Vout = VDD)
AC Parameters
CTCSS Decoder
Sensitivity
Response Time
De-Response Time
Frequency Range
(Pure CTCSS Tone)
(Composite Signal)
(Composite Signal)
CTCSS Detector - Fast Detect
Sensitivity
(Pure CTCSS Tone)
Response Time
(Composite Signal)
Frequency Range
CTCSS Detector - Fast Predictive
Sensitivity
(Pure CTCSS Tone)
Response Time
(Composite Signal)
Frequency Range
Decode Bandwidth
CTCSS Encoder
Frequency Range
Tone Frequency Resolution
Tone Amplitude Tolerance
Total Harmonic Distortion
1997 Consumer Microcircuits Limited
Notes
Min.
Typ.
Max.
Units
1, 2
1, 2
1, 2
1, 2
-
0.6
0.35
3.5
1.6
1.0
0.6
6.0
2.5
mA
mA
mA
mA
6
70%
-1.0
90%
-
-
30%
1.0
7.5
10%
10
VDD
VDD
µA
pF
VDD
VDD
µA
5
60
-26.0
140
145
-
253
dB
ms
ms
Hz
5
60
-26.0
56.0
253
dB
ms
Hz
5
7
60
-
-26.0
37.0
40
253
-
dB
ms
Hz
Hz
60
-1.0
-
0
2.0
253
0.3
+1.0
-
Hz
%
dB
%
1
9
22
D/818/4
CTCSS Signalling Processor
FX818
Audio Band-Pass Filter
Passband
Passband Gain (at 1.0kHz)
Passband Ripple (w.r.t. gain at 1.0kHz)
Stopband Attenuation
Residual Hum and Noise
Alias Frequency
Notes
Min.
Typ.
Max.
Units
8
8
8
8
300
-2
33.0
-
0
-50.0
63
3000
+0.5
-
Hz
dB
dB
dB
dBp
kHz
-
2.0
500
-
10
-
70.0
5.0
6.0
-
dB
MHz
MΩ
kΩ
-0.2
-1.0
0
-
0.2
1.0
dB
dB
-
600
15.0
-
Ω
kΩ
-0.2
-0.6
0
-
0.2
0.6
dB
dB
-
600
-
Ω
1
-
0.95
242
-
ms
ms
40.0
10.0
20.0
-
-
ns
MΩ
dB
Output Impedances
TX SUB-AUDIO OUT and (Enabled)
RX AUDIO OUT
(Disabled)
Rx Amp and Summing Amp
Open Loop Gain
(I/P = 1mV at 100Hz)
Unity Gain Bandwidth
Input Impedance
(at 100Hz)
Output Impedance
(Open Loop)
Transmitter Modulator Drives:
Mod.1 Attenuator
Attenuation (at 0dB)
Cumulative Attenuation Error
(wrt attenuation at 0dB)
Output Impedance
Input Impedance (at 100Hz)
3
Mod.2 Attenuator
Attenuation (at 0dB)
Cumulative Attenuation Error
(wrt attenuation at 0dB)
Output Impedance
3
General Purpose Timer
Timing Period Range
Count Interval
Xtal/Clock Input
Pulse Width ('High' or 'Low')
Input Impedance (at 100Hz)
Gain (I/P = 1mVrms at 100Hz)
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
4
k
k
At VDD = 5.0V only. Signal levels or currents are proportional to VDD.
Not including any current drawn from the device pins by external circuitry.
Small signal impedance, at VDD = 5.0V and Tamb = 25°C.
Timing for an external input to the XTAL/CLOCK pin.
With input gain components set as recommended in Figure 2.
IRQN pin.
From one tone to another tone.
See filter response (Figure 3).
Measured at MOD1 or MOD2 output.
1997 Consumer Microcircuits Limited
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D/818/4
CTCSS Signalling Processor
1.7.1
FX818
Electrical Performance (continued)
10
0
-20
250Hz
Gain (dB)
-10
-30
-40
-60
10
3kHz
300Hz
-50
100
1000
10000
100000
Frequency (Hz)
Figure 3 Audio Band-Pass Filter Frequency Response
1997 Consumer Microcircuits Limited
24
D/818/4
CTCSS Signalling Processor
1.7.1
FX818
Electrical Performance (continued)
Timing Diagrams
Figure 4 "C-BUS" Timing
For the following conditions unless otherwise specified:
Xtal Frequency = 4.032MHz, VDD = 3.3V to 5.0V, Tamb = -40°C to +85°C.
Parameter
Notes
Min.
Typ.
Max.
Units
tCSE
"CS-Enable to Clock-High"
2.0
-
µs
tCSH
Last "Clock-High to CS-High"
4.0
-
µs
tHIZ
"CS-High to Reply Output 3-state"
-
2.0
µs
tCSOFF
"CS-High" Time between transactions
2.0
-
µs
tNXT
"Inter-Byte" Time
4.0
-
µs
tCK
"Clock-Cycle" time
2.0
-
µs
Notes:
1. Depending on the command, 1 or 2 bytes of COMMAND DATA are transmitted to the peripheral
MSB (Bit 7) first, LSB (Bit 0) last. REPLY DATA is read from the peripheral MSB (Bit 7) first, LSB
(Bit 0) last.
2. Data is clocked into and out of the peripheral on the rising SERIAL CLOCK edge.
3. Loaded commands are acted upon at the end of each command.
4. To allow for differing µController serial interface formats "C-BUS" compatible ICs are able to work
with either polarity SERIAL CLOCK pulses.
1997 Consumer Microcircuits Limited
25
D/818/4
CTCSS Signalling Processor
1.7.2
FX818
Packaging
Figure 5 Mechanical Outline: Order as part no. FX818D2
Figure 6 Mechanical Outline: Order as part no. FX818D5
Handling precautions: This product includes input protection, however, precautions should be taken to prevent
device damage from electro-static discharge. CML does not assume any responsibility for the use of any
circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at any time without
notice to change the said circuitry and this product specification. CML has a policy of testing every product
shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing
of all circuit parameters is not necessarily performed.
CONSUMER MICROCIRCUITS LIMITED
1 WHEATON ROAD
WITHAM - ESSEX
CM8 3TD - ENGLAND
Telephone:
Telefax:
e-mail:
+44 1376 513833
+44 1376 518247
[email protected]
http://www.cmlmicro.co.uk