LINER LTC3586-1 Power management solution for application processor Datasheet

LTC3676/LTC3676-1
Power Management Solution
for Application Processors
Features
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Description
Quad I2C Adjustable High Efficiency Step Down
DC/DC Converters: 2.5A, 2.5A, 1.5A, 1.5A
Three 300mA LDO Regulators (Two Adjustable)
DDR Power Solution with VTT and VTTR Reference
Pushbutton ON/OFF Control with System Reset
Independent Enable Pin-Strap or I2C Sequencing
Programmable Autonomous Power-Down Control
Dynamic Voltage Scaling
Power Good and Reset Functions
Selectable 2.25MHz or 1.12MHz Switching Frequency
Always Alive 25mA LDO Regulator
12µA Standby Current
Low Profile 40-Lead 6mm  6mm QFN and 48-Lead
Exposed Pad LQFP
Applications
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Supports Freescale i.MX6, ARM Cortex, and Other
Application Processors
Handheld Instruments and Scanners
Portable Industrial and Medical Devices
Automotive Infotainment
High End Consumer Devices
Multi-Rail Systems
The LTC®3676 is a complete power management solution
for advanced portable application processor-based systems. The device contains four synchronous step-down
DC/DC converters for core, memory, I/O, and system
on-chip (SoC) rails and three 300mA LDO regulators for
low noise analog supplies. The LTC3676-1 has a ±1.5A
buck regulator configured to support DDR termination
plus a VTTR reference output. An I2C serial port is used
to control regulator enables, power-down sequencing,
output voltage levels, dynamic voltage scaling, operating
modes and status reporting.
Regulator start-up is sequenced by connecting outputs to
enable pins in the desired order or via the I2C port. System
power-on, power-off and reset functions are controlled by
pushbutton interface, pin inputs, or I2C.
The LTC3676 supports i.MX, PXA and OMAP processors
with eight independent rails at appropriate power levels.
Other features include interface signals such as the VSTB
pin that toggles between programmed run and standby
output voltages on up to four rails simultaneously. The
device is available in a 40-lead 6mm  6mm QFN and
48‑lead exposed pad LQFP packages.
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
of Analog Devices, Inc. All other trademarks are the property of their respective owners.
Typical Application
VIN
2.7V TO 5.5V
VRTC
3V
25mA
VDD(HIGH)
2.97V
300mA
VLDO3
1.8V
300mA
3V
300mA
LDO1
1µF
VIN
SW3
LTC3676-1
LDO2
SW2
Start-Up Sequence
1.5µH
1.5µH
1µF
LDO3
SW4
SW1
VDDR (VDDQ)
1.5V
47µF 2.5A
1.5µH
VTT
1/2 VDDQ
1.5A
47µF
1µF
6
ENABLES VTTR
PWR_ON WAKE
ON
PGOOD
I 2C
GND
VSOC
1.38V
47µF 1.5A
1.5µH
1µF
LDO4
VARM
1.38V
47µF 2.5A
WAKE
5V/DIV
VLDO3
1V/DIV
VARM AND VSOC
VDDR
1V/DIV
VTTR (1/2 VDDQ)
WAKE
2
VDD(HIGH)
VTT AND VTTR
1ms/DIV
3676 TA01b
TO µPROCESSOR
3676 TA01a
3676ff
For more information www.linear.com/LTC3676
1
LTC3676/LTC3676-1
Absolute Maximum Ratings
(Note 1)
VIN, DVDD, SW1, SW2, SW3, SW4................ –0.3V to 6V
SW1, SW2, SW3, SW4
(Transient t < 1µs, Duty Cycle < 5%)................ –2V to 7V
PVIN1, PVIN2, PVIN3, PVIN4, VIN_L2,
VIN_L3, VIN_L4................................... –0.3V to VIN + 0.3V
LDO1, FB_L1, LDO2, FB_L2, LDO3, LDO4, FB_L4,
FB_B1, FB_B2, FB_B3, FB_B4, PGOOD, VSTB, EN_B1,
EN_B2, EN_B3, EN_B4, EN_L2, EN_L3, EN_L4, ON,
WAKE, RSTO, PWR_ON, IRQ, VTTR,
VDDQIN........................................................ –0.3V to 6V
SDA, SCL.......................................–0.3V to DVDD + 0.3V
Operating Junction Temperature Range
(Notes 2, 3)............................................. –40°C to 150°C
Storage Temperature Range.......................–65 to 150°C
Pin Configuration
40 39 38 37 36 35 34 33 32 31
SW2
IRQ
WAKE
EN_B2
PVIN2
PVIN1
EN_B1
TOP VIEW
RSTO
PGOOD
SW1
SW2
IRQ
WAKE
EN_B2
PVIN2
PVIN1
EN_B1
TOP VIEW
RSTO
PGOOD
LTC3676-1
SW1
LTC3676
40 39 38 37 36 35 34 33 32 31
FB_L2 1
30 EN_L2
FB_L2 1
30 EN_L2
VIN_L2 2
29 ON
VIN_L2 2
29 ON
LDO2 3
28 LDO1
LDO2 3
LDO3 4
27 VIN
LDO3 4
VIN_L3 5
28 LDO1
27 VIN
26 FB_L1
VIN_L3 5
25 FB_B2
LDO4 6
VIN_L4 7
24 FB_B1
VIN_L4 7
24 FB_B1
FB_L4 8
23 FB_B4
VDDQIN 8
23 FB_B4
EN_L4 9
22 FB_B3
VTTR 9
EN_L3 10
21 PWR_ON
41
GND
26 FB_L1
25 FB_B2
22 FB_B3
EN_L3 10
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
SW3
VSTB
EN_B3
EN_B4
PVIN3
PVIN4
SCL
SDA
DVDD
SW3
VSTB
EN_B3
EN_B4
PVIN3
PVIN4
SCL
SDA
11 12 13 14 15 16 17 18 19 20
DVDD
11 12 13 14 15 16 17 18 19 20
SW4
21 PWR_ON
SW4
LDO4 6
41
GND
UJ PACKAGE
40-LEAD (6mm × 6mm) PLASTIC QFN
TJMAX = 150°C, JA = 33°C/W, JC = 2°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
LTC3676
TJMAX = 150°C, JA = 33°C/W, JC = 2°C/W
EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB
LTC3676-1
TOP VIEW
49
GND
36
35
34
33
32
31
30
29
28
27
26
25
NC
EN_L2
ON
LDO1
VIN
FB_L1
FB_B2
FB_B1
FB_B4
FB_B3
PWR_ON
NC
NC 1
FB_L2 2
VIN_L2 3
LDO2 4
LDO3 5
VIN_L3 6
LD04 7
VIN_L4 8
VDDQIN 9
VTTR 10
EN_L3 11
NC 12
49
GND
36
35
34
33
32
31
30
29
28
27
26
25
NC
EN_L2
ON
LDO1
VIN
FB_L1
FB_B2
FB_B1
FB_B4
FB_B3
PWR_ON
NC
NC 13
SW4 14
DVDD 15
SDA 16
SCL 17
PVIN4 18
PVIN3 19
EN_B4 20
EN_B3 21
VSTB 22
SW3 23
NC 24
NC 13
SW4 14
DVDD 15
SDA 16
SCL 17
PVIN4 18
PVIN3 19
EN_B4 20
EN_B3 21
VSTB 22
SW3 23
NC 24
NC 1
FB_L2 2
VIN_L2 3
LDO2 4
LDO3 5
VIN_L3 6
LD04 7
VIN_L4 8
FB_L4 9
EN_L4 10
EN_L3 11
NC 12
48
47
46
45
44
43
42
41
40
39
38
37
48
47
46
45
44
43
42
41
40
39
38
37
NC
SW1
PGOOD
RST0
EN_B1
PVIN1
PVIN2
EN_B2
WAKE
IRQ
SW2
NC
NC
SW1
PGOOD
RST0
EN_B1
PVIN1
PVIN2
EN_B2
WAKE
IRQ
SW2
NC
TOP VIEW
LXE PACKAGE
48-LEAD (7mm × 7mm) PLASTIC LQFP
LXE PACKAGE
48-LEAD (7mm × 7mm) PLASTIC LQFP
TJMAX = 150°C, JA = 19°C/W, JC = 3°C/W
EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB
TJMAX = 150°C, JA = 19°C/W, JC = 3°C/W
EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB
3676ff
2
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
Order Information
http://www.linear.com/product/LTC3676#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3676EUJ#PBF
LTC3676EUJ#TRPBF
LTC3676UJ
40-Lead (6mm  6mm) Plastic QFN
–40°C to 125°C
LTC3676IUJ#PBF
LTC3676IUJ#TRPBF
LTC3676UJ
40-Lead (6mm  6mm) Plastic QFN
–40°C to 125°C
LTC3676HUJ#PBF
LTC3676HUJ#TRPBF
LTC3676UJ
40-Lead (6mm  6mm) Plastic QFN
–40°C to 150°C
LTC3676EUJ-1#PBF
LTC3676EUJ-1#TRPBF
LTC3676UJ-1
40-Lead (6mm  6mm) Plastic QFN
–40°C to 125°C
LTC3676IUJ-1#PBF
LTC3676IUJ-1#TRPBF
LTC3676UJ-1
40-Lead (6mm  6mm) Plastic QFN
–40°C to 125°C
LTC3676HUJ-1#PBF
LTC3676HUJ-1#TRPBF
LTC3676UJ-1
40-Lead (6mm  6mm) Plastic QFN
–40°C to 150°C
LEAD FREE FINISH
TRAY
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3676ELXE#PBF
LTC3676ELXE#PBF
LTC3676LXE
48-Lead (7mm  7mm) Plastic eLQFP
–40°C to 125°C
LTC3676ILXE#PBF
LTC3676ILXE#PBF
LTC3676LXE
48-Lead (7mm  7mm) Plastic eLQFP
–40°C to 125°C
LTC3676HLXE#PBF
LTC3676HLXE#PBF
LTC3676LXE
48-Lead (7mm  7mm) Plastic eLQFP
–40°C to 150°C
LTC3676ELXE-1#PBF
LTC3676ELXE-1#PBF
LTC3676LXE-1
48-Lead (7mm  7mm) Plastic eLQFP
–40°C to 125°C
LTC3676ILXE-1#PBF
LTC3676ILXE-1#PBF
LTC3676LXE-1
48-Lead (7mm  7mm) Plastic eLQFP
–40°C to 125°C
LTC3676HLXE-1#PBF
LTC3676HLXE-1#PBF
LTC3676LXE-1
48-Lead (7mm  7mm) Plastic eLQFP
–40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
3676ff
For more information www.linear.com/LTC3676
3
LTC3676/LTC3676-1
Electrical Characteristics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_L2 = VIN_L3 =
VIN_L4 = DVDD = 3.8V. All regulators disabled unless otherwise noted.
PARAMETER
CONDITIONS
Operating Input Supply Voltage, VIN
VIN Standby Current
MIN
l
PWR_ON = 0V
TYP
2.7
12
l
MAX
UNITS
5.5
V
21
µA
PVIN
V
50
200
300
µA
µA
µA
0.05
µA
Step-Down Switching Regulators 1, 2, 3 and 4
Output Voltage Range
VFB
Burst Mode VIN Quiescent Current
Pulse-Skipping Mode VIN Quiescent Current
Forced Continuous VIN Quiescent Current
VFB = 850mV (Note 5)
VFB = 850mV (Note 5)
VFB = 0V (Note 5)
Feedback Pin Input Current
VFB = 850mV
Maximum Duty Cycle
VFB = 0V
®
23
120
170
l
l
l
–0.05
100
%
SW Pull-Down Resistance
Regulator Disabled
625
Ω
Feedback Reference Soft-Start Rate
(Note 6)
0.8
V/ms
High Feedback Regulation Voltage (VFB)
DVBxA[4:0] = DVBxB[4:0] = 11111,
VIN = 2.7V to 5.5V
l
788
800
812
mV
Default Feedback Regulation Voltage (VFB)
DVBxA[4:0] = DVBxB[4:0] = 11001,
VIN = 2.7V to 5.5V
l
714
725
736
mV
Low Feedback Regulation Voltage (VFB)
DVBxA[4:0] = DVBxB[4:0] = 00000,
VIN = 2.7V to 5.5V
l
404
412.5
421
mV
Feedback LSB Step Size
Switching Frequency
12.5
BUCKx[2] = 0
BUCKx[2] = 1
l
l
1.7
0.85
l
2
2.25
1.125
mV
2.7
1.35
MHz
MHz
1.5A Step-Down Switching Regulators 1 and 2
PMOS Current Limit
A
PMOS On-Resistance (Note 7)
160
mΩ
NMOS On-Resistance (Note 7)
80
mΩ
2.5A Step-Down Switching Regulators 3 and 4
PMOS Current Limit
l
3.0
A
PMOS On-Resistance (Note 7)
120
mΩ
NMOS On-Resistance (Note 7)
70
mΩ
Step-Down Switching Regulator 1 and VTTR (LTC3676-1)
Buck 1 Feedback Regulation Voltage
VDDQIN = 1.5V
l
VTTR – 10
VTTR
VTTR + 10
mV
VTTR Output Voltage
VDDQIN = 1.5V
l
0.49•VDDQIN
0.5•VDDQIN
0.51•VDDQIN
mV
l
–10
VTTR Maximum Output Current
IVIN VTTR Enabled
10
mA
1
mA
10
V/ms
625
Ω
LDO Regulators 2, 3 and 4
Feedback Reference Soft-Start Rate
Output Pull-Down Resistance
Regulator Disabled
LDO Regulator 1
Output Voltage Range
VIN
VFB_L1
Feedback Regulation Voltage (VFB_L1)
l
689
725
761
mV
Line Regulation
ILDO1 = 1mA, VLDO1 = 1.2V,
VIN = 2.7V to 5.5V
0.15
%/V
Load Regulation
ILDO1 = 0.1mA to 25mA,
VLDO1 = 3.3V
0.1
%
3676ff
4
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
Electrical Characteristics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_L2 = VIN_L3 =
VIN_L4 = DVDD = 3.8V. All regulators disabled unless otherwise noted.
PARAMETER
CONDITIONS
Available Output Current
MIN
l
Short-Circuit Output Current Limit
Dropout Voltage (Note 4)
ILDO1 = 25mA, VLDO1 = 3.3V
Feedback Pin Input Current
VFB_L1 = 850mV
TYP
MAX
25
UNITS
mA
65
100
mA
200
280
mV
–0.05
0.05
µA
1.7
VIN
V
VFB_L2
VIN_L2
V
LDO Regulator 2
VIN_L2 Input Voltage
LDO2 Output Voltage Range
l
ILDO2 = 1mA
Available Output Current
l
300
mA
VIN_L2 Quiescent Current
VIN_L2 Shutdown Current
Regulator Enabled, ILDO2 = 0A
Regulator Disabled
l
l
12
0
25
1
µA
µA
VIN Quiescent Current
Regulator Enabled
l
50
85
µA
0.725
0.743
V
Feedback Regulation Voltage (VFB_L2)
l
0.707
Line Regulation
ILDO2 =1mA, VIN = 2.7V to 5.5V
0.01
%/V
Load Regulation
ILDO2 = 1mA to 300mA
0.01
%
Dropout Voltage (Note 4)
ILDO2 = 300mA, VLDO2 = 2.5V
ILDO2 = 300mA, VLDO2 = 1.2V
210
450
Feedback Pin Input Current
VFB_L2 = 725mV
Short-Circuit Current Limit
–0.05
770
mA
260
615
mV
mV
0.05
µA
VIN
V
1.854
V
LDO Regulator 3
VIN_L3 Input Voltage
Output Voltage
VIN_L3 = VIN, ILDO3 = 1mA
Available Output Current
l
2.35
l
1.746
l
300
1.8
mA
VIN_L3 Quiescent Current
VIN_L3 Shutdown Current
Regulator Enabled, ILDO3 = 0A
Regulator Disabled
l
l
14
0
25
1
50
85
VIN Quiescent Current
Regulator Enabled
l
Line Regulation
ILDO3 =1mA, VIN = 2.7V to 5.5V
0.01
%/V
Load Regulation
ILDO3 = 1mA to 300mA
0.05
%
ILDO3 = 300mA, VLDO3 = 1.8V
280
Short-Circuit Current Limit
Dropout Voltage (Note 4)
µA
µA
µA
770
mA
350
mV
1.7
VIN
V
VFB_L4
VIN_L4
V
LDO Regulator 4
VIN_L4 Input Voltage
LDO4 Output Voltage Range (LTC3676)
l
ILDO4 = 1mA
Feedback Regulation Voltage (LTC3676) (VFB_L4)
Output Voltage (LTC3676-1)
ILDO4 = 1mA, LDOB[4:3] = 00
LDOB[4:3] = 01
LDOB[4:3] = 10
LDOB[4:3] = 11
Available Output Current
l
0.707
0.725
0.743
V
l
l
l
l
1.164
2.425
2.716
2.91
1.2
2.5
2.8
3.0
1.236
2.575
2.884
3.09
V
V
V
V
l
300
mA
VIN_L4 Quiescent Current
VIN_L4 Shutdown Current
Regulator Enabled, ILDO4 = 0A
Regulator Disabled
l
l
12
0
25
1
µA
µA
VIN Quiescent Current
Regulator Enabled
l
50
85
µA
Line Regulation
ILDO4 =1mA, VIN = 2.7V to 5.5V
0.01
%/V
3676ff
For more information www.linear.com/LTC3676
5
LTC3676/LTC3676-1
Electrical Characteristics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_L2 = VIN_L3 =
VIN_L4 = DVDD = 3.8V. All regulators disabled unless otherwise noted.
PARAMETER
CONDITIONS
Load Regulation (LTC3676)
Load Regulation (LTC3676-1)
ILDO4 = 1mA to 300mA
MIN
0.01
0.05
TYP
Dropout Voltage (Note 4)
ILDO4 = 300mA, VLDO4 = 2.5V
ILDO4 = 300mA, VLDO4 = 1.2V
210
450
Feedback Pin Input Current (LTC3676)
VFB_L4 = 725mV
Short-Circuit Current Limit
–0.05
MAX
UNITS
%
%
770
mA
260
615
mV
mV
0.05
µA
1.2
V
Enable Inputs
0.75
Threshold Rising
All Enables Low
l
Threshold Falling
One Enable High
l
0.4
0.7
Precision Threshold
One or More Enables
l
0.370
0.400
Input Pull-Down Resistance
0.430
4.5
V
MΩ
VSTB, PWR_ON Inputs
Threshold
l
0.370
Pull-Down Resistance
0.400
0.430
4.5
V
MΩ
Pushbutton Interface
ON Threshold Rising
ON Threshold Falling
ON Input Current
l
l
ON = VIN
ON = 0V
0.4
–1
0.75
0.7
–40
1.2
V
V
1
µA
µA
ON Low Time to IRQ Low
50
ms
ON High Time to IRQ High
0.2
µs
ON Low Time to WAKE High
ON Low Time to Hard Reset
CNTRL[6] = 0
IRQ Minimum Pulse Width
400
ms
10
sec
50
ms
IRQ Blanking from WAKE Low
1
sec
Minimum WAKE Low Time
1
sec
WAKE High Time with PWR_ON = 0V
5
sec
PWR_ON High to WAKE High
3
ms
PWR_ON Low to WAKE Low
3
ms
Status Output Pins (WAKE, PGOOD, RSTO, IRQ)
WAKE Output Low Voltage
IWAKE = 3mA
WAKE Output High Leakage Current
VWAKE = 3.8V
PGOOD Output Low Voltage
IPGOOD = 3mA
PGOOD Output High Leakage Current
VPGOOD = 3.8V
0.1
–0.1
0.1
–0.1
PGOOD Threshold Rising
PGOOD Threshold Falling
0.4
V
0.1
µA
0.4
V
0.1
µA
–6
–8
RSTO Output Low Voltage
IRSTO = 3mA
RSTO Output High Leakage Current
VRSTO = 3.8V
0.1
–0.1
LDO1 Power Good Threshold Rising
LDO1 Power Good Threshold Falling
%
%
0.4
V
0.1
µA
–7.5
–10
IRQ Output Low Voltage
IIRQ = 3mA
IRQ Output High Leakage Current
VIRQ = 3.8V
0.1
–0.1
%
%
0.4
V
0.1
µA
3676ff
6
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
Electrical Characteristics
The l denotes the specifications which apply over the specified operating
junction temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = PVIN1 = PVIN2 = PVIN3 = PVIN4 = VIN_L2 = VIN_L3 =
VIN_L4 = DVDD = 3.8V. All regulators disabled unless otherwise noted.
PARAMETER
CONDITIONS
Undervoltage Lockout Rising
Undervoltage Lockout Falling
Undervoltage Warning
SYMBOL
I2C Port
DVVDD
IDVDD
DVVDD_UVLO
ADDRESS
VIH
VIL
IIH
IIL
VOL_SDA
fSCL
tBUF
tHD_STA
tSU_STA
tSU_STO
tHD_DAT(O)
tHD_DAT(I)
tSU_DAT
tLOW
tHIGH
tf
tr
tSP
l
l
MIN
TYP
MAX
UNITS
2.35
2.55
2.45
2.65
V
V
PARAMETER
DVDD Input Supply Voltage
DVDD Quiescent Current
DVDD UVLO Level
LTC3676 Device Address
LTC3676-1 Device Address
SDA/SCL Input Threshold Rising
SDA/SCL Input Threshold Falling
SDA/SCL High Input Current
SDA/SCL Low Input Current
SDA Output Low Voltage
Clock Operating Frequency
Bus Free Time Between Stop and Start
Condition
Hold Time After Repeated Start Condition
Repeated Start Condition Setup Time
Stop Condition Setup Time
Data Hold Time Output
Data Hold Time Input
Data Setup Time
SCL Clock Low Period
SCL Clock High Period
Clock/Data Fall Time
Clock/Data Rise Time
Input Spike Suppression Pulse Width
V
V
V
V
V
V
V
V
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
CNTRL[4:2] = 000 (POR Default)
CNTRL[4:2] = 001
CNTRL[4:2] = 010
CNTRL[4:2] = 011
CNTRL[4:2] = 100
CNTRL[4:2] = 101
CNTRL[4:2] = 110
CNTRL[4:2] = 111
CONDITIONS
MIN
l
1.6
SCL/SDA = 0kHz
SDA = SCL = 5.5V
SDA = SCL = 0V
ISDA = 3mA
TYP
–1
–1
0.3
1
0111100[R/W]
0111101[R/W]
70
30
0
0
MAX
5.5
1
1
1
0.4
400
1.3
CB = Capacitance of BUS Line (pF)
CB = Capacitance of BUS Line (pF)
Note 1: Stresses beyond those listed Under Absolute Maximum ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3676 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3676E is guaranteed to meet specifications from
0°C to 85°C junction temperature. Specifications over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3676I is guaranteed over the –40°C to 125°C operating junction
temperature range and the LTC3676H is guaranteed over the full –40°C to
150°C operating junction temperature range. High junction temperatures
0.6
0.6
0.6
0
0
100
1.3
0.6
20 + 0.1CB
20 + 0.1CB
900
300
300
50
UNITS
V
µA
V
%DVDD
%DVDD
µA
µA
V
kHz
µs
µs
µs
µs
ns
ns
ns
µs
µs
ns
ns
ns
degrade operating lifetimes; operating lifetime is derated for junction
temperatures greater than 125°C. The junction temperature (TJ in °C) is
calculated from the ambient temperature (TA in °C) and power dissipation
(PD, in Watts), and package to junction ambient thermal impedance
(JA in Watts/°C ) according to the formula:
TJ = TA + (PD • JA).
Note that the maximum ambient temperature consistent with these
specifications is determined by specific operating conditions in
conjunction with board layout, the rated package thermal impedance and
other environmental factors.
3676ff
For more information www.linear.com/LTC3676
7
LTC3676/LTC3676-1
Electrical Characteristics
Note 3: The LTC3676 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 150°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 4: Dropout voltage is defined as (VIN – VLDO1) for LDO1 or
(VIN_Lx – VLDOx) for other LDOs when VLDOx is 3% lower than VLDOx
measured with VIN = VIN_Lx = 4.3V.
Note 5: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency.
Note 6: Soft-Start measured in test mode with regulator error amplifier in
unity-gain mode.
Note 7: The switching regulator PMOS and NMOS on-resistance is
guaranteed by correlation to wafer level measurements.
Typical Performance Characteristics
Standby IVIN vs VIN
Step-Down Switching Regulator
IVIN vs VIN
LDO2 to LDO4 IVIN vs VIN
16
900
250
ENABLE 3 LDOs
14
8
6
4
ENABLE 2 LDOs
150
ENABLE 1 LDO
100
400
ENABLE ONE BUCK
200
100
3.5
4.0
4.5
5.0
0
2.50
5.5
4.50
3.50
1200
Burst Mode OPERATION
VIN CURRENT (µA)
ENABLE TWO BUCKS
ENABLE ONE BUCK
60
2.30
ALL REGULATORS ENABLED
2.25
PULSE-SKIPPING
ENABLE THREE BUCKS
80
40
800
600
400
Burst Mode OPERATION
3.0
3.5
4.0
4.5
VOLTAGE (V)
5.0
5.5
3676 G04
0
–50
2.20
2.15
2.10
2.05
200
20
2.5
5.5
Oscillator Frequency
vs Temperature
1000
ENABLE FOUR BUCKS
5.0
3676 G03
Input Supply Current
vs Temperature
160
120
3.5
4.0
4.5
VOLTAGE (V)
3.0
3676 G02
Step-Down Switching Regulator
IVIN vs VIN
100
2.5
VIN (V)
3676 G01
140
0
5.50
FREQUENCY (MHz)
3.0
VOLTAGE (V)
IVIN (µA)
ENABLE TWO BUCKS
500
300
50
0
2.5
0
ENABLE THREE BUCKS
600
2
180
ENABLE FOUR BUCKS
700
IVIN (µA)
VIN CURRENT (µA)
10
PULSE-SKIPPING MODE
800
200
12
IVIN (µA)
VIN = 3.8V, TA = 25°C unless otherwise noted
STANDBY
0
100
50
TEMPERATURE (°C)
150
3676 G05
2.00
–50
0
50
100
TEMPERATURE (°C)
150
3676 G06
3676ff
8
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
Typical Performance Characteristics
Oscillator Frequency Change
vs VIN
100
0.4
90
90
80
80
BURST
70
EFFICIENY (%)
0.2
0
–0.2
60
PULSE
SKIPPING
50
40
FORCED
CONTINUOUS
30
–0.4
3.5
3.0
4.0
4.5
5.0
0
5.5
1
VIN (V)
1
1000
100
10
LOAD CURRENT (mA)
3676 G09
Buck RDS(ON) vs VIN
200
250
VIN = 3.3V
90 PULSE-SKIPPING MODE
180
VOUT = 2.5V
VOUT = 1.2V
50
40
BUCK 1, 2 PMOS
150
140
BUCK 3, 4 PMOS
BUCK 1, 2 NMOS
100
30
BUCK 3, 4 PMOS
120
100
BUCK 1, 2 NMOS
80
BUCK 3, 4 NMOS
60
BUCK 3, 4 NMOS
50
20
BUCK 1, 2 PMOS
160
200
RDS(ON) (mΩ)
EFFICIENY (%)
VIN = 5V
VOUT = 1.2V
0
Buck RDS(ON) vs Temperature
100
60
FORCED
CONTINUOUS
3676 G08
Step-Down Switching Regulators 3
and 4 Efficiency vs IOUT
70
40
10
1000
100
10
LOAD CURRENT (mA)
3676 G07
80
PULSE
SKIPPING
50
20
VIN = 3.3V
VOUT = 1.2V
10
–0.8
2.5
60
30
20
–0.6
BURST
70
RDS(ON) (mΩ)
PERCENT CHANGE (%)
0.6
100
EFFICIENY (%)
0.8
40
20
10
0
Step-Down Switching Regulators 1
and 2 Efficiency vs IOUT
Step-Down Switching Regulators 1
and 2 Efficiency vs IOUT
100
10
LOAD CURRENT (mA)
1
0
–50
1000
0
50
100
TEMPERATURE (°C)
3676 G10
150
0
VIN (V)
3676 G12
3676 G11
Step-Down Switching Regulator
Current Limit vs Temperature
5.5
4.5
3.5
2.5
LTC3676-1 VDDQIN, VTTR and
VTT Start-Up
Step-Down Switching Regulator
Load Step
4.5
CURRENT (A)
PGOOD
5V/DIV
BUCK 3, 4
4.0
VDDQIN
1V/DIV
3.5
500mA/DIV
VTT (BUCK1)
1V/DIV
2.5
2.0
1.5
–50
ILOAD = 0.5A TO 1.5A
VTTR
1V/DIV
BUCK 1, 2
3.0
400µs/DIV
0
50
100
TEMPERATURE (°C)
VOUT = 1.2V
100mV/DIV
3676 G14
COUT = 44µF
10µs/DIV
3676 G15
150
3676 G13
3676ff
For more information www.linear.com/LTC3676
9
LTC3676/LTC3676-1
Typical Performance Characteristics
LDO1 Dropout Voltage
vs Temperature
400
LTC3676-1
ILOAD = –1.2A TO 1.2A
1A/DIV
COUT = 88µF
80
ILDO1 = 25mA
350
VTT = 0.75V
DROPOUT VOLTAGE (mV)
100mV/DIV
LDO1 Short-Circuit Current
vs Temperature
LDO1 SHORT-CIRCUIT CURRENT (mA)
LTC3676-1 VTT Load Step
40µs/DIV
VLDO1 = 1.8V
300
250
VLDO1 = 3.3V
200
150
100
3676 G16
50
0
–55
0
50
70
65
60
55
50
45
40
–55
150
100
TEMPERATURE (°C)
75
0
50
100
TEMPERATURE (°C)
3676 G17
450
ILDO = 200mA
400
DROPOUT VOLTAGE (mV)
1.2V
20mA
ILDO1
10mA/DIV
3676 G18
LDO2 to LDO4 Dropout Voltage
vs Temperature
LDO1 Load Step Response
VLDO1
50mV/DIV
1mA
40µs/DIV
150
3676 G19
VLDO = 1.2V
350
300
VLDO = 1.8V
250
200
VLDO = 3.3V
150
100
50
0
–50
0
50
100
TEMPERATURE (°C)
150
3676 G20
LDO2 to LDO4 Short-Circuit
Current vs Temperature
LDO2 to LDO4 Load Step Response
LDO SHORT-CIRCUIT CURRENT (mA)
800
750
700
50mV/DIV
VLDO = 1.8V
650
600
ILOAD = 220mA
550
100mA/DIV
500
10mA
450
400
10µs/DIV
350
300
–50
0
50
100
TEMPERATURE (°C)
3676 G22
150
3676 G21
3676ff
10
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
Pin Functions
(QFN/LQFP)
FB_L2 (Pin 1/Pin 2): Feedback Input for LDO2. Set fullscale output voltage using a resistor divider connected
from LDO2 to this pin to ground.
SW4 (Pin 11/Pin 14): Switch Pin for Step-Down Switching Regulator 4. Connect one side of step-down switching
regulator 4 inductor to this pin.
VIN_L2 (Pin 2/Pin 3): Power Input for LDO2. This pin
should be bypassed to ground with a 1μF or greater
ceramic capacitor.Voltage on VIN_L2 should not exceed
voltage on VIN pin.
DVDD (Pin 12/Pin 15): Supply Voltage for I2C Serial Port.
This pin sets the logic reference level of SCL and SDA I2C
pins. DVDD resets I2C registers to power-on state when
driven to <1V. SCL and SDA logic levels are scaled to
DVDD. Connect a 0.1µF decoupling capacitor from this
pin to ground.
LDO2 (Pin 3/Pin 4): Output Voltage of LDO2. Nominal
output voltage is set with a resistor feedback divider that
servos to a fixed 725mV reference. This pin must be bypassed to ground with a 1µF or greater ceramic capacitor.
LDO3 (Pin 4/Pin 5): Output Voltage of LDO3. Nominal
output voltage is a fixed 1.8V. This pin must be bypassed
to ground with a 1µF or greater ceramic capacitor.
VIN_L3 (Pin 5/Pin 6): Power Input for LDO3. This pin
should be bypassed to ground with a 1µF or greater
ceramic capacitor.Voltage on VIN_L3 should not exceed
voltage on VIN pin.
LDO4 (Pin 6/Pin 7): Output Voltage of LDO4. Nominal
output voltage is set with a resistor feedback divider that
servos to a fixed 725mV reference. This pin must be bypassed to ground with a 1µF or greater ceramic capacitor.
VIN_L4 (Pin 7/Pin 8): Power Input for LDO4. This pin
should be bypassed to ground with a 1μF or greater
ceramic capacitor.Voltage on VIN_L4 should not exceed
voltage on VIN pin.
FB_L4 (Pin 8/Pin 9): Feedback Input for LTC3676 LDO4.
Set full-scale output voltage using a resistor divider connected from LDO4 to this pin to ground.
VDDQIN (Pin 8/Pin 9): VDD Sense Input for LTC3676-1.
Tie DDR memory VDD supply to this pin.
EN_L4 (Pin 9/Pin 10): Enable LDO4 Input for LTC3676.
Active high enables LDO4. A weak pull-down pulls EN_L4
low when left floating.
VTTR (Pin 9/Pin 10): DDR VREF Output Pin for LTC3676‑1.
Buffered reference equal to one-half VDDQIN voltage on
Pin 8.
EN_L3 (Pin 10/Pin 11): Enable LDO3 Input. Active high
enables LDO3. A weak pull-down pulls EN_L3 low when
left floating.
SDA (Pin 13/Pin 16): Data Pin for the I2C Serial Port. The
I2C logic levels are scaled with respect to DVDD.
SCL (Pin 14/Pin 17): Clock Pin for the I2C Serial Port. The
I2C logic levels are scaled with respect to DVDD.
PVIN4 (Pin 15/Pin 18): Power Input for Step-Down Switching Regulator 4. Tie this pin to VIN supply. This pin should
be bypassed to ground with a 10μF or greater ceramic
capacitor.
PVIN3 (Pin 16/Pin 19): Power Input for Step-Down Switching Regulator 3. Tie this pin to the VIN supply. This pin
should be bypassed to ground with a 10μF or greater
ceramic capacitor.
EN_B4 (Pin 17/Pin 20): Enable Step-Down Switching
Regulator 4. Active high input enables step-down switching
regulator 4. A weak pull-down pulls EN_B4 low when left
floating.
EN_B3 (Pin 18//Pin 21): Enable Step-Down Switching
Regulator 3. Active high input enables step-down switching
regulator 3. A weak pull-down pulls EN_B3 low when left
floating.
VSTB (Pin 19/Pin 22): Voltage Standby. When VSTB is
low, the DAC registers are selected by command register
bit DVBxA[5]. When VSTB is high, the DAC registers are
forced to DVBxB registers. Tie VSTB to ground if unused.
SW3 (Pin 20/Pin 23): Switch Pin for Step-Down Switching Regulator 3. Connect one side of step-down switching
regulator 3 inductor to this pin.
PWR_ON (Pin 21/Pin 26): External Power On. Handshaking
pin to acknowledge successful power-on sequence.
PWR_ON must be driven high within five seconds of
WAKE going high to keep power on. PWR_ON can be
3676ff
For more information www.linear.com/LTC3676
11
LTC3676/LTC3676-1
Pin Functions
used to activate the WAKE output by driving high. Drive
low to shut down WAKE.
FB_B3 (Pin 22/Pin 27): Feedback Input for Step-Down
Switching Regulator 3. Set full-scale output voltage using
resistor divider connected from the output of step-down
switching regulator 3 to this pin to ground.
FB_B4 (Pin 23/Pin 28): Feedback Input for Step-Down
Switching Regulator 4. Set full-scale output voltage using
resistor divider connected from the output of step-down
switching regulator 4 to this pin to ground.
FB_B1 (Pin 24/Pin 29): Feedback Input for Step-Down
Switching Regulator 1. Set full-scale output voltage using
resistor divider connected from the output of step-down
switching regulator 1 to this pin to ground.
FB_B2 (Pin 25/Pin 30): Feedback Input for Step-Down
Switching Regulator 2. Set full-scale output voltage using
resistor divider connected from the output of step-down
switching regulator 2 to this pin to ground.
FB_L1 (Pin 26/Pin 31): Feedback Input for LDO1. Set
output voltage using a resistor divider connected from
LDO1 to this pin to ground.
VIN (Pin 27/Pin 32): Supply Voltage Input. This pin should
be bypassed to ground with a 1μF or greater ceramic
capacitor. All switching regulator PVIN supplies should
be tied to VIN.
LDO1 (Pin 28/Pin 33): Always On LDO1 Output. This pin
provides an always-on supply voltage useful for light loads
such as a watchdog microprocessor or a real time clock.
Connect a 1μF capacitor from LDO1 to ground.
ON (Pin 29/Pin 34): Pushbutton Input. A weak internal
pull-up forces ON high when left floating. A normally open
pushbutton is connected from ON to ground forcing a low
state when pushed.
EN_L2 (Pin 30/Pin 35): Enable LDO2 Input. Active high
enables LDO2. A weak pull-down pulls EN_L2 low when
left floating.
SW2 (Pin 31/Pin 38): Switch Pin for Step-Down Switching Regulator 2. Connect one side of step-down switching
regulator 2 inductor to this pin.
IRQ (Pin 32/Pin 39): Interrupt Request Output. Open-drain
driver is pulled low for power good, undervoltage, and
overtemperature warning and fault conditions. Clear IRQ
by writing to the I2C CLIRQ command register.
WAKE (Pin 33/Pin 40): System Wake Up. Open-drain
driver output releases high when signaled by pushbutton
activation or PWR_ON input. It may be used to initiate
a pin-strapped power-up sequence by connecting to a
regulator enable pin.
EN_B2 (Pin 34/Pin 41): Enable Step-Down Switching
Regulator 2. Active high input enables step-down switching
regulator 2. A weak pull-down pulls EN_B2 low when left floating.
PVIN2 (Pin 35/Pin 42): Power Input for Step-Down Switching Regulator 2. Tie this pin to VIN supply. This pin should
be bypassed to ground with a 10μF or greater ceramic
capacitor.
PVIN1 (Pin 36/Pin 43): Power Input for Step-Down Switching
Regulator 1. Tie this pin to VIN supply. This pin should be bypassed
to ground with a 10μF or greater ceramic capacitor.
EN_B1 (Pin 37/Pin 44): Enable Step-Down Switching
Regulator 1. Active high enables step-down switching
regulator 1. The LTC3676-1 EN_B1 pin enables both VTTR
output and switching regulator 1. A week pull-down pulls
EN_B1 low when left floating.
RSTO (Pin 38/Pin 45): Reset Output. Open-drain output
pulls low when the always-on regulator LDO1 is below
regulation or during a hard reset initiated by a pushbutton
input or command registers.
PGOOD (Pin 39/Pin 46): Power Good Output. Open-drain
output pulls low when any enabled regulator falls below
power good threshold or during dynamic voltage slew
unless disabled in command register. Pulls low when all
regulators are disabled.
SW1 (Pin 40/Pin 47): Switch Pin for Step-Down Switching Regulator 1. Connect one side of step-down switching
regulator 1 inductor to this pin.
GND (Exposed Pad Pin 41/Pin 49): Ground. The exposed
pad must be connected to a continuous ground plane of
the printed circuit board by multiple interconnect vias
directly under the LTC3676 to maximize electrical and
thermal conduction.
3676ff
12
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
Block Diagram—LTC3676
VIN
LDO1
BUCK1
EN
725mV
DAC
LDO1
FB_L1
DEFAULT = 725mV
VREF
EN
BUCK2
PUSHBUTTON
ON/OFF
CONTROL
DAC
DEFAULT = 725mV
DAC
EN_B3
PRECISION ENABLE
THRESHOLD AND
SEQUENCE DELAY
EN_L3
7
DEFAULT = 725mV
VREF
EN
OK
SCL
7
7
DAC
I2C COMMAND
REGISTERS
DEFAULT = 725mV
VREF
EN
OK
FAULT DETECTION
UNDER VOLTAGE
OVER TEMPERATURE
725mV
VREF
FB_B4
LDO2
EN
OK
VA 4x5
VREF
VB 4x5
FB_L2
LDO3
VIN_L3
LDO3
5
DYNAMIC VOLTAGE
SCALING CONTROL
VIN_L2
LDO2
VSEL
VSTB
PVIN4
SW4
RANGE = 800mV
TO 412.5mV
IRQ
PGOOD
FB_B3
BUCK4
DVDD
PVIN3
SW3
RANGE = 800mV
TO 412.5mV
EN_L4
SDA
FB_B2
BUCK3
EN_B2
PVIN2
SW2
EN
OK
EN_B1
EN_L2
VREF
RANGE = 800mV
TO 412.5mV
RSTO
EN_B4
FB_B1
OK
WAKE
PWR_ON
SW1
RANGE = 800mV
TO 412.5mV
ON
PVIN1
5
EN
OK
5
5
VREF
LDO4
VIN_L4
LDO4
GND
(EXPOSED PAD)
EN
OK
FB_L4
3676 BD
3676ff
For more information www.linear.com/LTC3676
13
LTC3676/LTC3676-1
Block Diagram—LTC3676-1
VIN
LDO1
BUCK1
EN
725mV
VREF
SW1
LDO1
FB_L1
EN
WAKE
PWR_ON
FB_B1
OK
ON
BUCK2
PUSHBUTTON
ON/OFF
CONTROL
DAC
DEFAULT = 725mV
VREF
EN
FB_B2
OK
BUCK3
EN_B1
DAC
EN_B2
EN_B3
EN_B4
EN_L2
PRECISION ENABLE
THRESHOLD AND
SEQUENCE DELAY
7
DEFAULT = 725mV
VREF
EN
OK
7
DAC
VDDQIN
DEFAULT = 725mV
SDA
VREF
EN
OK
7
725mV
I2C COMMAND
REGISTERS
VREF
FB_B4
LDO2
VIN_L2
LDO2
EN
OK
IRQ
VREF
PGOOD
PVIN4
SW4
RANGE = 800mV
TO 412.5mV
VDDQIN/2
SCL
FB_B3
BUCK4
DVDD
PVIN3
SW3
RANGE = 800mV
TO 412.5mV
EN_L3
VTTR
PVIN2
SW2
RANGE = 800mV
TO 412.5mV
RSTO
PVIN1
FAULT DETECTION
UNDER VOLTAGE
OVER TEMPERATURE
FB_L2
LDO3
VIN_L3
LDO3
EN
OK
VSEL
VA 4x5
VB 4x5
VREF
5
VSTB
DYNAMIC VOLTAGE
SCALING CONTROL
5
LDO4
VIN_L4
LDO4
5
EN
OK
GND
(EXPOSED PAD)
36761 BD
3676ff
14
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
Operation
INTRODUCTION
PVINB1
VTTR
The LTC3676-1 supports DDR memory applications by
replacing the LTC3676 LDO4 feedback and enable pins
with VDDQIN and VTTR pins. The DDR VDD supply is
connected to the LTC3676-1 VDDQIN pin. A buffered DDR
termination voltage equal to one half the voltage on VDDQIN is output on VTTR. The VTTR voltage is connected
internally on the LTC3676-1 to the reference side of the
Buck1 error amplifier. When Buck1 is configured with a
gain of one, its output can be used as at DDR termination
supply. Table 1 shows the functional differences between
the LTC3676 and LTC3676-1.
Table 1. Functional Differences LTC3676 vs LTC3676-1
LTC3676
LTC3676-1
Buck1 Default
Frequency
2.25MHz
1.125MHz
Buck1 Default
Mode
Pulse-Skipping
Forced Continuous
Buck1 Output
External Resistor Divider.
Slewing DAC Reference
External Unity Gain.
VTTR Reference
LDO4 Enable
EN_L4 Pin or I2C
I2C
LDO4 Output
External Resistor Divider.
725mV Reference
I2C Select 1 of 4 Fixed
Outputs
FB_L4 Pin
External Resistor Divider
—
EN_L4 Pin
Enable LDO4.
—
VDDQIN Pin
—
Connect to DDR Memory
Supply
VTTR Pin
—
Buffered Output Equals
One-Half VDDQIN
I2C Device
Address
Write = 0x78
Read = 0x79
Write = 0x7A
Read = 0x7B
BUCK1
VDDQIN/2
DDR
REF
PWM
The LTC3676 is a complete power management solution
for portable microprocessors and peripheral devices. It
generates a total of eight voltage rails for supplying power
to the processor core, DDR memory, I/O, always-on realtime clock and HDD functions. Supplying the voltage rails
are an always-on low quiescent current 25mA LDO, two
2.5A step-down regulators, two 1.5A step-down regulators, and three 300mA low dropout regulators. Supporting
the multiple regulators is a highly configurable power-on
sequencing capability, dynamic voltage scaling DAC output
voltage control, a pushbutton interface controller, control
via an I2C interface, and extensive status and interrupt
outputs.
VDDQIN
ERROR
AMP
SW1
VDDQIN/2
CFB
FB_B1
R1
COUT
3676 F01
Figure 1. VTT Buck Regulator and VTTR Reference Block Diagram
Always-On 25mA Low Dropout Regulator
The LTC3676 includes a low quiescent current low dropout
regulator that remains powered whenever a valid supply is
present on VIN. The always-on LDO1 remains active until
VIN drops below 2.0V (typical). This is below the 2.5V
undervoltage threshold in effect for the rest of the LTC3676
circuits. The always-on LDO is used to provide power to a
standby microcontroller, real-time clock, or other keep-alive
circuits. The LDO is guaranteed to support a 25mA load. A
1µF low impedance ceramic bypass capacitor from LDO1 to
GND is required for compensation. A power good monitor
pulls RSTO low whenever LDO1 is 8% below its regulation
target. LDO1 has current limit circuitry to protect from
short circuit and overloading. The output voltage of LDO1
is set with a resistor divider connected from LDO1 output
pin to the feedback pin FB_L1, as shown in Figure 2. The
output voltage is calculated using the following formula:
⎛ R1⎞
VLDO1 = 725 • ⎜ 1+ ⎟ (mV )
⎝ R2 ⎠
300mA Low Dropout Regulators
Three LDO regulators on the LTC3676 will each deliver
up to 300mA output. Each LDO regulator has separate
input supply to help manage power loss in the LDO output
devices. The LDO regulators are enabled by pin input or I2C
command register. When disabled, the regulator outputs
are pulled to ground through a 625Ω resistor. A low ESR
1µF ceramic capacitor should be tied from the LDO output
to ground. The 300mA LDO regulators have current limit
control circuits. The LDO input voltages, VIN_L2, VIN_L3,
and VIN_L4 must be at potential of VIN or less.
The LDO regulator I2C command register controls are
shown in Table 2 and Table 3.
3676ff
For more information www.linear.com/LTC3676
15
LTC3676/LTC3676-1
Operation
LTC3676 Resistor Programmable LDO2 and LDO4
LDO2 and LDO4 output voltages are programmed by resistor dividers tied from the LDO output pin to the feedback
pin as shown in Figure 2. The output voltage is calculated
using the following formula:
⎛ R1⎞
VLDO = 725 • ⎜ 1+ ⎟ (mV )
⎝ R2 ⎠
output is 1.2V with selectable outputs of 2.5V, 2.8V, and
3.0V. LDO4 is enabled only through the command register
bit LDOB[2].
LDO4 Command Register Controls
Table 3. LDO4 Control Command Register Settings
COMMAND
REGISTER[BIT] VALUE SETTING
LDOB[0]
0*
1
Do Not Keep Alive LDO4 in Standby
Keep Alive LDO4 in Standby
LDOB[1]
0*
1
Enable LDO4 at Any Output Voltage
Enable LDO4 Only if Output Voltage is <300mV
LDOB[2]
(LTC3676)
0*
1
LDO4 Disabled if EN_L4 is Low
LDO4 Enabled
LDOB[2]
(LTC3676-1)
0*
1
LDO4 Disabled
LDO4 Enabled
LDOB[4:3]
(LTC3676-1)
00*
LDO4 Output = 1.2V
LDOB[4:3]
(LTC3676-1)
01
LDO4 Output = 2.5V
Fixed Output LDO3
LDOB[4:3]
(LTC3676-1)
10
LDO4 Output = 2.8V
Regulator LDO3 has a fixed voltage output of 1.8V.
LDOB[4:3]
(LTC3676-1)
11
LDO4 Output = 3V
Table 2. LDO2 and LDO3 Control Command Register Settings
*denotes default power-on value.
COMMAND
REGISTER[BIT] VALUE SETTING
STEP-DOWN SWITCHING REGULATORS
VIN
0.725V
+
–
LDO
FB
1µF
R1
R2
3676 F02
Figure 2. LDO1, LDO2 and LDO4 Application Circuit
LDOA[0]
0*
1
Do Not Keep Alive LDO2 in Standby
Keep Alive LDO2 in Standby
LDOA[1]
0*
1
Enable LDO2 at Any Output Voltage
Enable LDO2 Only if Output Voltage is <300mV
LDOA[2]
0*
1
LDO2 Disabled if EN_L2 is Low
LDO2 Enable
LDOA[3]
0*
1
Do Not Keep Alive LDO3 in Standby
Keep Alive LDO3 in Standby
LDOA[4]
0*
1
Enable LDO3 at Any Output Voltage
Enable LDO3 0nly if Output Voltage is <300mV
LDOA[5]
0*
1
LDO3 Disabled if EN_L3 is Low
LDO3 Enabled
*denotes default power-on value.
LDO4 Operation LTC3676-1
LDO4 on the LTC3676-1 has neither enable nor feedback
pins. There are four LDO4 output voltages selectable by
command register bits LDOB[4:3]. The power-on default
The LTC3676 contains four buck regulators. Two of the
buck regulators are capable of delivering up to 2.5A load
current and the other two can deliver up to 1.5A each. The
regulators have forward and reverse current limiting, softstart, and switch slew rate control for lower radiated EMI.
The LTC3676 buck regulators are capable of 100% duty
cycle, or dropout, regulation. When in dropout the regulator
output voltage is equal to PVIN minus the load current times
RDS(ON) of the converters PMOS device and inductor DCR.
Each buck regulator is enabled using its enable pin or I2C
command register control. Operating modes, start-up option, reference voltage, and switch slew rate are controlled
using the I2C port.
The buck converter I2C command register controls are
shown in Table 4, Table 5, Table 6, and Table 7.
3676ff
16
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
Operation
Operating Modes
The buck regulators can operate in either pulse-skipping,
Burst Mode operation, or forced continuous mode. In
pulse-skipping setting the regulator will skip pulses at
light loads but will operate at constant frequency. In Burst
Mode setting the regulator operates in Burst Mode operation at light loads and in constant frequency PWM mode
at higher load. In forced continuous setting the inductor
current is allowed to be less than zero over the full range
of duty cycles. In forced continuous operation the buck
regulator has the ability to sink output current. Because
the regulator is switching every cycle regardless of output
load, forced continuous mode results in the least output
voltage ripple at light load.
Output Voltage Programming
Each of the step-down converters uses a dynamically slewing DAC for its reference. The output voltage of the DAC
reference is selectable using a 5-bit I2C command register.
The output voltage is set by using a resistor divider connected from the step-down switching regulator output to
its feedback pin as shown in Figure 3. The output voltage
is calculated using the following formula:
⎛ R1⎞
VOUT = ⎜ 1+ ⎟ • (DVBx •12.5+ 412.5) (mV )
⎝ R2 ⎠
voltage of 725mV. Typical values for R1 are in the range
of 40k to 1M. Capacitor CFB cancels the pole created by
the feedback resistors and the input capacitance on the
FB pin and helps to improve load step transient response.
A value of 10pF is recommended.
Inductor Selection
The choice of step-down switching regulator inductor
influences the efficiency and output voltage ripple of the
converter. A larger inductor improves efficiency since the
peak current is closer to the average output current. Larger
inductors generally have higher series resistance that
counters the efficiency advantage of reduced peak current.
Inductor ripple current is a function of switching frequency,
inductance, VIN, and VOUT as shown in this equation:
ΔIL =
⎛ V ⎞
1
• VOUT • ⎜ 1– OUT ⎟
f •L
VIN ⎠
⎝
A good starting design point is to use an inductor that
gives ripple equal to 30% output current. Select an inductor with a DC current rating at least 1.5 times larger than
the maximum load current to ensure the inductor does
not saturate.
Input and Output Capacitor Selection
DVBx is the decimal value of the 5-bit binary number in
the I2C command registers. The default DAC input code is
11001 (25 in decimal) which corresponds to a reference
PVIN
Low ESR ceramic capacitors should be used at both the
output and input supply of the switching regulators. Only
X5R or X7R ceramic capacitors should be used since they
have better temperature and voltage stability than other
ceramic types.
Operating Frequency
EN
MODE
2
PWM
CONTROL
SW
COUT
CFB
FB
R1
R2
5
DAC
DEFAULT
725mV
3676 F03
Figure 3. Step-Down Switching Regulator Application Circuit
The switching frequency of each of the LTC3676 switching
regulators may be set using the I2C command registers.
The default switching frequency is 2.25MHz and the selectable frequency is 1.125MHz. Operation at lower frequency
improves efficiency by reducing internal gate charge and
switching losses at the expense of a larger inductor.
The lowest duty cycle of the step-down converter is determined by minimum on-time. Minimum on-time is the
shortest time duration that the converter can turn its top
PMOS on and off again. The time is the sum of gate charge
3676ff
For more information www.linear.com/LTC3676
17
LTC3676/LTC3676-1
Operation
time plus internal delays of the peak current sense and
PWM control. If the converters duty cycle will be 20% or
less at 2.25MHz it is recommended to use the 1.125MHz
setting to avoid minimum duty cycle. If the duty cycle falls
below the minimum on-time of the converter, the output
voltage ripple will increase as the converter skips cycles.
Table 4. Buck1 Control Command Register
COMMAND
REGISTER[BIT]
VALUE SETTING
BUCK1[0]
0*
1
Switch Slew Rate Normal
Switch Slew Rate Fast
BUCK1[1]
The default setting for the LTC3676-1 Buck1 switching
frequency is 1.125MHz to ensure minimum on time effects are avoided at DDR termination reference voltages.
0*
1
Do Not Keep Enabled in Device Standby
Keep Enabled in Device Standby
BUCK1[2]
(LTC3676)
0*
1
Switching Frequency 2.25MHz
Switching Frequency 1.125MHz
BUCK1[2]
(LTC3676-1)
0*
1
Switching Frequency 1.125MHz
Switching Frequency 2.25MHz
Phase Selection
BUCK1[3]
0*
1
Clock Phase 1
Clock Phase 2
To reduce the cycle by cycle peak current drawn by the
switching regulators, the clock phase at which each of the
LTC3676 buck’s PMOS switch turns on can be set using
I2C command register settings.
BUCK1[4]
0*
1
Enable at Any Output Voltage
Enable Only if Output Voltage Is <300mV
BUCK1[6:5]
00*
01
10
Pulse-Skipping Mode
Burst Mode Operation
Forced Continuous Mode
BUCK1[7]
0*
1
Buck1 Disabled if EN_B1 Pin Is Low
Buck1 Enabled
φ1
φ2
φ1
*denotes default power on-value.
2.25MHz
φ1
1.125MHz
Table 5. Buck2 Control Command Register
φ2
3676 F04
COMMAND
REGISTER[BIT]
VALUE SETTING
BUCK2[0]
0*
1
Switch Slew Rate Normal
Switch Slew Rate Fast
Switch Slew Rate Control
BUCK2[1]
0*
1
Do Not Keep Enabled in Device Standby
Keep Enabled in Device Standby
To help reduce EMI the switch rise time of each buck regulator is slew limited by default. A faster setting is selectable
using the I2C buck command registers. The faster setting
will improve efficiency if limited edge rate is not required.
BUCK2[2]
0*
1
Switching Frequency 2.25MHz
Switching Frequency 1.125MHz
BUCK2[3]
0*
1
Clock Phase 1
Clock Phase 2
BUCK2[4]
Soft-Start
0*
1
Enable at Any Output Voltage
Enable Only if Output Voltage Is <300mV
BUCK2[6:5]
00*
01
10
Pulse-Skipping Mode
Burst Mode Operation
Forced Continuous Mode
BUCK2[7]
0*
1
Buck2 Disabled if EN_B2 Pin Is Low
Buck2 Enabled
Figure 4. Phase Settings Full- and Half-Speed Buck Clock
To reduce inrush current at start-up each buck regulator
soft starts when enabled. When enabled the internal reference voltage is ramped from ground to the level of the
slewing DAC output at a rate of 0.8V/ms. During soft-start
the converter is forced to pulse-skipping mode regardless
of command register mode settings.
*denotes default power-on value.
3676ff
18
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
Operation
Dynamic Voltage Scaling
Table 6. Buck3 Control Command Register
COMMAND
REGISTER[BIT]
VALUE SETTING
BUCK3[0]
0*
1
Switch Slew Rate Normal
Switch Slew Rate Fast
BUCK3[1]
0*
1
Do Not Keep Enabled in Device Standby
Keep Enabled in Device Standby
BUCK3[2]
0*
1
Switching Frequency 2.25MHz
Switching Frequency 1.125MHz
BUCK3[3]
0*
1
Clock Phase 1
Clock Phase 2
BUCK3[4]
0*
1
Enable at Any Output Voltage
Enable Only if Output Voltage Is <300mV
BUCK3[6:5]
00*
01
10
Pulse-Skipping Mode
Burst Mode Operation
Forced Continuous Mode
BUCK3[7]
0*
1
Buck3 Disabled if EN_B3 Pin Is Low
Buck3 Enabled
*denotes default power-on value.
Table 7. Buck4 Control Command Register
COMMAND
REGISTER[BIT]
VALUE SETTING
BUCK4[0]
0*
1
Switch Slew Rate Normal
Switch Slew Rate Fast
BUCK4[1]
0*
1
Do Not Keep Enabled in Device Standby
Keep Enabled in Device Standby
BUCK4[2]
0*
1
Switching Frequency 2.25MHz
Switching Frequency 1.125MHz
BUCK4[3]
0*
1
Clock Phase 1
Clock Phase 2
BUCK4[4]
0*
1
Enable at Any Output Voltage
Enable Only if Output Voltage Is <300mV
BUCK4[6:5]
00*
01
10
Pulse-Skipping Mode
Burst Mode Operation
Forced Continuous Mode
BUCK4[7]
0*
1
Buck4 Disabled if EN_B4 Pin Is Low
Buck4 Enabled
Table 8 shows the command registers used to control
dynamic voltage scaling (DVS) of the step-down switching
regulators input reference DAC. The command register
bits DVB1A[4:0] and DVB1B[4:0] store two 5-bit inputs
to the DAC reference for Buck1. The bit stored in command register DVB1A[5] selects either the 5 bits stored
in DVB1A[4:0] or DVB1B[4:0] DAC as input to the DAC
reference. Buck2, Buck3, and Buck4 operate the same
way using their assigned “A” and “B” command registers
shown in Table 8. When the DAC detects a change in its
input code it automatically slews to the new value at a rate
of 3.5mV/µs. A DVS can be initiated using the I2C select
bit or using the VSTB pin.
The LTC3676 VSTB pin HIGH selects the 5 bits stored in
all four DVBx “B” registers. This facilitates a simultaneous
DAC slew between the values in the “A” registers and the
values in the “B” registers. The VSTB pin is logically ORed
with the I2C command register bit. If the I2C select bit is
already set high, the “B” registers are already selected and
VSTB will have no effect. If no change in output is desired
using the VSTB pin, set the value in the “A” register equal
to the value in the “B”.
Command register bits DVB1B[5], DVB2B[5], DVB3B[5],
and DVB4B[5] control whether the PGOOD status pin is
pulled low while the DAC output is slewing. The default
command register setting is to pull PGOOD pin low during DAC slew. During the DVS, PGOOD will be held low
for just the duration of the DVS and the PGSTAT register
is not affected.
*denotes default power-on value.
VOUT
200mV/DIV
SLEWING DAC REFERENCE OPERATION
Each LTC3676 step-down switching regulators error amplifier reference voltage is supplied by a 5-bit DAC with
an output voltage range of 412.5mV to 800mV in 12.5mV
steps. One of two 5-bit codes stored in I2C command
registers is selected for input to the DAC. When a change
in code is detected by the DAC control circuits, the output
of the DAC is slewed at 3.5mV/µs to the new value.
PGOOD
5V/DIV
VSTB
5V/DIV
100µs/DIV
3676 F05
Figure 5. Dynamic Voltage Scaling
3676ff
For more information www.linear.com/LTC3676
19
LTC3676/LTC3676-1
Operation
Table 8. Buck1, Buck2, Buck3, and Buck4 Slewing DAC Control
Command Registers
COMMAND
REGISTER[BIT]
VALUE
SETTING
DVB1A[4:0]
bbbbb
Buck1 Reference DAC Input A
DVB1A[5]
DVB1B[4:0]
DVB1B[5]
DVB2A[4:0]
DVB2A[5]
DVB2B[4:0]
DVB2B[5]
DVB3A[4:0]
DVB3A[5]
DVB3B[4:0]
DVB3B[5]
DVB4A[4:0]
DVB4A[5]
DVB4B[4:0]
DVB4B[5]
0*
1
bbbbb
0*
1
bbbbb
0*
1
bbbbb
0*
1
bbbbb
0*
1
bbbbb
0*
1
bbbbb
0*
1
bbbbb
0*
1
VIN HIGH
ENABLE
INHIBITED AND
WAKE LOW
POR/HRST
Select DVB1A[4:0]
Select DVB1B[4:0]
Buck1 Reference DAC Input B
ON 400ms
OR PWR_ON
ENABLE
ALLOWED AND
WAKE HIGH
Pull PGOOD Low Slewing Buck1
Do Not Pull PGOOD Slewing Buck1
5 SEC
PWR_ON
TIMER
Buck2 Reference DAC Input A
Select DVB2A[4:0]
Select DVB2B[4:0]
Buck2 Reference DAC Input B
Pull PGOOD Low Slewing Buck2
Do Not Pull PGOOD Slewing Buck2
Buck3 Reference DAC Input A
Select DVB3A[4:0]
Select DVB3B[4:0]
STANDBY
ON 400ms
OR PWR_ON
PWR_ON
OR FAULT
Buck3 Reference DAC Input B
Pull PGOOD Low Slewing Buck3
Do Not Pull PGOOD Slewing Buck3
Buck4 Reference DAC Input A
1 SEC OFF
TIMER
STANDBY
Select DVB4A[4:0]
Select DVB4B[4:0]
Buck4 Reference DAC Input B
Pull PGOOD Low Slewing Buck4
Do Not Pull PGOOD Slewing Buck4
*denotes default power-on value.
PUSHBUTTON OPERATION
Operating Mode State Diagram
Figure 6 shows the state diagram of the LTC3676 enable
and sequence controller. First application of power to
VIN pin brings the controller to the power-on reset/hard
reset (POR/HRST) state. In this state the I2C command
registers have been set to their default values, only LDO1
is operating, and the device is waiting for pushbutton or
PWR_ON inputs. Regulator enable pins and command
register enable bits are ignored in POR/HRST state. In the
POR/HRST state VIN draws typically 12µA.
ON
ON 10 SEC
OR I2C HRST
ON 10 SEC
OR I2C HRST
ON 10 SEC
OR I2C HRST
1 SEC OFF
TIMER
HRST
3676 F06
Figure 6. LTC3676 Operating Mode State Diagram
Power Up Using Pushbutton
When the ON pin is held low for 400ms the WAKE pin is
pulled high, enable pins are recognized, and the five second
PWR_ON timer is started. If in the ON state and PWR_ON
is low or a fault is detected, then WAKE is brought low and
after a 1 second power-down time, the STANDBY state
is entered. In STANDBY, the enable bits in the command
registers are cleared and enable pins are ignored. Table 9
shows the control of command registers, enables, and
WAKE at each state.
The 5 second power-on state is intended for the system to
detect that power rails are correct and either drive PWR_ON
pin high or set command register bit CNTRL[7] high to
keep the rails active. If there were a system level problem
3676ff
20
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
Operation
status register bit, the controller can detect a pushbutton
request. If a power-down into standby state is desired
then the controller should drive PWR_ON low and set
command register bit CNTRL[7] low.
ON (PB)
400ms
WAKE
<5 SEC
PWR_ON
(PIN OR I2C)
Button Status Indication
µC/µP CONTROL
3676 F07
Figure 7. Power Up Using Pushbutton
keeping the processor from driving PWR_ON, then the
LTC3676 will pull WAKE low, shut off all regulators, and
enter the STANDBY state. The STANDBY state is also a
low power, 12µA (typical) state.
Table 9. Register, Enable, WAKE Control During Operating
Mode State Control
STATE
REGISTERS ENABLES
WAKE
POR/HRST DEFAULT
R/W
Inhibited
LOW
5 SEC PWR_ON TIMER
R/W
Allowed
HIGH
ON
R/W
Allowed
HIGH
1 SEC OFF TIMER HRST
Set to POR
Defaults
Sequence Down
LOW
1 SEC OFF TIMER
STANDBY
I2C Enable
and SW
Mode Bits
Cleared
Sequence Down
STANDBY
R/W
Inhibited
Power Up and Down with PWR_ON
The PWR_ON pin is an alternative way to power up the
LTC3676 instead of using the ON pin. When PWR_ON is
driven high or command register CNTRL[7] is set high,
WAKE is pulled HIGH and the LTC3676 passes through
the 5 second PWR_ON timer to the ON state. Figure 9
shows PWR_ON and WAKE timing. WAKE stays high for
a minimum of 5 seconds.
5 SEC
PWR_ON
(PIN OR I2C)
LOW
µC/µP CONTROL
3ms
3ms
WAKE
LOW
3676 F09
Figure 9. Power Up and Down with PWR_ON
Power Down Using Pushbutton
When in the ON state, the system controller is responsible
for deciding what action to take when a pushbutton event
occurs. By monitoring the IRQ status pin and IRQSTAT[0]
POWER ON SEQUENCING
Enable Pin Operation
The LTC3676 enable pins facilitate pin-strapping output
rails to enable pins to up-sequence the LTC3676 regulators
in any order. Figure 10 shows an example of pin-strapped
sequence connections. The enable pins normally have a
0.8V (typical) input voltage threshold.
<10 SEC
ON (PB)
50ms
IRQ
IRQSTAT[0]
WAKE
3ms
PWR_ON
(PIN OR I2C)
When a pushbutton pulls ON low for 50ms in the ON state,
IRQ is pulled low and the PB status bit in the IRQSTAT[0]
status register is set. IRQ and the IRQSTAT status bit are
active while ON is low or for a minimum of 50ms.
µC/µP CONTROL
3676 F08
Figure 8. Power-Down Using Pushbutton
If any enable is driven high, the remaining enable input
thresholds switches to an accurate 400mV threshold. To
ensure separation of the sequenced rails, there is a builtin 450µs delay from the enable pin threshold crossing to
the internal enable of the regulator. Figure 11 shows the
start-up timing of the example shown in Figure 10.
3676ff
For more information www.linear.com/LTC3676
21
LTC3676/LTC3676-1
Operation
bits, or the operating state of the LTC3676. A hard reset
or fault shutdown resets the keep alive bits.
PWR_ON
LTC3676
WAKE
EN_B1
SW1
EN_B2
SW2
EN_B3
SW3
EN_B4
SW4
EN_L2
LDO2
EN_L3
LDO3
EN_L4
LDO4
ON
PWR_ON
VIN
VB1 = 1.2V
VB2 = 1.8V
VB3 = 2.5V
VB4 = 1.2V
VL2 = 1.2V
VL3 = 1.8V
VL4 = 2.8V
3676 F10
Figure 10. Pin-Strapped Power-On Sequence Application
POWER OFF SEQUENCING
Sequence down command registers SQD1 and SQD2
are used to set the time, relative to WAKE falling, that a
regulator is disabled either by lowering PWR_ON, or a
fault induced shutdown. Table 10 shows register settings
for SQD1 and SQD2.
Table 10.Sequence Down Control Command Register Settings
COMMAND
REGISTER[BIT]
WAKE
VB1
VB2
1.2V
450µs
0.4V
00*
01
10
11
Disable Buck1 at Falling WAKE
Disable Buck1 at Falling WAKE + 100ms
Disable Buck1 at Falling WAKE + 200ms
Disable Buck1 at Falling WAKE + 300ms
SQD1[3:2]
00*
01
10
11
Disable Buck2 at Falling WAKE
Disable Buck2 at Falling WAKE + 100ms
Disable Buck2 at Falling WAKE + 200ms
Disable Buck2 at Falling WAKE + 300ms
SQD1[5:4]
00*
01
10
11
Disable Buck3 at Falling WAKE
Disable Buck3 at Falling WAKE + 100ms
Disable Buck3 at Falling WAKE + 200ms
Disable Buck3 at Falling WAKE + 300ms
SQD1[7:6]
00*
01
10
11
Disable Buck4 at Falling WAKE
Disable Buck4 at Falling WAKE + 100ms
Disable Buck4 at Falling WAKE + 200ms
Disable Buck4 at Falling WAKE + 300ms
SQD2[1:0]
00*
01
10
11
Disable LDO2 at Falling WAKE
Disable LDO2 at Falling WAKE + 100ms
Disable LDO2 at Falling WAKE + 200ms
Disable LDO2 at Falling WAKE + 300ms
SQD2[3:2]
00*
01
10
11
Disable LDO3 at Falling WAKE
Disable LDO3 at Falling WAKE + 100ms
Disable LDO3 at Falling WAKE + 200ms
Disable LDO3 at Falling WAKE + 300ms
SQD2[5:4]
00*
01
10
11
Disable LDO4 at Falling WAKE
Disable LDO4 at Falling WAKE + 100ms
Disable LDO4 at Falling WAKE + 200ms
Disable LDO3 at Falling WAKE + 300ms
1.8V
2.5V
1.2V
VB3
VB4
1.2V
450µs
1.8V
VL2
2.8V
VL3
VL4
3676 F11
Figure 11. Pin-Strapped Power-On Sequence
Software Control Mode
Once a power-up sequence is completed, each regulator
may be enabled and disabled individually by the system
as needed for power management requirements by using
the command register bit CNTRL[5]. When CNTRL[5] is
set high the regulators ignore the state of their enable pins
and respond only to I2C command register bit settings.
The software control mode bit is reset in the one second
standby and hard reset timer states so a pin strapped
sequence begins at the next LTC3676 power on.
Keep Alive Operation
Each regulator has a dedicated command register keep
alive bit that, when set, forces a regulator to be enabled
regardless of the enable pins, command register enable
SETTING
SQD1[1:0]
450µs
0.4V
VALUE
*denotes default power-on value.
Figure 12 shows an example of a shutdown sequence. In
this example, the bits in command registers SQD1 and
SQD2 are set so that LDO2, LDO3, and LDO4 shut off at
the same time as WAKE. Buck2 and Buck4 shut off 100ms
after WAKE. Buck3 shuts off 200ms after wake and Buck1
shuts off 300ms after WAKE.
3676ff
22
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LTC3676/LTC3676-1
Operation
Over Temperature
WAKE
VB1
VB2
1.2V
To prevent thermal damage the LTC3676 incorporates an
overtemperature (OT) circuit. When the die temperature
reaches 155°C the OT circuits create a FAULT condition
that forces the LTC3676 into standby. When the OT circuit detects the temperature falls below 140°C the FAULT
condition is cleared. The LTC3676 also has an OT warning
circuit that indicates the die temperature is approaching
the OT fault threshold. The OT warning threshold is user
programmable as shown in Table 12.
300ms
200ms
1.8V
100ms
VB3
VB4
VL2
VL3
VL4
2.5V
1.2V
1.2V
1.8V
Table 12. Overtemperature Warning Threshold Command
Register Settings
2.8V
COMMAND
REGISTER[BIT]
CNTRL[1:0]
3676 F12
Figure 12. Power-Down Sequence
The LTC3676 has fault detection circuits that monitor
for VIN undervoltage, die overtemperature, and regulator
output undervoltage. Status of the fault detect circuits is
indicated by the IRQ and PGOOD pins and the IRQSTAT
and PGSTAT status registers.
VIN Undervoltage
The undervoltage (UV) circuit monitors the input supply
voltage, VIN, and when the voltage falls below 2.45V creates a FAULT condition that forces the LTC3676 into the
standby state. The LTC3676 also provides a (UV) warning
that is triggered at user programmable VIN voltages as
shown in Table 11.
Table 11. Undervoltage Warning Threshold Command Register
Settings
VALUE
000*
001
010
011
100
101
110
111
*denotes default power-on value.
00*
01
10
11
OT WARNING THRESHOLD
10°C Below OT Fault
20°C Below OT Fault
30°C Below OT Fault
40°C Below OT Fault
*denotes default power-on value.
PGOOD Status Pin
FAULT DETECTION AND REPORTING
COMMAND
REGISTER[BIT]
CNTRL[4:2]
VALUE
FALLING VIN THRESHOLD
2.7V
2.8V
2.9V
3.0V
3.1V
3.2V
3.3V
3.4V
The PGOOD open-drain status pin is pulled low when all
regulators are disabled. PGOOD is released when all enabled
regulator outputs are above 93% of programmed value.
When any enabled regulator output falls below 92% of its
programmed value for longer than 50µs the PGOOD pin is
pulled low. The 50µs transient filter on PGOOD prevents
PGOOD glitches due to transients. If the error condition
persists for longer than 20ms, the IRQ pin is pulled low and
status register IRQSTAT bit 2 is set to indicate a persistent
PGOOD fault. The PGOOD pin is held low for the duration
of the low output condition plus 1ms. Figure 13 shows the
timing of PGOOD during enable and fault events.
ENx
VOUTx
450µs
1ms
50µs
1ms
50µs
20ms
PGOOD
IRQ
3676 F13
Figure 13. Output Low Voltage PGOOD and IRQ Timing
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23
LTC3676/LTC3676-1
Operation
PGSTAT and MSKPG Registers
Table 14. Power Good Status Masking Command Register
The power good status of each regulator is accessible
through the LTC3676 I2C interface by reading the contents
of the PGSTAT status register. Table 13 shows the PGSTAT
register contents. The data in the PGSTATL register is held
for the length of the low voltage condition plus 1ms. The
data in the PGSTATRT register is held only for the duration
of the low voltage condition.
Table 13. Power Good Status Register
STATUS
REGISTER[BIT]
VALUE
REGULATOR OUTPUT LOW STATUS
COMMAND
REGISTER[BIT]
VALUE
MSKPG [0]
0
1*
Mask Buck1 PGOOD Status
Pass Buck1 PGOOD Status
MSKPG [1]
0
1*
Mask Buck2 PGOOD Status
Pass Buck2 PGOOD Status
MSKPG [2]
0
1*
Mask Buck3 PGOOD Status
Pass Buck3 PGOOD Status
MSKPG [3]
0
1*
Mask Buck4 PGOOD Status
Pass Buck4 PGOOD Status
MSKPG [5]
0
1*
Mask LDO2 PGOOD Status
Pass LDO2 PGOOD Status
PGSTAT[0]
0
1
Buck1 Output Low
Buck1 Output OK
MSKPG [6]
0
1*
Mask LDO3 PGOOD Status
Pass LDO3 PGOOD Status
PGSTAT[1]
0
1
Buck2 Output Low
Buck2 Output OK
MSKPG [7]
0
1*
Mask LDO4 PGOOD Status
Pass LDO4 PGOOD Status
PGSTAT[2]
0
1
Buck3 Output Low
Buck3 Output OK
*denotes default power-on value.
PGSTAT[3]
0
1
Buck4 Output Low
Buck4 Output OK
IRQ Status Pin
PGSTAT[4]
0
1
LDO1 Output Low
LDO1 Output OK
PGSTAT[5]
0
1
LDO2 Output Low
LDO2 Output OK
PGSTAT[6]
0
1
LDO3 Output Low
LDO3 Output OK
PGSTAT[7]
0
1
LDO4 Output Low
LDO4 Output OK
The IRQ pin is pulled and latched low when undervoltage,
overtemperature or persistent PGOOD events occur. The
IRQ pin is cleared by addressing the CLIRQ command
register or by holding ON low for 50ms.
Table 15. Interrupt Request Status Register
STATUS
REGISTER[BIT]
Each regulator has a corresponding bit in the MSKPG status
register as shown in Table 14. When set, a bit blocks the
PGOOD pin from being pulled low in the event of a low
output voltage fault from its matching regulator. Setting
a bit in the MSKPG command register does not mask the
status in the PGSTAT status register.
VALUE
IRQSTAT REGISTER BIT MEANING
IRQSTAT [0]
0
1
Pushbutton Status Active (Real Time)
IRQSTAT [1]
0
1
Hard Reset Occurred
IRQSTAT [2]
0
1
PGOOD Timeout Occurred
IRQSTAT [3]
0
1
Undervoltage Warning
IRQSTAT [4]
0
1
Undervoltage Standby Occurred
IRQSTAT [5]
0
1
Overtemperature Warning
IRQSTAT [6]
0
1
Overtemperature Standby Occurred
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For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
Operation
IRQSTAT and MSKIRQ Registers
The bits in the MSKIRQ command register are set to mask
warning, fault, and pushbutton status reporting to the IRQ
pin. When set to mask, the IRQ pin is not pulled low as a
result of a fault or warning. Even though the IRQ pin is not
pulled low the masked bit is set in the IRQSTAT register.
When undervoltage, overtemperature faults, and hard
reset signals are masked, the IRQ pin is not pulled low
but LTC3676 state controller is pushed into the STANDBY
or POR/HRST state. Accessing the CLIRQ status register
clears the latched bits in the IRQSTAT status register and
releases the IRQ pin.
Table 16. Interrupt Request Mask Command Register
COMMAND
REGISTER[BIT]
VALUE
MSKIRQ [0]
0*
1
Pass Pushbutton Status
Mask Pushbutton Status
MSKIRQ [2]
0*
1
Pass PGOOD Timeout
Mask PGOOD Timeout
MSKIRQ [3]
0*
1
Pass Undervoltage Warning
Mask Undervoltage Warning
MSKIRQ [4]
0*
1
Pass Undervoltage Shutdown
Mask Undervoltage Shutdown
MSKIRQ [5]
0*
1
Pass Overtemperature Warning
Mask Overtemperature Warning
MSKIRQ [6]
0*
1
Pass Overtemperature Shutdown
Mask Overtemperature Shutdown
*denotes default power-on value.
IRQ and IRQSTAT are not cleared by hard reset or fault
shutdown. If VIN remains applied while the LTC3676 is in
STANDBY or POR/HRST then IRQSTAT may be read on
the subsequent power up to determine if a fault or hard
reset occurred.
RSTO Status Pin
The LTC3676 RSTO status pin is pulled low when alwayson LDO1 is 8% below its programmed value or when the
LTC3676 is in the one second HRST timer state.
Hard Reset
A hard reset can be initiated by holding the ON pin low
or writing to the HRST command register. Bit six of the
CNTRL command register determines how long ON must
remain low to initiate the hard reset. A hard reset sets
all I2C command register bits to their default power-on
state. Table 17 shows the command register control of
hard reset function.
Table 17. Hard Reset Time Control Command Register
COMMAND
REGISTER[BIT]
CNTRL[6]
VALUE
SETTING
0*
1
10 seconds
5 seconds
*denotes default power-on value.
A hard reset command will push the LTC3676 state controller through the 1 second HRST timer state and into
the POR/HRST state.
Fault Shutdown
An undervoltage or overtemperature fault will push the
LTC3676 state controller through the 1 second standby
timer state and into standby state. If a down sequence
is selected in the command registers, it will be executed
during the 1 second power down interval.
LTC3676-1 Operation
The LTC3676-1 option supports DDR memory operation
by generating a DDR termination reference and supply
rail equal to one-half the voltage applied to VDDQIN Pin 8.
An internal resistive divider creates a reference voltage of
one-half the voltage on VDDQIN. This reference is used
by the VTT reference buffer to output one-half of VDDQIN
on VTTR Pin 9. The VTTR voltage is used as the reference
for 1.5A switching regulator 1 which is used as the DDR
termination supply. The LTC3676-1 EN_B1 pin and command register bit Buck1[7] enable both VTTR output and
switching regulator 1. The LTC3676-1 switching regulator 1 settings are fixed to one-half frequency and forced
continuous operation.
Figure 1 shows typical application connections for the
LTC3676-1 DDR termination reference and termination
supply.
LDO4 has I2C command register selectable output voltages of 1.2V (default), 2.5V, 2.8V and 3V and is enabled
only using the I2C command register. Table 18 shows
the LDO4 command register controls for the LTC3676-1.
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25
LTC3676/LTC3676-1
Operation
Table 18. LDO4 Control Command Register Setting (LTC3676-1)
COMMAND
REGISTER[BIT] VALUE SETTING
LDOB[0]
0*
1
Do Not Keep Alive LDO4 in Standby
Keep Alive LDO4 in Standby
LDOB[1]
0*
1
Enable LDO4 at Any Output Voltage
Enable LDO4 Only if Output Voltage Is <300mV
LDOB[2]
0*
1
LDO4 Disabled
LDO4 Enable
LDOB[4:3]
00*
01
10
11
1.2V
2.5V
2.8V
3.0V
*denotes default power-on value.
A bus master signals the beginning of communications
by transmitting a START condition. A START condition is
generated by transitioning SDA from HIGH to LOW while
SCL is HIGH. The master may transmit either the slave
write or the slave read address. Once data is written to the
LTC3676, the master may transmit a STOP condition which
commands the LTC3676 to act upon its new command
set. A STOP condition is sent by the master by transitioning SDA from LOW to HIGH while SCL is HIGH. The bus
is then free for communication with another I2C device.
I2C Byte Format
I2C OPERATION
The LTC3676 communicates with a bus master using
the standard I2C 2-wire interface. The timing diagram in
Figure 14 shows the relationship of the signals on the
bus. The two bus lines, SDA and SCL must be high when
the bus is not in use. External pull-up resistors or current
sources, such as the LTC1694 SMBus accelerator, are
required on SDA and SCL. The LTC3676 is both a slave
receiver and slave transmitter. The I2C control signals,
SDA and SCL are scaled internally to the DVDD supply.
DVDD must be connected to the same power supply as
the bus pull-up resistors.
The I2C port has an undervoltage lockout on the DVDD
pin. When DVDD is below approximately 1V, the I2C
serial port is cleared and the command registers are set
to default POR values.
The complete I2C command register table is shown in
Table 20.
I2C Bus Speed
I2C
I2C START and STOP Conditions
port operates at speeds up to 400kHz. It has
The
built in timing delays to ensure correct operation when
addressed from an I2C compliant master device. It also
contains input filters designed to suppress glitches should
the bus become corrupted.
Each byte sent to or received from the LTC3676 must
be 8 bits long followed by an extra clock cycle for the
acknowledge bit. The data should be sent to the LTC3676
most significant bit (MSB) first.
I2C Acknowledge
The acknowledge signal is used for handshaking between
the master and the slave. When the LTC3676 is written
to, it acknowledges its write address and subsequent data
bytes. When it is read from, the LTC3676 acknowledges
its read address only. The bus master should acknowledge
data returned from the LTC3676.
An acknowledge generated by the LTC3676 lets the master
know that the latest byte of information was received.
The master generates the acknowledge related clock and
releases the SDA line during the acknowledge clock cycle.
The LTC3676 pulls down the SDA line during the write
acknowledge clock pulse so that it is a stable LOW during
the HIGH period of this clock pulse.
At the end of a byte of data transferred from the LTC3676
during a READ operation, the LTC3676 releases the SDA
line to allow the master to acknowledge receipt of the
data. Failure of the master to acknowledge data from the
LTC3676 has no effect on the operation of the I2C port.
3676ff
26
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
Operation
SDA
tSU, DAT
tLOW
tSU, STA
tHD, DAT
tHD, STA
tBUF
tSU, STO
3676 F14
SCL
tHIGH
tHD, STA
START
CONDITION
tr
tSP
REPEATED START
CONDITION
tf
STOP
CONDITION
START
CONDITION
Figure 14. LTC3676 I2C Serial Port Timing
I2C Slave Address
The LTC3676 responds to factory programmed read and
write addresses. The least significant bit of the address byte
is 0 when writing data and 1 when reading data. Table 19
shows read and write addresses for the LTC3676 options.
Table 19. LTC3676 and LTC3676-1 I2C Read and Write
Addresses
LTC PART NUMBER
LTC3676
R/W
ADDRESS
W
0111 1000, 0x78
LTC3676
R
0111 1001, 0x79
LTC3676-1
W
0111 1010, 0x7A
LTC3676-1
R
0111 1011, 0x7B
I2C Write Operation
The LTC3676 has twenty-two command registers for
control input. They are accessed by the I2C port via a
sub-addressed writing system.
A single write cycle of the LTC3676 consists of exactly
three bytes except when a clear interrupt or hard reset
command is written. The first byte is always the LTC3676
write address. The second byte represents the LTC3676
sub-address. The sub-address is a pointer which directs
the subsequent data byte within the LTC3676. The third
byte consists of the data to be written to the location
pointed to by the sub-address.
The LTC3676 will keep interim writes to the registers when
a repeat START condition occurs. A repeat start may be
used to set up other devices on the I2C bus prior to sending a STOP condition. The LTC3676 will act on the data
written prior to the repeat start when a STOP condition
is detected.
I2C Read Operation
Figure 16 shows the LTC3676 command register read
sequence. The bus master reads a byte of data from a
LTC3676 command or status register by first writing the
LTC3676 write address followed by the sub-address to
be read from. The LTC3676 acknowledges each of the
two bytes. Next, the bus master initiates a new START
condition and sends the LTC3676 read address. Following the acknowledge of the read address by the LTC3676,
the LTC3676 pushes data onto the I2C bus for the 8 clock
cycles. The bus master then acknowledges the data on
its ninth clock.
The last read sub-address that is written to the LTC3676
is stored. This allows repeated polling of a command or
status register without the need to re-write its sub-address.
Additionally, the last register written may be immediately read by issuing a START condition followed by read
address and clocking out the data.
As shown in Figure 15, the LTC3676 supports multiple
sub-addressed write operations. Data pairs sent following
the chip write address are interpreted as sub-address and
data. Any number of sub-address and data pairs may be
sent. The data in the command registers is not acted on
by the LTC3676 until a STOP signal is issued.
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27
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4
2
1
1
0
SCL
6
0
0
5
1
1
1
START
3
1
1
ADDRESS
0
2
1
SCL
1
1
SDA
1
0
1
SDA
START
0
3
1
1
7
0
0
9
ACK
4
1
1
5
1
1
ADDRESS
8
0
W
6
0
0
1
S7
7
0
0
2
S6
8
0
W
3
9
ACK
4
S4
6
S2
7
S1
8
S0
9
ACK
1
D7
2
D6
3
D5
4
5
D3
DATA
D4
6
D2
7
D1
8
D0
9
ACK
1
S7
2
S6
3
4
S4
1
S7
2
S6
4
5
S3
6
S2
7
S1
8
S0
9
ACK
START
1
0
0
2
1
1
3
1
1
4
1
1
5
1
1
ADDRESS
6
0
0
7
0
0
Figure 16. LTC3676 I2C Serial Port Read Pattern
3
S4
SUB ADDRESS
S5
8
1
R
9
ACK
5
S3
1
R7
6
S2
SUB ADDRESS
S5
Figure 15. LTC3676 I2C Serial Port Multiple Write Pattern
5
S3
SUB ADDRESS
S5
2
R6
7
S1
3
R5
8
S0
1
4
5
R3
DATA
R4
9
ACK
D7
6
R2
2
D6
7
R1
3
D5
8
R0
4
9
ACK
5
D3
DATA
D4
7
D1
3676 F16
STOP
6
D2
8
D0
9
ACK
3676 F15
STOP
LTC3676/LTC3676-1
Operation
3676ff
LTC3676/LTC3676-1
Operation
Table 20. LTC3676 Command Registers
REG
NAME
B[4]
B[3]
0x01
BUCK1 Enable:
Mode:
0 = Disabled if 00 = Pulse-Skipping
EN_B1 Low 01 = Burst
1 = Enabled 10 = Forced Continuous
Start-Up:
0 = Enable at
Any Output
Voltage
Switch DV/DT 0000 0000
Control:
0 = Slow
1 = Fast
1 = Enable
Only if Output
<300mV
Phase Select: Clock Rate:
Keep Alive
0 = Clock
0 = 2.25MHz Buck1:
Phase 1
1 = 1.125MHz 0 = Do Not
Keep Alive
1 = Clock
Phase 2
Mode:
BUCK2 Enable:
0 = Disabled if 00 = Pulse-Skipping
EN_B2 Low 01 = Burst
1 = Enabled 10 = Forced Continuous
Start-Up:
0 = Enable at
Any Output
Voltage
Switch DV/DT 0000 0000
Control:
0 = Slow
1 = Fast
1 = Enable
Only if Output
<300mV
Phase Select: Clock Rate:
Keep Alive
0 = Clock
0 = 2.25MHz Buck2:
Phase 1
1 = 1.125MHz 0 = Do Not
Keep Alive
1 = Clock
Phase 2
Mode:
BUCK3 Enable:
0 = Disabled if 00 = Pulse-Skipping
EN_B3 Low 01 = Burst
1 = Enabled 10 = Forced Continuous
Start-Up:
0 = Enable at
Any Output
Voltage
Switch DV/DT 0000 0000
Control:
0 = Slow
1 = Fast
1 = Enable
Only if Output
<300mV
Phase Select: Clock Rate:
Keep Alive
0 = Clock
0 = 2.25MHz Buck3:
Phase 1
1 = 1.125MHz 0 = Do Not
Keep Alive
1 = Clock
Phase 2
Mode:
BUCK4 Enable:
0 = Disabled if 00 = Pulse-Skipping
EN_B4 Low 01 = Burst
1 = Enabled 10 = Forced Continuous
Start-Up:
0 = Enable at
Any Output
Voltage
Phase Select: Clock Rate:
Keep Alive
0 = Clock
0 = 2.25MHz Buck4:
Phase 1
1 = 1.125MHz 0 = Do Not
Keep Alive
1 = Clock
Switch DV/DT 0000 0000
Control:
0 = Slow
1 = Fast
Keep Alive
LDO3:
0 = Do Not
Keep Alive
Enable LDO2: Start-Up LDO2:
0 = Disabled if 0 = Enable at
Any Output
EN_L2 Low
Voltage
1 = Enabled
Keep Alive
LDO2:
0 = Do Not
Keep Alive
Enable LDO4: Start-Up LDO4:
0 = Disabled if 0 = Enable at
Any Output
EN_L4 Low
Voltage
1 = Enabled
Keep Alive
LDO4:
0 = Do Not
Keep Alive
0x02
0x03
0x04
0x05
LDOA
B[7]
Reserved
B[6]
Reserved
B[5]
1 = Enable
Only if Output
<300mV
Enable LDO3: Start-Up LDO3:
0 = Disabled if 0 = Enable at
Any Output
EN_L3 Low
1 = Enabled Voltage
1 = Enable
Only if Output
<300mV
0x06
0x07
LDOB
SQD1
Reserved
Reserved
Sequence Down Buck4:
00 = With WAKE
01 = WAKE + 100ms
10 = WAKE + 200ms
11 = WAKE + 300ms
Reserved
1 = Keep Alive
in Shutdown.
B[1]
B[0]
DEFAULT
1= Keep Alive in
Shutdown.
1 = Keep Alive
in Shutdown
1 = Keep Alive
in Shutdown
Phase 2
LTC3676-1 LDO4 Output
Voltage:
00 = 1.2V
01 = 2.5V
10 = 2.8V
11 = 3.0V
Sequence Down Buck3:
00 = With WAKE
01 = WAKE + 100ms
10 = WAKE + 200ms
11 = WAKE + 300ms
B[2]
1 = Keep Alive
in Shutdown
1 = Enable
Only if Output
<300mV
Sequence Down Buck2:
00 = With WAKE
01 = WAKE + 100ms
10 = WAKE + 200ms
11 = WAKE + 300ms
1 = Enable
Only if Output
<300mV
XX00 0000
1 = Keep Alive
in Shutdown
XX00 0000
1 = Keep Alive
in Shutdown
Sequence Down Buck1:
00 = With WAKE
01 = WAKE + 100ms
10 = WAKE + 200ms
11 = WAKE + 300ms
0000 0000
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29
LTC3676/LTC3676-1
Operation
REG
NAME
B[7]
B[6]
B[5]
0x08
SQD2
Reserved
Reserved
Sequence Down LD04:
00 = With WAKE
01 = WAKE + 100ms
10 = WAKE + 200ms
11 = WAKE + 300ms
0x09
CNTRL PWR_ON:
0 = Not
PWR_ON
Pushbutton
Hard Reset
Timer:
1 = PWR_ON 0 = 10 sec
1 = 5 sec
"ORed" with
PWR_ON PIN
0x0A DVB1A Reserved
Reserved
B[4]
B[3]
B[2]
Sequence Down LD03:
00 = With WAKE
01 = WAKE + 100ms
10 = WAKE + 200ms
11 = WAKE + 300ms
Software
Control Mode:
0 = Pin or
Register
Control
UV Warning Threshold:
000 = 2.7V
001 = 2.8V
010 = 2.9V
011 = 3.0V
1 = Inhibit Pin 100 = 3.1V
101 = 3.2V
Control
110 = 3.3V
111 = 3.4V
Buck1
Reference
Select:
0=
DVB1A[4-0]
B[1]
B[0]
DEFAULT
Sequence Down LD02:
00 = With WAKE
01 = WAKE + 100ms
10 = WAKE + 200ms
11 = WAKE + 300ms
XX00 0000
Over temperature Warning
Levels:
00 = 10°C Below
Overtemperature
0000 0000
01 = 20°C Below
Overtemperature
10 = 30°C Below
Overtemperature
11 = 40°C Below
Overtemperature
Buck1 Feedback Reference Input (VA):
00000 = 412.5mV
11001 = 725mV
11111 = 800mV
12.5mV Step Size
XX01 1001
Buck1 Feedback Reference Input (VB):
00000 = 412.5mV
11001 = 725mV
11111 = 800mV
12.5mV Step Size
XX01 1001
Buck2 Feedback Reference Input (VA):
00000 = 412.5mV
11001 = 725mV
11111 = 800mV
12.5mV Step Size
XX01 1001
Buck2 Feedback Reference Input (VB):
00000 = 412.5mV
11001 = 725mV
11111 = 800mV
12.5mV Step Size
XX01 1001
Buck3 Feedback Reference Input (VA):
00000 = 412.5mV
11001 = 725mV
11111 = 800mV
12.5mV Step Size
XX01 1001
1=
DVB1B[4-0]
0x0B DVB1B Reserved
Reserved
PGOOD Mask:
0 = PGOOD
Low When
Slewing
1 = PGOOD
Not Forced
Low When
Slewing
0x0C DVB2A Reserved
Reserved
Buck2
Reference
Select:
0=
DVB2A[4-0]
1=
DVB2B[4-0]
0x0D DVB2B Reserved
Reserved
PGOOD Mask:
0 = PGOOD
Low When
Slewing
1 = PGOOD
Not Forced
Low When
Slewing
0x0E
DVB3A Reserved
Reserved
Buck3
Reference
Select:
0=
DVB3A[4-0]
1=
DVB3B[4-0]
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LTC3676/LTC3676-1
Operation
REG
NAME
0x0F
DVB3B Reserved
B[7]
B[6]
B[5]
B[4]
Reserved
PGOOD Mask:
0 = PGOOD
Low When
Slewing
Buck3 Feedback Reference Input (VB):
00000 = 412.5mV
11001 = 725mV
11111 = 800mV
12.5mV Step Size
XX01 1001
Buck4 Feedback Reference Input (VA):
00000 = 412.5mV
11001 = 725mV
11111 = 800mV
12.5mV Step Size
XX01 1001
Buck4 Feedback Reference Input (VB):
00000 = 412.5mV
11001 = 725mV
11111 = 800mV
12.5mV Step Size
XX01 1001
1 = PGOOD
Not Forced
Low When
Slewing
0x10
DVB4A Reserved
Reserved
Buck4
Reference.
Select:
0=
DVB4A[4-0]
B[3]
B[2]
B[1]
B[0]
DEFAULT
1=
DVB4B[4-0]
0x11
DVB4B Reserved
Reserved
PGOOD Mask:
0 = PGOOD
Low When
Slewing
1 = PGOOD
Not Forced
Low When
Slewing
0x12
MSKIRQ Reserved
0x13
Mask
Mask PGOOD Reserved
Undervoltage Timeout
Warning
Mask Push
X000 00X0
Button Status
MSKPG Allow LDO 4 Allow LDO 3 Allow LDO 2 Reserved
PGOOD Fault PGOOD Fault PGOOD Fault
Allow Buck 4 Allow Buck 3
PGOOD Fault PGOOD Fault
Allow Buck 2
PGOOD Fault
Allow Buck 1 1111 1111
PGOOD Fault
0x14
USER
User Bit 3
User Bit 1
User Bit 0
0x1E
HRST
Hard Reset Command. No Data.
0x1F
CLIRQ
Clear IRQ Command. No Data
User Bit 7
Mask Overtemperature
Shutdown
User Bit 6
Mask Overtemperature
Warning
User Bit 5
Mask
Undervoltage
Shutdown
User Bit 4
User Bit 2
0000 0000
Table 22. LTC3676 Status Registers
B[6]
B[5]
B[4]
B[3]
B[2]
B[1]
B[0]
0x15
REG
IRQSTAT Reserved
NAME
B[7]
Overtemperature
Shutdown
Overtemperature
Warning
Undervoltage
Shutdown
Undervoltage
Warning
PGOOD
Timeout
Hard Reset
Pushbutton
Status (Real
Time)
0x16
PGSTATL LDO4 PGOOD
Hold 1ms
LDO3 PGOOD
Hold 1ms
LDO2 PGOOD
Hold 1ms
LDO1 PGOOD
Hold 1ms
Buck4 PGOOD Buck3 PGOOD Buck2 PGOOD Buck1 PGOOD
Hold 1ms
Hold 1ms
Hold 1ms
Hold 1ms
0x17 PGSTATRT LDO4 PGOOD
LDO3 PGOOD
LDO2 PGOOD
LDO1 PGOOD
Buck4 PGOOD Buck3 PGOOD Buck2 PGOOD Buck1 PGOOD
Reserved Bits
The bits marked as reserved in command registers cannot be written to and will return inconsistent data when
read. These bits must be considered invalid and masked
by software when reading.
3676ff
For more information www.linear.com/LTC3676
31
LTC3676/LTC3676-1
Applications Information
THERMAL CONSIDERATIONS AND BOARD LAYOUT
Printed Circuit Board Power Dissipation
In order to ensure optimal performance and the ability
to deliver maximum output power to any regulator, it is
critical that the exposed ground pad on the backside of the
LTC3676 package be soldered to a ground plane on the
board. The exposed pad is the only GND connection for the
LTC3676. Correctly soldered to a 2500mm2 ground plane
on a double-sided 1oz copper board, the LTC3676 has a
thermal resistance(JA) of approximately 34°C/W. Failure
to make good thermal contact between the exposed pad
on the backside of the package and an adequately sized
ground plane will result in thermal resistances far greater
than 34°C/W. To ensure the junction temperature of the
LTC3676 die does not exceed the maximum rated limit
and to prevent overtemperature faults, the power output
of the LTC3676 must be managed by the application. The
total power dissipation in the LTC3676 is approximated by
summing the power dissipation in each of the switching
regulators and the LDO regulators. The power dissipation
in a switching regulator is estimated by:
100-Eff%
PD(SWx ) = VOUTx •IOUTx •
( W)
100
Where VOUTx is the programmed output voltage IOUTx is
the load current and Eff is the % efficiency that can be
measured or looked up from the efficiency curves for the
programmed output voltage.
The power dissipated by an LDO regulator is estimated by:
PD(LDOx) = VIN(LDOx) − VLDOx • ILDOx (W)
where VLDOx is the programmed output voltage, VIN(LDOx)
is the LDO supply voltage, and ILDOx is the output load
current. If one of the switching regulator outputs is used
as an LDO supply voltage, remember to include the LDO
supply current in the switching regulator load current for
calculating power loss.
An example using the equations above with the parameters in Table 23 shows an application that is at a junction
temperature of 120°C at an ambient temperature of 55°C.
LDO2, LDO3, and LDO4 are powered by step-down Buck2
and Buck4. The total load on Buck2 and Buck4 is the sum
of the application load and the LDO load. This example
is with the LDO regulators at one third rated current and
the switching regulators at three quarters rated current.
Table 23. LTC3676 Power Loss Example
VIN
VOUT
APPLICATION
LOAD (A)
TOTAL
LOAD (A)
EFF
(%)
PD (mW)
LDO1
3.8
1.2
0.01
0.010
–
26.00
LDO2
1.8
1.2
0.1
0.100
–
60.00
LDO3
3.3
1.8
0.1
0.100
–
150.00
LDO4
3.3
2.5
0.1
0.100
–
80.00
Buck1
3.8
1.2
1.875
1.875
80
450.00
Buck2
3.8
1.8
1.775
1.875
85
506.25
Buck3
3.8
1.25
1.125
1.125
80
281.25
Buck4
3.8
3.3
0.925
1.125
90
371.25
Total Power =
1925
Internal Junction Temperature at 55°C Ambient
120°C
Printed Circuit Board Layout
When laying out the printed circuit board, the following
checklist should be followed to ensure proper operation
of the LTC3676:
1. Connect the exposed pad of the package (Pin 41) directly to a large ground plane to minimize thermal and
electrical impedance.
2. The switching regulator input supply traces to their
decoupling capacitors should be as short as possible.
Connect the GND side of the capacitors directly to the
ground plane of the board. The decoupling capacitors
provide the AC current to the internal power MOSFETs
and their drivers. It is important to minimize inductance
from the capacitors to the LTC3676 pins.
3. Minimize the switching power traces connecting SW1,
SW2, SW3, and SW4 to the inductors to reduce radiated EMI and parasitic coupling. Keep sensitive nodes
such as the feedback pins away from or shielded from
the large voltage swings on the switching nodes.
4. Minimize the length of the connection between the
step-down switching regulator inductors and the output
capacitors. Connect the GND side of the output capacitors directly to the thermal ground plane of the board.
3676ff
32
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
Typical Applications
LTC3676 PMIC Configured to Support Freescale i.MX6 Processor
22µF
FREESCALE
i.MX6
22µF
22µF
VIN
3.3V TO 5V
27
22µF
36
35
16
15
PVIN1
PVIN2
PVIN3
PVIN4
VIN
SW3
1µF
FB_B3
VRTC
3V
25mA
28
1µF
634k
WAKE
37
34
ARM
18
17
VDDHIGH
30
I/O
10
I/O
9
68k
68k
68k
RSTO
32
IRQ
39
PGOOD
12
4.7k
SCA
VSTB
PWR_ON
38
4.7k
14
13
19
21
29
(1.37V)
10pF
178k
SW1
FB_L1
FB_B1
40
24
1.5µH
(1.37V)
10pF
VSNVS_IN
VDDARM_IN
47µF
200k
LTC3676
33
22
1µH
LDO1
200k
68k
SCL
26
20
ARM
0.9V TO 1.5V
AT 2.5A
178k
SOC
0.9V TO 1.5V
AT 1.5A
VDDSOC_IN
47µF
200k
WAKE
EN_B1
SW2
EN_B2
EN_B3
FB_B2
EN_B4
31
25
1.5µH
(3.3V)
10pF
715k
47µF
200k
EN_L2
EN_L3
SW4
EN_L4
RSTO
FB_B4
IRQ
VIN_L2
PGOOD
DVDD
LDO2
SCL
FB_L2
SDA
VIN_L3
VSTB
PWR_ON
LDO3
ON
VIN_L4
LDO4
FB_L4
GND
41
11
23
VDDHIGH_IN
DDR
1.5V AT 2.5A
1µH
VDD_DDR_IO
10pF
2
215k
47µF
200k
3
619k
1
5
SEQUENCE:
WAKE
1µF
1µF
LDO3
1.8V
300mA
1µF
LDO4
3V
300mA
4
1µF
6
634k
DDR
≤ 4 CHIPS
NO TERM
1µF
200k
7
GND
VDDHIGH
2.97V
300mA
1µF
8
I/O
3.3V
1.5A
ARM
SOC
I/O
VDDHIGH
LDO3
DDR
200k
3676 TA02
3676ff
For more information www.linear.com/LTC3676
33
LTC3676/LTC3676-1
Typical Applications
LTC3676-1 PMIC Configured to Support Freescale i.MX6 Processor with DDR VTT and VTTR
22µF
22µF
VIN
3V TO 5.5V
27
22µF
36
35
16
15
PVIN1
PVIN2
PVIN3
PVIN4
VIN
SW3
1µF
FB_B3
LDO1
3V
25mA
28
1µF
634k
26
WAKE
37
34
18
17
VDDHIGH
30
ARM
10
I/O
68k
68k
68k
RSTO
32
IRQ
39
PGOOD
12
4.7k
SCL
SCA
VSTB
PWR_ON
SW2
FB_L1
FB_B2
4.7k
14
13
19
21
29
ARM
0.9V TO 1.5V
AT 2.5A
(1.37V)
10pF
31
178k
25
1.5µH
10pF
VDDARM_IN
47µF
SOC
0.9V TO 1.5V
AT 1.5A
(1.37V)
178k
VDDSOC_IN
47µF
200k
WAKE
EN_B1
SW4
EN_B2
EN_B3
FB_B4
EN_B4
11
23
DDR
1.5V AT 2.5A
1µH
10pF
215k
VDD_DDR_IO
47µF
200k
EN_L2
EN_L3
SW1
38
22
1µH
200k
LTC3676-1
33
20
VDDHIGH
LDO1
200k
68k
FREESCALE
i.MX6
VSNVS_IN
VDDHIGH_IN
22µF
RSTO
FB_B1
40
24
VTT
0.75V AT 1.5A
1µH
10pF
215k
47µF
GND
IRQ
PGOOD
DVDD
VDDQIN
VTTR
VIN_L2
SCL
SDA
VSTB
LDO2
PWR_ON
ON
FB_L2
VIN_L3
LDO3
VIN_L4
GND
LDO4
DDR
8 CHIPS
WITH TERM
8
9
2
0.047µF
1µF
3
619k
1
5
1µF
VDDHIGH
2.97V
300mA
SEQUENCE:
WAKE
200k
1µF
1µF
LDO3
1.8V
300mA
1µF
LDO4
3V
300mA
4
7
1µF
6
41
ARM
SOC
VDDHIGH
LDO3
DDR
VTT
3676 TA03
3676ff
34
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
Package Description
Please refer to http://www.linear.com/product/LTC3676#packaging for the most recent package drawings.
UJ Package
40-Lead Plastic QFN (6mm × 6mm)
(Reference LTC DWG # 05-08-1728 Rev Ø)
0.70 ±0.05
6.50 ±0.05
5.10 ±0.05
4.42 ±0.05
4.50 ±0.05
(4 SIDES)
4.42 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
6.00 ±0.10
(4 SIDES)
0.75 ±0.05
R = 0.10
TYP
R = 0.115
TYP
39 40
0.40 ±0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
4.50 REF
(4-SIDES)
4.42 ±0.10
2
PIN 1 NOTCH
R = 0.45 OR
0.35 × 45°
CHAMFER
4.42 ±0.10
(UJ40) QFN REV Ø 0406
0.200 REF
0.25 ±0.05
0.00 – 0.05
NOTE:
1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
3676ff
For more information www.linear.com/LTC3676
35
LTC3676/LTC3676-1
Package Description
Please refer to http://www.linear.com/product/LTC3676#packaging for the most recent package drawings.
LXE Package
48-Lead Plastic Exposed Pad LQFP (7mm × 7mm)
(Reference LTC DWG #05-08-1927 Rev A)
Exposed Pad Variation AA
7.15 – 7.25
5.50 REF
1
48
37
36
0.50 BSC
C0.30
5.50 REF
7.15 – 7.25
0.20 – 0.30
4.15 ±0.05
4.15 ±0.05
12
13
PACKAGE OUTLINE
24
25
1.30 MIN
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
9.00 BSC
7.00 BSC
48
4.15 ±0.10
37
SEE NOTE: 3
1
48
37
36
36
1
C0.30
9.00 BSC
7.00 BSC
4.15 ±0.10
A
A
12
25
25
12
C0.30 – 0.50
13
24
13
BOTTOM OF PACKAGE—EXPOSED PAD (SHADED AREA)
24
11° – 13°
1.35 – 1.45
R0.08 – 0.20
1.60
MAX
GAUGE PLANE
0.25
0° – 7°
LXE48 (AA) LQFP 0416 REV A
11° – 13°
0.09 – 0.20
1.00 REF
0.50
BSC
0.17 – 0.27
0.05 – 0.15
SIDE VIEW
0.45 – 0.75
SECTION A – A
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.25mm (10 MILS) BETWEEN THE LEADS AND ON ANY
SIDE OF EXPOSED PAD, MAX 0.50mm (20 MILS) AT CORNER OF EXPOSED
PAD, IF PRESENT
3. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER
4. DRAWING IS NOT TO SCALE
3676ff
36
For more information www.linear.com/LTC3676
LTC3676/LTC3676-1
Revision History
REV
DATE
DESCRIPTION
A
12/13
Modified the Typical Application Circuit
PAGE NUMBER
1
Modified Start-Up Sequence Path
1
Changed Conditions on VIN Burst Mode Quiescent Current
3
Removed Transient Response comment from VOUT Programming
16
Modified Command Registers table
Modified PD equation in PCB Power Dissipation section Table 23
Changed R and C values in Typical Applications
B
09/14
Changed C values in application circuits
Corrected pin names in Conditions in Electrical Characteristics table
Corrected units on Current Limit graph
28-30
31
32, 33, 36
1, 32, 33, 36
3 to 5
8
Corrected units on LDO1 Dropout and LDO1 Load Response graphs
9
Corrected Operation Introduction section
14
Modified LTC3676-1 Operation section
24
Changed table reference in I2C Operation section
25
Changed table number for Command Registers section
28
Clarified Command Registers table
30
C
09/14
Added LQFP Package (LXE)
1 to 3, 11,
12, 36
D
05/15
Modified Thermal Resistance of LXE Package
2
Modified Pin Description of EN_B1
12
Modified Figure 1 GND
15
Clarified LTC3676-1 Operation Section
25
Amended Package Drawing
36
E
04/17
Added thermal resistances ThetaJC
2
F
09/17
Modified Buck RDS(ON) curves
9
Modified LTC3676-1 Operation section
25
Added Reserved Bits section to Table 22
31
3676ff
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its circuits
as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC3676
37
LTC3676/LTC3676-1
Typical Application
Sequenced Power for High Performance Processor and DDR Memory Using LTC3375 Parallelable Buck Converters
22µF
22µF
22µF
VIN
5V
VTT
0.75V
1.5A
POWER GOOD
FROM VIN SUPPLY
47µF
1.5µH
215k
PVIN3
PVIN4
PWR_ON
SW1
LDO1
FB_B1
FB_L1
SW2
47µF
294k
634k
LTC3676-1
VIN_L2
LDO2
FB_B3
47µF
200k
LDO3
1µH
SW4
634k
1µF
SW2
2.8V
300mA
0.01µF
100µF
SW3
174k
SW4
FB1
LTC3375
200k
FB3
PB
FB4
CT
SW5
2.2µH
715k
200k
EN2
IO18ANALOG
1.8V
1µF 300mA
I033
3.3V
22µF 1A
FB5
SYNC
IO33
ARM
1.35V
4A
2.2µH
FB2
EN3
SW6
EN4
SW7
EN7
SW8
EN8
FB6
FB7
2.2µH
215k
DRAM
1.5V
3A
68µF
200k
FB8
ON
EN1
WDO
EN5
IRQ
IRQ
EN6
PGOOD
RST
WAKE
KILL
RSTO
LDO4
1µF
DVDD
EN_B1
EN_B2
EN_B3
EN_B4
EN_L3
EN_L2
VTTR
750mV
±10mA
VIN8
VCC
RT
FB_B4
VIN_L4
VDDQIN
VTTR
VIN6 VIN7
SW1
10pF
200k IO18
1.2V
300mA
1µF
10pF
VIN_L3
VIN4 VIN5
10µF
10µF
VSHNT
FBVCC
IO33
200k
SW3
VIN2 VIN3
10µF
10µF
1.02M
FB_L2
1µH
VDDHIGH
3V
2.5A
1Ω
VIN1
10µF
10µF
576k
1µF
576k
174k
3.3V
10µF
10pF
200k
47µF
VRTC
3V
1µF 25mA
200k
FB_B2
SOC
1.35V
2.5A
21.5k
PVIN1
VIN
10pF
1.5µH
IO18
1.8V
1.5A
PVIN2
10µF
10µF
22µF
ON
4.7k
4.7k
SDA
SDA
SCL
SCL
VSTB
WDI
TEMP
GND
MICROPROCESSOR
CONTROL
GND
3676 TA04
Related Parts
PART
NUMBER
DESCRIPTION
COMMENTS
LTC3101
1.8V to USB, Multioutput DC/
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Power Controller
Seamless Transition Between Multiple Input Power Sources, VIN Range: 1.8V to 5.5V, Buck-Boost
Converter VOUT Range: 1.5V to 5.25V, 3.3VOUT at 800mA for VIN ≥ 3V, Dual 350mA Buck Regulators,
VOUT: 0.6V to VIN, 38μA Quiescent Current in Burst Mode Operation, 24-Lead 4mm  4mm  0.75mm
QFN Package
LTC3375
8-Channel Programmable,
Parallelable 1A Buck DC/DCs
8-Channel Independent Step-Down DC/DCs. Master Slave Configurable for Up to 4A per Output Channel
with a Single Inductor, Die Temperature Monitor Output, 48-Lead 7mm  7mm QFN Package
LTC3589/
8-Output Regulator with
LTC3589-1/ Sequencing and I2C
LTC3589-2
LTC3586/
LTC3586-1
Triple I2C Adjustable High Efficiency Step-Down DC/DC Converters: 1.6A, 1A, 1A. High Efficiency 1.2A
Buck-Boost DC/DC Converter. Triple 250mA LDO Regulators. Pushbutton ON/OFF Control with System
Reset. Flexible Pin-Strap Sequencing Operation. I2C and Independent Enable Control Pins, DVS and
Slew Rate Control, 40-Lead 6mm  6mm  0.75mm QFN Package
Switching USB Power Manager
Complete Multifunction PMIC: Switching Power Manager, 1A Buck-Boost + 2 Bucks + Boost + LDO,
PMIC with Li-Ion/Polymer Charger 4mm  6mm QFN-38 Package, LTC3586-1 Version Has 4.1V VFLOAT.
3676ff
38
LT 0917 REV F • PRINTED IN USA
For more information www.linear.com/LTC3676
www.linear.com/LTC3676
© LINEAR TECHNOLOGY CORPORATION 2013