IDT CPS-1616 16-port, 16-lane, 80gbps, gen2 rapidio switch Datasheet

16-Port, 16-Lane, 80Gbps,
Gen2 RapidIO Switch
CPS-1616
Datasheet
Description
Features
The CPS-1616 (80HCPS1616) is a RapidIO Specification (Rev. 2.1)
compliant Central Packet Switch whose functionality is central to
routing packets for distribution among DSPs, processors, FPGAs,
other switches, or any other RapidIO-based devices. It can also be
used in RapidIO backplane switching. The CPS-1616 supports Serial
RapidIO (S-RIO) packet switching (unicast, multicast, and an optional
broadcast) from any of its 16input ports to any of its 16 output ports.
• RapidIO ports
— 16 bidirectional S-RIO lanes
— Port widths of 1x, 2x, and 4x allow up to 20 Gbps per port
— Port speeds selectable: 6.25, 5, 3.125, 2.5, or 1.25 Gbaud
— Support Level I defined short or long haul reach, and Level II
defined short-, medium-, or long-run reach for each PHY speed
— Error Management Extensions support
— Software-assisted error recovery, supporting hot swap
• I2C Interfaces
— Provides I2C port for maintenance and error reporting
— Master or Slave operation
— Master allows power-on configuration from external ROM
— Master mode configuration with external image compressing and
checksum
• Switch
— 80 Gbps peak throughput
— Non-blocking data flow architecture
— Configurable for Cut-Through or Store-and-Forward data flow
— Very low latency for all packet lengths and load conditions
— Internal queuing buffer and retransmit buffer
— Standard transmitter- or receiver-controlled flow control
— Global routing or Local Port routing capability
— Supports up to 40 simultaneous multicast masks, with broadcast
— Performance monitoring counters for performance and
diagnostics analysis. Per input port and output port counters
• SerDes
— Transmitter pre-emphasis and drive strength + receiver
equalization provides best possible signal integrity
— Embedded PRBS generation and detection with programmable
polynomials support Bit Error Rate testing
• Additional Information
— Packet Trace/Mirror. Each input port can copy all incoming
packets matching user-defined criteria to a “trace” output port.
— Packet Filter. Each input port can filter (drop) all incoming packets
matching user-defined criteria.
— Device configurable through any of S-RIO ports, I2C, or JTAG
— Full JTAG Boundary Scan Support (IEEE1149.1 and 1149.6)
— Lidded/Lidless 784-FCBGA Package: 21 21 mm, 1.0 mm ball
pitch
Block Diagram
Quadrant 0
Quadrant 3
Lanes 0-3
Lanes 12-15
Ports 0-3
Ports 12-15
CPS-1616
RapidIO Gen2
Switch Fabric
Event Management and Maintenance
Registers
I2C Controller
JTAG Controller
Ports 4-7
Lanes 4-7
Ports 8-11
Lanes 8-11
Quadrant 1
Quadrant 2
Typical Applications
•
•
•
•
High-performance computing
Wireless
Defense and aerospace
Video and imaging
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CPS-1616 Datasheet
Table of Contents
1.
About This Document.................................................................................................................... 4
Introduction............................................................................................................................................................................................................ 4
Additional Resources............................................................................................................................................................................................. 4
Document Conventions and Definitions................................................................................................................................................................. 4
Revision History..................................................................................................................................................................................................... 4
2.
Device Description ........................................................................................................................ 6
Specification Compliancy....................................................................................................................................................................................... 7
3.
Functional Overview ..................................................................................................................... 7
4.
Interface Overview........................................................................................................................ 8
S-RIO Ports ........................................................................................................................................................................................................... 8
I2C Bus .................................................................................................................................................................................................................. 8
JTAG TAP Port...................................................................................................................................................................................................... 8
Interrupt (IRQ_N) ................................................................................................................................................................................................... 8
Reset (RST_N) ...................................................................................................................................................................................................... 8
Clock (REF_CLK_P/N) .......................................................................................................................................................................................... 8
Rext (REXT_N/P) .................................................................................................................................................................................................. 9
Speed Select (SPD[2:0])........................................................................................................................................................................................ 9
Quadrant Config (QCFG[7:0])................................................................................................................................................................................ 9
Port Disable (PD[15:0]_N) ..................................................................................................................................................................................... 9
Frequency Select (FSEL[1:0]) ............................................................................................................................................................................... 9
Multicast (MCAST)................................................................................................................................................................................................. 9
5.
Configuration Pins ....................................................................................................................... 10
Speed Select Pins SPD[2:0]................................................................................................................................................................................ 10
Quadrant Configuration Pins QCFG[7:0]............................................................................................................................................................. 10
6.
Absolute Maximum Ratings ........................................................................................................ 14
7.
Recommended Operating Conditions ......................................................................................... 15
8.
AC Test Conditions...................................................................................................................... 16
9.
Power Consumption .................................................................................................................... 18
10. I2C Bus ......................................................................................................................................... 18
I2C Master Mode and Slave Mode....................................................................................................................................................................... 19
I2C Device Address ............................................................................................................................................................................................. 19
Signaling.............................................................................................................................................................................................................. 19
Read/Write Figures.............................................................................................................................................................................................. 20
I2C DC Electrical Specifications........................................................................................................................................................................... 22
I2C AC Electrical Specifications........................................................................................................................................................................... 24
I2C Timing Waveforms......................................................................................................................................................................................... 25
11. Interrupt (IRQ_N) Electrical Specifications ................................................................................ 26
12. Configuration (Static) Pin Specification ..................................................................................... 27
13. S-RIO Ports .................................................................................................................................. 28
Overview.............................................................................................................................................................................................................. 28
Definition of Amplitude and Swing....................................................................................................................................................................... 29
1.25, 2.5, and 3.125 Gbaud LP-Serial Links........................................................................................................................................................ 30
Level I Electrical Specification ............................................................................................................................................................................. 30
5 and 6.25 Gbaud LP-Serial Links....................................................................................................................................................................... 37
Level II Electrical Specifications .......................................................................................................................................................................... 37
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14. Reference Clock .......................................................................................................................... 47
Reference Clock Electrical Specifications ........................................................................................................................................................... 47
15. Reset (RST_N) Specification ....................................................................................................... 49
16. JTAG Interface ............................................................................................................................ 50
Description........................................................................................................................................................................................................... 50
IEEE 1149.1 (JTAG) and IEEE 1149.6 (AC Extest) Compliance ........................................................................................................................ 50
System Logic TAP Controller Overview............................................................................................................................................................... 50
Signal Definitions ................................................................................................................................................................................................. 51
Test Data Register (DR) ...................................................................................................................................................................................... 52
Boundary Scan Registers.................................................................................................................................................................................... 52
Instruction Register (IR)....................................................................................................................................................................................... 55
EXTEST............................................................................................................................................................................................................... 56
Configuration Register Access ............................................................................................................................................................................ 58
JTAG DC Electrical Specifications....................................................................................................................................................................... 59
JTAG AC Electrical Specifications....................................................................................................................................................................... 60
JTAG Timing Waveforms..................................................................................................................................................................................... 61
17. Pinout and Pin Listing ................................................................................................................. 62
Pinout — Top View .............................................................................................................................................................................................. 62
Pin Listing ............................................................................................................................................................................................................ 63
18. Package Specifications .............................................................................................................. 69
Package Physical Specifications ......................................................................................................................................................................... 69
Package Outline Drawings .................................................................................................................................................................................. 69
Thermal Characteristics....................................................................................................................................................................................... 74
19. Ordering Information ................................................................................................................... 76
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1.
About This Document
Introduction
The CPS-1616 Datasheet provides hardware information about the CPS-1616, such as electrical and packaging characteristics. It is intended for
hardware engineers who are designing system interconnect applications with the device.
Additional Resources
The CPC-1616 User Manual describes the functionality and configuration capabilities of the device. In addition, there are many other resources
available that support the CPS-1616. For more information, please contact IDT for support.
Document Conventions and Definitions
This document uses the following conventions and definitions:
•
To indicate signal states:
– Differential signals use the suffix “_P” to indicate the positive half of a differential pair.
– Differential signals use the suffix “_N” to indicate the negative half of a differential pair.
– Non-differential signals use the suffix “_N” to indicate an active-low state.
•
To define buses, the most significant bit (MSB) is on the left and least significant bit (LSB) is on the right. No leading zeros are included.
•
To represent numerical values, either decimal, binary, or hexadecimal formats are used. The binary format is as follows: 0bDDD, where “D”
represents either 0 or 1; the hexadecimal format is as follows: 0xDD, where “D” represents the hexadecimal digit(s); otherwise, it is decimal.
•
Unless otherwise denoted, a byte refers to an 8-bit quantity; a word refers to a 32-bit quantity, and a double word refers to an 8-byte (64-bit)
quantity. This is in accordance with RapidIO convention.
•
A bit is set when its value is 0b1. A bit is cleared when its value is 0b0.
•
A read-only register, bit, or field is one that can be read but not modified.
This symbol indicates important configuration information or suggestions.
This symbol indicates procedures or operating levels that may result in misuse or damage to
the device.
Revision History
June 26, 2017
• Updated the Package Outline Drawings; no technical changes
• Updated the Ordering Information
April 4, 2016
•
Added an R_X2 symbol to Table 20
•
Updated the Package Physical Specifications
•
Added HMG and HLG part numbers to Ordering Information
July 25, 2013
•
Updated Heat Sink Requirement and Analysis
•
Completed several minor improvements
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CPS-1616 Datasheet
July 17, 2013
•
Added HR FCBGA (Lidded) package information to Package Outline Drawings
•
Added HR FCBGA thermal data to Thermal Characteristics
•
Added HR FCBGA package information to Ordering Information
June 12, 2013
•
Updated the note associated with VDD3A (pin T18)
June 8, 2012
•
Changed the maximum 3.3V supply requirement to 3.47V in Table 6 and note 2 below the table
•
Updated the REF_CLK parameter in Table 29 to +/-50 ppm
•
Added two cautionary notes about lane reordering to Pin Listing
December 9, 2011
•
Loosened the Clock Input signal rise/fall minimum time specification
•
Added an additional note to the power sequencing requirements
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2.
Device Description
The CPS-1616 is a S-RIO-compliant performance-optimized switch. This device is ideally suited for intensive processing applications which
require a multiplicity of DSPs, CPUs, and / or FPGAs working together in a cluster. Its very low latency, reliable packet-transfer, and high
throughput make it ideal in embedded applications including communications, imaging, or industrial controls. A switched S-RIO architecture allows
a flat topology with true peer-to-peer communications. It supports four standard RapidIO levels of priority, and can unicast, multicast, or broadcast
packets to destination ports. With link rates to 6.25 Gbaud and transmitter pre-emphasis and receiver equalization, the device can provide up to 20
Gbps per port across 100 cm (40 inches) of FR4 with 2 connectors. This makes the device ideally suited for communicating across backplanes or
cables.
The CPS-1616 receives packets from up to 16 ports. The CPS-1616 offers full support for switching as well as enhanced functions:
1. Switching — All packets are switched in accordance with the RapidIO Specification (Rev. 2.1), with packet destination IDs (destID) determining
how the packet is routed.
Four main switching options exist:
a. Unicast: Packets are sent according to the packet’s destID to a single destination port in compliance with the RapidIO Specification (Rev. 2.1).
b. Multicast: Packets with a destID pointing to a multicast mask will multicast to all destination ports provided by the multicast mask. Multicasting
is performed in compliance with the RapidIO Specification (Rev. 2.1).
c. Maintenance packets: In compliance with the RapidIO Specification (Rev. 2.1), maintenance packets with hop_count > 0 pass through the
switch. Maintenance packets with hop_count = 0 will operate on the switch.
d. Broadcast: Each multicast mask can be configured so all output ports, including the source port, are included among the destination ports for
that multicast operation. This feature is IDT-specific.
The CPS-1616 supports a peak throughput of 80 Gbps which is the line rate for 16 Ports in 1x configuration, (each at 5.0 Gbaud = 6.25 Gbaud
minus the S-RIO defined 8b/10b encoding), and switches dynamically in accordance with the packet headers and priorities.
5. Enhanced functions — Enhanced features are provided for support of system debug. These features which are optional for the user consist of
following functions:
a. Packet Trace: The Packet Trace feature provides at-speed checking of the first 160 bits (header plus a portion of any payload) of every incoming
packet against user-defined comparison register values. The trace feature is available on all S-RIO ports, each acting independently from one
another. If the trace feature is enabled for a port, every incoming packet is checked for a match against up to four comparison registers. If a
match occurs, either of two possible user-defined actions may occur:
i) Not only does the packet route normally through the switch to its appropriate destination port, but this same packet is copied to a “debug port”
or “trace port.” The trace port itself can be any of the standard S-RIO ports. The port used for the trace port is defined by the user through
simple register configuration.
ii) The packet is dropped. If there is no match, the packets route normally through the switch with no action taken. The Packet Trace feature can
be used during system bring-up and prototyping to identify specific packet types of interest to the user. It might be used in security applications,
where packets must be checked for either correct or incorrect tags in either of the header or payload. Identified (match) packets are then routed
to the trace port for receipt by a host processor, which can perform an intervention at the software level.
b. Port Loopback: The CPS-1616 offers internal loopback for each port that can be used for system debug of the high-speed S-RIO ports. By
enabling loopback on a port, packets sent to the port’s receiver are immediately looped back at the physical layer to the transmitter - bypassing
the higher logical or transport layers.
c. Broadcast: The device switching operation supports broadcast traffic (any input port to all output ports).
d. Security functions: The aforementioned packet trace / filter capabilities allow packets matching trace criteria to be blocked at the input port. This
function can, for example, allow untrusted (unknown source or destination) packets to be filtered, malicious or errant maintenance packets to be
filtered, or boot packets to be identified to pass to a slave device.
The CPS-1616 can be programmed through any one or combination of S-RIO, I2C, or JTAG. Note that any S-RIO port can be used for
programming. The CPS-1616 can also configure itself on power-up by reading directly from EPROM over I2C in master mode.
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Specification Compliancy
•
RapidIO Specification (Rev. 2.1), Part 1: Input/Output Logical Specification, 08/2009, RTA
•
RapidIO Specification (Rev. 2.1), Part 2: Message Passing Logical Specification, 08/2009, RTA
•
RapidIO Specification (Rev. 2.1), Part 3: Common Transport Specification, 08/2009, RTA
•
RapidIO Specification (Rev. 2.1), Part 6: LP-Serial Physical Layer Specification, 08/2009, RTA
•
RapidIO Specification (Rev. 2.1), Part 7: System and Device Interoperability Specification, 08/2009, RTA
•
RapidIO Specification (Rev. 2.1), Part 8: Error Management Extensions Specification, 08/2009, RTA
•
RapidIO Specification (Rev. 2.1), Part 9: Flow Control Logic Layer Extensions Specification, 08/2009, RTA
•
RapidIO Specification (Rev. 2.1), Part 11: Multicast Extensions Specification, 08/2009, RTA
•
RapidIO Specification (Rev. 2.1), Annex I: Software/System Bring Up Specification, 08/2009, RTA
•
IEEE Std 1149.1-2001 IEEE Standard Test Access Port and Boundary-Scan Architecture
•
IEEE Std 1149.6-2003 IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks
•
The I2C-BUS Specification (v 2.1), January 2000, Philips
3.
Functional Overview
The CPS-1616 is optimized for line card and backplane switching. Its primary function is to switch data plane and control plane data packets using
S-RIO between a set of devices that reside on the same line card. In addition, it can bridge communications between multiple on-board (or local)
devices and a set of external line cards by providing long run RapidIO backplane interconnects. In this manner, for example, the device can serve
as a switch between a set of RF cards and a set of RapidIO based DSPs in a wireless basestation.
The CPS-1616 supports packet switching from its 16 RapidIO ports. Packets can be unicast, multicast, or broadcast. The encoded data rate for
each of the lanes are configurable to either 1.25, 2.5, 3.125, 5, or 6.25 Gbaud. The device supports lane groupings such that 1x, 2x, and 4x
operation is provided, as defined in the RapidIO Specification (Rev. 2.1).
The CPS-1616 supports the reception of S-RIO maintenance packets (type 8) which are directed to it (that is, a hop count of 0). The device can
properly process and forward received maintenance packets with a hop count > 0 as defined in the RapidIO Specification (Rev. 2.1). With the
exception of maintenance packets, received packets are transmitted unmodified.
The CPS-1616 supports four priority levels plus Critical Request Flow (CRF), as defined in the RapidIO Specification (Rev. 2.1), Part 6. It is
programmable by all of the following: S-RIO ports, I2C, and JTAG Interface.
From a switching perspective the CPS-1616 functions statically. As such, all input to output port mappings are configurable through registers.
Unless register configurations are changed, the input to output mappings remains static regardless of the received data. The switching
functionality does not dynamically “learn” which destIDs are tied to a port endpoint by examining S-RIO header fields and dynamically updating
internal routing tables.
The CPS-1616 supports “Store and Forward” or “Cut-Through” packet forwarding (for more information, see the “Switch Fabric” chapter in the
CPC-1616 User Manual).
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CPS-1616 Datasheet
4.
Interface Overview
Rext
16 Differential S-RIO Lanes
1.25, 2.5, 3.125, 5 or 6.25
Gbps
JTAG Interface
CPS-1616
SPD[2:0]
QCFG[7:0]
PD_N[15:0]
RST_N
REF_CLK
FSEL[1:0]
I2C Interface
400 kHz
MCAST
IRQ_N
Figure 1: CPS-1616 Interfaces
S-RIO Ports
The S-RIO ports are the main communication ports on the chip. These ports are compliant with the RapidIO Specification (Rev. 2.1). For more
information, see the RapidIO Specification (Rev. 2.1).
The device provides up to 16 S-RIO lanes. The encoded data rate for each of the lanes is configurable to either 1.25, 2.5, 3.125, 5, or 6.25 Gbaud
as defined in the RapidIO Specification (Rev. 2.1), Part 6.
I2C Bus
This interface can be used instead of the standard S-RIO or JTAG ports to program the chip and to check the status of registers - including the
error reporting registers. It is fully compliant with the I2C specification, it supports master and slave modes and supports both Fast and
Standard-mode buses [1]. For more information, see I2C Bus.
JTAG TAP Port
This TAP interface is IEEE1149.1 (JTAG) and 1149.6 (AC Extest) compliant [11, 12]. It can be used instead of the standard S-RIO or I2C ports to
program the chip and to check the status of registers - including the error reporting registers. It has 5 pins. For more information, see JTAG
Interface.
Interrupt (IRQ_N)
An interrupt output is provided in support of Error Handling functionality. This output can flag a host processor if error conditions occur within the
device. For more information, see the “Event Management" chapter in the CPC-1616 User Manual.
Reset (RST_N)
A single Reset pin is used for full reset of the CPS-1616, including setting all registers to power-up defaults. For more information, see the "Reset
and Initialization" chapter in the CPC-1616 User Manual.
Clock (REF_CLK_P/N)
The single system clock (REF_CLK_P/N) is a 156.25-MHz differential clock.
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Rext (REXT_N/P)
These pins establish the drive bias on the SerDes output. An external bias resistor is required. The two pins must be connected to one another
with a 9.1k Ohm resistor. This provides robust SerDes stability across process and temperature.
Speed Select (SPD[2:0])
These pins define the S-RIO port speed at RESET for all ports. SPD[2:0] can be configured as follows:
•
000 = 1.25 Gbaud
•
001 = 2.5 Gbaud
•
01X = 5 Gbaud
•
100 = Reserved
•
101 = 3.125 Gbaud
•
11X = 6.25 Gbaud
For more information, see Speed Select Pins SPD[2:0].
Quadrant Config (QCFG[7:0])
These pins define the S-RIO port width (x1, x2, x4) at RESET for all ports. QCFG[1:0] defines port width for Quadrant 0, QCFG[3:2] defines port
width for Quadrant 1, QCFG[5:4] defines port width for Quadrant 2, and QCFG[7:6] defines port width for Quadrant 3. For more information, see
Quadrant Configuration Pins QCFG[7:0].
Port Disable (PD[15:0]_N)
These pins define the active state of the specific port at RESET. PD15_N defines port 15 and PD0_N defines port 0.
Frequency Select (FSEL[1:0])
FSEL1 pin defines the input reference clock, and FSEL0 pin defines the internal clock frequency, full or half rate.
Multicast (MCAST)
The Multicast-Event Control Symbol Trigger (MCAST) pin provides an optional mechanism to trigger the generation of a Multicast-Event Control
Symbol. The multicast-event control symbol allows a user-defined system event to be multicast throughout a system (for example, synchronously
reset a system or its internal timers).
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5.
Configuration Pins
Speed Select Pins SPD[2:0]
There are three port-speed selection pins that select the initial speed of the RapidIO ports (see Table 1). The RESET setting can be overridden by
programming the PLL n Control 1 Register and Lane n Control Register (for more information, see “Lane and Port Speeds” in the CPC-1616 User
Manual).
Table 1: Port Speed Selection Pin Values
Value on the Pins
(SPD2, SPD1, SPD0)
Port Rate (Gbaud)
000
1.25
001
2.5
01X
5.0
100
Reserved
101
3.125
11X
6.25
Quadrant Configuration Pins QCFG[7:0]
There are eight quadrant configuration selection pins, QCFG[7:0], or two pins per quadrant (see Figure 2). These pins configure the device’s
power-up settings for port width and lane to port mapping. After power-up these settings can be changed by updating the Quadrant Configuration
Register (for more information, see “Lane to Port Mapping” in the CPS-1616 User Manual).
Lanes 0-3
Lanes 12-15
Quadrant 0
Ports 0-3
QCFG[1:0]
Quadrant 3
Ports 12-15
QCFG[7:6]
Quadrant 1
Ports 4-7
QCFG[3:2]
Quadrant 2
Ports 8-11
QCFG[5:4]
Lanes 4-7
Lanes 8-11
Figure 2: Quadrant Configuration using QCFG[7:0]
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Figure 3 shows a lane to port mapping example for Quadrant 0 based on QCFG[1:0] set to 01.
0
1
2
Port 0
3
Port 2
Quadrant 0
QCFG[1:0] = 01
Figure 3: Quadrant 0 Configuration Example — QCFG[1:0] = 01
The following table describes the complete lane-to-port mapping options for the CPS-1616 based on the setting of the QCFG[7:0] pins.
Table 2: Lane to Port Mapping
Quadrant/
Quad
0
Mapping
QCFG Pins
QCFG Pin
Setting
PLL
Port Width
Port
Lane(s)
QCFG[1:0]
00
0, 4
4x
0
0–3
-
1, 2, 3
-
2x
0
0–1
2x
2
2–3
-
-
1, 3
-
0, 4
2x
0
0–1
1x
2
2
1x
3
3
-
1
-
1x
0
0
1x
1
1
1x
2
2
1x
3
3
01
10
11
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Table 2: Lane to Port Mapping (Continued)
Quadrant/
Quad
1
QCFG Pins
PLL
Port Width
Port
Lane(s)
QCFG[3:2]
00
1, 5
4x
4
4–7
-
5, 6, 7
-
2x
4
4–5
2x
6
6–7
-
-
5, 7
-
1, 5
2x
4
4–5
1x
6
6
1x
7
7
-
5
-
1x
4
4
1x
5
5
1x
6
6
1x
7
7
4x
8
8–11
-
9, 10, 11
-
2x
8
8–9
2x
10
10–11
-
-
9, 11
-
2, 6
2x
8
8–9
1x
10
10
1x
11
11
-
9
-
1x
8
8
1x
9
9
1x
10
10
1x
11
11
01
10
11
2
Mapping
QCFG Pin
Setting
QCFG[5:4]
00
01
10
11
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1, 5
1, 5
2, 6
2, 6
2, 6
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CPS-1616 Datasheet
Table 2: Lane to Port Mapping (Continued)
Quadrant/
Quad
3
Mapping
QCFG Pins
QCFG Pin
Setting
PLL
Port Width
Port
Lane(s)
QCFG[7:6]
00
3, 7
4x
12
12–15
-
13, 14, 15
-
2x
12
12–13
2x
14
14–15
-
-
13, 15
-
3, 7
2x
12
12–13
1x
14
14
1x
15
15
-
13
-
1x
12
12
1x
13
13
1x
14
14
1x
15
15
01
10
11
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6.
Absolute Maximum Ratings
Table 3: Absolute Maximum Rating1
Rating
Symbol
Parameter
Minimum
Maximum
Unit
VDD3
VDD3 voltage with respect to GND
-0.5
3.6
V
VDD
VDD voltage with respect to GND
-0.5
1.2
V
VDDT
VDDT voltage with respect to GNDS (VDDS = 0V)
-0.5
1.2
V
VDDT voltage with respect to GNDS (VDDS = 1.0V)
-0.5
1.4
V
VDDA and VDDS
VDDA AND VDDS voltage with respect to GNDS
-0.5
1.2
V
TBIAS2
Temperature under bias
-55
125
C
TSTG
Storage temperature
-65
150
C
TJN
Junction temperature
-
125
C
IOUT (for VDD3 = 3.3V)
DC output current
-
30
mA
IOUT (for VDD3 = 2.5V)
DC output current
-
30
mA
Notes:
1. Stresses greater than those listed under Absolute Maximum Ratings can cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods can affect reliability.
2. Ambient Temperature under DC Bias, no AC conditions. Can not exceed maximum Junction temperature.
3. IDT recommends not to exceed ripple voltage of 50 mV max on VDDT/VDDS/VDDA and 50 mV/100 mV (maximum) on VDD/VDD3 respectively.
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7.
Recommended Operating Conditions
Table 4: Recommended Operating Conditions1
Rating
Symbol2
Parameter
Minimum
Maximum
Unit
VDD3-supplied interfaces3 5
Input or I/O terminal voltage with respect to GND
-0.3
VDD3 + 0.3
V
VDD
VDD voltage with respect to GND
0.95
1.05
V
VDDA AND VDDS voltage with respect to GNDS
0.95
1.05
V
VDDT
VDDT voltage with respect to GNDS
1.14
1.26
V
VDD3 and VDD3A
VDD3 voltage (3.3 V) with respect to GND
3.14
3.47
V
VDD3 voltage (2.5 V) with respect to GND
2.4
2.6
V
VDDA and VDDS
4
Notes:
1. The following power-up sequence is necessary in order for the device to function properly: The SerDes voltage (VDDS) needs to power-up first
followed by SerDes voltage (VDDT). VDD, VDDA, and VDD3(a) can be powered up in any order. The device is not sensitive to supply rise and fall times,
and thus these are not specified.
2. VDDT, VDDA, and VDDS share a common ground (GNDS). Core supply and ground are VDD and GND respectively.
3. VDD3 can be operated at either 3.3V or 2.5V simply by providing that supply voltage. For those interfaces operating on this supply, this datasheet
provides input and output specifications at each of these voltages.
4. VDDS and VDDA can be tied to a common power plane. VDD (core, digital supply) should have its own power plane. If the same voltage regulator is
used for VDDS/VDDA and VDD, the VDDS/VDDA plane should be isolated to prevent noise from the VDD plane to couple onto the VDDS/VDDA plane.
5. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. The voltage on any Input or I/O
pin cannot exceed its corresponding supply voltage during power supply ramp up.
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8.
AC Test Conditions
Table 5: AC Test Conditions (VDD3 = 3.3V / 2.5V): JTAG, I2C, RST
Input Pulse Levels
GND to 3.0V / GND to 2.4V
Input Rise / Fall Times
2 ns
Input Timing Reference
Levels
1.5V / 1.25V
Output Reference Levels
1.5V / 1.25V
Output Load
See Figure 4
DATAout
50 Ohm
50 Ohm
1.5V / 1.25V
10pF (TESTER)
Figure 4: AC Output Test Load (JTAG)
3.3V / 2.5V
2–10k Ohm
IRQ
400pF (max)
Figure 5: AC Output Test Load (IRQ)
Note: The IRQ_N pin is an open-drain driver. IDT recommends a weak pull-up resistor (2-10k Ohm) be placed on this pin to VDD3.
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3.3V / 2.5V
2k Ohm
SDA,
SCL
400pF (max)
Figure 6: AC Output Test Load (I2C)
Note: The SDA and SCL pins are open-drain drivers. For information on the appropriate selection of pull-up resistors for each, see the Philips I2C
Specification [1].
C1
TXP
Internal
To Device
Z0
RXP
R1
Tx
Rx
Vbias
TXN
R2
RXN
Z0
C2
Figure 7: S-RIO Lanes Test Load
The characteristic impedance Z0 should be designed for 100 Ohms differential. An inline capacitor C1 and C2 at each input of the receiver
provides AC-coupling and a DC-block. The IDT recommended values are 75 - 200nF for each. Thus, any DC bias differential between the two
devices on the link is negated. The differential input resistance at the receiver is 100 Ohms, as defined in the RapidIO Specification (Rev. 2.1).
Thus, R1 and R2 are 50 Ohms each. Note that VBIAS is the internal bias voltage of the device’s receiver.
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9.
Power Consumption
Heat generated by the packaged IC and increase in voltage supplies have an adverse effect on the device power consumption. In order to control
its functional and maximum design temperature limits, IDT recommends at a minimum to have adequate airflow. The typical and maximum power
numbers provided below take into consideration the following characteristics, Theta Ja = 11oC/W with 2m/s of airflow. For more information on
thermal analysis, see Thermal Characteristics.
An estimate of the device power figure for an application usage can be determined by using the device’s “Power Calculator” modeling tool
available on the IDT secure site.
The typical power condition refers to nominal voltage for all rails and is 4.2W in total for all ports enabled as 16 1x at 6.25 Gbaud under 50% switch
load.
The maximum power condition refers to maximum voltage for all rails and is 7.2W in total for all ports enabled as 16 1x at 6.25 Gbaud under 100%
switch load.
Table 6: Power Consumption
Power Supplies
Core Supply
(VDD)
SerDes Supply
(VDDS)
SerDes Supply
Xmt (VDDT)
PLL Supply
(VDDA)
I/O Supply
(VDD3)
Line Rate
Gbaud
Current/
Power
Typ
1.0V
Max
1.05V
Typ
1.0V
Max
1.05V
Typ
1.2V
Max
1.26V
Typ
1.0V
Max
1.05V
Typ
3.3V
Max
3.47V
6.25
Amps
2.53
4.73
0.84
1.00
0.46
0.55
0.27
0.30
0.015
0.032
Watts
2.53
4.97
0.84
1.05
0.55
0.69
0.27
0.32
0.050
0.12
Amps
2.43
4.52
0.76
0.90
0.46
0.55
0.27
0.30
0.015
0.032
Watts
2.43
4.75
0.76
0.95
0.55
0.69
0.27
0.32
0.050
0.12
Amps
2.36
4.37
0.69
0.82
0.46
0.55
0.27
0.30
0.015
0.032
Watts
2.36
4.59
0.69
0.86
0.55
0.69
0.27
0.32
0.050
0.12
Amps
2.31
4.28
0.65
0.77
0.46
0.55
0.27
0.30
0.015
0.032
Watts
2.31
4.49
0.65
0.81
0.55
0.69
0.27
0.32
0.050
0.12
Amps
2.27
4.15
0.58
0.70
0.46
0.55
0.27
0.30
0.015
0.032
Watts
2.27
4.36
0.58
0.74
0.55
0.69
0.27
0.32
0.050
0.12
5.0
3.125
2.5
1.25
Total
Typ
Power
Max
Power
4.24
7.15
4.06
6.83
3.92
6.58
3.83
6.43
3.72
6.23
Notes:
1. Typical conditions: VDD, VDDS, VDDA = 1.0V, VDDT = 1.2V, VDD3 = 3.3V at Ambient Temperature of 60oC (Theta Ja = 11oC/W @ 2m/s airflow).
2. Maximum conditions: VDD, VDDS, VDDA = 1.05V, VDDT = 1.26V, VDD3 = 3.47V at max Junction Temperature (125oC).
10.
I2C Bus
The CPS-1616 is compliant with the I2C specification [1]. This specification provides the functional information and electrical specifications
associated with the I2C bus, including signaling, addressing, arbitration, AC timing, and DC specifications. The CPS-1616 supports both master
mode and slave mode, which is selected by MM_N pin.
The I2C bus consists of the Serial Data (SDA) and Serial Clock (SCL) pins. It can be used to attach a CPU or a configuration memory. The I2C
Interface supports Fast/Standard (F/S) mode (400/100 kHz).
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I2C Master Mode and Slave Mode
The CPS-1616 support both master mode and slave mode. The operating mode is selected by the MM_N static configuration pin. For more
information, see Signaling.
I2C Device Address
The device address for the CPS-1616 is fully pin-defined by 10 external pins while in slave mode. This provides full flexibility in defining the slave
address to avoid conflicting with other I2C devices on a bus. The CPS-1616 can be operated as either a 10-bit addressable device or a 7-bit
addressable device based on another external pin, address select (ADS). If the ADS pin is tied to VDD3, then the CPS-1616 operates as a 10-bit
addressable device and the device address will be defined as ID[9:0]. If the ADS pin is tied to GND, then the CPS-1616 operates as a 7-bit
addressable device with the device address defined by ID[6:0]. The addressing mode must be established at power-up and remain static
throughout operation. Dynamic changes will result in unpredictable behavior.
Table 7: I2C Static Address Selection Pin Configuration
Pin
I2C Address Bit (pin_addr)
ID9
9 (don’t care in 7-bit mode)
ID8
8 (don’t care in 7-bit mode)
ID7
7 (don’t care in 7-bit mode)
ID6
6
ID5
5
ID4
4
ID3
3
ID2
2
ID1
1
ID0
0
All of the CPS-1616’s registers are addressable through I2C. These registers are accessed using 22-bit addresses and 32-bit word boundaries
through standard reads and writes. These registers also can be accessed through the S-RIO and JTAG Interfaces.
Signaling
Communication with the CPS-1616 on the I2C bus follows these three cases:
1. Suppose a master device wants to send information to the CPS-1616:
– Master device addresses CPS-1616 (slave)
– Master device (master-transmitter), sends data to CPS-1616 (slave- receiver)
– Master device terminates the transfer
2. If a master device wants to receive information from the CPS-1616:
– Master device addresses CPS-1616 (slave)
– Master device (master-receiver) receives data from CPS-1616 (slave- transmitter)
– Master device terminates the transfer
3. If CPS-1616 polls configuration image from external memory
– CPS-1616 addresses the memory
– Memory transmits the data
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– CPS-1616 gets the data
All signaling is fully compliant with I2C (for signaling information, see the Philips I2C Specification) [1]. Standard signaling and timing waveforms are
displayed below.
Connecting to Standard-, Fast-, and Hs-mode Devices
The CPS-1616 supports Fast/Standard (F/S) modes of operation. Per I2C specification, in mixed speed communication the CPS-1616 supports
Hs- and Fast-mode devices at 400 Kbps, and Standard-mode devices at 100 Kbps. For information on speed negotiation on a mixed speed bus,
see the I2C specification.
CPS-1616-Specific Memory Access (Slave Mode)
There is a CPS-1616-specific I2C memory access implementation. This implementation is fully I2C compliant. It requires the memory address to be
specified during writes. This provides directed memory accesses through the I2C bus. Subsequent reads begin at the address specified during the
last write.
The write procedure requires the 3 bytes (22 bits) of memory address to be provided following the device address. Thus, the following are
required: device address – one or two bytes depending on 10-bit / 7-bit addressing, memory address – 3 bytes yielding 22 bits of memory address,
and a 32-bit data payload – 4-byte words. To remain consistent with S-RIO standard maintenance packet memory address convention, the I2C
memory address provided must be the 22 MSBs. Since I2C writes to memory apply to double-words (32 bits), the two LSBs are “don’t care” as the
LSBs correspond to word and byte pointers.
The read procedure has the memory address section of the transfer removed. Thus, to perform a read, the proper access would be to perform a
write operation and issue a repeated start after the acknowledge bit following the third byte of memory address. Then, the master would issue a
read command selecting the CPS-1616 through the standard device address procedure with the R/W bit high. Note that in 10-bit device address
mode (ADS=1), only the two MSBs need be provided during this read. Data from the previously loaded address would immediately follow the
device address protocol. A stop or repeated start can be issued anytime during the write data payload procedure, but must be before the final
acknowledge; that is, canceling the write before the write operation is completed and performed. Also, the master would be allowed to access
other devices attached to the I2C bus before returning to select the CPS-1616 for the subsequent read operation from the loaded address.
Read/Write Figures
R=1 | W=0
0
18
9
DATA
Input Data
[23:16]
Memory
Address [9:2]
A
DATA
Input Data
[15:8]
A
A
DATA
82
_
A A
P
Input Data
[7:0]
STOP
ACK
A
DATA
72
ACK
Input Data
[31:24]
63
ACK
DATA
Memory
Address [17:10]
A
ACK
54
DATA
ACK
Memory
Address [23:18]
A
45
ACK
DATA
36
ACK
START
Device
Address [7:0]
Device
Address [9:8]
A
ACK
SLAVE ADDR
ACK
R/W
S 1 1 1 1 0 S A 0 A
27
Figure 8: Write Protocol with 10-bit Slave Address (ADS is 1)
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I2C writes to memory align on 32-bit word boundaries, thus the 24 address MSBs must be provided while the two LSBs associated with word and
byte pointers are “don’t care”, and therefore are not transmitted.
R=1 | W=0
0
18
9
DATA
Memory
Address [17:10]
A
DATA
A
Memory
Address [9:2]
ACK
Memory
Address [23:18]
A
45
ACK
DATA
36
ACK
START
Device
Address [7:0]
Device
Address [9:8]
A
ACK
SLAVE ADDR
ACK
R/W
S 1 1 1 1 0 S A 0 A
27
R=1 | W=0
DATA
Output Data
[15:8]
A
DATA
Output Data
[7:0]
A
DATA
83
_ _
P
AA
Output Data
[7:0]
STOP
NACK
Output Data
[23:16]
A
STOP
NACK
DATA
92
_ _
P
AA
ACK
Output Data
[31:24]
A
82
ACK
ACK
R/W
START
repeated
Device
Address [9:8]
DATA
73
ACK
Sr 1 1 1 1 0 S A 1 A
64
ACK
55
Figure 9: Read Protocol with 10-bit Slave Address (ADS is 1)
R=1 | W=0
0
9
Memory
Address [23:18]
A
DATA
Memory
Address [17:10]
A
DATA
A
Memory
Address [9:2]
ACK
DATA
36
ACK
START
Device
Address [6:0]
0 A
27
ACK
SLAVE ADDR
ACK
R/W
S
18
R=1 | W=0
46
Output Data
[31:24]
A
DATA
Output Data
[23:16]
73
A
DATA
ACK
DATA
64
ACK
START
repeated
Device
Address [6:0]
1 A
ACK
R/W
Sr SLAVE ADDR
55
Output Data
[15:8]
Figure 10: Write Protocol with 7-bit Slave Address (ADS is 0)
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I2C writes to memory align on 32-bit word boundaries, thus the 24 address MSBs must be provided while the two LSBs associated with word and
byte pointers are “don’t care”, and therefore are not transmitted.
R=1 | W=0
0
9
Memory
Address [23:18]
A
DATA
Memory
Address [17:10]
A
DATA
A
Memory
Address [9:2]
ACK
DATA
36
ACK
START
Device
Address [6:0]
0 A
27
ACK
SLAVE ADDR
ACK
R/W
S
18
R=1 | W=0
46
Output Data
[23:16]
A
DATA
Output Data
[15:8]
A
DATA
Output Data
[7:0]
STOP
NACK
DATA
83
_ _
P
AA
ACK
Output Data
[31:24]
A
73
ACK
DATA
64
ACK
START
repeated
Device
Address [6:0]
1 A
ACK
R/W
Sr SLAVE ADDR
55
Figure 11: Read Protocol with 7-bit Slave Address (ADS is 0)
CPS-1616 Configuration and Image (Master mode)
There is both a power-up master and a command master mode. If powered up in master mode, the CPS-1616 polls configuration image from
external memory after the device reset sequence has completed. Once the device has completed its configuration sequence, it will revert to slave
mode. Through a configuration register write, the device can be commanded to enter master mode, which provides more configuration sequence
flexibility. For more information, see the “I2C Interface” chapter in the CPC-1616 User Manual.
I2C DC Electrical Specifications
Note that the ADS and ID pins will all run off the VDD3 (3.3V/2.5V) power supply, and these pins are required to be fixed during operation. Thus,
these pins must be statically tied to the 3.3V/2.5V supply or GND.
Table 8 to Table 10 list the SDA and SCL electrical specifications for F/S-mode I2C devices.
At recommended operating conditions with VDD3 = 3.3V ± 5%.
Table 8: I2C DC Electrical Specifications (3.3V)
Symbol
Min
Max
Unit
Input high voltage level
VIH
0.7 x VDD3
VDD3(max) + 0.5
V
Input low voltage level
VIL
-0.5
0.3 x VDD3
V
Hysteresis of Schmitt trigger inputs
VHYS
0.05 x VDD3
-
V
Output low voltage
VOL
0
0.4
ns
Output fall time from VIH(min) to VIL(max) with a
bus capacitance from 10pF to 400pF
tOF
20 + 0.1 x Cb
250
ns
Pulse width of spikes which must be
suppressed by the input filter
tSP
0
50
ns
Input current each I/O pin (input voltage is
between 0.1 x VDD3 and 0.9 x VDD3 (max))
II
-10
10
uA
Capacitance for each I/O pin
CI
-
10
pF
Parameter
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At recommended operating conditions with VDD3 = 2.5V ± 100mV.
Table 9: I2C DC Electrical Specifications (2.5V)
Symbol
Min
Max
Unit
Input high voltage level
VIH
0.7 x VDD3
VDD3(max) + 0.1
V
Input low voltage level
VIL
-0.5
0.3 x VDD3
V
Hysteresis of Schmitt trigger inputs
VHYS
0.05 x VDD3
-
V
Output low voltage
VOL
0
0.4
ns
Output fall time from VIH(min) to VIL(max) with a
bus capacitance from 10pF to 400pF
tOF
20 + 0.1 x Cb
250
ns
Pulse width of spikes which must be
suppressed by the input filter
tSP
0
50
ns
Input current each I/O pin (input voltage is
between 0.1 x VDD3 and 0.9 x VDD3 (max))
II
-10
10
uA
Capacitance for each I/O pin
CI
-
10
pF
Parameter
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I2C AC Electrical Specifications
Table 10: Specifications of the SDA and SCL Bus Lines for F/S-mode I2C Bus Devices
Signal
Symbol
Reference
Edge
I2C(1,4)
SCL
SDA(2,3)
Start or repeated start
condition
Stop condition
Standard
Mode
Fast
Mode
Unit
Min
Max
Min
Max
0
100
0
400
kHz
tHD;STA
4.0
-
0.6
-
us
tr
-
1000
-
300
ns
tF
-
300
-
300
ns
fSCL
none
tSU;DAT
SCL rising
250
-
100
-
ns
tHD;DAT
SCL falling
0
3.45
0
0.9
us
tr
-
-
1000
10
300
ns
tF
-
-
300
10
300
ns
tSU;STA
SDA falling
4.7
-
0.6
-
us
4.0
-
0.6
-
us
tSU;STO
tSU;STO
SDA rising
4.0
-
0.6
-
us
Bus free time between a
stop and start condition
tBUF
-
4.7
-
1.3
-
us
Capacitive load for each
bus line
CB
-
-
400
-
400
pF
Notes:
1. For more information, see the I2C-Bus Specification by Philips Semiconductor.
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined
region of the falling edge of SCL.
3. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT > 250 ns must then be met. This will
automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL
signal, it must output the next data bit to the SDA line tRMAX + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification)
before the SCL line is released.
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I2C Timing Waveforms
tBUF
SDA
tLOW
tHD;STA
tHD;DAT
tHIGH
tSU;STA
tSU;DAT
tHD;STA
tSU;STO
SCL
Figure 12: I2C Timing Waveforms
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11.
Interrupt (IRQ_N) Electrical Specifications
At recommended operating conditions with VDD3 = 3.3V ± 5%.
Table 11: IRQ_N Electrical Specifications (VDD3 = 3.3V ± 5%)
Parameter
Symbol
Min
Max
Unit
Output low voltage (IOL = 4mA, VDD3 = Min.)
VOL
0
0.4
V
Output fall time from VIH(min) to VIL(max) with a
bus capacitance from 10pF to 400pF
tOF
-
25
ns
Input current each I/O pin (input voltage is
between 0.1 x VDD3 and 0.9 x VDD3 (max))
II
-10
10
uA
Capacitance for IRQ_N
CI
-
10
pF
At recommended operating conditions with VDD3 = 2.5V ± 100mV.
Table 12: IRQ_N Electrical Specifications (VDD3 = 2.5V ± 100mV)
Parameter
Symbol
Min
Max
Unit
Output low voltage (IOL = 2mA, VDD3 = Min.)
VOL
0
0.4
V
Output fall time from VIH(min) to VIL(max) with a
bus capacitance from 10pF to 400pF
tOF
-
25
ns
Input current each I/O pin (input voltage is
between 0.1 x VDD3 and 0.9 x VDD3 (max))
II
-10
10
uA
Capacitance for IRQ_N
CI
-
10
pF
Figure 13: IRQ_N Timing Diagram
The IRQ_N pin is an open-drain driver. IDT recommends a weak pull-up resistor (2-10k Ohm) be placed on this pin to VDD3. The IRQ_N pin goes
active low when any special error filter error flag is set, and is cleared when all error flags are reset.
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12.
Configuration (Static) Pin Specification
The following are the configuration pins this specification applies to; FSEL[1:0], MCAST2, PD[15:0]_N, RST_N, QCFG[7:0] and SPD[2:0].
Table 13: Configuration Pin Electrical Specification1
Min
Max
Symbol
2.5V
3.3V
2.5V
3.3V
Unit
Input Low Voltage
VIL
-0.3
-0.3
0.7
0.8
V
Input High Voltage
VIH
1.7
2.0
2.8
3.6
V
Parameter
Notes:
1. Configuration pins must be set prior to or coincident with reset de-assertion and remain static following reset de-assertion. Any change on the
configuration pins after reset is de-asserted can result in unexpected behavior.
2. The MCAST pin is asynchronous signal and sampled on the rising edge of the internal core clock.
The following internal pull-up resistor specification applies to following configuration pins; FSEL[1:0], MM_N, PD[15:0]_N, QCFG[7:0], TDI, TMS and
TRST_N.
Table 14: Pull-up Resistor Specification
Parameter
Pull-up Resistor Values
©2017 Integrated Device Technology, Inc.
Min
Typ
Max
Unit
29
39
63
K Ohms
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13.
S-RIO Ports
Overview
The CPS-1616’s SerDes are in full compliance to the RapidIO AC specifications for the LP-Serial Physical Layer [5]. This section provides those
specifications for reference only; the user should see the specification for complete requirements.
Chapter 9 of the LP-Serial Physical Layer Specification, “1.25 Gbaud, 2.5 Gbaud, and 3.125 Gbaud LP-Serial Links” defines Level I links
compatible with the 1.3 version of the Physical Layer Specification, that supports throughput rates of 1.25, 2.5, and 3.125 Gbaud. Chapter 10 of
the specification, “5 Gbaud and 6.25 Gbaud LP-Serial Links” defines Level II links that support throughput rates of 5 and 6.25 Gbaud.
A Level I link should:
•
Allow 1.25, 2.5, or 3.125 Gbaud rates
•
Support AC coupling
•
Support hot swap
•
Support short run (SR) and long run (LR) links achieved with two transmitters
•
Support single receiver specification that will accept signals from both the short run and long run transmitter specifications
•
Achieve Bit Error Ratio of lower than 10-12 per lane
A Level II link should:
•
Allow 5 or 6.25 Gbaud baud rates
•
Support AC coupling
•
Support hot swap
•
Support short run (SR), medium run (MR), and long run (LR) links achieved with two transmitters and two receivers
•
Achieve Bit Error Ratio of lower than 10-15 per lane
Together, these specifications allow for solutions ranging from simple chip-to-chip interconnect to board-to-board interconnect driving two
connectors across a backplane. The faster and wider electrical interfaces specified here are required to provide higher density and/or lower cost
interfaces.
The short run defines a transmitter and a receiver that should be used mainly for chip-to-chip connections on either the same printed circuit board
or across a single connector. This covers the case where connections are made to a mezzanine (daughter) card. The smaller swings of the short
run specification reduces the overall power used by the transceivers.
The long run defines a transmitter and receiver that use larger voltage swings and channel equalization that allows a user to drive signals across
two connectors and backplanes.
The two transmitter specifications allows for a medium run specification that also uses larger voltage swings that can drive signals across a
backplane but simplifies the receiver requirements to minimize power and complexity. This option has been included to allow the system integrator
to deploy links that take advantage of either channel materials and/or construction techniques that reduce channel loss to achieve lower power
systems.
The electrical specifications are based on loss, jitter, and channel cross-talk budgets and defines the characteristics required to communicate
between a transmitter and a receiver using nominally 100 Ohm differential copper signal traces on a printed circuit board. Rather than specifying
materials, channel components, or configurations, this specification focuses on effective channel characteristics. Therefore, a short length of
poorer material should be equivalent to a longer length of premium material. A 'length' is effectively defined in terms of its attenuation rather than
physical distance.
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Definition of Amplitude and Swing
LP-Serial links use differential signaling. This section defines the terms used in the description and specification of these differential signals.
Figure 14 shows how these signals are defined and sets out the relationship between absolute and differential voltage amplitude. The figure
shows waveforms for either the transmitter output (TD and TD_N) or a receiver input (RD and RD_N).
Figure 14: Definition of Transmitter Amplitude and Swing
Each signal swings between the voltages VHIGH and VLOW where
VHIGH > VLOW
The differential voltage, VDIFF is defined as
VDIFF = VD+ - VDwhere VD+ is the voltage on the positive conductor and VD- is the voltage on the negative conductor of a differential transmission line. VDIFF
represents either the differential output signal of the transmitter, VOD, or the differential input signal of the receiver, VID where
VOD = VTD - VTD
and
VID = VRD - VRD
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The common mode voltage, VCM, is defined as the average or mean voltage present on the same differential pair. Therefore
VCM = | VD+ + VD- | / 2
The maximum value, or the peak-to-peak differential voltage, is calculated on a per unit interval and is defined as
VDIFFp-p = 2 x max | VD+ - VD- |
because the differential signal ranges from VD+ - VD- to -(VD+ - VD-)
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter and each of its outputs, TD and
TD_N, has a swing that goes between VHIGH = 2.5V and VLOW = 2.0V, inclusive. Using these values the common mode voltage is calculated to be
2.25 V and the single-ended peak voltage swing of the signals TD and TD_N is 500 mVpp. The differential output signal ranges between 500 mV
and -500 mV, inclusive. therefore the peak-to-peak differential voltage is 1000 mVppd.
1.25, 2.5, and 3.125 Gbaud LP-Serial Links
This section explains the requirements for Level I RapidIO LP-Serial short and long run electrical interfaces of nominal baud rates of 1.25, 2.5, and
3.125 Gbaud using NRZ coding (thus, 1 bit per symbol at the electrical level). The CPS-1616’s SerDes meet all of the requirements listed below.
The electrical interface is based on a high speed, low voltage logic with a nominal differential impedance of 100 Ohm. Connections are
point-to-point balanced differential pair and signaling is unidirectional.
The level of links defined in this section are identical to those defined in the RapidIO Specification (Rev. 1.3), 1x/4x LP-Serial Electrical
Specification.
Equalization
With the use of high speed serial links, the interconnect media will cause degradation of the signal at the receiver. Effects such as Inter-Symbol
Interference (ISI) or data dependent jitter are produced. This loss can be large enough to degrade the eye opening at the receiver beyond what is
allowed in the specification. To negate a portion of these effects, equalization can be used in the transmitter and/or receiver, but it is not required at
baud rates less than 3.5 Gbaud.
Explanatory Note on Level I Transmitter and Receiver Specifications
AC electrical specifications are provided for the transmitter and receiver. Long run and short run interfaces at three baud rates are described.
The parameters for the AC electrical specifications are guided by the XAUI electrical interface specified in Clause 47 of IEEE 802.3ae-2002.[1] The
goal of this standard is that electrical designs for Level I electrical designs can reuse XAUI, suitably modified for applications at the baud intervals
and runs described herein.
Level I Electrical Specification
Level I Transmitter Characteristics
Level I LP-Serial transmitter electrical and timing specifications are stated in the text and tables of this section. The differential return loss, S11, of
the transmitter in each case must be better than:
-10 dB for (Baud Frequency) / 10 < Freq(f) < 625 MHz, and
-10 dB + 10log(f/625 MHz) dB for 625 MHz <= Freq(f) <= Baud Frequency
The reference impedance for the differential return loss measurements is 100 Ohm resistive. Differential return loss includes contributions from
on-chip circuitry, chip packaging and any off-chip components related to the driver. The output impedance requirement applies to all valid output
levels.
The CPS-1616 satisfies the specification requirement that the 20%-80% rise/fall time of the transmitter, as measured at the transmitter output, in
each case has a minimum value 60 ps.
Similarly, the timing skew at the output of an LP-Serial transmitter between the two signals that comprise a differential pair does not exceed 25 ps
at 1.25 Gbaud, 20 ps at 2.5 Gbaud, and 15 ps at 3.125 Gbaud.
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Level I Short Run Transmitter Specifications
Table 15: Level I Short Run Transmitter AC Timing Specifications
Symbol
Reference
Min
Typ
Max
Units
Baud Rate
Section 9.4.1.2
1.25
-
3.125
Gbaud
Absolute Output Voltage
Section 9.4.1.3
-0.40
-
2.30
Volts
T_Vdiff
Output Differential Voltage
(into floating load Rload = 100 Ohm)
Section 9.4.1.3
500
-
1000
mVppd
T_Rd
Differential Resistance
Section 9.4.1.5
80
100
120
ohm
T_tr, T_tf
Recommended output rise and fall times
(20% to 80%)
Section 9.4.1.4
60
-
-
ps
T_SDD22
Differential Output Return Loss
(T_baud/10 < f < T_baud/2)
Section 9.4.1.6
-
-
-
dB
-
-
-
dB
-
-
Note 3
dB
-
-
Note 4
mVppd
T_Baud
VO
Characteristics
Differential Output Return Loss
(T_baud/10 < f < T_baud/2)
T_TCC22
Common Mode Return Loss
(625 MHz < f < T_baud)
Section 9.4.1.6
T_Ncm
Transmitter Common Mode Noise1
T_Vcm
Output Common Mode Voltage
Load Type 02
0
-
2.1
V
SMO
Multiple output skew, N < 4
Section 9.4.1.7
-
-
1000
ps
SMO
Multiple output skew, N > 4
Section 9.4.1.7
-
-
2UI + 1000
ps
-
320
-
800
ps
UI
Unit Interval
Notes:
1. For all Load Types: R_Rdin = 100 Ohm +/- 20 Ohm.
2. Load Type 0 with min. T_Vdiff, AC-coupling or floating load.
3. It is suggested that T_SCC22 be -6 dB to be compatible with Level II transmitter requirements.
4. It is suggested that T_Ncm be limited to 5% of T_Vdiff to be compatible with Level II transmitter requirements.
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Level I Long Run Transmitter Specifications
Table 16: Level I Long Run Transmitter AC Timing Specifications
Characteristics
Symbol
Reference
Min
Typ
Max
Units
T_Baud
Section 9.4.2.2
1.25
-
3.125
Gbaud
VO
Section 9.4.2.3
-0.40
-
2.30
Volts
Output Differential Voltage
(into floating load Rload = 100 Ohm)
T_Vdiff
Section 9.4.2.3
800
-
1600
mVppd
Differential Resistance
T_Rd
Section 9.4.1.5
80
100
120
ohm
Recommended output rise and fall
times
(20% to 80%)
T_tr, T_tf
-
60
-
-
ps
Differential Output Return Loss
(T_baud/10 < f < T_baud/2)
T_SDD22
Section 9.4.1.6
-
-
-
dB
-
-
-
dB
-
-
Note 3
dB
-
-
Note 4
mVppd
Baud Rate
Absolute Output Voltage
Differential Output Return Loss
(T_baud/10 < f < T_baud/2)
Common Mode Return Loss
(625 MHz < f < T_baud)
T_TCC22
Section 9.4.1.6
Transmitter Common Mode Noise1
T_Ncm
Output Common Mode Voltage
T_Vcm
Load Type 02
0
-
2.1
V
Multiple output skew, N < 4
SMO
-
-
-
1000
ps
Multiple output skew, N > 4
SMO
-
-
-
2UI + 1000
ps
UI
-
320
-
800
ps
Unit Interval
Notes:
1. For all Load Types: R_Rdin = 100 Ohm +/- 20 Ohm.
2. Load Type 0 with min. T_Vdiff, AC-coupling or floating load.
3. It is suggested that T_SCC22 be -6 dB to be compatible with Level II transmitter requirements.
4. It is suggested that T_Ncm be limited to 5% of T_Vdiff to be compatible with Level II transmitter requirements.
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For each baud rate at which the LP-Serial transmitter is specified to operate, the output eye pattern of the transmitter falls entirely within the
unshaded portion of the Transmitter Output Compliance Mask displayed in Figure 15 when measured at the output pins of the device and the
device is driving a 100 Ohm + 5% differential resistive load. The specification allows the output eye pattern of a LP-Serial transmitter that
implements pre-emphasis (to equalize the link and reduce inter-symbol interference) to only comply with the Transmitter Output Compliance Mask
when pre-emphasis is disabled or minimized
Figure 15: Transition Symbol Transmit Eye Mask
Table 17: Level I Near-End (Tx) Template Intervals
Symbol
Near-End
Short Run
Value
Near-End
Long Run
Value
Units
Eye Mask
T_X1
0.17
0.17
UI
Eye Mask
T_X2
0.39
0.39
UI
Eye Mask
T_Y1
250
400
mV
Eye Mask
T_Y2
500
800
mV
Eye Mask
T_Y3
N/A
N/A
mV
T_UBHPJ
0.17
0.17
UIpp
T_DCD
0.05
0.05
UIpp
T_TJ
0.35
0.35
UIpp
Characteristics
Uncorrelated Bounded High
Probability Jitter
Duty Cycle Distortion
Total Jitter
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Level I Receiver Specifications
Level I LP-Serial receiver electrical and timing specifications are stated in the text and tables of this section.
Table 18: Level I Receiver Electrical Input Specifications
Characteristics
Symbol
Reference
Min
Typ
Max
Units
Rx Baud Rate (1.25 Gbaud)
R_Baud
-
-
1.250
-
Gbaud
Rx Baud Rate (2.5 Gbaud)
-
-
2.500
-
Gbaud
Rx Baud Rate (3.125 Gbaud)
-
-
3.125
-
Gbaud
-
-
Absolute Input Voltage
R_Vin
Section 9.4.3.4
Input Differential Voltage
R_Vdiff
Section 9.4.3.3
200
-
1600
mVppd
Differential Resistance
R_Rdin
Section 9.4.3.7
80
100
120
ohm
R_SDD11
Section 9.4.3.7
-
-
-
dB
-
-
-
-
-
-
-
dB
Differential Input Return Loss
(100 MHz < f < R_Baud/2)
Differential Input Return Loss
(R_Baud/2 < f < R_Baud)
Common Mode Input Return Loss
(625 MHz < f < T_baud)
Termination Voltage1,2
Input Common Mode Voltage1,2
R_SCC11
Section 9.4.3.7
R_Vtt
R_Vtt floating4
R_Vrcm
R_Vtt floating3,4
-0.05
-
1.85
V
n
-
-
10
-
-
Wander Divider
Not Specified
V
Notes:
1. Input common mode voltage for AC-coupled or floating load input with min. T_Vdiff.
2. Receiver is required to implement at least one of the specified nominal R_Vtt values, and usually implements only one of these values. Receiver is
only required to meet R_Vrcm parameter values that correspond to R_Vtt values supported.
3. Input common mode voltage for AC-coupled or floating load input with min. T_Vdiff.
4. For floating load, input resistance must be > 1K Ohm.
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Table 19: Level I Receiver Input Jitter Tolerance Specifications
Characteristics
Symbol
Reference
Min
Typ
Max
Units
BER
-
-
-
10-12
-
R_BHPJ
Section 9.4.3.8
-
-
0.37
UIpp
R_SJ-max
Section 9.4.3.8
-
-
8.5
UIpp
R_SJ-hf
Section 9.4.3.8
-
-
0.1
UIpp
Total Jitter (Does not include Sinusoidal
Jitter)
R_TJ
Section 9.4.3.8
-
-
0.55
UIpp
Total Jitter Tolerance1
R_JT
-
-
-
0.65
UIpp
Eye Mask
R_X1
Section 9.4.3.8
-
-
0.275
UI
Eye Mask
R_Y1
Section 9.4.3.8
-
-
100
mV
Eye Mask
R_Y2
Section 9.4.3.8
-
-
800
mV
Bit Error Ratio
Bounded High Probability Jitter
Sinusoidal Jitter, maximum
Sinusoidal Jitter, High Frequency
Notes:
1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinusoidal jitter can have
any amplitude and frequency in the unshaded region of the following figure. The sinusoidal jitter component is included to ensure margin for the low
frequency jitter, wander, noise, crosstalk and other variable system effects.
Figure 16: Single Frequency Sinusoidal Jitter Limits
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Level I Receiver Eye Diagram
For each baud rate at which the a LP-Serial receiver is specified to operate, the receiver meets the corresponding Bit Error Ratio specification in
Table 20 when the eye pattern of the receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the Receiver
Input Compliance Mask displayed in Figure 17. The eye pattern of the receiver test signal is measured at the input pins of the receiving device with
the device replaced with a 100 Ohm + 5% differential resistive load.
Figure 17: Level I Receiver Input Mask
Table 20: Level I Far-End (Rx) Template Intervals
Symbol
Far-End
Value
Units
Eye Mask
R_X1
0.275
UI
Eye Mask
R_X2
0.40
UI
Eye Mask
R_Y1
100
mV
Eye Mask
R_Y2
800
mV
High Probability Jitter
R_HPJ
0.37
UIpp
R_TJ
0.55
UIpp
Characteristics
Total Jitter (Does not include
Sinusoidal Jitter)
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5 and 6.25 Gbaud LP-Serial Links
This chapter describes the requirements for Level II RapidIO LP-Serial short, medium, and long run electrical interfaces of nominal baud rates of
5.0 and 6.25 Gbaud using NRZ coding (thus, 1 bit per symbol at the electrical level). The electrical interface is based on a high speed low voltage
logic with a nominal differential impedance of 100 Ohm. Connections are point-to-point balanced differential pair and signaling is unidirectional.
Explanatory Note on Level I Transmitter and Receiver Specifications
AC electrical specifications are provided for transmitters and receivers. Long run, medium run and short run interfaces at two baud rates are
described. The parameters for the AC electrical specifications are guided by the OIF CEI Electrical and Jitter Inter-operability agreement for
CEI-6G-SR and CEI-6G-LR.
OIF CEI-6G-SR and CEI-6G-LR have similar application goals to S-RIO, as described in Section 10.1, “Level II Application Goals.” The goal of this
standard is that electrical designs for S-RIO can reuse electrical designs for OIF CEI-6G, suitably modified for applications at the baud intervals
and runs described herein.
Level II Electrical Specifications
The electrical interface is based on high speed, low voltage logic with nominal differential impedance of 100 Ohm. Connections are point-to-point
balanced differential pair and signaling is unidirectional.
Level II Transmitter Characteristics
Level II LP-Serial transmitter electrical and timing specifications are stated in the text and tables of this section.
The differential return loss must be better than A0 from f0 to f1 and better than
A0 + Slope*log10(f/f1)
Where f is the frequency from f1 to f2 (see section 8.5.11, Figure 8-12 of the RapidIO Specification (Rev. 2.1). Differential return loss is measured
at compliance points T and R. If AC coupling is used, then all components (internal or external) are to be included in this requirement. The
reference impedance for the differential return loss measurements is 100 Ohm.
Common mode return loss measurement must be better than -6dB between a minimum frequency of 100 MHz and a maximum frequency of 0.75
times the baud rate. The reference impedance for the common mode return loss is 25 Ohm.
The CPS-1616 satisfies the specification requirement that the 20%-80% rise/fall time of the transmitter, as measured at the transmitter output, in
each case has a minimum value 30 ps.
Similarly, the timing skew at the output of an LP-Serial transmitter between the two signals that comprise a differential pair does not exceed 10 ps
at 5.0 and 6.25 Gbaud.
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Level II Short Run Transmitter Specifications
Table 21: Level II Short Run Transmitter Output Electrical Specifications
Characteristics
Baud Rate (5 Gbaud)
Symbol
Reference
Min
Typ
Max
Units
T_Baud
Section
10.4.2.1.2
5.00 -0.01%
5.00
5.00 +0.01%
Gbaud
6.25 -0.01%
6.25
6.25 +0.01%
Gbaud
Baud Rate (6.25 Gbaud)
Absolute Output Voltage
VO
Section
10.4.2.1.3
-0.40
-
2.30
Volts
Output Differential Voltage
(into floating load Rload = 100
Ohm)
T_Vdiff
Section
10.4.2.1.3
400
-
750
mVppd
Differential Resistance
T_Rd
Section
10.4.2.1.6
80
100
120
ohm
Recommended output rise and fall
times (20% to 80%)
T_tr, T_tf
Section
10.4.2.1.4
30
-
-
ps
Skew between signals comprising
a differential pair
T_SKEWd
iff
Section
10.4.2.1.5
-
-
15
ps
Differential Output Return Loss
(100 MHz to 0.5 *T_Baud)
T_SDD22
Section
10.4.2.1.6
-
-
-8
dB
-
-
-
dB
Differential Output Return Loss
(0.5*T_Baud to T_Baud)
Common Mode Return Loss
(100 MHz to 0.75 *T_Baud)
Transmitter Common Mode Noise
Output Common Mode Voltage
T_SCC22
Section
10.4.2.1.6
-
-
-6
dB
T_Ncm
-
-
-
5% of T_Vdiff
mVppd
T_Vcm
Load Type 01
100
-
1700
mV
630
-
1100
mV
Section 8.5.3
Load Type
12,3
Section 8.5.3
Notes:
1. Load Type 0 with min T_Vdiff, AC-Coupling or floating load.
2. For load Type 1 through 3: R_Zvtt < 30 Ohm; Vtt is defined for each load type as follows: Load Type 1 R_Vtt = 1.2V +5% / - 8%; Load Type 2 R_Vtt
= 1.0V +5% / -8%; Load Type 3 R_Vtt = 0.8V +5% / -8%.
3. DC Coupling compliance is optional (Type 1 through 3). Only Transmitters that support DC coupling are required to meet this parameter. It is
acceptable for a transmitter to restrict the range of T_Vdiff in order to comply with the specified T_Vcm range. For a transmitter which supports
multiple T_Vdiff levels, it is acceptable for a transmitter to claim DC Coupling Compliance if it meets the T_Vcm ranges for at least one of its T_Vdiff
setting as long as those setting(s) that are compliant are indicated.
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Level II Medium Run Transmitter Specifications
Table 22: Level II Medium Run Transmitter Output Electrical Specifications
Characteristics
Baud Rate (5 Gbaud)
Symbol
Reference
Min
Typ
Max
Units
T_Baud
Section
10.6.2.1.2
5.00 -0.01%
5.00
5.00 +0.01%
Gbaud
6.25 -0.01%
6.25
6.25 +0.01%
Gbaud
Baud Rate (6.25 Gbaud)
Absolute Output Voltage
VO
Section
10.6.2.1.3
-0.40
-
2.30
Volts
Output Differential Voltage
(into floating load Rload = 100
Ohm)
T_Vdiff
Section
10.6.2.1.31
800
-
1200
mVppd
Differential Resistance
T_Rd
Section
10.6.2.1.6
80
100
120
ohm
Recommended output rise and fall
times (20% to 80%)
T_tr, T_tf
Section
10.6.2.1.4
30
-
-
ps
Skew between signals comprising
a differential pair
T_SKEWd
iff
Section
10.6.2.1.5
-
-
15
ps
Differential Output Return Loss
(100 MHz to 0.5 *T_Baud)
T_SDD22
Section
10.6.2.1.6
-
-
-8
dB
-
-
-
dB
Differential Output Return Loss
(0.5*T_Baud to T_Baud)
Common Mode Return Loss
(100 MHz to 0.75 *T_Baud)
T_S11
Section
10.6.2.1.6
-
-
-6
dB
Transmitter Common Mode Noise
T_Ncm
-
-
-
5% of T_Vdiff
mVppd
T_Vcm
Load Type 02
100
-
1700
mV
630
-
1100
mV
Output Common Mode Voltage
Section 8.5.3
Load Type
13,4
Section 8.5.3
Notes:
1. The transmitter must be able to produce a minimum T_Vdiff greater than or equal to 800mVppd. In applications where the channel is better than
the worst case allowed, a Transmitter device can be provisioned to produce T_Vdiff less than this minimum value, but greater than or equal to
400mVppd, and is still compliant with this specification.
2. Load Type 0 with min T_Vdiff, AC-Coupling or floating load.
3. For load Type 1: R_Zvtt < 30 Ohm; T_Vtt and R_Vtt = 1.2V +5% / - 8%.
4. DC Coupling compliance is optional (Load Type 1). Only Transmitters that support DC coupling are required to meet this parameter.
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Level II Long Run Transmitter Specifications
Table 23: Level II Long Run Transmitter Output Electrical Specifications
Characteristics
Baud Rate (5 Gbaud)
Symbol
Reference
Min
Typ
Max
Units
T_Baud
Section
10.5.2.1.2
5.00 -0.01%
5.00
5.00 +0.01%
Gbaud
6.25 -0.01%
6.25
6.25 +0.01%
Gbaud
Baud Rate (6.25 Gbaud)
Absolute Output Voltage
VO
Section
10.5.2.1.3
-0.40
-
2.30
Volts
Output Differential Voltage
(into floating load Rload = 100
Ohm)
T_Vdiff
Section
10.5.2.1.31
800
-
1200
mVppd
Differential Resistance
T_Rd
Section
10.5.2.1.6
80
100
120
ohm
Recommended output rise and fall
times (20% to 80%)
T_tr, T_tf
Section
10.5.2.1.4
30
-
-
ps
Skew between signals comprising
a differential pair
T_SKEWd
iff
Section
10.5.2.1.5
-
-
15
ps
Differential Output Return Loss
(100 MHz to 0.5 *T_Baud)
T_SDD22
Section
10.5.2.1.6
-
-
-8
dB
-
-
-
dB
Differential Output Return Loss
(0.5*T_Baud to T_Baud)
Common Mode Return Loss
(100 MHz to 0.75 *T_Baud)
T_S11
Section
10.5.2.1.6
-
-
-6
dB
Transmitter Common Mode Noise
T_Ncm
-
-
-
5% of T_Vdiff
mVppd
T_Vcm
Load Type 02
100
-
1700
mV
630
-
1100
mV
Output Common Mode Voltage
Section 8.5.3
Load Type
13,4
Section 8.5.3
Notes:
1. The transmitter must be able to produce a minimum T_Vdiff greater than or equal to 800mVppd. In applications where the channel is better than
the worst case allowed, a Transmitter device can be provisioned to produce T_Vdiff less than this minimum value, but greater than or equal to
400mVppd, and is still compliant with this specification.
2. Load Type 0 with min T_Vdiff, AC-Coupling or floating load.
3. For load Type 1: R_Zvtt < 30 Ohm; T_Vtt and R_Vtt = 1.2V +5% / - 8%.
4. DC Coupling compliance is optional (Load Type 1). Only Transmitters that support DC coupling are required to meet this parameter.
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For 5 and 6.25 Gbaud links the Transmitters eye mask will also be evaluated during the steady-state where there are no symbol transitions – for
example, a 1 followed by a 1 or a 0 followed by a 0 – and the signal has been de-emphasized. This additional transmitter eye mask constraint is
displayed in the following figure
Figure 18: Transition and Steady State Symbol Eye Mask
During the steady-state, the eye mask prevents the transmitter from de-emphasizing the low frequency content of the data too much and limiting
the available signal-to-noise at the receiver. The de-emphasis introduces a jitter artifact that is not accounted for in this eye mask. This additional
jitter is the result of the finite rise/fall time of the transmitter and the non-uniform voltage swing between the transitions. This additional deterministic
jitter must be accounted for as part of the high probability jitter and is specified in the following table.
Table 24: Level II Near-End (Tx) Template Intervals
Symbol
Near-End
Short Run Value
Near-End Medium
Run/Long Run Value
Comments
Units
Eye Mask
T_X1
0.15
0.15
-
UI
Eye Mask
T_X2
0.40
0.40
-
UI
Eye Mask
T_Y1
200
200
For
connection to
short run Rx
mV
400
For
connection to
long run Rx
375
For
connection to
short run Rx
600
For
connection to
long run Rx
Characteristics
Eye Mask
©2017 Integrated Device Technology, Inc.
T_Y2
375
41
mV
June 26, 2017
CPS-1616 Datasheet
Table 24: Level II Near-End (Tx) Template Intervals
Characteristics
Eye Mask
Uncorrelated Bounded High
Probability Jitter
Duty Cycle Distortion
Total Jitter
©2017 Integrated Device Technology, Inc.
Symbol
Near-End
Short Run Value
Near-End Medium
Run/Long Run Value
Comments
Units
T_Y3
125
N/A
-
mV
T_UBHPJ
0.15
0.15
-
UIpp
T_DCD
0.05
0.05
-
UIpp
T_TJ
0.30
0.30
-
UIpp
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Level II Short Run Receiver Specifications
Table 25: Level II Short Run Receiver Electrical Input Specifications
Characteristics
Symbol
Reference
Min
Typ
Max
Units
Rx Baud Rate (5 Gbaud)
R_Baud
Section
10.4.2.2.1
5.00 -0.01%
5.00
5.00 +0.01%
Gbaud
6.25 -0.01%
6.25
6.25 +0.01%
Gbaud
Rx Baud Rate (6.25 Gbaud)
Absolute Input Voltage
R_Vin
Section
10.4.2.2.3
-
-
-
-
Input Differential Voltage
R_Vdiff
Section
10.4.2.2.3
125
-
1200
mVppd
Differential Resistance
R_Rdin
Section
10.4.2.2.7
80
100
120
ohm
Bias Voltage Source Impedance1
(load types 1 to 3)
R_Zvtt
-
-
-
30
ohm
R_SDD11
Section
10.4.2.2.7
-
-
-8
dB
-
-
-
-
-
-
-6
dB
Differential Input Return Loss
(100 MHz to 0.5*R_Baud)
Differential Input Return Loss
(0.5*R_Baud to R_Baud)
Common Mode Input Return Loss
(100 MHz to 0.5*R_Baud)
Termination Voltage1,2
Input Common Mode Voltage1,2
Wander Divider
R_SCC11
Section
10.4.2.2.7
R_Vtt
R_Vtt floating4
R_Vrcm
n
Not Specified
V
R_Vtt = 1.2V
Nominal
1.2 -8%
-
1.2 +5%
V
R_Vtt = 1.0V
Nominal
1.0 -8%
-
1.0 +5%
V
R_Vtt = 0.8V
Nominal
0.8 -8%
-
0.8 +5%
V
Load Type 02
0
-
1800
mV
Load Type
11,3
595
-
R_Vtt - 60
mV
Section 8.4.5,
8.4.6
-
10
-
-
Notes:
1. DC Coupling compliance is optional. For Vcm definition, see Figure 14.
2. Receiver is required to implement at least one of the specified nominal R_Vtt values, and usually implements only one of these values. Receiver is
only required to meet R_Vrcm parameter values that correspond to R_Vtt values supported.
3. Input common mode voltage for AC-coupled or floating load input with min. T_Vdiff.
4. For floating load, input resistance must be > 1K Ohm.
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Level II Medium Run Receiver Specifications
Table 26: Level II Medium Run Receiver Electrical Input Specifications
Characteristics
Symbol
Reference
Min
Typ
Max
Units
Rx Baud Rate (5 Gbaud)
R_Baud
Section
10.6.2.2.1
5.00 -0.01%
5.00
5.00 +0.01%
Gbaud
6.25 -0.01%
6.25
6.25 +0.01%
Gbaud
Rx Baud Rate (6.25 Gbaud)
Absolute Input Voltage
R_Vin
Section
10.6.2.2.3
-
-
-
-
Input Differential Voltage
R_Vdiff
Section
10.6.2.2.3
-
-
1200
mVppd
Differential Resistance
R_Rdin
Section
10.6.2.2.7
80
100
120
ohm
Bias Voltage Source Impedance
(load type 1)1
R_Zvtt
-
-
-
30
ohm
R_SDD11
Section
10.6.2.2.7
-
-
-8
dB
-
-
-
-
Differential Input Return Loss
(100MHz to 0.5*R_Baud)
Differential Input Return Loss
(0.5*R_Baud to R_Baud)
Common Mode Input Return Loss
(100MHz to 0.5*R_Baud)
Input Common Mode Voltage1,2
R_SCC11
Section
10.6.2.2.7
-
-
-6
dB
R_Vfcm
Load Type 02
0
-
1800
mV
Load Type
11,3
595
-
R_Vtt - 60
mV
Section 8.4.5,
8.4.6
-
10
-
-
Wander Divider
n
Notes:
1. DC Coupling compliance is optional (Load Type 1). Only receivers that support DC coupling are required to meet this parameter.
2. Load Type 0 with min T_Vdiff, AC-Coupling or floating load. For floating load, input resistance must be > 1K Ohm.
3. For Load Type 1: T_Vtt and R_Vtt = 1.2V +5% / -8%.
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Level II Long Run Receiver Specifications
Table 27: Level II Long Run Receiver Electrical Input Specifications
Characteristics
Symbol
Reference
Min
Typ
Max
Units
Rx Baud Rate (5 Gbaud)
R_Baud
Section
10.5.2.2.1
5.00 -0.01%
5.00
5.00 +0.01%
Gbaud
6.25 -0.01%
6.25
6.25 +0.01%
Gbaud
Rx Baud Rate (6.25 Gbaud)
Absolute Input Voltage
R_Vin
Section
10.5.2.2.3
-
-
-
-
Input Differential Voltage
R_Vdiff
Section
10.5.2.2.3
-
-
1200
mVppd
Differential Resistance
R_Rdin
Section
10.5.2.2.7
80
100
120
ohm
Bias Voltage Source Impedance
(load type 1)1
R_Zvtt
-
-
-
30
ohm
R_SDD11
Section
10.5.2.2.7
-
-
-8
dB
-
-
-
-
Differential Input Return Loss
(100MHz to 0.5*R_Baud)
Differential Input Return Loss
(0.5*R_Baud to R_Baud)
Common Mode Input Return Loss
(100MHz to 0.5*R_Baud)
Input Common Mode Voltage1,2
R_SCC11
Section
10.5.2.2.7
-
-
-6
dB
R_Vfcm
Load Type 02
0
-
1800
mV
Load Type
11,3
595
-
R_Vtt - 60
mV
Section 8.4.5,
8.4.6
-
10
-
-
Wander Divider
n
Notes:
1. DC Coupling compliance is optional (Load Type 1). Only receivers that support DC coupling are required to meet this parameter.
2. Load Type 0 with min T_Vdiff, AC-Coupling or floating load. For floating load, input resistance must be > 1K Ohm.
3. For Load Type 1: T_Vtt and R_Vtt = 1.2V +5% / -8%.
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CPS-1616 Datasheet
Level II Receiver Eye Diagram
For a Level II link the receiver mask it is defined as displayed in the following figure. Specific parameter values for both masks are called out in the
following table
Figure 19: Level II Receiver Input Compliance Mask
Table 28 defines the parameters that will be specified for receivers that have an open eye at the far-end. The termination conditions used to
measure the received eye are defined in the above Level II Receiver Specification tables.
Table 28: Level II Short Run Far-End (Rx) Template Intervals
Symbol
Far-End
Value
Units
Eye Mask
R_X1
0.30
UI
Eye Mask
R_Y1
62.5
mV
Eye Mask
R_Y2
375
mV
Uncorrelated Bounded High
Probability Jitter
R_UBHPJ
0.15
UIpp
Correlated Bounded High Probability
Jitter
R_CBHPJ
0.30
UIpp
R_TJ
0.60
UIpp
Characteristics
Total Jitter (Does not include
Sinusoidal Jitter)
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CPS-1616 Datasheet
14.
Reference Clock
The differential reference clock (REF_CLK_P//N) generates the S-RIO PHY and internal clocks used in the CPS-1616.
Reference Clock Electrical Specifications
The reference clock is 156.25 MHz, and is AC-coupled with the following electrical specifications.
LI, CLK
REF_CLK_P
CI, CLK
RL,CLK
+
REF_CLK
VBIAS, CLK
RL,CLK
LI, CLK
REF_CLK_N
CI, CLK
External
to Device
Internal
to Device
5686 drw07
Figure 20: REF_CLK Representative Circuit
The series capacitors are descretes that must be placed external to the device’s receivers. All other
elements are associated with the input structure internal to the device. VBIAS is generated internally.
Table 29: Input Reference Clock Jitter Specifications
Name
Units
Description
Min
Nom
Max
REF_CLK clock operating at 156.25 MHz
-50
-
+50
ppm
Phase Jitter (rms) (1–20 MHz)
-
-
1
ps
tDUTY_REF
REF_CLK duty cycle
40
50
60
%
tRCLK/tFCLK
Input signal rise/fall time (20%-80%)
80
500
650
ps
Differential peak-peak REF_CLK input
swing
400
-
2400
mV
RL_CLK
Input termination resistance
40
50
60
ohm
LI_CLK
Input inductance
-
-
4
nH
CI_CLK
Input capacitance
-
-
5
pF
REF_CLK1
Phase Jitter (rms)
vIN_CML2
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Note:
1. The RapidIO Specification (Rev. 2.1) requires that outgoing signals from separate links which belong to the same port should not be separated by
more than +100 ppm. For additional information, see the CPS-1616 Device Errata. For additional clock support, contact IDT technical support.
2. The vIN_CML specification is met by a LVDS driver with VOD > 200 mV (see TIA/EIA-644-A).
The CPS-1616 differential input clock requires a current-mode driver such as LVDS or HCSL. AC-coupling is required. For more information, see
the following example reference clock interface diagrams.
Figure 21: LVDS Reference Clock Input Circuit
Figure 22: HCSL Reference Clock Input Circuit
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CPS-1616 Datasheet
15.
Reset (RST_N) Specification
To reset CPS-1616, RST_N signal has to be asserted (LOW), and it is de-asserted after 5 REF_CLK cycles. 45us later, the device completes the
reset process. Once completed, access to the device from I2C/JTAG is possible and the device is fully functional. Control and data traffic will not
be accepted by the device until this process is fully completed.
REF_CLK
RST_N
5 REF_CLK Cycles min
45us min
I2C/JTAG Access
Figure 23: Reset Timing
Note:
1. During the assertion (LOW) of RST_N signal, all ports are disabled and all logic/FSM is at their default state.
2. To access the device through S-RIO maintenance packet, additional time is required for the link to be establish with the link-partner, refer to table
below.
Table 30: Reset Specification
Description
Min
Typ
Max
Units
Soft / Hard Reset to Receipt of
I2C/JTAG Access
45
-
100
us
This includes reset time as well as internal PLL lock
time.
Soft / Hard Reset to Receipt of S-RIO
Maintenance Packet Access
0.5
-
1
ms
This includes reset time as well as link initialization
time.
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Comments
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CPS-1616 Datasheet
16.
JTAG Interface
Description
The CPS-1616 offers full JTAG (Boundary Scan) support for both its slow speed and high speed pins. This allows “pins-down” testing of newly
manufactured printed circuit boards as well as troubleshooting of field returns. The JTAG TAP Interface offers another method for Configuration
Register Access (CRA) (along with the S-RIO and I2C ports). Thus, this port can program the CPS-1616’s many registers.
Boundary scan testing of the AC-coupled IOs is performed in accordance with IEEE 1149.6 (AC Extest).
IEEE 1149.1 (JTAG) and IEEE 1149.6 (AC Extest) Compliance
All DC pins are in full compliance with IEEE 1149.1 [10]. All AC-coupled pins fully comply with IEEE 1149.6 [11]. All 1149.1 and 1149.6 boundary
scan cells are on the same chain. No additional control cells are provided for independent selection of negative and/or positive terminals of the TXor RX-pairs.
System Logic TAP Controller Overview
The system logic uses a 16-state, six-bit TAP Controller, a four-bit instruction register, and five dedicated pins to perform a variety of functions. The
primary use of the JTAG TAP Controller state machine is to allow the five external JTAG control pins to control and access the CPS-1616's many
external signal pins. The JTAG TAP Controller can also be used for identifying the device part number. The JTAG logic of the CPS-1616 is
displayed in the following figure.
Boundary Scan Register
m
u
x
Device ID Register
Bypass Register
Instruction Register Decoder
TDI
4-Bit Instruction Register
m
u
x
TDO
TMS
TCK
Tap Controller
TRST_N
Figure 24: JTAG Logic
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Signal Definitions
JTAG operations such as Reset, State-transition control and Clock sampling are handled through the signals listed in Table 31. A functional
overview of the TAP Controller and Boundary Scan registers are provided below.
Table 31: JTAG Pin Descriptions
Pin Name
Type
Description
TRST_N1,2
Input
JTAG RESET
Asynchronous reset for JTAG TAP Controller (internal pull-up3)
TCK
Input
JTAG Clock. Requires an external pull-up.
Test logic clock. JTAG_TMS and JTAG_TDI are sampled on the rising edge.
JTAG_TDO is output on the falling edge.
TMS
Input
JTAG Mode Select.
Controls the state transitions for the TAP Controller state machine (internal
pull-up3)
TDI
Input
JTAG Input
Serial data input for BSC chain, Instruction Register, IDCODE register, and
BYPASS register (internal pull-up3)
TDO
Output
JTAG Output
Serial data out. Tri-stated except when shifting while in Shift-DR and
SHIFT-IR TAP Controller states.
Note:
1. At power-up, the TRST_N signal must be asserted LOW to bring the TAP Controller up in a known, reset state. As per the IEEE 1149.1 Specification,
the user can alternatively hold the TMS pin high while clocking TCK five times (minimum) to reset the controller. To deactivate JTAG, tie TRST_N
low so that the TAP Controller remains in a known state at all times. All of the other JTAG input pins are internally biased such that by leaving them
unconnected they are automatically disabled. Note that JTAG inputs are OK to float because they have leakers (as required by the IEEE 1149.1
Specification).
2. If a JTAG debug tool is used, combine the RST_N and the TRST signal from a JTAG header with an AND gate and use the output to drive the
TRST_N pin. If JTAG is not used, pull TRST_N to GND with a 1K resistor.
3. The internal pull-up resistors values for min., typ., and max. are 29K, 39K and 63K Ohm respectively.
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CPS-1616 Datasheet
The system logic TAP Controller transitions from state to state, according to the value present on TMS, as sampled on the rising edge of TCK. The
Test-Logic Reset state can be reached either by asserting TRST_N or by applying a 1 to TMS for five consecutive cycles of TCK. A state diagram
for the TAP Controller appears in Figure 25. The value next to state represent the value that must be applied to TMS on the next rising edge of
TCK, to transition in the direction of the associated arrow.
1
Test- Logic
Reset
0
Run-Test/
Idle
1
0
1
SelectDR-Scan
1
SelectIR-Scan
0
1
1
Capture-DR
0
Shift-DR
0
Capture-IR
0
0
Shift-IR
1
Exit1 -DR
0
Pause-DR
1
1
Exit2-DR
0
0
Pause-IR
Exit2-IR
1
1
1
0
0
1
0
Update-DR
0
1
Exit1-IR
1
0
0
Update-IR
1
0
Figure 25: State Diagram of CPS-1616 TAP Controller
Test Data Register (DR)
The Test Data register contains the following:
•
The Bypass register
•
The Boundary Scan registers
•
The Device ID register
These registers are connected in parallel between a common serial input and a common serial data output, and are described in the following
sections. For more information, see the IEEE Standard Test Access port (IEEE Std. 1149.1-1990).
Boundary Scan Registers
The CPS-1616 boundary scan chain is 103 bits long. The five JTAG pins do not have scan elements associated with them. Full boundary scan
details reside in the associated BSDL file, which can be downloaded from our website at www.IDT.com. The boundary scan chain is connected
between TDI and TDO when the EXTEST or SAMPLE/PRELOAD instructions are selected. Once EXTEST is selected and the TAP Controller
passes through the UPDATE-IR state, whatever value that is currently held in the boundary scan register’s output latches is immediately
transferred to the corresponding outputs or output enables.
Therefore, the SAMPLE/PRELOAD instruction must first load suitable values into the boundary scan cells so that inappropriate values are not
driven out on the system pins. All of the boundary scan cells feature a negative edge latch, which guarantees that clock skew cannot cause
incorrect data to be latched into a cell. The input cells are sample-only cells.
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The simplified logic configuration is displayed in the following figure.
Input
Pin
MUX
To core logic
From previous cell
D
To next cell
Q
shift_dr
clock_dr
Figure 26: Observe-only Input Cell
The simplified logic configuration of the output cells is displayed in the following figure.
EXTEST
To Next Cell
MUX
Data from Core
D
MUX
Data from Previous Cell
To Output Pad
Q
D
Q
shift_dr
clock_dr
update_dr
Figure 27: Output Cell
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CPS-1616 Datasheet
The output enable cells are also output cells. The simplified logic appears in the following figure.
To next cell
EXTEST
Output Enable
From Core
Data from previous cell
MUX
MUX
To output enable
D
Q
D
Q
shift_dr
clock_dr
update_dr
Figure 28: Output Enable Cell
The bidirectional cells are composed of only two boundary scan cells. They contain one output enable cell and one capture cell, which contains
only one register. The input to this single register is selected using a mux that is selected by the output enable cell when EXTEST is disabled.
When the Output Enable Cell is driving a high out to the pad (which enables the pad for output) and EXTEST is disabled, the Capture Cell will be
configured to capture output data from the core to the pad.
However, in the case where the Output Enable Cell is low (signifying a tri-state condition at the pad) or EXTEST is enabled, the Capture Cell will
capture input data from the pad to the core. The configuration is displayed graphically in the following figure.
From previous cell
Output enable from core
Output Enable Cell
EXTEST
Input to core
MUX
Output from core
Capture Cell
I/O
Pin
To next cell
Figure 29: Bidirectional Cell
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Instruction Register (IR)
The Instruction register allows an instruction to be shifted serially into the CPS-1616 at the rising edge of TCK. The instruction is then used to
select the test to be performed or the test register to be accessed, or both. The instruction shifted into the register is latched at the completion of
the shifting process, when the TAP Controller is at the Update-IR state.
The Instruction Register contains four shift-register-based cells that can hold instruction data. This register is decoded to perform the following
functions:
•
To select test data registers that can operate while the instruction is current. The other test data registers should not interfere with chip operation
and selected data registers.
•
To define the serial test data register path used to shift data between TDI and TDO during data register scanning.
The Instruction Register consists of four bits to decode instructions, as displayed in the following table.
Table 32: Instructions Supported by CPS-1616 JTAG Boundary Scan
Instruction
Definition
OPcode
[3:0]
EXTEST
Mandatory instruction allowing the testing of board level interconnections. Data is
typically loaded on the latched parallel outputs of the boundary scan shift register
using the SAMPLE/PRELOAD instruction using the EXTEST instruction. EXTEST
will then hold these values on the outputs while being executed. Also see the
CLAMP instruction for similar capability.
0000
SAMPLE/
PRELOAD
Mandatory instruction that allows data values to be loaded on the latched parallel
output of the boundary-scan shift register before selecting the other boundary-scan
test instruction. The Sample instruction allows a snapshot of data flowing from the
system pins to the on-chip logic or vice versa.
0001
IDCODE
Provided to select Device Identification to read out manufacturer’s identity, part,
and version number.
0010
HIGHZ
Tri-states all output and bidirectional boundary scan cells.
0011
CLAMP
Provides JTAG user the option to bypass the part’s JTAG Controller while keeping
the part outputs controlled similar to EXTEST.
0100
EXTEST_PULSE
AC Extest instruction implemented in accordance with the requirements of the IEEE
std. 1149.6 specification.
0101
EXTEST_TRAIN
AC Extest instruction implemented in accordance with the requirements of the IEEE
std. 1149.6 specification.
0110
RESERVED
Behaviorally equivalent to the BYPASS instruction as per the IEEE std. 1149.1
specification. However, the user is advised to use the BYPASS instruction.
CONFIGURATIO
N REGISTER
ACCESS (CRA)
CPS-1616-specific opcode to allow reading and writing of the configuration
registers. Reads and writes must be 32-bits. For more information, see
Configuration Register Access.
PRIVATE
For internal use only. Do not use.
RESERVED
Behaviorally equivalent to the BYPASS instruction as per the IEEE std. 1149.1
specification. However, the user is advised to use the BYPASS instruction.
1101
PRIVATE
For internal use only. Do not use.
1110
BYPASS
The BYPASS instruction truncates the boundary scan register as a single bit in
length.
1111
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1010
1011–1100
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CPS-1616 Datasheet
EXTEST
The external test (EXTEST) instruction controls the boundary scan register, once it has been initialized using the SAMPLE/PRELOAD instruction.
Using EXTEST, the user can then sample inputs from or load values on the external pins of the CPS-1616. Once this instruction is selected, the
user then uses the SHIFT-DR TAP Controller state to shift values into the boundary scan chain. When the TAP Controller passes through the
UPDATE-DR state, these values will be latched on the output pins or into the output enables.
SAMPLE/PRELOAD
The sample/preload instruction has a dual use. The primary use of this instruction is for preloading the boundary scan register before enabling the
EXTEST instruction. Failure to preload will result in unknown random data being driven on the output pins when EXTEST is selected. The
secondary function of SAMPLE/PRELOAD is for sampling the system state at a specific moment.
BYPASS
The BYPASS instruction truncates the boundary scan register to a single bit in length. During system level use of the JTAG, the boundary scan
chains of all the devices on the board are connected in series. In order to facilitate rapid testing of a device, all other devices are put into BYPASS
mode. Therefore, instead of having to shift 103 times to get a value through the CPS-1616, the user only needs to shift one time to get the value
from TDI to TDO. When the TAP Controller passes through the CAPTURE-DR state, the value in the BYPASS register is updated to be 0.
If the device being used does not have an IDCODE register, then the BYPASS instruction will automatically be selected into the instruction register
when the TAP Controller is reset. Therefore, the first value that will be shifted out of a device without an IDCODE register is 0. Devices such as the
CPS-1616 that include an IDCODE register will automatically load the IDCODE instruction when the TAP Controller is reset, and they will shift out
an initial value of 1. This is done to allow the user to distinguish between devices having IDCODE registers and those that do not.
CLAMP
This instruction, listed as optional in the IEEE 1149.1 JTAG Specifications, allows the boundary scan chain outputs to be clamped to fixed values.
When the clamp instruction is issued, the scan chain will bypass the CPS-1616 and pass through to devices further down the scan chain.
IDCODE
The IDCODE instruction is automatically loaded when the TAP Controller state machine is reset either by the use of the TRST_N signal or by the
application of a 1 on TMS for five or more cycles of TCK as per the IEEE Std 1149.1 specification. The least significant bit of this value must be 1.
Therefore, if a device has a IDCODE register, it will shift out a 1 on the first shift if it is brought directly to the SHIFT-DR TAP Controller state after
the TAP Controller is reset. The board- level tester can then examine this bit and determine if the device contains a DEVICE_ID register (the first
bit is a 1), or if the device only contains a BYPASS register (the first bit is 0).
However, even if the device contains an IDCODE register, it must also contain a BYPASS register. The only difference is that the BYPASS register
will not be the default register selected during the TAP Controller reset. When the IDCODE instruction is active and the TAP Controller is in the
Shift-DR state, the 32-bit value that will be shifted out of the deviceID register is 0x00378067 for Revision A, 0x10378067 for Revision B or C.
Table 33: System Controller deviceID Register
Bit(s)
Mnemonic
Description
R
Reset
0
reserved
reserved
11:1
Manuf_ID
Manufacturer Identity (11 bits)
IDT
0x033
R
0x033
27:12
Part_number
Part Number (16 bits)
This field identifies the part number of the processor
derivative.
For the CPS-1616, this value is 0x0378.
R
Impl.
Dep.
31:28
Version
Version (4 bits)
This field identifies the version number of the processor
derivative.
For the CPS-1616, this value is 0x0 for Revision A, 0x2 for
Revision B or C
R
Impl.
Dep.
©2017 Integrated Device Technology, Inc.
0x1
R/W
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Table 34: CPS-1616 System Controller deviceID Instruction Format for Rev A
Version
Part Number
Manufacturer ID
LSB
0000
0000|0011|0111|1000
0000|0110|011
1
Table 35: CPS-1616 System Controller deviceID Instruction Format for Rev B or C
Version
Part Number
Manufacturer ID
LSB
0010
0000|0011|0111|1000
0000|0110|011
1
EXTEST PULSE
This IEEE 1149.6 instruction applies only to the AC-coupled pins. All DC pins will perform as if the IEEE Std 1149.1 EXTEST instruction is
operating whenever the EXTEST_PULSE instruction is effective.
The EXTEST_PULSE instruction enables edge-detecting behavior on signal paths containing AC pins, where test receivers reconstruct the
original waveform created by a driver even when signals decay due to AC-coupling.
As the operation name suggests, enabling EXTEST_PULSE causes a pulse to be issued which can be detected even on AC-coupled receivers.
For information, see the IEEE Std 1149.6 Specification. Below is a short synopsis.
If enabled, the output signal is forced to the value in its associated Boundary-Scan Register data cell for its driver (true and inverted values for a
differential pair) at the falling edge of TCK in the Update-IR and Update-DR TAP Controller states. The output subsequently transitions to the
opposite of that state (an inverted state) on the first falling edge of TCK that occurs after entering the Run-Test/Idle TAP Controller state. It then
transitions back again to the original state (a non-inverted state) on the first falling edge of TCK after leaving the Run-Test/Idle TAP Controller
state.
EXTEST TRAIN
This IEEE 1149.6 instruction applies only to the AC-coupled pins. All DC pins will perform as if the IEEE Std 1149.1 EXTEST instruction is
operating whenever the EXTEST_PULSE instruction is effective.
The EXTEST_TRAIN instruction enables edge-detecting behavior on signal paths containing AC pins, where test receivers reconstruct the original
waveform created by a driver even when signals decay due to AC-coupling.
As the operation name suggests, enabling EXTEST_TRAIN causes a pulse train to be issued which can be detected even on AC-coupled
receivers. Once in an enabled state, the train will be sent continuously in response to the TCK clock. No other signaling is required to generate the
pulse train while in this state. For information, see the IEEE Std 1149.6 Specification. Below is a short synopsis.
First, the output signal is forced to the state matching the value (a non-inverted state) in its associated Boundary-Scan Register data cell for its
driver (true and inverted values for a differential pair), at the falling edge of TCK in update-IR. Then the output signal transitions to the opposite
state (an inverted state) on the first falling edge of TCK that occurs after entering the Run-Test/Idle TAP Controller state. While remaining in this
state, the output signal will continue to invert on every falling edge of TCK, thereby generating a pulse train.
RESERVED
Reserved instructions are not implemented, but default to a BYPASS mode. IDT recommends using the standard BYPASS opcode rather than
RESERVED opcodes if BYPASS functionality is desired.
PRIVATE
Private instructions implement various test modes used in the device manufacturing process. The user should not enable these instructions.
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CPS-1616 Datasheet
Configuration Register Access
As previously mentioned, the JTAG port can read and write to the CPS-1616’s configuration registers. The same JTAG instruction (4b1010) is
used for both writes and reads.
Table 36: JTAG Configuration Register Access
Bits
Field Name
Size
Description
0
jtag_config_wr_n
1
0 = Write configuration register
1 = Read configuration register
22:1
jtag_config_addr
22
Starting address of the memory-mapped configuration register. 22 address bits map to a unique
double-word aligned on a 32-bit boundary. This provides accessibility to and is consistent with the
S-RIO memory mapping.
54:23
jtag_config_data
32
Reads: Data shifted out (one 32-bit word per read) is read from the configuration register at address
jtag_config_addr.
Writes: Data shifted in (one 32-bit word per write) is written to the configuration register at address
jtag_config_addr.
The CPS-1616’s JTAG functionality does not support register access when it is part of a chain of JTAG
devices. The CPS-1616 must be the only device on the JTAG bus when its registers are accessed using
JTAG. Register access, however, can still be performed from the RapidIO or I2C interfaces.
Writes during Configuration Register Access
A write is performed by shifting the CRA OPcode into the Instruction Register (IR), then shifting in first a read / write select bit, then both the 22-bit
target address and 32-bit data into the Data Register (DR). When bit 0 of the data stream is 0, data shifted in after the address will be written to the
address specified in jtag_config_addr. The TDO pin will transmit all 0s (for the associated timing diagram, see the following figure).
Select_dr_scan
TAP controller
state
Shift_dr
TDI
TDO
Exit1_dr
Capture_dr
Address
Exit1_dr
Exit2_dr
Pause_dr
Shift_dr
Exit2_dr
Update_dr
Pause_dr
Data
Z
Z
Internal
address
Address
Internal
data
Data
Z
Figure 30: Implementation of Write during Configuration Register Access
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CPS-1616 Datasheet
Reads during Configuration Register Access
Reads are much like writes except that target data is not provided. When bit 0 of the data stream is 1, data shifted out will be read from the address
specified in jtag_config_addr. TDI will not be used after the address is shifted in. As a function of read latency in the architecture, the first 16 bits
will be zeros and must be ignored. The following bits will contain the actual register bits.
Select_dr_scan
TAP controller
state
Shift_dr
TDI
TDO
Exit1_dr
Capture_dr
Exit2_dr
Pause_dr
Exit1_dr
Shift_dr
Update_dr
Exit2_dr
Pause_dr
Address
Z
Data
Read latency
Internal
address
Z
Z
Data 1
Address
Internal
data
Data
Figure 31: Implementation of Read during Configuration Register Access
JTAG DC Electrical Specifications
At recommended operating conditions with VDD3 = 3.3V ± 5%.
Table 37: JTAG DC Electrical Specifications (VDD3 = 3.3V ± 5%)
Symbol
Min
Max
Unit
Input high voltage level
VIH
2.0
VDD3(max) + 0.15
V
Input low voltage level
VIL
-0.3
0.8
V
Output high voltage (IOH = -4mA, VDD3 =
Min.)
VOH
2.4
-
V
Output low voltage (IOL = 4mA, VDD3 = Min.)
VOL
-
0.4
V
Input current for JTAG pins (input voltage is
between 0.1 x VDD3 and 0.9 x VDD3 (max))
ILI
-30
30
uA
Capacitance for each Input pin
CIN
-
8
pF
COUT
-
10
pF
Parameter
Capacitance for each I/O or Output pin
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CPS-1616 Datasheet
At recommended operating conditions with VDD3 = 2.5V ± 100mV.
Table 38: JTAG DC Electrical Specifications (VDD3 = 2.5V ± 100mV )
Symbol
Min
Max
Unit
Input high voltage level
VIH
1.7
VDD3(max) + 0.1
V
Input low voltage level
VIL
-0.3
0.7
V
Output high voltage (IOH = -2mA, VDD3 =
Min.)
VOH
2.0
-
V
Output low voltage (IOL = 2mA, VDD3 = Min.)
VOL
-
0.4
V
Input current for JTAG pins (input voltage is
between 0.1 x VDD3 and 0.9 x VDD3 (max))
ILI
-30
30
uA
Capacitance for each Input pin
CIN
-
8
pF
COUT
-
10
pF
Parameter
Capacitance for each I/O or Output pin
JTAG AC Electrical Specifications
Table 39: JTAG AC Electrical Specifications
Symbol
Parameter
Min.
Max.
Units
tJCYC
JTAG Clock Input Period
0
10
MHz
tJCH
JTAG Clock HIGH
40
-
ns
tJCL
JTAG Clock LOW
40
-
ns
ns
tJR
JTAG Clock Rise Time
-
3(1)
tJF
JTAG Clock Fall Time
-
3(1)
ns
tJRST
JTAG Reset
50
-
ns
tJRSR
JTAG Reset Recovery
50
-
ns
tJCD
JTAG Data Output
-
25
ns
tJDC
JTAG Data Output Hold
0
-
ns
tJS
JTAG Setup
15
-
ns
tJH
JTAG Hold
15
-
ns
Notes:
1. Guaranteed by design.
2. See AC Test Conditions.
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CPS-1616 Datasheet
JTAG Timing Waveforms
tJF
tJCL
tJCYC
tJR
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJS
Device Outputs(2)/
TDO
tJDC
tJH
tJRSR
tJCD
TRST
,
5686 drw 08
tJRST
Figure 32: JTAG Timing Specifications
Notes:
1. Device Inputs = All other device input pins.
2. Device Outputs = All other device output pins.
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CPS-1616 Datasheet
17.
Pinout and Pin Listing
Pinout — Top View
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
GND
TMS
GND
VDDT
TX3_N
TX3_P
VDDT
TX2_N
TX2_P
VDDT
TX1_N
TX1_P
VDDT
TX0_N
TX0_P
VDDT
ID6
SDA
SCL
GND
B
TDO
TCK
GND
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
ID7
ID2
ID1
ID0
C
TDI
TRST_N
GND
VDD3
RX3_N
RX3_P
GNDS
RX2_N
RX2_P
GNDS
RX1_N
RX1_P
GNDS
RX0_N
RX0_P
VDD3
ID8
ID5
ID4
ID3
D
IRQ_N
VDD3
GND
GND
GND
GNDS
GNDS
GNDS
VDDA
VDDA
VDDA
VDDA
GNDS
GNDS
GND
MM_N
ID9
VDD3
GNDS
VDDT
E
VDDT
GNDS
VDD3
GND
VDD
VDD
VDDS
VDDS
PD3_N
PD2_N
PD1_N
PD0_N
VDDS
VDDS
VDD
ADS
GND
RX15_N
GNDS
TX15_N
F
TX8_P
GNDS
RX8_P
GND
VDD
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
VDD
GND
RX15_P
GNDS
TX15_P
G
TX8_N
GNDS
RX8_N
GNDS
VDDS
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
VDDS
GNDS
GNDS
GNDS
VDDT
H
VDDT
GNDS
GNDS
GNDS
VDDS
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDDS
GNDS RX14_N
GNDS
TX14_N
J
TX9_P
GNDS
RX9_P
VDDA
PD8_N
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
PD15_N
VDDA
RX14_P
GNDS
TX14_P
K
TX9_N
GNDS
RX9_N
VDDA
PD9_N
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
PD14_N
VDDA
GNDS
GNDS
VDDT
L
VDDT
GNDS
GNDS
VDDA PD10_N
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
PD13_N
VDDA RX13_N
GNDS
TX13_N
M
TX10_P
GNDS RX10_P
VDDA PD11_N
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
PD12_N
VDDA
RX13_P
GNDS
TX13_P
N
TX10_N
GNDS RX10_N
GNDS
VDDS
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDDS
GNDS
GNDS
GNDS
VDDT
P
VDDT
GNDS
GNDS
VDDS
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
VDDS
GNDS RX12_N
GNDS
TX12_N
R
TX11_P
GNDS RX11_P
GND
VDD
VDD
VDD
GND
GND
VDD
VDD
GND
GND
VDD
VDD
GND
GND
RX12_P
GNDS
TX12_P
T
TX11_N
GNDS RX11_N
GND
QCFG1
GND
VDDS
VDDS
PD4_N
PD5_N
PD6_N
PD7_N
VDDS
VDDS
DNC
DNC
VDD3
VDD3A
GNDS
VDDT
U
VDDT
GNDS
VDD3
QCFG0 QCFG2
GND
GNDS
GNDS
VDDA
VDDA
VDDA
VDDA
GNDS
GNDS
GND
GND
VDD3
VDD3
VDDA
REF_CL
K_N
V
RST_N
DNC
GND
QCFG3
VDD3
RX4_P
RX4_N
GNDS
RX5_P
RX5_N
GNDS
RX6_P
RX6_N
GNDS
RX7_P
RX7_N
VDD3
VDD3
SPD0
REF_CL
K_P
W
QCFG4 QCFG5 QCFG6 QCFG7
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
VDDA
SPD1
SPD2
VDDT
TX4_P
TX4_N
VDDT
TX5_P
TX5_N
VDDT
TX6_P
TX6_N
VDDT
TX7_P
TX7_N
VDDT REXT_N REXT_P
Y
GND
MCAST
GNDS
FSEL0
FSEL1
GND
Figure 33: Pinout
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CPS-1616 Datasheet
Pin Listing
Table 40: Pin List (Alphabetical)
Pin
Number
Pin Name
Function
Supply / Interface
Pin Function Description
Note: Statically biased pins should be fixed to a voltage level and not be changed after reset de-assertion.
E16
ADS
I2 C
T15, T16, V2
Y4,
Y3
FSEL1,
FSEL0
Frequency
Select
(VDD3, GND) / CMOS
Input
I2C address width select. Set ADS = GND for 7-bit CPS-1616
slave address. ADS = VDD3 for 10-bit.
DNC
DO NOT CONNECT. These pins should be left FLOATING.
They should not be connected to any other signals or power
rails.
(VDD3, GND) / CMOS
Input
FSEL1: Input reference clock frequency selector:
0 = Not supported.
1 = 156.25 MHz (Default value; required for 6.25 Gbaud line
rates)
FSEL0: Internal core clock frequency selector:
0 = 156.25 MHz (All speeds up to 3.125 Gbaud with Idle2; all
speed up to 2.5 Gbaud with Idle1)
1 = 312.5 MHz (Default value; All speeds including 6.25 Gbaud)
These pins have an internal pull-up.
These pins must remain STATICALLY BIASED after reset.
A1, A3, A20, B3, C3, D3, D4, D5, D15, E4, E17,
F4, F8, F9, F12, F13, F17, G8, G9, G12, G13,
H6, H7, H10, H11, H14, H15, J6, J7, J10, J11,
J14, J15, K8, K9, K12, K13, L8, L9, L12, L13,
M6, M7, M10, M11, M14, M15, N6, N7, N10,
N11, N14, N15, P8, P9, P12, P13, R4, R8, R9,
R12, R13, R16, R17, T4, T6, U6, U15, U16, V3,
Y1, Y20
GND
Digital Ground (CMOS)
B4, B5, B6, B7, B8, B9, B10, B11, B12, B13,
B14, B15, B16, C7, C10, C13, D6, D7, D8, D13,
D14, D19, E2, E19, F2, F19, G2, G4, G17, G18,
G19, H2, H3, H4, H17, H19, J2, J19, K2, K18,
K19, L2, L3, L19, M2, M19, N2, N4, N17, N18,
N19, P2, P3, P4, P17, P19, R2, R19, T2, T19,
U2, U7, U8, U13, U14, V8, V11, V14, W5, W6,
W7, W8, W9, W10, W11, W12, W13, W14, W15,
W16, W17
GNDS
Analog Ground (CMOS)
D17, C17,
B17, A17,
C18, C19,
C20, B18,
B19, B20
ID[9:0]
I2 C
©2017 Integrated Device Technology, Inc.
Digital ground. All pins must be tied to single potential power
supply ground plane.
Note: IDT recommends both GND and GNDS pins be
connected to the common ground plane.
Analog ground. All pins must be tied to single potential ground
supply plane.
Note: IDT recommends both GND and GNDS pins be
connected to the common ground plane.
(VDD3, GND) / CMOS
Input
I2C Slave ID addresses.
These pins must remain STATICALLY BIASED after reset.
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Table 40: Pin List (Alphabetical)
Pin
Number
D1
Pin Name
IRQ_N
Function
Interrupt
Supply / Interface
(VDD3, GND) /
CMOS Open Drain
Output
Pin Function Description
The interrupt output pin whose value is provided by the Error
Management Block.
Note: This is an open-drain output and requires an external
pull-up resistor.
Y2
MCAST
Multicast
(VDD3, GND) / CMOS
Input
This rising edge triggered pin allows the user to generate a
Multicast Control Symbol to all Multicast Event participant
egress ports.
D16
MM_N
I2 C
(VDD3, GND) / CMOS
Input
Select the I2C Master or Slave mode. Logic low for Master
mode.
This pin has an internal pull-up for a default configuration of
slave mode.
This pin must remain STATICALLY BIASED after reset.
J16, K16, L16,
M16, M5, L5,
K5, J5, T12,
T11, T10, T9,
E9, E10, E11,
E12
PD[15:0]_N
Port Disable
(VDD3, GND) / CMOS
Input
Port Disable pins.
These active LOW pins enable / disable S-RIO port at RESET
for all ports. The RESET setting can be overridden by
subsequent programming of the PORT_N_CTRL_CSR register.
Each pin corresponds to a port.
0 = Port disabled
1 = Port enabled
These pins have an internal pull-up for a default configuration to
enable all ports.
These pins must remain STATICALLY BIASED after reset.
W4, W3
QCFG[7:6]
W2, W1
QCFG[5:4]
V4, U5
QCFG[3:2]
T5, U4
QCFG[1:0]
Quadrant
Config
(VDD3, GND) / CMOS
Input
S-RIO Quadrant Configuration pins.
The RESET setting can be overridden by subsequent
programming of the Quadrant Configuration Register. For more
information, see Quadrant Configuration Pins QCFG[7:0].
These pins have an internal pull-up for a default configuration
for all ports. It is required to use an external pull-down resistor
when configuring to settings other than default.
These pins must remain STATICALLY BIASED after reset.
V20, U20
REF_CLK_P,
REF_CLK_N
SerDes Clock
(VDDA, GND) /
Differential Input
This clock is used as the 156.25 MHz reference for standard
SerDes operation.
Y18, Y19
REXT_N,
REXT_P
Rext
(VDDS, GNDS)
External bias resistor. REXT_N must be connected to REXT_P
with a 9.1k Ohm +/- 1% resistor. This establishes the drive bias
on the SerDes output. This provides CML driver stability across
process and temperature.
V1
RST_N
Reset
(VDD3, GND) / CMOS
Input
Global Reset. Sets all internal registers to default values.
Resets all PLLs. Resets all port configurations. This is a HARD
Reset.
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CPS-1616 Datasheet
Table 40: Pin List (Alphabetical)
Pin
Number
Pin Name
Function
Supply / Interface
Pin Function Description
C15, C14
RX0_P,
RX0_N
S-RIO
Receive
(VDDS, GNDS) /
RIO Differential Input
Differential receiver inputs, Lane 0
C12, C11
RX1_P,
RX1_N
S-RIO
Receive
(VDDS, GNDS) /
RIO Differential Input
Differential receiver inputs, Lane 1
C9, C8
RX2_P,
RX2_N
S-RIO
Receive
(VDDS, GNDS) /
RIO Differential Input
Differential receiver inputs, Lane 2
C6, C5
RX3_P,
RX3_N
S-RIO
Receive
(VDDS, GNDS) /
RIO Differential Input
Differential receiver inputs, Lane 3
V6, V7
RX4_P,
RX4_N
S-RIO
Receive
(VDDS, GNDS) /
RIO Differential Input
Differential receiver inputs, Lane 4
V9, V10
RX5_P,
RX5_N
S-RIO
Receive
(VDDS, GNDS) /
RIO Differential Input
Differential receiver inputs, Lane 5
V12, V13
RX6_P,
RX6_N
S-RIO
Receive
(VDDS, GNDS) /
RIO Differential Input
Differential receiver inputs, Lane 6
V15, V16
RX7_P,
RX7_N
S-RIO
Receive
(VDDS, GNDS) /
RIO Differential Input
Differential receiver inputs, Lane 7
F3, G3
RX8_P,
RX8_N
S-RIO
Receive
(VDDS, GNDS) /
RIO Differential Input
Differential receiver inputs, Lane 8
J3, K3
RX9_P,
RX9_N
S-RIO
Receive
(VDDS, GNDS) /
RIO Differential Input
Differential receiver inputs, Lane 9
M3, N3
RX10_P,
RX10_N
S-RIO
Receive
(VDDS, GNDS) /
RIO Differential Input
Differential receiver inputs, Lane 10
R3, T3
RX11_P,
RX11_N
S-RIO
Receive
(VDDS, GNDS) /
RIO Differential Input
Differential receiver inputs, Lane 11
R18, P18
RX12_P,
RX12_N
S-RIO
Receive
(VDDS, GNDS) /
RIO Differential Input
Differential receiver inputs, Lane 12
M18, L18
RX13_P,
RX13_N
S-RIO
Receive
(VDDS, GNDS) /
RIO Differential Input
Differential receiver inputs, Lane 13
J18, H18
RX14_P,
RX14_N
S-RIO
Receive
(VDDS, GNDS) /
RIO Differential Input
Differential receiver inputs, Lane 14
F18, E18
RX15_P,
RX15_N
S-RIO
Receive
(VDDS, GNDS) /
RIO Differential Input
Differential receiver inputs, Lane 15
A19
SCL
I2 C
(VDD3, GND) /CMOS
Input
I2C Clock
A18
SDA
I2 C
(VDD3, GND) / CMOS
IO
I2C Serial Data IO. Data direction is determined by the I2C
Read/ Write bit. For more information, see I2C Bus.
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Table 40: Pin List (Alphabetical)
Pin
Number
W20, W19,
V19
Pin Name
SPD[2:0]
Function
SPEED
Supply / Interface
(VDD3, GND) / CMOS
Input
Pin Function Description
Speed Select Pins. These pins define S-RIO port speed at
RESET for all ports. For more information, see Speed Select
Pins SPD[2:0].
SPD[2:0] =
000 = 1.25 Gbaud
001 = 2.5 Gbaud
01X = 5.0 Gbaud
100 = Reserved
101 = 3.125 Gbaud
11X = 6.25 Gbaud
These pins must remain STATICALLY BIASED after reset.
B2
TCK
JTAG
(VDD3, GND) / CMOS
Input
JTAG Tap Port Clock
C1
TDI
JTAG
(VDD3, GND) / CMOS
Input
JTAG Tap Port Input
This pin has an internal pull-up.
B1
TDO
JTAG
(VDD3, GND) /
CMOS output
JTAG Tap Port Output
A2
TMS
JTAG
(VDD3, GND) / CMOS
Input
JTAG Tap Port Mode Select
This pin has an internal pull-up.
C2
TRST_N
JTAG
(VDD3, GND) / CMOS
Input
JTAG Tap Port Asynchronous Reset
This pin has an internal pull-up.
A15, A14
TX0_P,
TX0_N
S-RIO
Transmit
(VDDT, GNDS) /
RIO Differential Output
Differential transmitter outputs, Lane 0
A12, A11
TX1_P,
TX1_N
S-RIO
Transmit
(VDDT, GNDS) /
RIO Differential Output
Differential transmitter outputs, Lane 1
A9, A8
TX2_P,
TX2_N
S-RIO
Transmit
(VDDT, GNDS) /
RIO Differential Output
Differential transmitter outputs, Lane 2
A6, A5
TX3_P,
TX3_N
S-RIO
Transmit
(VDDT, GNDS) /
RIO Differential Output
Differential transmitter outputs, Lane 3
Y6, Y7
TX4_P,
TX4_N
S-RIO
Transmit
(VDDT, GNDS) /
RIO Differential Output
Differential transmitter outputs, Lane 4
Y9, Y10
TX5_P,
TX5_N
S-RIO
Transmit
(VDDT, GNDS) /
RIO Differential Output
Differential transmitter outputs, Lane 5
Y12, Y13
TX6_P,
TX6_N
S-RIO
Transmit
(VDDT, GNDS) /
RIO Differential Output
Differential transmitter outputs, Lane 6
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Table 40: Pin List (Alphabetical)
Pin
Number
Pin Name
Function
Supply / Interface
Pin Function Description
Y15, Y16
TX7_P,
TX7_N
S-RIO
Transmit
(VDDT, GNDS) /
RIO Differential Output
Differential transmitter outputs, Lane 7
F1, G1
TX8_P,
TX8_N
S-RIO
Transmit
(VDDT, GNDS) /
RIO Differential Output
Differential transmitter outputs, Lane 8
J1, K1
TX9_P,
TX9_N
S-RIO
Transmit
(VDDT, GNDS) /
RIO Differential Output
Differential transmitter outputs, Lane 9
M1, N1
TX10_P,
TX10_N
S-RIO
Transmit
(VDDT, GNDS) /
RIO Differential Output
Differential transmitter outputs, Lane 10
R1, T1
TX11_P,
TX11_N
S-RIO
Transmit
(VDDT, GNDS) /
RIO Differential Output
Differential transmitter outputs, Lane 11
R20, P20
TX12_P,
TX12_N
S-RIO
Transmit
(VDDT, GNDS) /
RIO Differential Output
Differential transmitter outputs, Lane 12
M20, L20
TX13_P,
TX13_N
S-RIO
Transmit
(VDDT, GNDS) /
RIO Differential Output
Differential transmitter outputs, Lane 13
J20, H20
TX14_P,
TX14_N
S-RIO
Transmit
(VDDT, GNDS) /
RIO Differential Output
Differential transmitter outputs, Lane 14
F20, E20
TX15_P,
TX15_N
S-RIO
Transmit
(VDDT, GNDS) /
RIO Differential Output
Differential transmitter outputs, Lane 15
VDD
1.0V Digital Power
(CMOS)
Digital power. All pins must be tied to single potential power
supply plane.
E5, E6, E15, F5, F6, F7, F10, F11, F14, F15,
F16, G6, G7, G10, G11, G14, G15, H8, H9, H12,
H13, J8, J9, J12, J13, K6, K7, K10, K11, K14,
K15, L6, L7, L10, L11, L14, L15, M8, M9, M12,
M13, N8, N9, N12, N13, P6, P7, P10, P11, P14,
P15, R5, R6, R7, R10, R11, R14, R15
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Table 40: Pin List (Alphabetical)
Pin
Number
Pin Name
Function
C4, C16, D2, D18, E3, T17, T18, U3, U17, U18,
V5, V17, V18
Supply / Interface
VDD3
3.3V/2.5V Digital IO
Power (CMOS)
Pin Function Description
Digital Interface power. All pins must be tied to single potential
power supply plane.
Note: The T18 pin (VDD3A) supplies power to the internal
SerDes analog bandgap circuitry to generate a stable internal
voltage reference. The VDD3A power supply is internally
isolated from the VDD3 supply. The VDD3 and VDD3A supplies
may use the same external power supply. It is recommended
that a decoupling capacitor of 0.01uF be placed directly on the
break-out via for the VDD3A pin under the BGA on the bottom
side of the PCB.
D9, D10, D11, D12, J4, J17, K4, K17, L4, L17,
M4, M17, U9, U10, U11, U12, U19, W18
VDDA
1.0V Analog Power
(CMOS)
Analog power. IDT recommends to use common power source
for VDDS and VDDA. VDD (core, digital supply) and VDDT should
have its own supply and plane.
E7, E8, E13, E14, G5, G16, H5, H16, N5, N16,
P5, P16, T7, T8, T13, T14
VDDS
1.0V SerDes Power
(CMOS)
Analog power for SerDes and RX pairs. IDT recommends to
use common power source for VDDS and VDDA. VDD (core,
digital supply) and VDDT should have its own supply and plane.
A4, A7, A10, A13, A16, D20, E1, G20, H1, K20,
L1, N20, P1, T20, U1, Y5, Y8, Y11, Y14, Y17
VDDT
1.2V SerDes Power
(CMOS)
Analog power for TX pairs. IDT recommends to use common
power source for VDDS and VDDA. VDD (core, digital supply) and
VDDT should have its own supply and plane.
Note:
1. RX and TX (differential input/output) are all CML based signaling.
2. Automatic swapping of a differential pair, and automatic reordering of lanes are not supported in Level I links (except when connected to another
IDT S-RIO Gen2 device) only supported in Level II links.
RapidIO Gen1 devices support the IDLE1 sequence only. It is not possible to reverse the lane ordering of a
CPS-1616 port when the IDLE1 sequence is used; therefore, the link partner’s lanes must be connected in
the correct order.
The use of lane reordering is not recommended for links that support hot swap, or that are expected to
successfully downgrade if there is a hardware error. Lane reordering should be restricted to on-board,
chip-to-chip links operating with the IDLE2 sequence between IDT Gen2 switches.
3. Unused RX and TX differential pins can be left unconnected.
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CPS-1616 Datasheet
18.
Package Specifications
Package Physical Specifications
Package: FlipChip BGA (FCBGA)
Dimensions: 21 x 21 mm
Ball count: 400
Ball diameter: 0.6 mm
Ball pitch: 1.0 mm
Lid material: Nickel platted copper
Max ground (GND)-to-package lid resistance: 10 Ohms
Package Outline Drawings
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Figure 34: Lidded Package Drawing (HR/HLG Package) – Sheet 1
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Figure 35: Lidded Package Drawing (HR/HLG Package) – Sheet 2
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CPS-1616 Datasheet
Figure 36: Lidless Package Drawing (RM/HMG Package) – Sheet 1
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CPS-1616 Datasheet
Figure 37: Lidless Package Drawing (RM/HMG Package) – Sheet 2
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CPS-1616 Datasheet
Thermal Characteristics
Heat generated by the packaged IC has to be removed from the package to ensure that the IC is maintained within its functional and maximum
design temperature limits. If heat buildup becomes excessive, the IC temperature may exceed the temperature limits. A consequence of this is that
the IC may fail to meet the performance specifications and the reliability objectives may be affected.
Failure mechanisms and failure rate of a device have an exponential dependence of the IC operating temperatures. Thus, the control of the
package temperature, and by extension the Junction Temperature, is essential to ensure product reliability. The CPS-1616 is specified safe for
operation when the Junction Temperature is within the recommended limits.
Junction-to-Board/Case Thermal Characteristics (Theta jb/jc)
Table 41 shows the Theta jb and Theta jc thermal characteristics of the CPS-1616 RM/HMG FCBGA package.
Table 41: Thermal Characteristics
Interface
Results
Theta Jb (junction to board)
8.94 oC/watt
Theta Jc (junction to case)
0.22 oC/watt
Table 42 shows the Theta jb and Theta jc thermal characteristics of the CPS-1616 HR/HLG FCBGA package.
Table 42: Thermal Characteristics
Interface
Results
Theta Jb (junction to board)
6.48 oC/watt
Theta Jc (junction to case)
0.88 oC/watt
Junction-to-Ambient Thermal Characteristics (Theta ja)
Table 43 shows the Theta Ja thermal characteristic of the CPS-1616 FCBGA packages. The results in the table are based on a JEDEC Thermal
Test Board configuration (JESD51-9) and do not factor in system-level characteristics. As such, these values are for reference only.
The Theta Ja thermal resistance characteristics of a package depend on multiple system level variables.
Table 43: Junction to Ambient Characteristics
Theta Ja at Specified Airflow (no Heat Sink)
Packagesa
0 m/s
1 m/s
2 m/s
RM/HMG FCBGA
17.8 oC/watt
12.7 oC/watt
11.0 oC/watt
HR/HLG FCBGA
16.7 oC/watt
12.3 oC/watt
10.4 oC/watt
a. Based on JEDEC PCB 2s2p (114.3 x 101.6 mm) and includes the effect of 49 PCB thermal
vias.
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System-level Characteristics
In an application, the following system-level characteristics and environmental issues must be taken into account:
•
Package mounting (vertical / horizontal)
•
System airflow conditions (laminar / turbulent)
•
Heat sink design and thermal characteristics (see Heat Sink Requirement and Analysis)
•
Heat sink attachment method (see Heat Sink Requirement and Analysis)
•
PWB size, layer count and conductor thickness
•
Influence of the heat dissipating components assembled on the PWB (neighboring effects)
Example on Thermal Data Usage
Based on the ThetaJA data and specified conditions, the following formula can be used to derive the junction temperature (TJ) of the CPS-1616
RM package with a 0 m/s airflow:
•
TJ = ӨJA * P + TAMB
Where: TJ is Junction Temperature, ӨJA is ThetaJA, P is the Power consumption, TAMB is the Ambient Temperature
Assuming a power consumption (P) of 3.5 W and an ambient temperature (TAMB) of 60oC, the resulting junction temperature (TJ) would be
122.3oC.
Heat Sink Requirement and Analysis
The CPS-1616 is packaged in a Flip-Chip Ball Grid Array (FCBGA). If a heat sink is required to maintain junction temperatures at or below
specified maximum values, it is important that attachment techniques and thermal requirements be critically analyzed to ensure reliability of this
interface. Factors to be considered include, but are not limited to the following:
•
Surface preparations
•
Selection of thermal interface materials
•
Curing process
•
Shock and vibration requirements
•
Thermal expansion coefficient
Each design should be individually analyzed to ensure that a reliable thermal solution is achieved.
Both mechanical and adhesive techniques are available for heat sink attachment. IDT makes no
recommendations as to the reliability or effectiveness of either approach. The designer must critically
analyze heat sink requirements, selection criteria, and attachment techniques.
For heat sink attachment methods that induce a compressive load to the FCBGA package, the maximum force that can be applied to the package
should be limited to 5 gm / BGA ball (provided that the board is supported to prevent any flexing or bowing). The maximum force for the CPS-1616
package is 2.0 Kg.
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19.
Ordering Information
XXXXX
A
A
A
Device
Type
Revision
Package
Process/
Temp. Range
No Identifier
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
RM
HMG
400-FCBGA, Lidless, RoHS Compliant with exemption
400-FCBGA, Lidless, Pb-free, RoHS Compliant
HR
HLG
400-FCBGA, Lidded, RoHS Compliant with exemption
400-FCBGA, Lidded, Pb-free, RoHS Compliant
No Identifier
C
Revision A or B
Revision C
80HCPS1616 Central Packet Switch
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CPS-1616 Datasheet
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Sales
Tech Support
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Fax: 408-284-2775
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DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,
without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same
way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability
of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not
convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property
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